| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.01 | 95.46 | 93.77 | 95.25 | 94.47 | 97.53 | 99.58 |
| T2762 | /workspace/coverage/cover_reg_top/19.xbar_error_random.3861094673 | Jun 30 08:14:54 PM PDT 24 | Jun 30 08:15:24 PM PDT 24 | 629820304 ps | ||
| T2763 | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.1233025685 | Jun 30 08:13:03 PM PDT 24 | Jun 30 08:14:33 PM PDT 24 | 8217431047 ps | ||
| T2764 | /workspace/coverage/cover_reg_top/19.xbar_random.2706685953 | Jun 30 08:14:42 PM PDT 24 | Jun 30 08:15:11 PM PDT 24 | 256336350 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.1541383160 | Jun 30 08:22:31 PM PDT 24 | Jun 30 08:24:16 PM PDT 24 | 6227335220 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/77.xbar_error_random.3598155920 | Jun 30 08:26:19 PM PDT 24 | Jun 30 08:26:48 PM PDT 24 | 807466946 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.1659576126 | Jun 30 08:26:19 PM PDT 24 | Jun 30 08:26:28 PM PDT 24 | 50104752 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1712922889 | Jun 30 08:27:55 PM PDT 24 | Jun 30 08:28:43 PM PDT 24 | 2647609945 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.387966911 | Jun 30 08:11:28 PM PDT 24 | Jun 30 08:13:13 PM PDT 24 | 5713807491 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.2915786521 | Jun 30 08:23:29 PM PDT 24 | Jun 30 08:24:35 PM PDT 24 | 1412320034 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.2469879651 | Jun 30 08:21:06 PM PDT 24 | Jun 30 08:38:45 PM PDT 24 | 102198318076 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.627151140 | Jun 30 08:17:53 PM PDT 24 | Jun 30 08:20:27 PM PDT 24 | 2908005765 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.3273083795 | Jun 30 08:25:38 PM PDT 24 | Jun 30 08:27:29 PM PDT 24 | 6313494840 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.164569400 | Jun 30 08:15:19 PM PDT 24 | Jun 30 08:16:50 PM PDT 24 | 8278736949 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/5.xbar_random.1113213461 | Jun 30 08:08:46 PM PDT 24 | Jun 30 08:08:56 PM PDT 24 | 76677835 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1438835847 | Jun 30 08:24:15 PM PDT 24 | Jun 30 08:24:29 PM PDT 24 | 102111624 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/13.xbar_random.2978836845 | Jun 30 08:12:40 PM PDT 24 | Jun 30 08:13:08 PM PDT 24 | 272134802 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3645591811 | Jun 30 08:24:37 PM PDT 24 | Jun 30 08:30:19 PM PDT 24 | 2547209961 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.4134898806 | Jun 30 08:26:58 PM PDT 24 | Jun 30 08:27:47 PM PDT 24 | 502116431 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/43.xbar_same_source.3207570232 | Jun 30 08:20:11 PM PDT 24 | Jun 30 08:21:17 PM PDT 24 | 2118801694 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.3905099635 | Jun 30 08:23:28 PM PDT 24 | Jun 30 08:24:12 PM PDT 24 | 509364788 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.3487970414 | Jun 30 08:20:59 PM PDT 24 | Jun 30 08:21:36 PM PDT 24 | 756568246 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/24.chip_tl_errors.819850668 | Jun 30 08:16:09 PM PDT 24 | Jun 30 08:21:49 PM PDT 24 | 3798001758 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2816858337 | Jun 30 08:20:31 PM PDT 24 | Jun 30 08:21:02 PM PDT 24 | 642149505 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1173444733 | Jun 30 08:05:53 PM PDT 24 | Jun 30 08:16:05 PM PDT 24 | 2723788714 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.3752000662 | Jun 30 08:23:30 PM PDT 24 | Jun 30 08:23:38 PM PDT 24 | 54110534 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/3.xbar_stress_all.2430060802 | Jun 30 08:07:48 PM PDT 24 | Jun 30 08:13:52 PM PDT 24 | 9032961279 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.778709680 | Jun 30 08:11:44 PM PDT 24 | Jun 30 08:13:11 PM PDT 24 | 474011642 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.256181526 | Jun 30 08:20:14 PM PDT 24 | Jun 30 08:21:45 PM PDT 24 | 8681935494 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.397409756 | Jun 30 08:23:02 PM PDT 24 | Jun 30 08:26:24 PM PDT 24 | 10936514852 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.465612862 | Jun 30 08:18:43 PM PDT 24 | Jun 30 08:19:12 PM PDT 24 | 248706530 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/28.xbar_smoke.1100217902 | Jun 30 08:17:05 PM PDT 24 | Jun 30 08:17:14 PM PDT 24 | 186453171 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.3506374148 | Jun 30 08:27:50 PM PDT 24 | Jun 30 08:29:48 PM PDT 24 | 6788332727 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/26.xbar_error_random.2760066162 | Jun 30 08:16:38 PM PDT 24 | Jun 30 08:16:47 PM PDT 24 | 63210977 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/88.xbar_smoke.3236648988 | Jun 30 08:28:07 PM PDT 24 | Jun 30 08:28:14 PM PDT 24 | 43888753 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.1302084752 | Jun 30 08:28:02 PM PDT 24 | Jun 30 08:28:11 PM PDT 24 | 62611497 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.2132455328 | Jun 30 08:28:04 PM PDT 24 | Jun 30 08:28:30 PM PDT 24 | 401983854 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/40.xbar_stress_all.3844876422 | Jun 30 08:19:48 PM PDT 24 | Jun 30 08:23:48 PM PDT 24 | 5301604366 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/65.xbar_same_source.462631595 | Jun 30 08:24:19 PM PDT 24 | Jun 30 08:24:38 PM PDT 24 | 210657938 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.1917561876 | Jun 30 08:08:47 PM PDT 24 | Jun 30 08:11:51 PM PDT 24 | 9634936684 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/85.xbar_random.2897475177 | Jun 30 08:27:36 PM PDT 24 | Jun 30 08:28:20 PM PDT 24 | 1019730233 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/5.xbar_error_random.2202163305 | Jun 30 08:08:53 PM PDT 24 | Jun 30 08:09:00 PM PDT 24 | 41240492 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.1209046562 | Jun 30 08:28:42 PM PDT 24 | Jun 30 08:39:52 PM PDT 24 | 17952278735 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/33.xbar_error_random.1286366402 | Jun 30 08:18:11 PM PDT 24 | Jun 30 08:18:59 PM PDT 24 | 367814492 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/76.xbar_error_random.243106153 | Jun 30 08:26:13 PM PDT 24 | Jun 30 08:27:02 PM PDT 24 | 1127763713 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/3.chip_tl_errors.1528220426 | Jun 30 08:06:59 PM PDT 24 | Jun 30 08:13:33 PM PDT 24 | 4484627000 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/34.xbar_smoke.3769517694 | Jun 30 08:18:16 PM PDT 24 | Jun 30 08:18:36 PM PDT 24 | 186334395 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/2.xbar_smoke.2993441865 | Jun 30 08:06:12 PM PDT 24 | Jun 30 08:06:22 PM PDT 24 | 203342768 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1516844593 | Jun 30 08:12:42 PM PDT 24 | Jun 30 08:57:14 PM PDT 24 | 148516895244 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.1505122407 | Jun 30 08:25:38 PM PDT 24 | Jun 30 08:27:15 PM PDT 24 | 8530602368 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.2629013250 | Jun 30 08:20:23 PM PDT 24 | Jun 30 08:21:26 PM PDT 24 | 1417007812 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.2836711700 | Jun 30 08:21:29 PM PDT 24 | Jun 30 08:22:24 PM PDT 24 | 1184772772 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.2917237151 | Jun 30 08:26:39 PM PDT 24 | Jun 30 08:27:00 PM PDT 24 | 469106879 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.2810176747 | Jun 30 08:29:59 PM PDT 24 | Jun 30 08:43:08 PM PDT 24 | 19061388305 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3268562913 | Jun 30 08:19:46 PM PDT 24 | Jun 30 08:25:54 PM PDT 24 | 1454771034 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.1239241192 | Jun 30 08:19:40 PM PDT 24 | Jun 30 08:31:30 PM PDT 24 | 6519381102 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.734477153 | Jun 30 08:29:12 PM PDT 24 | Jun 30 08:31:57 PM PDT 24 | 394792593 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1546706549 | Jun 30 08:28:15 PM PDT 24 | Jun 30 08:29:26 PM PDT 24 | 4015678777 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.1375525506 | Jun 30 08:20:47 PM PDT 24 | Jun 30 08:20:55 PM PDT 24 | 48060432 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.3467214620 | Jun 30 08:18:43 PM PDT 24 | Jun 30 08:28:26 PM PDT 24 | 32595518585 ps | ||
| T379 | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.1999209648 | Jun 30 08:10:52 PM PDT 24 | Jun 30 09:06:57 PM PDT 24 | 28559788616 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/71.xbar_error_random.3707015710 | Jun 30 08:25:19 PM PDT 24 | Jun 30 08:25:35 PM PDT 24 | 371490376 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3196171383 | Jun 30 08:22:27 PM PDT 24 | Jun 30 08:29:27 PM PDT 24 | 8042537472 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.3730224981 | Jun 30 08:26:11 PM PDT 24 | Jun 30 08:39:21 PM PDT 24 | 47222074856 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.2327982887 | Jun 30 08:30:02 PM PDT 24 | Jun 30 08:31:12 PM PDT 24 | 4380316137 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.1292156914 | Jun 30 08:25:03 PM PDT 24 | Jun 30 08:31:33 PM PDT 24 | 35455045690 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.425457502 | Jun 30 08:18:38 PM PDT 24 | Jun 30 08:24:59 PM PDT 24 | 10856833306 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/25.xbar_same_source.1241584910 | Jun 30 08:16:45 PM PDT 24 | Jun 30 08:17:46 PM PDT 24 | 1925479967 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.3601528952 | Jun 30 08:16:22 PM PDT 24 | Jun 30 08:18:56 PM PDT 24 | 13585578860 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.3452456539 | Jun 30 08:15:23 PM PDT 24 | Jun 30 08:15:49 PM PDT 24 | 195004362 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.3815362667 | Jun 30 08:22:01 PM PDT 24 | Jun 30 08:25:09 PM PDT 24 | 2365649719 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/49.xbar_same_source.3234611334 | Jun 30 08:21:16 PM PDT 24 | Jun 30 08:21:54 PM PDT 24 | 467612236 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/48.xbar_stress_all.3173837165 | Jun 30 08:21:13 PM PDT 24 | Jun 30 08:23:30 PM PDT 24 | 1078356826 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.27567468 | Jun 30 08:08:01 PM PDT 24 | Jun 30 09:34:53 PM PDT 24 | 35722597080 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/64.xbar_smoke.4159318265 | Jun 30 08:24:00 PM PDT 24 | Jun 30 08:24:07 PM PDT 24 | 52270542 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/91.xbar_error_random.660302192 | Jun 30 08:28:46 PM PDT 24 | Jun 30 08:29:08 PM PDT 24 | 649762050 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.993809086 | Jun 30 08:11:01 PM PDT 24 | Jun 30 08:12:08 PM PDT 24 | 3985538780 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/7.xbar_stress_all.431880622 | Jun 30 08:10:24 PM PDT 24 | Jun 30 08:12:57 PM PDT 24 | 1565145447 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/46.xbar_smoke.2831532144 | Jun 30 08:20:37 PM PDT 24 | Jun 30 08:20:48 PM PDT 24 | 212839908 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/58.xbar_stress_all.600695063 | Jun 30 08:23:13 PM PDT 24 | Jun 30 08:24:28 PM PDT 24 | 2006228860 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.3366117802 | Jun 30 08:28:21 PM PDT 24 | Jun 30 08:33:16 PM PDT 24 | 7340930646 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.3358029241 | Jun 30 08:23:24 PM PDT 24 | Jun 30 08:24:30 PM PDT 24 | 1349770865 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3364426330 | Jun 30 08:14:46 PM PDT 24 | Jun 30 08:16:03 PM PDT 24 | 4338526976 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.3364287305 | Jun 30 08:30:00 PM PDT 24 | Jun 30 08:31:28 PM PDT 24 | 4992381953 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.2269774307 | Jun 30 08:18:50 PM PDT 24 | Jun 30 08:19:28 PM PDT 24 | 833236159 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1833786149 | Jun 30 08:04:50 PM PDT 24 | Jun 30 08:18:14 PM PDT 24 | 14586997484 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/13.xbar_smoke.673106258 | Jun 30 08:12:35 PM PDT 24 | Jun 30 08:12:48 PM PDT 24 | 237663760 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/37.xbar_smoke.449639476 | Jun 30 08:18:49 PM PDT 24 | Jun 30 08:19:01 PM PDT 24 | 227554020 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/61.xbar_error_random.3414763918 | Jun 30 08:23:19 PM PDT 24 | Jun 30 08:24:41 PM PDT 24 | 2077595912 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/46.xbar_random.1998107327 | Jun 30 08:20:44 PM PDT 24 | Jun 30 08:21:27 PM PDT 24 | 468143572 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1638319025 | Jun 30 08:16:44 PM PDT 24 | Jun 30 08:17:07 PM PDT 24 | 561020722 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.2642547980 | Jun 30 08:18:50 PM PDT 24 | Jun 30 08:22:48 PM PDT 24 | 4154519841 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.20561946 | Jun 30 08:28:13 PM PDT 24 | Jun 30 08:46:15 PM PDT 24 | 66070128331 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.2947959151 | Jun 30 08:19:20 PM PDT 24 | Jun 30 08:23:30 PM PDT 24 | 24419005855 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1284752627 | Jun 30 08:12:55 PM PDT 24 | Jun 30 08:22:11 PM PDT 24 | 3863590933 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.3191022455 | Jun 30 08:06:04 PM PDT 24 | Jun 30 08:12:08 PM PDT 24 | 7396417276 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.304500718 | Jun 30 08:19:52 PM PDT 24 | Jun 30 08:19:59 PM PDT 24 | 51829244 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/16.xbar_random.461075572 | Jun 30 08:13:45 PM PDT 24 | Jun 30 08:15:35 PM PDT 24 | 2613198735 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1889844216 | Jun 30 08:18:21 PM PDT 24 | Jun 30 08:20:18 PM PDT 24 | 2872757509 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/81.xbar_random.2478431066 | Jun 30 08:26:58 PM PDT 24 | Jun 30 08:27:31 PM PDT 24 | 323427135 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3257122877 | Jun 30 08:24:45 PM PDT 24 | Jun 30 08:35:45 PM PDT 24 | 5922550665 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.2284952971 | Jun 30 08:22:32 PM PDT 24 | Jun 30 08:22:49 PM PDT 24 | 204763117 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.1881695435 | Jun 30 08:24:34 PM PDT 24 | Jun 30 08:26:09 PM PDT 24 | 5240879999 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.1491930860 | Jun 30 08:19:10 PM PDT 24 | Jun 30 08:21:04 PM PDT 24 | 961607606 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.3721969204 | Jun 30 08:24:50 PM PDT 24 | Jun 30 08:26:38 PM PDT 24 | 2736595797 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/47.xbar_error_random.1799387074 | Jun 30 08:20:54 PM PDT 24 | Jun 30 08:21:06 PM PDT 24 | 250681890 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.287957263 | Jun 30 08:16:27 PM PDT 24 | Jun 30 08:16:46 PM PDT 24 | 366855071 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/62.xbar_error_random.3928355722 | Jun 30 08:23:36 PM PDT 24 | Jun 30 08:23:46 PM PDT 24 | 67206360 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.2139643807 | Jun 30 08:18:00 PM PDT 24 | Jun 30 08:25:06 PM PDT 24 | 8012503037 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.3803030720 | Jun 30 08:18:06 PM PDT 24 | Jun 30 08:24:51 PM PDT 24 | 35533238271 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.3580072575 | Jun 30 08:29:12 PM PDT 24 | Jun 30 08:29:41 PM PDT 24 | 227711329 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1992458816 | Jun 30 08:04:29 PM PDT 24 | Jun 30 08:11:19 PM PDT 24 | 7844311677 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/66.xbar_stress_all.1710842678 | Jun 30 08:24:26 PM PDT 24 | Jun 30 08:29:34 PM PDT 24 | 7624178528 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.2632738139 | Jun 30 08:21:40 PM PDT 24 | Jun 30 08:22:18 PM PDT 24 | 641167883 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/15.chip_csr_rw.474996968 | Jun 30 08:13:41 PM PDT 24 | Jun 30 08:19:38 PM PDT 24 | 4870433435 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/4.xbar_same_source.4007250169 | Jun 30 08:08:23 PM PDT 24 | Jun 30 08:08:45 PM PDT 24 | 570535082 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.4193402239 | Jun 30 08:21:48 PM PDT 24 | Jun 30 08:23:20 PM PDT 24 | 411576014 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.1144238874 | Jun 30 08:17:14 PM PDT 24 | Jun 30 08:28:40 PM PDT 24 | 36910843929 ps | ||
| T42 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1000849064 | Jun 30 08:30:17 PM PDT 24 | Jun 30 08:34:21 PM PDT 24 | 4093272275 ps | ||
| T43 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3107679361 | Jun 30 08:30:13 PM PDT 24 | Jun 30 08:34:18 PM PDT 24 | 4605600006 ps | ||
| T44 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2676152179 | Jun 30 08:30:16 PM PDT 24 | Jun 30 08:34:29 PM PDT 24 | 4968851188 ps | ||
| T181 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2898827286 | Jun 30 08:30:17 PM PDT 24 | Jun 30 08:35:04 PM PDT 24 | 4897711064 ps | ||
| T182 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.736990278 | Jun 30 08:30:17 PM PDT 24 | Jun 30 08:33:54 PM PDT 24 | 3480848812 ps | ||
| T183 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1937758927 | Jun 30 08:30:13 PM PDT 24 | Jun 30 08:34:25 PM PDT 24 | 4963055070 ps | ||
| T184 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.555498105 | Jun 30 08:30:17 PM PDT 24 | Jun 30 08:34:50 PM PDT 24 | 6216213680 ps | ||
| T185 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1249374038 | Jun 30 08:30:19 PM PDT 24 | Jun 30 08:35:00 PM PDT 24 | 4526661118 ps | ||
| T186 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3362211285 | Jun 30 08:30:15 PM PDT 24 | Jun 30 08:33:53 PM PDT 24 | 3805591696 ps | ||
| T187 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3805354577 | Jun 30 08:30:13 PM PDT 24 | Jun 30 08:34:53 PM PDT 24 | 4783626635 ps |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.3345127916 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3053776472 ps |
| CPU time | 322.52 seconds |
| Started | Jun 30 07:55:33 PM PDT 24 |
| Finished | Jun 30 08:00:56 PM PDT 24 |
| Peak memory | 607464 kb |
| Host | smart-831b47d2-53e4-4c0a-8632-c248464bbb43 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345127916 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.3345127916 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.3700782371 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4002998560 ps |
| CPU time | 328.78 seconds |
| Started | Jun 30 08:11:21 PM PDT 24 |
| Finished | Jun 30 08:16:50 PM PDT 24 |
| Peak memory | 595892 kb |
| Host | smart-ffc7c896-a0be-4322-af04-447ba8c11f05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700782371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.3700782371 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.3255757005 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 6304134906 ps |
| CPU time | 1441.03 seconds |
| Started | Jun 30 07:46:38 PM PDT 24 |
| Finished | Jun 30 08:10:40 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-2573131b-b03b-49be-b7ae-6519088690d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255757005 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.3255757005 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.4233286664 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 6590314285 ps |
| CPU time | 245.62 seconds |
| Started | Jun 30 08:27:17 PM PDT 24 |
| Finished | Jun 30 08:31:24 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-66ad9e75-eeae-45d2-90d2-46ab33cd398c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233286664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.4233286664 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.1770522416 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 156295493446 ps |
| CPU time | 2678.77 seconds |
| Started | Jun 30 08:21:07 PM PDT 24 |
| Finished | Jun 30 09:05:46 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-bc51e650-15e4-4ad4-8d14-737ab003c188 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770522416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.1770522416 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1000849064 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4093272275 ps |
| CPU time | 243.43 seconds |
| Started | Jun 30 08:30:17 PM PDT 24 |
| Finished | Jun 30 08:34:21 PM PDT 24 |
| Peak memory | 648520 kb |
| Host | smart-c2a75274-5ac4-4cd2-abab-a0c3063e6476 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000849064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.1000849064 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3224577636 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 154249152865 ps |
| CPU time | 2740.43 seconds |
| Started | Jun 30 08:22:05 PM PDT 24 |
| Finished | Jun 30 09:07:47 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-1395a79b-2db9-44a2-91a7-abcea2b2b058 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224577636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.3224577636 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.857123280 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 5454227128 ps |
| CPU time | 540.82 seconds |
| Started | Jun 30 07:30:48 PM PDT 24 |
| Finished | Jun 30 07:39:49 PM PDT 24 |
| Peak memory | 607208 kb |
| Host | smart-de0dd7ab-33d6-4d91-b0ac-5d1ebba5df96 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85 7123280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.857123280 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.728157309 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 76365803772 ps |
| CPU time | 1336.26 seconds |
| Started | Jun 30 08:16:38 PM PDT 24 |
| Finished | Jun 30 08:38:55 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-e36477f4-a923-466d-a61d-b1f363a3af11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728157309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_d evice_slow_rsp.728157309 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.309208433 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 45060789396 ps |
| CPU time | 5593.66 seconds |
| Started | Jun 30 07:43:50 PM PDT 24 |
| Finished | Jun 30 09:17:04 PM PDT 24 |
| Peak memory | 618088 kb |
| Host | smart-ada216c6-21bf-46ca-8efe-ff1ddb783959 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309208433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_lc_walkthrough_rma.309208433 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.850041209 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 123413437478 ps |
| CPU time | 2179.03 seconds |
| Started | Jun 30 08:09:47 PM PDT 24 |
| Finished | Jun 30 08:46:07 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-0363566c-5a16-4f4d-b8e8-bad8d1a335b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850041209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_de vice_slow_rsp.850041209 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3789747234 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3031148339 ps |
| CPU time | 323.26 seconds |
| Started | Jun 30 07:32:44 PM PDT 24 |
| Finished | Jun 30 07:38:07 PM PDT 24 |
| Peak memory | 607176 kb |
| Host | smart-541a719d-dce3-4515-a058-124d28422834 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789 747234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.3789747234 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2237779102 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 15304403320 ps |
| CPU time | 4644.25 seconds |
| Started | Jun 30 07:46:00 PM PDT 24 |
| Finished | Jun 30 09:03:26 PM PDT 24 |
| Peak memory | 608648 kb |
| Host | smart-2ca5c22d-130f-4713-8f42-4f8de720686a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22377 79102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.2237779102 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.518793059 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 23782270720 ps |
| CPU time | 2210.91 seconds |
| Started | Jun 30 07:57:57 PM PDT 24 |
| Finished | Jun 30 08:34:49 PM PDT 24 |
| Peak memory | 608704 kb |
| Host | smart-e88e4ec2-f9a6-431d-a7b9-d01491b771eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 518793059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.518793059 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1076212065 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 2739901430 ps |
| CPU time | 297.77 seconds |
| Started | Jun 30 07:34:02 PM PDT 24 |
| Finished | Jun 30 07:39:00 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-50e18413-60ed-4c31-84fe-f13a0461cf42 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1076212065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.1076212065 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2012445217 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 16262890706 ps |
| CPU time | 3985.95 seconds |
| Started | Jun 30 07:41:08 PM PDT 24 |
| Finished | Jun 30 08:47:35 PM PDT 24 |
| Peak memory | 608088 kb |
| Host | smart-7eb39959-63c5-46f4-af7e-638913d56e7d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012445217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2012445217 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.2709439187 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3398228185 ps |
| CPU time | 213.49 seconds |
| Started | Jun 30 07:38:50 PM PDT 24 |
| Finished | Jun 30 07:42:24 PM PDT 24 |
| Peak memory | 606636 kb |
| Host | smart-4e6e2dee-a577-4378-b541-cecb694dad30 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709439187 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.2709439187 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.3365905178 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 147921253725 ps |
| CPU time | 2468.68 seconds |
| Started | Jun 30 08:28:37 PM PDT 24 |
| Finished | Jun 30 09:09:47 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-d379eb26-0ab7-4746-a540-7f8ffd05241c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365905178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_ device_slow_rsp.3365905178 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.2176045761 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 4964783330 ps |
| CPU time | 726.65 seconds |
| Started | Jun 30 07:57:12 PM PDT 24 |
| Finished | Jun 30 08:09:19 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-68fcc634-e1de-4d8e-b4a5-5d8f38565fda |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176045761 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.2176045761 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.3085759955 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 5346777288 ps |
| CPU time | 546.14 seconds |
| Started | Jun 30 08:10:23 PM PDT 24 |
| Finished | Jun 30 08:19:30 PM PDT 24 |
| Peak memory | 597652 kb |
| Host | smart-234c9b47-fdbd-41b5-ae03-9f0fe28103ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085759955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.3085759955 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3209672517 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 108378265195 ps |
| CPU time | 1919.37 seconds |
| Started | Jun 30 08:20:15 PM PDT 24 |
| Finished | Jun 30 08:52:16 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-0850f3f5-550a-4a0d-805f-c4d21e2c7620 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209672517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.3209672517 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.2014527663 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1163058013 ps |
| CPU time | 119.91 seconds |
| Started | Jun 30 08:22:56 PM PDT 24 |
| Finished | Jun 30 08:24:56 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-0e534393-4b60-4c9a-9136-c50879b5a797 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014527663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.2014527663 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2904822747 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4659885839 ps |
| CPU time | 675.36 seconds |
| Started | Jun 30 07:40:58 PM PDT 24 |
| Finished | Jun 30 07:52:14 PM PDT 24 |
| Peak memory | 624264 kb |
| Host | smart-9fafc224-6325-40cf-9552-7612bbe1a311 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904822747 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.2904822747 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.1928093997 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 31032004172 ps |
| CPU time | 3757.52 seconds |
| Started | Jun 30 08:13:37 PM PDT 24 |
| Finished | Jun 30 09:16:15 PM PDT 24 |
| Peak memory | 591872 kb |
| Host | smart-0326e08d-be2f-451c-92ee-ac1a077ece91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928093997 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.1928093997 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.375334518 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 7445809714 ps |
| CPU time | 1264.46 seconds |
| Started | Jun 30 07:55:03 PM PDT 24 |
| Finished | Jun 30 08:16:08 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-229e6a70-33cf-4868-b629-399d61573ff3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375334518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.375334518 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.1774175814 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 3390480400 ps |
| CPU time | 582.27 seconds |
| Started | Jun 30 07:46:59 PM PDT 24 |
| Finished | Jun 30 07:56:42 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-b8fa7f34-ecd1-4834-9953-6d48eabf5a41 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774175814 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.1774175814 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3561710566 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 23249204707 ps |
| CPU time | 421.53 seconds |
| Started | Jun 30 08:20:44 PM PDT 24 |
| Finished | Jun 30 08:27:46 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-33194ba7-1005-4982-8855-1479948ad654 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561710566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.3561710566 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1572135961 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 11550636680 ps |
| CPU time | 1191.23 seconds |
| Started | Jun 30 07:45:16 PM PDT 24 |
| Finished | Jun 30 08:05:08 PM PDT 24 |
| Peak memory | 608872 kb |
| Host | smart-ecc70a29-138d-4f02-ac73-c421238ff150 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572135961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.1572135961 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.3835779958 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 99373032623 ps |
| CPU time | 1118.72 seconds |
| Started | Jun 30 08:07:29 PM PDT 24 |
| Finished | Jun 30 08:26:08 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-9475b363-c861-4235-b8ed-e97ea297a52d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835779958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3835779958 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1538278579 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 42860356760 ps |
| CPU time | 5754.71 seconds |
| Started | Jun 30 07:30:54 PM PDT 24 |
| Finished | Jun 30 09:06:50 PM PDT 24 |
| Peak memory | 622764 kb |
| Host | smart-03fd50f7-90f1-46ad-8edd-a13d21d0bcf3 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1538278579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.1538278579 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.1070151465 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 20144325704 ps |
| CPU time | 2690.01 seconds |
| Started | Jun 30 07:25:47 PM PDT 24 |
| Finished | Jun 30 08:10:38 PM PDT 24 |
| Peak memory | 602016 kb |
| Host | smart-24f64481-db6c-4cfc-b4d9-ce5b264305f7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070151465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.1070151465 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1615141264 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 5254494893 ps |
| CPU time | 665.05 seconds |
| Started | Jun 30 07:29:05 PM PDT 24 |
| Finished | Jun 30 07:40:13 PM PDT 24 |
| Peak memory | 611112 kb |
| Host | smart-293dc70b-6d29-4b1b-b418-d6ad0d9b91a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615141264 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.1615141264 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1678041662 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 5453116808 ps |
| CPU time | 476.18 seconds |
| Started | Jun 30 07:31:40 PM PDT 24 |
| Finished | Jun 30 07:39:37 PM PDT 24 |
| Peak memory | 607640 kb |
| Host | smart-170632cc-60c7-4f4c-ae91-f4345cdbc2b4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16780416 62 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1678041662 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.4128530639 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 102669196931 ps |
| CPU time | 1721.86 seconds |
| Started | Jun 30 08:21:52 PM PDT 24 |
| Finished | Jun 30 08:50:35 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-689b16dd-edb1-4eed-be12-05b7dd0e7bbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128530639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.4128530639 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3446945893 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3188367195 ps |
| CPU time | 280.13 seconds |
| Started | Jun 30 07:39:39 PM PDT 24 |
| Finished | Jun 30 07:44:20 PM PDT 24 |
| Peak memory | 608288 kb |
| Host | smart-453f8414-6869-40ab-8b8c-1240fc2aef38 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446 945893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.3446945893 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.194521061 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 4768476067 ps |
| CPU time | 700.8 seconds |
| Started | Jun 30 07:47:48 PM PDT 24 |
| Finished | Jun 30 07:59:30 PM PDT 24 |
| Peak memory | 608096 kb |
| Host | smart-3860ee52-2790-4b27-a930-5bd372f9d157 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194521061 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.194521061 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.3958818583 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 9841553183 ps |
| CPU time | 434.9 seconds |
| Started | Jun 30 08:19:33 PM PDT 24 |
| Finished | Jun 30 08:26:48 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-1a7575b3-ff69-4870-a3f0-caa4750d261d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958818583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3958818583 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1554599485 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 58698494856 ps |
| CPU time | 10746.7 seconds |
| Started | Jun 30 07:39:54 PM PDT 24 |
| Finished | Jun 30 10:39:02 PM PDT 24 |
| Peak memory | 623428 kb |
| Host | smart-21a6fc7a-5756-48a9-a6c2-7174ca83ddca |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1554599485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.1554599485 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.387003795 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4549122604 ps |
| CPU time | 340.14 seconds |
| Started | Jun 30 07:49:59 PM PDT 24 |
| Finished | Jun 30 07:55:40 PM PDT 24 |
| Peak memory | 607192 kb |
| Host | smart-c16b7403-be6e-4f2a-8f16-ca88a8e5dfda |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387003795 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.387003795 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1079476446 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 4288944992 ps |
| CPU time | 532.06 seconds |
| Started | Jun 30 07:28:32 PM PDT 24 |
| Finished | Jun 30 07:37:24 PM PDT 24 |
| Peak memory | 608288 kb |
| Host | smart-be0efc2e-3293-4893-a709-ba519314f2ba |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1079476446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.1079476446 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.3576787504 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 4182292474 ps |
| CPU time | 375.3 seconds |
| Started | Jun 30 08:13:01 PM PDT 24 |
| Finished | Jun 30 08:19:17 PM PDT 24 |
| Peak memory | 603480 kb |
| Host | smart-4ebffdfe-6841-4bc6-b9f6-386914589a07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576787504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.3576787504 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.2781681440 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 4521609980 ps |
| CPU time | 1090.3 seconds |
| Started | Jun 30 07:45:08 PM PDT 24 |
| Finished | Jun 30 08:03:19 PM PDT 24 |
| Peak memory | 608136 kb |
| Host | smart-317afcb7-a967-4694-af08-957b34b23145 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781681440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.2781681440 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3846515489 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3458514081 ps |
| CPU time | 365.69 seconds |
| Started | Jun 30 07:49:50 PM PDT 24 |
| Finished | Jun 30 07:55:56 PM PDT 24 |
| Peak memory | 608276 kb |
| Host | smart-33f7f7f7-4d61-4563-8fb0-e1bed4a989c9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846 515489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.3846515489 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.2079227965 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 4962447340 ps |
| CPU time | 615.36 seconds |
| Started | Jun 30 08:10:08 PM PDT 24 |
| Finished | Jun 30 08:20:24 PM PDT 24 |
| Peak memory | 643424 kb |
| Host | smart-6ebb8232-6a2b-4032-8bf6-20066fe5b6af |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2079227965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.2079227965 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.3209603624 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 11723001242 ps |
| CPU time | 602.5 seconds |
| Started | Jun 30 08:20:07 PM PDT 24 |
| Finished | Jun 30 08:30:10 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-9fb5da3f-2e72-4efc-b734-b4dede56f76b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209603624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.3209603624 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.207988989 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 4331442308 ps |
| CPU time | 664.77 seconds |
| Started | Jun 30 08:03:39 PM PDT 24 |
| Finished | Jun 30 08:14:45 PM PDT 24 |
| Peak memory | 643652 kb |
| Host | smart-b619e5fd-3d6a-48f5-8d3e-ddbd82ce1427 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 207988989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.207988989 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1479010751 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 8504328750 ps |
| CPU time | 734.27 seconds |
| Started | Jun 30 08:00:26 PM PDT 24 |
| Finished | Jun 30 08:12:41 PM PDT 24 |
| Peak memory | 619020 kb |
| Host | smart-04d9c2f8-56b8-444a-8856-2f3c8220e033 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479010751 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.1479010751 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.1318077054 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1015626348 ps |
| CPU time | 45.68 seconds |
| Started | Jun 30 08:17:59 PM PDT 24 |
| Finished | Jun 30 08:19:07 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-a759c375-1402-4555-9876-c1f1ed240280 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318077054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.1318077054 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.196603904 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 7223612147 ps |
| CPU time | 1109.51 seconds |
| Started | Jun 30 07:46:22 PM PDT 24 |
| Finished | Jun 30 08:04:53 PM PDT 24 |
| Peak memory | 609116 kb |
| Host | smart-871bc6e6-58b2-4c21-a731-244bca2a12a7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196603904 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.196603904 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2653114767 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 3442041820 ps |
| CPU time | 460.87 seconds |
| Started | Jun 30 08:06:15 PM PDT 24 |
| Finished | Jun 30 08:13:56 PM PDT 24 |
| Peak memory | 647004 kb |
| Host | smart-b17fb111-8929-4816-a81e-15c846bbd0f0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653114767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2653114767 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.3464917451 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 6223527186 ps |
| CPU time | 858.4 seconds |
| Started | Jun 30 08:07:21 PM PDT 24 |
| Finished | Jun 30 08:21:40 PM PDT 24 |
| Peak memory | 643612 kb |
| Host | smart-4d045621-e66b-4193-863c-6a2e20bea20a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3464917451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.3464917451 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.4107267083 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 8864577574 ps |
| CPU time | 1868.87 seconds |
| Started | Jun 30 07:29:21 PM PDT 24 |
| Finished | Jun 30 08:00:31 PM PDT 24 |
| Peak memory | 617944 kb |
| Host | smart-2f829475-4e6b-4fdf-97ba-5b5760786cd4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107267083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.4107267083 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.2932321952 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 4486251200 ps |
| CPU time | 642.37 seconds |
| Started | Jun 30 08:04:00 PM PDT 24 |
| Finished | Jun 30 08:14:43 PM PDT 24 |
| Peak memory | 643364 kb |
| Host | smart-b30657fb-858e-43f8-a838-8e957b5285c5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2932321952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.2932321952 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.1947249769 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 4905051760 ps |
| CPU time | 546.04 seconds |
| Started | Jun 30 08:10:30 PM PDT 24 |
| Finished | Jun 30 08:19:36 PM PDT 24 |
| Peak memory | 644072 kb |
| Host | smart-2cb77b7b-4fe0-4fab-88ff-bedfcc9db9d9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1947249769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.1947249769 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3936065740 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 4407299602 ps |
| CPU time | 298.5 seconds |
| Started | Jun 30 08:08:40 PM PDT 24 |
| Finished | Jun 30 08:13:39 PM PDT 24 |
| Peak memory | 658900 kb |
| Host | smart-c6f52393-f14b-4c10-9712-308595d718e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936065740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.3936065740 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.658669603 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 4610001374 ps |
| CPU time | 878.81 seconds |
| Started | Jun 30 08:02:06 PM PDT 24 |
| Finished | Jun 30 08:16:45 PM PDT 24 |
| Peak memory | 608472 kb |
| Host | smart-6095ffbd-2b6c-4fe4-ac63-9e8a584b09ec |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=658669603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.658669603 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.3177911471 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 6763550272 ps |
| CPU time | 591.87 seconds |
| Started | Jun 30 07:33:15 PM PDT 24 |
| Finished | Jun 30 07:43:07 PM PDT 24 |
| Peak memory | 619608 kb |
| Host | smart-abcd4b7c-166c-403c-9b20-f836b095b938 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177911471 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.3177911471 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1743262258 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 8281743546 ps |
| CPU time | 916.02 seconds |
| Started | Jun 30 07:33:47 PM PDT 24 |
| Finished | Jun 30 07:49:04 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-dc2a4de5-9fae-42dd-91dd-666e429f09ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17432622 58 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.1743262258 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.1848722426 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 8411775416 ps |
| CPU time | 451.23 seconds |
| Started | Jun 30 08:15:28 PM PDT 24 |
| Finished | Jun 30 08:23:00 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-a2b7ee2b-fc8d-4cad-ae4e-58f89d78369b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848722426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.1848722426 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.338240217 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 5497627256 ps |
| CPU time | 1127.31 seconds |
| Started | Jun 30 07:32:06 PM PDT 24 |
| Finished | Jun 30 07:50:53 PM PDT 24 |
| Peak memory | 607140 kb |
| Host | smart-0d3d6234-7cd7-4aab-b62b-c3165d1508ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338240217 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_plic_all_irqs_0.338240217 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.2336654143 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 5097133061 ps |
| CPU time | 529.63 seconds |
| Started | Jun 30 08:12:31 PM PDT 24 |
| Finished | Jun 30 08:21:21 PM PDT 24 |
| Peak memory | 603556 kb |
| Host | smart-19e1d397-8492-49bf-94e7-48a414bb1aa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336654143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.2336654143 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1358396480 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5643463596 ps |
| CPU time | 445.37 seconds |
| Started | Jun 30 07:39:42 PM PDT 24 |
| Finished | Jun 30 07:47:08 PM PDT 24 |
| Peak memory | 608608 kb |
| Host | smart-bf1dbdd9-dbd6-4e69-b4d4-c6a2e6e66ef5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358396480 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.1358396480 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3108266823 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3354189767 ps |
| CPU time | 157.33 seconds |
| Started | Jun 30 07:51:14 PM PDT 24 |
| Finished | Jun 30 07:53:52 PM PDT 24 |
| Peak memory | 617648 kb |
| Host | smart-50a441cf-44a8-43f9-9759-da1adcb65dd9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31082668 23 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.3108266823 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.4191456335 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2575495810 ps |
| CPU time | 230.46 seconds |
| Started | Jun 30 07:33:19 PM PDT 24 |
| Finished | Jun 30 07:37:11 PM PDT 24 |
| Peak memory | 608152 kb |
| Host | smart-afa0bd96-1190-47cb-a154-f745d7727ad6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191456335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.4191456335 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.705601476 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 78392665044 ps |
| CPU time | 15036.7 seconds |
| Started | Jun 30 07:52:29 PM PDT 24 |
| Finished | Jul 01 12:03:08 AM PDT 24 |
| Peak memory | 633440 kb |
| Host | smart-836b608e-f052-45fe-a3fe-a5d3e83bb821 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=705601476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.705601476 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.1981321632 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 677124111 ps |
| CPU time | 81.34 seconds |
| Started | Jun 30 08:12:01 PM PDT 24 |
| Finished | Jun 30 08:13:22 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-5bd6543d-4f0b-41db-af99-76b1be7afd4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981321632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .1981321632 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1930553388 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 49847468364 ps |
| CPU time | 5788.04 seconds |
| Started | Jun 30 07:51:57 PM PDT 24 |
| Finished | Jun 30 09:28:26 PM PDT 24 |
| Peak memory | 617360 kb |
| Host | smart-591a623a-faa6-40f6-9992-3b3d86dd0fbf |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930553388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.1930553388 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2935282687 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 31671859432 ps |
| CPU time | 7605.41 seconds |
| Started | Jun 30 07:27:53 PM PDT 24 |
| Finished | Jun 30 09:34:40 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-5ceb290a-f2d8-4776-9367-1a376907b471 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2935282687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.2935282687 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.262965295 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 6166811536 ps |
| CPU time | 498.11 seconds |
| Started | Jun 30 08:16:58 PM PDT 24 |
| Finished | Jun 30 08:25:17 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-3a125eda-ed8f-438c-b6f2-e0c69d98df91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262965295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_ with_rand_reset.262965295 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.4010092810 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 4803016004 ps |
| CPU time | 1067.64 seconds |
| Started | Jun 30 07:31:47 PM PDT 24 |
| Finished | Jun 30 07:49:35 PM PDT 24 |
| Peak memory | 609100 kb |
| Host | smart-5edc2e17-87da-4730-975d-ac234e39df99 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010092810 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.4010092810 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.949393141 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 6252931040 ps |
| CPU time | 1355.1 seconds |
| Started | Jun 30 07:57:47 PM PDT 24 |
| Finished | Jun 30 08:20:23 PM PDT 24 |
| Peak memory | 607316 kb |
| Host | smart-1d31d46c-377d-4f05-8b86-58258a129afc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949393141 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_plic_all_irqs_0.949393141 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.775927797 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 5745509506 ps |
| CPU time | 339.62 seconds |
| Started | Jun 30 08:24:22 PM PDT 24 |
| Finished | Jun 30 08:30:02 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-fccdb6a7-9c36-4264-ba1b-0584b66499c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775927797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_reset_error.775927797 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1206319748 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 13060340776 ps |
| CPU time | 2642.72 seconds |
| Started | Jun 30 08:00:00 PM PDT 24 |
| Finished | Jun 30 08:44:04 PM PDT 24 |
| Peak memory | 617628 kb |
| Host | smart-a7596773-f985-4f6e-aa50-009672d34d16 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206319748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.1206319748 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1507760446 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6613041720 ps |
| CPU time | 881.44 seconds |
| Started | Jun 30 07:56:44 PM PDT 24 |
| Finished | Jun 30 08:11:26 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-fe62106a-7165-44ec-af69-10c73e9f0cf3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15077604 46 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.1507760446 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.2367512616 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 3865557180 ps |
| CPU time | 339.88 seconds |
| Started | Jun 30 08:05:08 PM PDT 24 |
| Finished | Jun 30 08:10:48 PM PDT 24 |
| Peak memory | 603548 kb |
| Host | smart-f5ae384e-a503-4eed-9add-909e58625d80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367512616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.2367512616 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3424240336 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 20294335952 ps |
| CPU time | 3787.1 seconds |
| Started | Jun 30 07:53:04 PM PDT 24 |
| Finished | Jun 30 08:56:12 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-d7c72dc8-25df-4b50-bb9d-e324fe78ab02 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424240336 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.3424240336 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.301984590 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1857025040 ps |
| CPU time | 147.73 seconds |
| Started | Jun 30 08:15:47 PM PDT 24 |
| Finished | Jun 30 08:18:15 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-2372908a-1528-4e13-bdae-3090715cf07b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301984590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.301984590 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.2999986028 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 6084298432 ps |
| CPU time | 465.2 seconds |
| Started | Jun 30 08:07:10 PM PDT 24 |
| Finished | Jun 30 08:14:56 PM PDT 24 |
| Peak memory | 657928 kb |
| Host | smart-a6b49ce1-2169-4e8b-bbf3-fb57beef9294 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999986028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.2999986028 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.223181264 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 12219029780 ps |
| CPU time | 1668.66 seconds |
| Started | Jun 30 07:39:38 PM PDT 24 |
| Finished | Jun 30 08:07:27 PM PDT 24 |
| Peak memory | 599204 kb |
| Host | smart-5b46de93-095d-47bb-a082-05b16ae2aa3f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223181264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_jtag_csr_rw.223181264 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.3507206664 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1122646716 ps |
| CPU time | 95.54 seconds |
| Started | Jun 30 08:18:43 PM PDT 24 |
| Finished | Jun 30 08:20:20 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-d8008910-11c0-4fd1-82fb-503d7418abd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507206664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .3507206664 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.3838776861 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 4326416290 ps |
| CPU time | 566.92 seconds |
| Started | Jun 30 07:31:28 PM PDT 24 |
| Finished | Jun 30 07:40:55 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-8facbe41-517c-4ed9-ba9b-1b1032ce6af3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838776861 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.3838776861 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.453523797 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 44414353332 ps |
| CPU time | 5320.76 seconds |
| Started | Jun 30 07:41:08 PM PDT 24 |
| Finished | Jun 30 09:09:50 PM PDT 24 |
| Peak memory | 623528 kb |
| Host | smart-b5ca91de-18b8-4bbd-b1b7-b46eb9e7d950 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=453523797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.453523797 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.971718726 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 3034598059 ps |
| CPU time | 267.9 seconds |
| Started | Jun 30 07:41:42 PM PDT 24 |
| Finished | Jun 30 07:46:10 PM PDT 24 |
| Peak memory | 616108 kb |
| Host | smart-efa9da53-4760-463d-bc20-1ff8f4d726ed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971718726 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.971718726 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1821414475 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 30804191004 ps |
| CPU time | 3757.47 seconds |
| Started | Jun 30 08:13:04 PM PDT 24 |
| Finished | Jun 30 09:15:42 PM PDT 24 |
| Peak memory | 592252 kb |
| Host | smart-dfceae1d-e5ae-42a4-a1c3-82e96e8c0edd |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821414475 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.1821414475 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1378424562 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4640112280 ps |
| CPU time | 416.84 seconds |
| Started | Jun 30 07:33:28 PM PDT 24 |
| Finished | Jun 30 07:40:26 PM PDT 24 |
| Peak memory | 617740 kb |
| Host | smart-be153ea3-0d89-410c-91a2-d7e9d34f292a |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 378424562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.1378424562 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.2118347535 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 1431256164 ps |
| CPU time | 247.97 seconds |
| Started | Jun 30 08:15:58 PM PDT 24 |
| Finished | Jun 30 08:20:06 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-ba54335f-de6a-4df7-8121-a82e00121dd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118347535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.2118347535 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2238211594 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 789477233 ps |
| CPU time | 350.58 seconds |
| Started | Jun 30 08:22:46 PM PDT 24 |
| Finished | Jun 30 08:28:38 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-61e0c07f-f3f3-4568-bca2-fded665d7008 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238211594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.2238211594 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2780150360 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 4643277832 ps |
| CPU time | 666.66 seconds |
| Started | Jun 30 08:02:21 PM PDT 24 |
| Finished | Jun 30 08:13:28 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-ee796aa2-300b-452b-a905-84746ca44ab5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27801503 60 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.2780150360 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.2621225822 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 3551652760 ps |
| CPU time | 279.71 seconds |
| Started | Jun 30 08:13:18 PM PDT 24 |
| Finished | Jun 30 08:17:58 PM PDT 24 |
| Peak memory | 597452 kb |
| Host | smart-7b24fd62-849a-4aa9-9984-0cd8298da8d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621225822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.2621225822 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3805354577 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 4783626635 ps |
| CPU time | 278.96 seconds |
| Started | Jun 30 08:30:13 PM PDT 24 |
| Finished | Jun 30 08:34:53 PM PDT 24 |
| Peak memory | 648512 kb |
| Host | smart-d644bfe4-6025-45bf-b0aa-5e47be1d0c16 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805354577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.3805354577 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.1142344153 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 4338043504 ps |
| CPU time | 742.25 seconds |
| Started | Jun 30 07:46:39 PM PDT 24 |
| Finished | Jun 30 07:59:02 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-8843974f-fd80-4188-9aa4-e2db2dbb54ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142344153 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.1142344153 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.400966882 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 1542312841 ps |
| CPU time | 284.72 seconds |
| Started | Jun 30 08:16:44 PM PDT 24 |
| Finished | Jun 30 08:21:29 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-ddb13d25-63a1-4ba6-8cdc-25d7e1c2faee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400966882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_reset_error.400966882 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2632154778 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 262702720 ps |
| CPU time | 160.68 seconds |
| Started | Jun 30 08:21:28 PM PDT 24 |
| Finished | Jun 30 08:24:09 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-65dd6fc8-186a-4661-a455-cd93e7767066 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632154778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.2632154778 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2610783188 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 34246354505 ps |
| CPU time | 4072.06 seconds |
| Started | Jun 30 07:28:46 PM PDT 24 |
| Finished | Jun 30 08:36:40 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-0cb44a8a-a1c0-4d3a-a832-d03fd836b80f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610783188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2610783188 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2686379142 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 18689275088 ps |
| CPU time | 608.16 seconds |
| Started | Jun 30 07:28:37 PM PDT 24 |
| Finished | Jun 30 07:38:46 PM PDT 24 |
| Peak memory | 617440 kb |
| Host | smart-11dae3ec-c476-4900-bbfc-a7353cb11544 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2686379142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2686379142 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.2472592417 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3938860920 ps |
| CPU time | 632.38 seconds |
| Started | Jun 30 07:41:07 PM PDT 24 |
| Finished | Jun 30 07:51:40 PM PDT 24 |
| Peak memory | 615868 kb |
| Host | smart-eb895d94-e22e-4931-903f-4e5331fd9398 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472592417 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.2472592417 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.1151001688 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4514152188 ps |
| CPU time | 513.57 seconds |
| Started | Jun 30 07:29:29 PM PDT 24 |
| Finished | Jun 30 07:38:03 PM PDT 24 |
| Peak memory | 606572 kb |
| Host | smart-f505a69f-f8f5-44f0-828f-861b602ff90f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151001688 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.1151001688 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2339164126 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 3609106970 ps |
| CPU time | 564.82 seconds |
| Started | Jun 30 07:33:09 PM PDT 24 |
| Finished | Jun 30 07:42:35 PM PDT 24 |
| Peak memory | 610892 kb |
| Host | smart-0b16a31d-330b-4c72-bec8-8c1cc14b0b9d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339164126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2339164126 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3381821948 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 42886859078 ps |
| CPU time | 5959.69 seconds |
| Started | Jun 30 07:50:33 PM PDT 24 |
| Finished | Jun 30 09:29:54 PM PDT 24 |
| Peak memory | 623096 kb |
| Host | smart-4b25f5c6-4d00-45d2-9a1b-cd74ce4c4563 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3381821948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.3381821948 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2607934202 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 2040056510 ps |
| CPU time | 333.79 seconds |
| Started | Jun 30 08:20:11 PM PDT 24 |
| Finished | Jun 30 08:25:45 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-f52bc378-d867-4d8b-90db-b515a44623c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607934202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.2607934202 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.2024167893 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 3457424945 ps |
| CPU time | 310.29 seconds |
| Started | Jun 30 08:16:55 PM PDT 24 |
| Finished | Jun 30 08:22:06 PM PDT 24 |
| Peak memory | 597312 kb |
| Host | smart-5a350117-b5c8-4ae9-9d14-956cc6658461 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024167893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.2024167893 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.3766359871 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 24604628895 ps |
| CPU time | 1134.27 seconds |
| Started | Jun 30 08:27:34 PM PDT 24 |
| Finished | Jun 30 08:46:29 PM PDT 24 |
| Peak memory | 576436 kb |
| Host | smart-5236052b-fa95-41c7-b869-4fb7c0197f27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766359871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.3766359871 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1684801070 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 3979438694 ps |
| CPU time | 589.95 seconds |
| Started | Jun 30 07:41:23 PM PDT 24 |
| Finished | Jun 30 07:51:14 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-0fc874de-5c46-45d8-a7f7-3287b6a0a95d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1684801070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.1684801070 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.2139643807 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 8012503037 ps |
| CPU time | 404.02 seconds |
| Started | Jun 30 08:18:00 PM PDT 24 |
| Finished | Jun 30 08:25:06 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-1a20016e-f75c-45bd-abe7-968c8d189557 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139643807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.2139643807 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3926557533 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 316270127 ps |
| CPU time | 137.44 seconds |
| Started | Jun 30 08:24:47 PM PDT 24 |
| Finished | Jun 30 08:27:05 PM PDT 24 |
| Peak memory | 576352 kb |
| Host | smart-fa3f3dc6-2b45-41e0-94a5-b33bb52ac32e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926557533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.3926557533 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2931996370 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 13056140070 ps |
| CPU time | 2633.46 seconds |
| Started | Jun 30 07:55:41 PM PDT 24 |
| Finished | Jun 30 08:39:35 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-74771571-9a83-49df-a740-05c1bb088c6c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29319 96370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.2931996370 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3104657027 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 3297512824 ps |
| CPU time | 441.32 seconds |
| Started | Jun 30 07:27:22 PM PDT 24 |
| Finished | Jun 30 07:34:44 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-c8e0fced-1c16-4c0b-9f09-6a49d0e994c7 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310465 7027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3104657027 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.3373134785 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 3276486255 ps |
| CPU time | 277.2 seconds |
| Started | Jun 30 08:15:14 PM PDT 24 |
| Finished | Jun 30 08:19:52 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-93194977-1d6b-4a68-abe8-5ae01f892c1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373134785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3373134785 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.572058749 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4064587215 ps |
| CPU time | 486.32 seconds |
| Started | Jun 30 07:51:07 PM PDT 24 |
| Finished | Jun 30 07:59:14 PM PDT 24 |
| Peak memory | 607092 kb |
| Host | smart-7b4cc296-1e8c-464f-9ae0-631dcd3e2424 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572058749 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.chip_sw_gpio.572058749 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.299392406 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 47691029857 ps |
| CPU time | 5457.21 seconds |
| Started | Jun 30 07:42:30 PM PDT 24 |
| Finished | Jun 30 09:13:28 PM PDT 24 |
| Peak memory | 614988 kb |
| Host | smart-cf33fffb-82cf-4778-aa87-483a4ff174c8 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299392406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_prod.299392406 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.2942203789 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 4451880082 ps |
| CPU time | 617.94 seconds |
| Started | Jun 30 07:36:25 PM PDT 24 |
| Finished | Jun 30 07:46:43 PM PDT 24 |
| Peak memory | 607900 kb |
| Host | smart-e2882f67-d74f-48ac-b532-f06282a299f6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942203789 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.2942203789 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1807046216 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 6112850736 ps |
| CPU time | 390.57 seconds |
| Started | Jun 30 07:51:26 PM PDT 24 |
| Finished | Jun 30 07:57:57 PM PDT 24 |
| Peak memory | 608160 kb |
| Host | smart-13bf83cb-c394-4409-b771-75f863edcf33 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807046216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.1807046216 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.3586389243 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 4057041233 ps |
| CPU time | 364.47 seconds |
| Started | Jun 30 08:14:20 PM PDT 24 |
| Finished | Jun 30 08:20:25 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-749ab67d-38de-4061-ae33-316b920a290d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586389243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.3586389243 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1852261359 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 63372393432 ps |
| CPU time | 10728.1 seconds |
| Started | Jun 30 07:35:34 PM PDT 24 |
| Finished | Jun 30 10:34:23 PM PDT 24 |
| Peak memory | 609236 kb |
| Host | smart-35ec7108-7fc4-456d-8b4d-e65d419d1c4d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1852261359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.1852261359 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.2347808915 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9029973768 ps |
| CPU time | 1219.28 seconds |
| Started | Jun 30 07:50:06 PM PDT 24 |
| Finished | Jun 30 08:10:26 PM PDT 24 |
| Peak memory | 601812 kb |
| Host | smart-2e97295b-f43b-4216-b214-4cb893ea4d70 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347808915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.2347808915 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.3233792994 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 6474971792 ps |
| CPU time | 778.83 seconds |
| Started | Jun 30 07:31:39 PM PDT 24 |
| Finished | Jun 30 07:44:39 PM PDT 24 |
| Peak memory | 647920 kb |
| Host | smart-9cd97a45-7831-4da6-a5c5-ba6ae356ebac |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3233792994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.3233792994 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.873248822 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 2422129172 ps |
| CPU time | 306.46 seconds |
| Started | Jun 30 07:51:06 PM PDT 24 |
| Finished | Jun 30 07:56:13 PM PDT 24 |
| Peak memory | 616448 kb |
| Host | smart-b01fdc47-a539-45a9-b2f4-436d77e014f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873248822 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.873248822 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.2238035204 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 5832110190 ps |
| CPU time | 562.52 seconds |
| Started | Jun 30 08:05:33 PM PDT 24 |
| Finished | Jun 30 08:14:56 PM PDT 24 |
| Peak memory | 648068 kb |
| Host | smart-5cad1727-3c2a-4047-8d50-d643dba9016e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2238035204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.2238035204 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.863810998 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 3227957567 ps |
| CPU time | 280.54 seconds |
| Started | Jun 30 08:19:54 PM PDT 24 |
| Finished | Jun 30 08:24:35 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-f2778b9a-c710-47b3-8040-f2fa6c42a606 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863810998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.863810998 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3884416358 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 3013254642 ps |
| CPU time | 484.23 seconds |
| Started | Jun 30 08:30:00 PM PDT 24 |
| Finished | Jun 30 08:38:05 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-61231316-b099-477b-9694-a5a26e352bef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884416358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.3884416358 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.3644731517 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4217147412 ps |
| CPU time | 644.45 seconds |
| Started | Jun 30 07:42:07 PM PDT 24 |
| Finished | Jun 30 07:52:51 PM PDT 24 |
| Peak memory | 607140 kb |
| Host | smart-1557b663-4336-4dcb-a8f4-06456f4b7186 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644731517 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.3644731517 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3929648020 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 5113213276 ps |
| CPU time | 596.61 seconds |
| Started | Jun 30 07:58:29 PM PDT 24 |
| Finished | Jun 30 08:08:26 PM PDT 24 |
| Peak memory | 609140 kb |
| Host | smart-f8ac3e6a-5ef4-4dd9-b8ed-534d3bb50a90 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3929648020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3929648020 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.3973534431 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 5508837266 ps |
| CPU time | 715.12 seconds |
| Started | Jun 30 08:03:34 PM PDT 24 |
| Finished | Jun 30 08:15:29 PM PDT 24 |
| Peak memory | 643252 kb |
| Host | smart-e1d7f716-e3bb-4f9c-87cc-9228f45dc71e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3973534431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.3973534431 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2560507834 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 14511686916 ps |
| CPU time | 4670.94 seconds |
| Started | Jun 30 07:39:46 PM PDT 24 |
| Finished | Jun 30 08:57:38 PM PDT 24 |
| Peak memory | 607976 kb |
| Host | smart-9282884e-0d91-41c9-b421-40a80ef23f0f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560507834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.2560507834 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2904564960 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 3505414574 ps |
| CPU time | 385.11 seconds |
| Started | Jun 30 07:29:44 PM PDT 24 |
| Finished | Jun 30 07:36:10 PM PDT 24 |
| Peak memory | 642212 kb |
| Host | smart-9e256b1d-013f-43f7-82ab-e741fdce9070 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904564960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.2904564960 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.856872546 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3518864240 ps |
| CPU time | 387.45 seconds |
| Started | Jun 30 07:44:11 PM PDT 24 |
| Finished | Jun 30 07:50:39 PM PDT 24 |
| Peak memory | 647048 kb |
| Host | smart-7b45a735-5deb-463c-9fd4-0f47c6e5056d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856872546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _alert_handler_lpg_sleep_mode_alerts.856872546 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.203813814 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 6042410080 ps |
| CPU time | 695.97 seconds |
| Started | Jun 30 07:41:18 PM PDT 24 |
| Finished | Jun 30 07:52:54 PM PDT 24 |
| Peak memory | 643312 kb |
| Host | smart-2d6d38d4-ca1a-444e-be30-1520b2a3aa38 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 203813814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.203813814 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.4026304804 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3253076308 ps |
| CPU time | 429.52 seconds |
| Started | Jun 30 08:02:22 PM PDT 24 |
| Finished | Jun 30 08:09:32 PM PDT 24 |
| Peak memory | 642512 kb |
| Host | smart-07a7a042-155f-4890-895f-2afb0d8420dc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026304804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4026304804 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.577174835 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 4503631720 ps |
| CPU time | 632.91 seconds |
| Started | Jun 30 08:03:30 PM PDT 24 |
| Finished | Jun 30 08:14:03 PM PDT 24 |
| Peak memory | 648224 kb |
| Host | smart-e876b7c9-ebae-4ed5-9df4-b06bd31c63c8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 577174835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.577174835 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3316464078 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 4378531976 ps |
| CPU time | 441.52 seconds |
| Started | Jun 30 08:04:08 PM PDT 24 |
| Finished | Jun 30 08:11:30 PM PDT 24 |
| Peak memory | 647340 kb |
| Host | smart-f5478cc7-3852-4b84-9811-f542a71faf6e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316464078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3316464078 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.3772573395 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 5791746064 ps |
| CPU time | 675.64 seconds |
| Started | Jun 30 08:02:55 PM PDT 24 |
| Finished | Jun 30 08:14:11 PM PDT 24 |
| Peak memory | 647864 kb |
| Host | smart-1c298ffb-d41d-440f-95e1-176a6a9c0016 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3772573395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.3772573395 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2215924474 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 4106324528 ps |
| CPU time | 420.14 seconds |
| Started | Jun 30 08:04:25 PM PDT 24 |
| Finished | Jun 30 08:11:26 PM PDT 24 |
| Peak memory | 646968 kb |
| Host | smart-eb953551-885c-4016-9c30-66daac19c164 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215924474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2215924474 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.4078158044 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 5964912074 ps |
| CPU time | 717.45 seconds |
| Started | Jun 30 08:02:43 PM PDT 24 |
| Finished | Jun 30 08:14:41 PM PDT 24 |
| Peak memory | 647896 kb |
| Host | smart-1d281a67-0bee-4d38-883c-d9d3dcd11fcd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4078158044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.4078158044 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2848302408 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3987234168 ps |
| CPU time | 418.51 seconds |
| Started | Jun 30 08:03:16 PM PDT 24 |
| Finished | Jun 30 08:10:15 PM PDT 24 |
| Peak memory | 647204 kb |
| Host | smart-a14a021e-c736-4ff9-a484-8334eaa4b66a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848302408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2848302408 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1634079063 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3703882330 ps |
| CPU time | 441.87 seconds |
| Started | Jun 30 08:05:05 PM PDT 24 |
| Finished | Jun 30 08:12:27 PM PDT 24 |
| Peak memory | 642244 kb |
| Host | smart-c4883c79-0ea2-458d-ab6a-cdd213afd38e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634079063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1634079063 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.3890638269 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 5504974248 ps |
| CPU time | 850.91 seconds |
| Started | Jun 30 08:02:24 PM PDT 24 |
| Finished | Jun 30 08:16:36 PM PDT 24 |
| Peak memory | 643404 kb |
| Host | smart-d4fd282b-ecef-4580-be5d-a8433769d698 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3890638269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.3890638269 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3334428684 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 3562289744 ps |
| CPU time | 426.71 seconds |
| Started | Jun 30 08:03:10 PM PDT 24 |
| Finished | Jun 30 08:10:18 PM PDT 24 |
| Peak memory | 646972 kb |
| Host | smart-4762ac2d-950f-4846-9c59-356036a15361 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334428684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3334428684 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.1804093688 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 5770289164 ps |
| CPU time | 723.36 seconds |
| Started | Jun 30 08:04:25 PM PDT 24 |
| Finished | Jun 30 08:16:29 PM PDT 24 |
| Peak memory | 643532 kb |
| Host | smart-5a266efd-89cd-461a-b245-2ce5cd0f5511 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1804093688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.1804093688 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3413650997 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 2949208346 ps |
| CPU time | 434.51 seconds |
| Started | Jun 30 08:06:35 PM PDT 24 |
| Finished | Jun 30 08:13:50 PM PDT 24 |
| Peak memory | 642208 kb |
| Host | smart-aa8e0f6e-4323-458b-8292-17c4080de09e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413650997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3413650997 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.3041659165 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4455394382 ps |
| CPU time | 744.61 seconds |
| Started | Jun 30 08:07:10 PM PDT 24 |
| Finished | Jun 30 08:19:36 PM PDT 24 |
| Peak memory | 643388 kb |
| Host | smart-56bc0dae-c871-4d65-a216-3aceea6c1a12 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3041659165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.3041659165 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1008405725 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 3993247350 ps |
| CPU time | 333.42 seconds |
| Started | Jun 30 08:03:54 PM PDT 24 |
| Finished | Jun 30 08:09:28 PM PDT 24 |
| Peak memory | 647092 kb |
| Host | smart-6e6b9e6c-269f-488e-9824-dcce94c85251 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008405725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1008405725 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.1426855432 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 5004305480 ps |
| CPU time | 798.06 seconds |
| Started | Jun 30 08:04:30 PM PDT 24 |
| Finished | Jun 30 08:17:48 PM PDT 24 |
| Peak memory | 643464 kb |
| Host | smart-a95192fb-858e-4e9e-9471-1d82db4c1b60 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1426855432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.1426855432 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.1271612727 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 4541402110 ps |
| CPU time | 595.39 seconds |
| Started | Jun 30 08:07:14 PM PDT 24 |
| Finished | Jun 30 08:17:10 PM PDT 24 |
| Peak memory | 643328 kb |
| Host | smart-bca25193-1715-4d55-be3b-3c1e08d7e3b1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1271612727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.1271612727 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.717811091 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 5414189320 ps |
| CPU time | 569.52 seconds |
| Started | Jun 30 08:03:53 PM PDT 24 |
| Finished | Jun 30 08:13:23 PM PDT 24 |
| Peak memory | 647824 kb |
| Host | smart-eab4edf0-d5ac-4197-a129-5ac8e00ff810 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 717811091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.717811091 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.665742241 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 3829326176 ps |
| CPU time | 366.36 seconds |
| Started | Jun 30 08:04:56 PM PDT 24 |
| Finished | Jun 30 08:11:03 PM PDT 24 |
| Peak memory | 647028 kb |
| Host | smart-a0b6f429-5ecd-4fe6-a857-775d39cb404b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665742241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_s w_alert_handler_lpg_sleep_mode_alerts.665742241 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1478243465 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 3981495472 ps |
| CPU time | 352.81 seconds |
| Started | Jun 30 08:03:50 PM PDT 24 |
| Finished | Jun 30 08:09:43 PM PDT 24 |
| Peak memory | 647028 kb |
| Host | smart-dcd7d8c4-8990-4a14-8a61-8cad1d8581c6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478243465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1478243465 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115619205 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 4127088928 ps |
| CPU time | 467.43 seconds |
| Started | Jun 30 08:06:40 PM PDT 24 |
| Finished | Jun 30 08:14:28 PM PDT 24 |
| Peak memory | 647092 kb |
| Host | smart-6e953f69-9882-4b1d-b41e-22ed11cf7ce9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115619205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1115619205 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.964409436 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 5116207480 ps |
| CPU time | 749.96 seconds |
| Started | Jun 30 08:04:28 PM PDT 24 |
| Finished | Jun 30 08:16:58 PM PDT 24 |
| Peak memory | 643252 kb |
| Host | smart-47741846-190b-4709-8104-d56754ef8eae |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 964409436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.964409436 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.138885689 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 3917788206 ps |
| CPU time | 319.77 seconds |
| Started | Jun 30 08:06:05 PM PDT 24 |
| Finished | Jun 30 08:11:25 PM PDT 24 |
| Peak memory | 647160 kb |
| Host | smart-0502e074-02da-4d2f-9544-e041c931f15f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138885689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_s w_alert_handler_lpg_sleep_mode_alerts.138885689 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.332608610 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 5400662400 ps |
| CPU time | 780.43 seconds |
| Started | Jun 30 08:04:29 PM PDT 24 |
| Finished | Jun 30 08:17:30 PM PDT 24 |
| Peak memory | 643444 kb |
| Host | smart-4015c1de-396e-4f8f-8b68-cd757adc8559 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 332608610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.332608610 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.662434031 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3691218854 ps |
| CPU time | 462.2 seconds |
| Started | Jun 30 08:05:02 PM PDT 24 |
| Finished | Jun 30 08:12:45 PM PDT 24 |
| Peak memory | 646920 kb |
| Host | smart-80baeef9-4f5a-4092-a25a-0d73904ce57d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662434031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_s w_alert_handler_lpg_sleep_mode_alerts.662434031 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.3837788354 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 5846109724 ps |
| CPU time | 899.23 seconds |
| Started | Jun 30 08:03:44 PM PDT 24 |
| Finished | Jun 30 08:18:44 PM PDT 24 |
| Peak memory | 643436 kb |
| Host | smart-606fb410-5012-4233-84eb-1602d333890b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3837788354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.3837788354 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2892867391 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 4178713796 ps |
| CPU time | 432.12 seconds |
| Started | Jun 30 08:00:55 PM PDT 24 |
| Finished | Jun 30 08:08:08 PM PDT 24 |
| Peak memory | 647288 kb |
| Host | smart-d187793e-56c6-49ee-bf57-1946fda7c479 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892867391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.2892867391 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.341417336 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 4339123180 ps |
| CPU time | 495.67 seconds |
| Started | Jun 30 08:04:40 PM PDT 24 |
| Finished | Jun 30 08:12:56 PM PDT 24 |
| Peak memory | 647288 kb |
| Host | smart-3f5bc965-1e17-4bc9-bbe8-83c05a74beb2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341417336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_s w_alert_handler_lpg_sleep_mode_alerts.341417336 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2763815349 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 3745775344 ps |
| CPU time | 412.66 seconds |
| Started | Jun 30 08:04:41 PM PDT 24 |
| Finished | Jun 30 08:11:34 PM PDT 24 |
| Peak memory | 646908 kb |
| Host | smart-ce0215f6-0ded-44c0-8dc8-d30865ba9e36 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763815349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2763815349 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.3609245902 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 5309650244 ps |
| CPU time | 610.71 seconds |
| Started | Jun 30 08:04:20 PM PDT 24 |
| Finished | Jun 30 08:14:31 PM PDT 24 |
| Peak memory | 643796 kb |
| Host | smart-2fb9914a-b6af-494e-9b8f-730743b9a93d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3609245902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.3609245902 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2896792846 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 3637092580 ps |
| CPU time | 484.98 seconds |
| Started | Jun 30 08:04:30 PM PDT 24 |
| Finished | Jun 30 08:12:35 PM PDT 24 |
| Peak memory | 642392 kb |
| Host | smart-0b8f953c-bb08-4507-9dec-a27321601df5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896792846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2896792846 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.851098613 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 5555841112 ps |
| CPU time | 873.09 seconds |
| Started | Jun 30 08:04:15 PM PDT 24 |
| Finished | Jun 30 08:18:49 PM PDT 24 |
| Peak memory | 643272 kb |
| Host | smart-f7d93fb0-78c2-4733-bbc7-ea86fcd39881 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 851098613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.851098613 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.1297591275 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 5609898430 ps |
| CPU time | 599.52 seconds |
| Started | Jun 30 08:05:01 PM PDT 24 |
| Finished | Jun 30 08:15:02 PM PDT 24 |
| Peak memory | 643708 kb |
| Host | smart-c6fa02d5-004f-4bb8-aed4-42c82e35a5a1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1297591275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.1297591275 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.3542474445 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 4835035160 ps |
| CPU time | 558.2 seconds |
| Started | Jun 30 08:07:16 PM PDT 24 |
| Finished | Jun 30 08:16:35 PM PDT 24 |
| Peak memory | 647812 kb |
| Host | smart-1637872e-6f2d-46d9-98e0-d3006565f02f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3542474445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.3542474445 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.1435325983 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 4465435500 ps |
| CPU time | 605.41 seconds |
| Started | Jun 30 08:02:57 PM PDT 24 |
| Finished | Jun 30 08:13:03 PM PDT 24 |
| Peak memory | 648176 kb |
| Host | smart-e6e55a6f-5236-450d-8fca-1d1d55aaf4ab |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1435325983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.1435325983 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.946624921 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 3860023656 ps |
| CPU time | 476.64 seconds |
| Started | Jun 30 08:05:16 PM PDT 24 |
| Finished | Jun 30 08:13:13 PM PDT 24 |
| Peak memory | 642116 kb |
| Host | smart-1285ae49-f899-4f72-b63b-ddc74add128e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946624921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_s w_alert_handler_lpg_sleep_mode_alerts.946624921 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2970381021 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 3935470100 ps |
| CPU time | 371.23 seconds |
| Started | Jun 30 08:05:28 PM PDT 24 |
| Finished | Jun 30 08:11:39 PM PDT 24 |
| Peak memory | 642140 kb |
| Host | smart-f37a9b39-7003-4127-ac1b-afa2ae0297b4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970381021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2970381021 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.4077534312 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 4482317584 ps |
| CPU time | 694.76 seconds |
| Started | Jun 30 08:05:57 PM PDT 24 |
| Finished | Jun 30 08:17:33 PM PDT 24 |
| Peak memory | 648096 kb |
| Host | smart-038c0e92-8f68-42af-9004-1094997225e9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4077534312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.4077534312 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2452423994 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4110964730 ps |
| CPU time | 393.84 seconds |
| Started | Jun 30 08:05:33 PM PDT 24 |
| Finished | Jun 30 08:12:08 PM PDT 24 |
| Peak memory | 647100 kb |
| Host | smart-f1706476-8b34-481a-8c71-5c84a372f5da |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452423994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2452423994 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.4162705097 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 4932651526 ps |
| CPU time | 664.24 seconds |
| Started | Jun 30 08:05:41 PM PDT 24 |
| Finished | Jun 30 08:16:46 PM PDT 24 |
| Peak memory | 643500 kb |
| Host | smart-f7704a21-604f-47ff-97b1-b975b1727fd5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4162705097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.4162705097 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2882936653 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 4135806672 ps |
| CPU time | 426.5 seconds |
| Started | Jun 30 08:06:29 PM PDT 24 |
| Finished | Jun 30 08:13:36 PM PDT 24 |
| Peak memory | 646912 kb |
| Host | smart-6fbea2b5-d592-4174-990b-02d543b2d41a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882936653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2882936653 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.115206963 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 5705463080 ps |
| CPU time | 584.72 seconds |
| Started | Jun 30 08:06:01 PM PDT 24 |
| Finished | Jun 30 08:15:46 PM PDT 24 |
| Peak memory | 643812 kb |
| Host | smart-130d290f-bd7c-4ddb-9e7d-6c4ec3a271d1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 115206963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.115206963 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2017348976 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 3066326032 ps |
| CPU time | 406.89 seconds |
| Started | Jun 30 08:06:43 PM PDT 24 |
| Finished | Jun 30 08:13:31 PM PDT 24 |
| Peak memory | 647032 kb |
| Host | smart-4213c655-8d97-48c4-bacc-a0ccb465bfc2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017348976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2017348976 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.864591672 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 5986850160 ps |
| CPU time | 720.8 seconds |
| Started | Jun 30 08:06:52 PM PDT 24 |
| Finished | Jun 30 08:18:53 PM PDT 24 |
| Peak memory | 642364 kb |
| Host | smart-729fcf20-7e08-4e63-bbb1-758e6e78738e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 864591672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.864591672 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2879435869 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 3952666180 ps |
| CPU time | 500.76 seconds |
| Started | Jun 30 08:07:50 PM PDT 24 |
| Finished | Jun 30 08:16:12 PM PDT 24 |
| Peak memory | 646952 kb |
| Host | smart-aa9ad1ba-8154-491d-bb95-622c2a96e841 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879435869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2879435869 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.2113519325 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 4733533700 ps |
| CPU time | 599.57 seconds |
| Started | Jun 30 08:07:53 PM PDT 24 |
| Finished | Jun 30 08:17:53 PM PDT 24 |
| Peak memory | 643496 kb |
| Host | smart-b04840d0-bca9-4a87-9f96-82477e7171b9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2113519325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.2113519325 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.1869917580 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 4436035692 ps |
| CPU time | 691.98 seconds |
| Started | Jun 30 08:00:37 PM PDT 24 |
| Finished | Jun 30 08:12:10 PM PDT 24 |
| Peak memory | 643416 kb |
| Host | smart-cc5fa8ad-8bf4-4053-acf7-fba04643863d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1869917580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.1869917580 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.4214372700 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 5764071520 ps |
| CPU time | 763.19 seconds |
| Started | Jun 30 08:07:57 PM PDT 24 |
| Finished | Jun 30 08:20:42 PM PDT 24 |
| Peak memory | 643336 kb |
| Host | smart-3a95524f-cf07-4363-98fb-fc6431ac2c21 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4214372700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.4214372700 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2049022503 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3802527560 ps |
| CPU time | 345.57 seconds |
| Started | Jun 30 08:07:48 PM PDT 24 |
| Finished | Jun 30 08:13:34 PM PDT 24 |
| Peak memory | 642676 kb |
| Host | smart-8cb1af9c-263c-4d77-bcbc-18080c084201 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049022503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2049022503 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.629472576 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 6466335160 ps |
| CPU time | 740.84 seconds |
| Started | Jun 30 08:09:42 PM PDT 24 |
| Finished | Jun 30 08:22:03 PM PDT 24 |
| Peak memory | 643356 kb |
| Host | smart-559a6466-b831-4e7c-abdf-7ce0d59d283a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 629472576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.629472576 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2752692775 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 3656028424 ps |
| CPU time | 410.6 seconds |
| Started | Jun 30 08:09:08 PM PDT 24 |
| Finished | Jun 30 08:15:59 PM PDT 24 |
| Peak memory | 647004 kb |
| Host | smart-a8975a63-06a9-4f3b-baab-0ebc7345fd5b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752692775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2752692775 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.2643353126 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 5701971280 ps |
| CPU time | 718.73 seconds |
| Started | Jun 30 08:07:41 PM PDT 24 |
| Finished | Jun 30 08:19:40 PM PDT 24 |
| Peak memory | 643560 kb |
| Host | smart-826a9a42-161f-4467-8e16-a5238fcfb72a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2643353126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.2643353126 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.1227820323 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 5499105784 ps |
| CPU time | 578.85 seconds |
| Started | Jun 30 08:09:50 PM PDT 24 |
| Finished | Jun 30 08:19:29 PM PDT 24 |
| Peak memory | 643416 kb |
| Host | smart-fbdc6604-e906-45b8-8dd0-c722520dee6b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1227820323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.1227820323 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1393736048 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 3516304100 ps |
| CPU time | 425.79 seconds |
| Started | Jun 30 08:08:09 PM PDT 24 |
| Finished | Jun 30 08:15:15 PM PDT 24 |
| Peak memory | 647108 kb |
| Host | smart-da44865d-1049-46a1-b346-059e6b121138 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393736048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1393736048 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.2233320993 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 4688260800 ps |
| CPU time | 518.66 seconds |
| Started | Jun 30 08:02:50 PM PDT 24 |
| Finished | Jun 30 08:11:29 PM PDT 24 |
| Peak memory | 643620 kb |
| Host | smart-c990a66c-209e-4f92-bf01-79b22ed41afe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2233320993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.2233320993 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1478432860 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 4023512832 ps |
| CPU time | 360.63 seconds |
| Started | Jun 30 08:08:50 PM PDT 24 |
| Finished | Jun 30 08:14:51 PM PDT 24 |
| Peak memory | 642304 kb |
| Host | smart-3bcae9ae-5008-4edc-ab75-ea0479b11e26 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478432860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1478432860 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.4263333350 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 4605985880 ps |
| CPU time | 598.23 seconds |
| Started | Jun 30 08:08:55 PM PDT 24 |
| Finished | Jun 30 08:18:53 PM PDT 24 |
| Peak memory | 643440 kb |
| Host | smart-7fa2dda1-7bfe-425f-9f27-5890ace0ddb9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4263333350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.4263333350 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2790158534 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 3676842192 ps |
| CPU time | 373.39 seconds |
| Started | Jun 30 08:08:44 PM PDT 24 |
| Finished | Jun 30 08:14:58 PM PDT 24 |
| Peak memory | 647308 kb |
| Host | smart-f0819af2-35f6-4df3-9649-ca1daf0f3d00 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790158534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2790158534 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.880441451 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 5803163436 ps |
| CPU time | 644.04 seconds |
| Started | Jun 30 08:02:00 PM PDT 24 |
| Finished | Jun 30 08:12:45 PM PDT 24 |
| Peak memory | 643356 kb |
| Host | smart-2de5df37-3530-42bb-ac5b-5c0bd68ba8e6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 880441451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.880441451 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2283588738 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 3874127820 ps |
| CPU time | 528.26 seconds |
| Started | Jun 30 08:09:16 PM PDT 24 |
| Finished | Jun 30 08:18:05 PM PDT 24 |
| Peak memory | 647048 kb |
| Host | smart-7ad2d473-685e-40ce-854c-dbc4377722b7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283588738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2283588738 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.574074733 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 3729605272 ps |
| CPU time | 414.6 seconds |
| Started | Jun 30 08:10:34 PM PDT 24 |
| Finished | Jun 30 08:17:30 PM PDT 24 |
| Peak memory | 647084 kb |
| Host | smart-3ea1a9a0-a939-44cd-b41e-16877b477408 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574074733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_s w_alert_handler_lpg_sleep_mode_alerts.574074733 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3438496580 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3283769300 ps |
| CPU time | 346.55 seconds |
| Started | Jun 30 08:11:10 PM PDT 24 |
| Finished | Jun 30 08:16:58 PM PDT 24 |
| Peak memory | 647296 kb |
| Host | smart-ec233ba5-64d1-43e8-b62a-ffe4c4582a51 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438496580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3438496580 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.2443314298 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 5981696744 ps |
| CPU time | 592.1 seconds |
| Started | Jun 30 08:11:38 PM PDT 24 |
| Finished | Jun 30 08:21:31 PM PDT 24 |
| Peak memory | 644132 kb |
| Host | smart-7b19a99a-188f-4922-8b32-36cac32fa1b3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2443314298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.2443314298 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.2835363336 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 8007123944 ps |
| CPU time | 2341.19 seconds |
| Started | Jun 30 07:46:17 PM PDT 24 |
| Finished | Jun 30 08:25:18 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-88a21b39-154a-40be-b72f-5e6f5b7d183f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2835363336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.2835363336 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.541626454 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 3282799230 ps |
| CPU time | 455.73 seconds |
| Started | Jun 30 07:33:50 PM PDT 24 |
| Finished | Jun 30 07:41:26 PM PDT 24 |
| Peak memory | 607380 kb |
| Host | smart-2df03e9a-ba20-4fbe-a35d-99ab070e0472 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541626454 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.541626454 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2952723697 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 7381149054 ps |
| CPU time | 601.01 seconds |
| Started | Jun 30 07:33:44 PM PDT 24 |
| Finished | Jun 30 07:43:45 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-8c08a98f-d9fa-4d25-b180-f8bcbb814c96 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2952723697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2952723697 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.2275048608 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 4760440954 ps |
| CPU time | 642.19 seconds |
| Started | Jun 30 07:56:11 PM PDT 24 |
| Finished | Jun 30 08:06:53 PM PDT 24 |
| Peak memory | 609088 kb |
| Host | smart-a0d5bc2f-c603-48ba-a34f-ea19f2e13247 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275048608 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.2275048608 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.3522811118 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 5715551282 ps |
| CPU time | 814.41 seconds |
| Started | Jun 30 08:01:53 PM PDT 24 |
| Finished | Jun 30 08:15:28 PM PDT 24 |
| Peak memory | 608596 kb |
| Host | smart-bbfb83e1-a098-4425-94b2-92b6c84dd886 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3522811118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.3522811118 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.341973563 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 4098954350 ps |
| CPU time | 708.4 seconds |
| Started | Jun 30 07:28:46 PM PDT 24 |
| Finished | Jun 30 07:40:35 PM PDT 24 |
| Peak memory | 608184 kb |
| Host | smart-b9952ff2-b8ef-4530-b21a-7616eedb2702 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341973563 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.341973563 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.4868362 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 47312656700 ps |
| CPU time | 6049.97 seconds |
| Started | Jun 30 07:29:15 PM PDT 24 |
| Finished | Jun 30 09:10:06 PM PDT 24 |
| Peak memory | 623596 kb |
| Host | smart-5757fe7b-95ff-43f2-bb30-ba60f62325bb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4868362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _lc_walkthrough_rma.4868362 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.4285931940 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 9041518828 ps |
| CPU time | 410.73 seconds |
| Started | Jun 30 07:29:11 PM PDT 24 |
| Finished | Jun 30 07:36:03 PM PDT 24 |
| Peak memory | 607116 kb |
| Host | smart-6ca5e608-e9b5-4829-bfcc-c1ff809545ca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285931940 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.4285931940 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3323682120 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 4578669284 ps |
| CPU time | 502.42 seconds |
| Started | Jun 30 07:34:09 PM PDT 24 |
| Finished | Jun 30 07:42:32 PM PDT 24 |
| Peak memory | 614848 kb |
| Host | smart-90783354-b58a-4dd6-ae1a-e80100db8a1d |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332368 2120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3323682120 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3791929928 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 2874684488 ps |
| CPU time | 394.08 seconds |
| Started | Jun 30 07:45:31 PM PDT 24 |
| Finished | Jun 30 07:52:05 PM PDT 24 |
| Peak memory | 606244 kb |
| Host | smart-967947f1-f607-4f96-b9da-024daf4d7d05 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791929928 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.3791929928 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2934840010 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 5507751483 ps |
| CPU time | 594.03 seconds |
| Started | Jun 30 07:34:22 PM PDT 24 |
| Finished | Jun 30 07:44:17 PM PDT 24 |
| Peak memory | 618276 kb |
| Host | smart-544d2c20-a083-47af-adc7-68b010d13669 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934840010 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.2934840010 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.3116111462 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 5887838450 ps |
| CPU time | 614.96 seconds |
| Started | Jun 30 07:59:25 PM PDT 24 |
| Finished | Jun 30 08:09:41 PM PDT 24 |
| Peak memory | 620388 kb |
| Host | smart-a9748f25-02e7-4aa9-bf62-435b54dce646 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3116111462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.3116111462 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.652916807 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 5336299410 ps |
| CPU time | 605.45 seconds |
| Started | Jun 30 08:05:47 PM PDT 24 |
| Finished | Jun 30 08:15:53 PM PDT 24 |
| Peak memory | 597520 kb |
| Host | smart-fee0a220-25c8-40b8-9a01-cb5875aa36c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652916807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.652916807 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.521027276 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 4513595256 ps |
| CPU time | 459.78 seconds |
| Started | Jun 30 08:11:20 PM PDT 24 |
| Finished | Jun 30 08:19:00 PM PDT 24 |
| Peak memory | 597580 kb |
| Host | smart-44c3db20-398f-4105-8a88-d976f8bb22da |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521027276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.521027276 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2941057403 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 147224214845 ps |
| CPU time | 2615.71 seconds |
| Started | Jun 30 08:12:25 PM PDT 24 |
| Finished | Jun 30 08:56:02 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-eb619c86-cad9-437d-a86f-9ea78119788f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941057403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.2941057403 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.4288352128 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 9651204470 ps |
| CPU time | 1072.99 seconds |
| Started | Jun 30 07:27:41 PM PDT 24 |
| Finished | Jun 30 07:45:34 PM PDT 24 |
| Peak memory | 609092 kb |
| Host | smart-d05e4aad-9359-469b-9967-c275cf8ef92b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=4288352128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.4288352128 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.454408293 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 3510151044 ps |
| CPU time | 382.39 seconds |
| Started | Jun 30 07:46:23 PM PDT 24 |
| Finished | Jun 30 07:52:46 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-253eccb5-aaf6-4114-a2fa-b382204307e0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454408293 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.454408293 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.1253806959 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 3412830988 ps |
| CPU time | 568.55 seconds |
| Started | Jun 30 07:28:28 PM PDT 24 |
| Finished | Jun 30 07:37:57 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-e333c04c-314f-4fab-a76b-8cf34ab68594 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253806959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.1253806959 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1781231503 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 7195549133 ps |
| CPU time | 1403.35 seconds |
| Started | Jun 30 07:32:06 PM PDT 24 |
| Finished | Jun 30 07:55:30 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-7759e863-2ce3-4b3d-bb38-3c1930ea2ae6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781231503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.1781231503 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1289676580 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 5166908886 ps |
| CPU time | 844.43 seconds |
| Started | Jun 30 07:32:52 PM PDT 24 |
| Finished | Jun 30 07:46:58 PM PDT 24 |
| Peak memory | 608212 kb |
| Host | smart-12031153-0f5e-4378-855f-90d1365afede |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289676580 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.1289676580 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1687656727 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 11195257930 ps |
| CPU time | 965.77 seconds |
| Started | Jun 30 07:31:13 PM PDT 24 |
| Finished | Jun 30 07:47:19 PM PDT 24 |
| Peak memory | 619176 kb |
| Host | smart-9df9dd9c-e480-466d-9e39-fa8a15f84276 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1687656727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.1687656727 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.930534062 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 12048672512 ps |
| CPU time | 2267.65 seconds |
| Started | Jun 30 07:30:02 PM PDT 24 |
| Finished | Jun 30 08:07:50 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-feb80f0a-a64d-4781-b78b-4844ef8591f9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930534 062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.930534062 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2764102972 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 4461118472 ps |
| CPU time | 683.34 seconds |
| Started | Jun 30 07:33:13 PM PDT 24 |
| Finished | Jun 30 07:44:37 PM PDT 24 |
| Peak memory | 608744 kb |
| Host | smart-8e6bddc9-2243-489c-a1fd-057c393336c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2764102972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.2764102972 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3302998725 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 2336186178 ps |
| CPU time | 289.44 seconds |
| Started | Jun 30 07:28:02 PM PDT 24 |
| Finished | Jun 30 07:32:52 PM PDT 24 |
| Peak memory | 616364 kb |
| Host | smart-c9d78048-a1ce-4ad8-a568-223c45062aa6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302998725 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.3302998725 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.3990381944 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 3794514827 ps |
| CPU time | 172.09 seconds |
| Started | Jun 30 08:16:38 PM PDT 24 |
| Finished | Jun 30 08:19:31 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-af925fc5-b42f-4c8d-8b6c-0271c65d2c46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990381944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3990381944 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1039876126 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 6458551049 ps |
| CPU time | 413.91 seconds |
| Started | Jun 30 08:17:35 PM PDT 24 |
| Finished | Jun 30 08:24:52 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-63ee83ea-c426-4bd7-88e2-4bd99fbb9e4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039876126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.1039876126 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.995723422 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 9565819995 ps |
| CPU time | 975.81 seconds |
| Started | Jun 30 08:23:44 PM PDT 24 |
| Finished | Jun 30 08:40:01 PM PDT 24 |
| Peak memory | 582632 kb |
| Host | smart-0cedb46b-7a93-4a74-b3c9-8abaaa9ae35e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995723422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_reset_error.995723422 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1861061171 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 11166591624 ps |
| CPU time | 906.66 seconds |
| Started | Jun 30 08:25:32 PM PDT 24 |
| Finished | Jun 30 08:40:40 PM PDT 24 |
| Peak memory | 582612 kb |
| Host | smart-dbebe970-eca8-43bf-bc72-e243b9024a2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861061171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.1861061171 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.3938146655 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2660717758 ps |
| CPU time | 241.87 seconds |
| Started | Jun 30 08:25:55 PM PDT 24 |
| Finished | Jun 30 08:29:58 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-7486f6b3-3769-4a59-b300-67a47bbb1a7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938146655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.3938146655 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.2196430611 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 1628401147 ps |
| CPU time | 57 seconds |
| Started | Jun 30 08:29:55 PM PDT 24 |
| Finished | Jun 30 08:30:53 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-652f9648-9370-494b-90f3-1f2989457166 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196430611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.2196430611 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.3684977698 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 4130018040 ps |
| CPU time | 467.8 seconds |
| Started | Jun 30 07:27:53 PM PDT 24 |
| Finished | Jun 30 07:35:41 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-00c6482c-2e28-437b-954e-d6e2ee1227bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684977698 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.3684977698 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.13811945 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 4758882680 ps |
| CPU time | 940.68 seconds |
| Started | Jun 30 07:29:03 PM PDT 24 |
| Finished | Jun 30 07:44:45 PM PDT 24 |
| Peak memory | 607028 kb |
| Host | smart-b78876f3-a34c-46c1-ab7a-dcdc53aca345 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13811 945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.13811945 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.2267533085 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 4836082103 ps |
| CPU time | 443.94 seconds |
| Started | Jun 30 07:58:14 PM PDT 24 |
| Finished | Jun 30 08:05:39 PM PDT 24 |
| Peak memory | 619968 kb |
| Host | smart-a30fbdb7-b617-403f-91ec-037fa7ac18b3 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267533085 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.2267533085 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.1013156678 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2954609228 ps |
| CPU time | 243.62 seconds |
| Started | Jun 30 07:51:06 PM PDT 24 |
| Finished | Jun 30 07:55:11 PM PDT 24 |
| Peak memory | 607936 kb |
| Host | smart-95ce71cf-5485-4db3-bb87-d0a833d382d8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013156678 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.1013156678 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.4230204632 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 5846290900 ps |
| CPU time | 384.29 seconds |
| Started | Jun 30 08:04:59 PM PDT 24 |
| Finished | Jun 30 08:11:23 PM PDT 24 |
| Peak memory | 661556 kb |
| Host | smart-0969e37b-2ca6-4662-be76-a64148d0b852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230204632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.4230204632 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3512660722 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 5121391780 ps |
| CPU time | 252.04 seconds |
| Started | Jun 30 08:05:47 PM PDT 24 |
| Finished | Jun 30 08:10:00 PM PDT 24 |
| Peak memory | 658048 kb |
| Host | smart-aa98bb06-90a9-4199-b2e3-6809a626602b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512660722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.3512660722 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2299601093 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 26026902077 ps |
| CPU time | 2069.13 seconds |
| Started | Jun 30 07:34:43 PM PDT 24 |
| Finished | Jun 30 08:09:14 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-0314dfc2-ec20-4ade-809e-89c42b75d06c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2299601093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.2299601093 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2019751664 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 19989562878 ps |
| CPU time | 2461.27 seconds |
| Started | Jun 30 07:29:24 PM PDT 24 |
| Finished | Jun 30 08:10:26 PM PDT 24 |
| Peak memory | 609020 kb |
| Host | smart-d2030926-8c1a-4a10-9965-61b4a1f7404e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2019751664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2019751664 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3252439331 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3287281680 ps |
| CPU time | 172.12 seconds |
| Started | Jun 30 07:34:53 PM PDT 24 |
| Finished | Jun 30 07:37:46 PM PDT 24 |
| Peak memory | 608364 kb |
| Host | smart-b8d2453a-4075-4080-ada7-6d7f5c506fac |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252439331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.3252439331 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.868010568 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 24574675046 ps |
| CPU time | 5848.12 seconds |
| Started | Jun 30 07:40:48 PM PDT 24 |
| Finished | Jun 30 09:18:17 PM PDT 24 |
| Peak memory | 608360 kb |
| Host | smart-f57b0ad8-834a-40be-b600-8a6604b2115b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=868010568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.868010568 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1912055971 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 40954075550 ps |
| CPU time | 5942.63 seconds |
| Started | Jun 30 08:04:05 PM PDT 24 |
| Finished | Jun 30 09:43:08 PM PDT 24 |
| Peak memory | 592308 kb |
| Host | smart-19581305-23f4-4a2f-a9be-ca2d25d4d96e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912055971 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.chip_csr_aliasing.1912055971 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3377819085 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 31872213400 ps |
| CPU time | 2877.72 seconds |
| Started | Jun 30 08:04:03 PM PDT 24 |
| Finished | Jun 30 08:52:01 PM PDT 24 |
| Peak memory | 589248 kb |
| Host | smart-2dbf7e28-78bc-48fb-9de1-4d56de82c1bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377819085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.3377819085 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.4115435401 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 5539779722 ps |
| CPU time | 645.23 seconds |
| Started | Jun 30 08:04:58 PM PDT 24 |
| Finished | Jun 30 08:15:44 PM PDT 24 |
| Peak memory | 598144 kb |
| Host | smart-01ec5624-d625-4cb4-9d91-592cc2c22003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115435401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.4115435401 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3577471647 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 12590224520 ps |
| CPU time | 467.06 seconds |
| Started | Jun 30 08:04:09 PM PDT 24 |
| Finished | Jun 30 08:11:56 PM PDT 24 |
| Peak memory | 590092 kb |
| Host | smart-367638a3-b2b8-4c2f-a015-dc7b5acc3013 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577471647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.3577471647 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1992458816 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 7844311677 ps |
| CPU time | 409.01 seconds |
| Started | Jun 30 08:04:29 PM PDT 24 |
| Finished | Jun 30 08:11:19 PM PDT 24 |
| Peak memory | 589592 kb |
| Host | smart-64fdf219-5579-42c3-8ae2-66b753e66c28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992458816 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.1992458816 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2577626646 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 27442817822 ps |
| CPU time | 2929.16 seconds |
| Started | Jun 30 08:04:12 PM PDT 24 |
| Finished | Jun 30 08:53:02 PM PDT 24 |
| Peak memory | 591888 kb |
| Host | smart-220c6ec9-7810-4f9a-95bc-7e41b1dae334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577626646 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.2577626646 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.2218417567 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 2871951600 ps |
| CPU time | 234.95 seconds |
| Started | Jun 30 08:04:05 PM PDT 24 |
| Finished | Jun 30 08:08:00 PM PDT 24 |
| Peak memory | 603480 kb |
| Host | smart-d65ca170-5444-477b-94a1-266b3c64fde6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218417567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.2218417567 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.2594522587 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 1641630249 ps |
| CPU time | 85.32 seconds |
| Started | Jun 30 08:04:35 PM PDT 24 |
| Finished | Jun 30 08:06:01 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-47dc4977-46eb-4bff-8440-bd50c1c9f8e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594522587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 2594522587 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1318982659 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 100166271328 ps |
| CPU time | 1825.65 seconds |
| Started | Jun 30 08:04:26 PM PDT 24 |
| Finished | Jun 30 08:34:53 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-0c78cf82-e3dd-4b96-b0eb-8866975fb586 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318982659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.1318982659 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2665067831 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 334005319 ps |
| CPU time | 41.14 seconds |
| Started | Jun 30 08:04:47 PM PDT 24 |
| Finished | Jun 30 08:05:29 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-704f3e55-e1fe-46d6-9ea7-df7091b3392d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665067831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .2665067831 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.1548603614 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 97661534 ps |
| CPU time | 11.35 seconds |
| Started | Jun 30 08:04:58 PM PDT 24 |
| Finished | Jun 30 08:05:10 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-6fa64874-8e05-4923-a57f-f8d45867bbdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548603614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1548603614 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.1347298302 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 554056256 ps |
| CPU time | 54.91 seconds |
| Started | Jun 30 08:04:20 PM PDT 24 |
| Finished | Jun 30 08:05:16 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-aeb100a7-c728-4b4a-ac67-588b1b56d78f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347298302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.1347298302 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3337899643 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 16148431434 ps |
| CPU time | 173.74 seconds |
| Started | Jun 30 08:04:38 PM PDT 24 |
| Finished | Jun 30 08:07:32 PM PDT 24 |
| Peak memory | 575188 kb |
| Host | smart-3107b552-d251-4485-983b-169b74bf0c1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337899643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3337899643 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1531449535 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 3607389044 ps |
| CPU time | 63.8 seconds |
| Started | Jun 30 08:04:26 PM PDT 24 |
| Finished | Jun 30 08:05:31 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-b00c783c-6c64-4ddd-bad6-68546bc57fb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531449535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1531449535 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.4231573677 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 169347872 ps |
| CPU time | 17.1 seconds |
| Started | Jun 30 08:04:25 PM PDT 24 |
| Finished | Jun 30 08:04:43 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-70c9ccdf-62c9-47a3-ac54-9729463d4d94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231573677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.4231573677 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.32257924 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 349023053 ps |
| CPU time | 25.36 seconds |
| Started | Jun 30 08:04:27 PM PDT 24 |
| Finished | Jun 30 08:04:53 PM PDT 24 |
| Peak memory | 575196 kb |
| Host | smart-0cdb62d5-4aa1-4b40-a35d-24be99bd332f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32257924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.32257924 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.257978420 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 191408930 ps |
| CPU time | 9.86 seconds |
| Started | Jun 30 08:04:17 PM PDT 24 |
| Finished | Jun 30 08:04:27 PM PDT 24 |
| Peak memory | 565876 kb |
| Host | smart-5a900df5-2ca8-4b5c-8e1a-bb88cf33814c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257978420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.257978420 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.699004297 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 7388654632 ps |
| CPU time | 87.28 seconds |
| Started | Jun 30 08:04:32 PM PDT 24 |
| Finished | Jun 30 08:06:00 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-89d3f526-c03b-4e2e-97f3-644943314265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699004297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.699004297 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1303355510 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 6166273054 ps |
| CPU time | 112.42 seconds |
| Started | Jun 30 08:04:32 PM PDT 24 |
| Finished | Jun 30 08:06:25 PM PDT 24 |
| Peak memory | 565996 kb |
| Host | smart-59b03587-b827-4011-bcfd-089e8d52049a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303355510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1303355510 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3988797329 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 54072139 ps |
| CPU time | 7.76 seconds |
| Started | Jun 30 08:04:27 PM PDT 24 |
| Finished | Jun 30 08:04:35 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-06cc77ff-8f70-4d59-97d0-01ca2d88de0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988797329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .3988797329 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.4241646106 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 1429104573 ps |
| CPU time | 160.35 seconds |
| Started | Jun 30 08:04:49 PM PDT 24 |
| Finished | Jun 30 08:07:30 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-8d53e0b1-1a6c-4561-b4c9-829b3c22f029 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241646106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.4241646106 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3050948736 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 1320238096 ps |
| CPU time | 32.83 seconds |
| Started | Jun 30 08:04:39 PM PDT 24 |
| Finished | Jun 30 08:05:12 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-c2d8de4e-f26b-4c05-b064-1756702febe3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050948736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3050948736 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1833786149 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 14586997484 ps |
| CPU time | 803.14 seconds |
| Started | Jun 30 08:04:50 PM PDT 24 |
| Finished | Jun 30 08:18:14 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-75990457-d0ae-4189-9e69-68912ecec1dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833786149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.1833786149 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3313772674 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 242046080 ps |
| CPU time | 137.23 seconds |
| Started | Jun 30 08:05:11 PM PDT 24 |
| Finished | Jun 30 08:07:28 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-4a2174af-7efa-47f3-a16c-053c3c50c202 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313772674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.3313772674 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1134999446 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 1061952400 ps |
| CPU time | 54.01 seconds |
| Started | Jun 30 08:04:32 PM PDT 24 |
| Finished | Jun 30 08:05:27 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-722e9d57-fb2f-461b-a186-d46f2ce04724 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134999446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1134999446 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3217754668 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 37345544354 ps |
| CPU time | 5610.57 seconds |
| Started | Jun 30 08:05:02 PM PDT 24 |
| Finished | Jun 30 09:38:33 PM PDT 24 |
| Peak memory | 592892 kb |
| Host | smart-7496e7c1-d703-4300-8707-13ca11f1b5c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217754668 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.3217754668 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.819602427 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 31419093696 ps |
| CPU time | 3511.6 seconds |
| Started | Jun 30 08:05:08 PM PDT 24 |
| Finished | Jun 30 09:03:41 PM PDT 24 |
| Peak memory | 591428 kb |
| Host | smart-39baccf1-10cf-4944-8519-40aa229268a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819602427 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.819602427 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2345182503 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 7538014420 ps |
| CPU time | 243.39 seconds |
| Started | Jun 30 08:05:07 PM PDT 24 |
| Finished | Jun 30 08:09:10 PM PDT 24 |
| Peak memory | 589248 kb |
| Host | smart-6e53289e-477d-4573-88ad-9a1b36f2cf00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345182503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.2345182503 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2383869375 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 17194875459 ps |
| CPU time | 764.84 seconds |
| Started | Jun 30 08:05:12 PM PDT 24 |
| Finished | Jun 30 08:17:57 PM PDT 24 |
| Peak memory | 590260 kb |
| Host | smart-d1fa4e2a-cd7c-4868-b3d1-8ba01edfe0fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383869375 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.2383869375 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.461140098 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 14556094483 ps |
| CPU time | 1801.8 seconds |
| Started | Jun 30 08:05:07 PM PDT 24 |
| Finished | Jun 30 08:35:10 PM PDT 24 |
| Peak memory | 591764 kb |
| Host | smart-afee9523-fa00-4e4e-9c4a-2fe9f6f4619c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461140098 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.chip_same_csr_outstanding.461140098 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.3071745229 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2006838865 ps |
| CPU time | 92.8 seconds |
| Started | Jun 30 08:05:26 PM PDT 24 |
| Finished | Jun 30 08:06:59 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-bc1c815a-8715-47ae-a00b-128c03f25c34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071745229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 3071745229 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3489080382 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 12213789569 ps |
| CPU time | 228.03 seconds |
| Started | Jun 30 08:05:31 PM PDT 24 |
| Finished | Jun 30 08:09:19 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-c0e6b06b-bd58-4eaf-9763-5c471da5b508 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489080382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.3489080382 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.200905935 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 1245293388 ps |
| CPU time | 58.92 seconds |
| Started | Jun 30 08:05:37 PM PDT 24 |
| Finished | Jun 30 08:06:37 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-fe23ea2f-be1c-4ba4-9322-18e9229efb7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200905935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr. 200905935 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.36687725 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 435898784 ps |
| CPU time | 36.49 seconds |
| Started | Jun 30 08:05:26 PM PDT 24 |
| Finished | Jun 30 08:06:03 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-02e30095-4790-4d18-aa73-dd829e82b6cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36687725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.36687725 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.345698170 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 121564521 ps |
| CPU time | 7.54 seconds |
| Started | Jun 30 08:05:16 PM PDT 24 |
| Finished | Jun 30 08:05:24 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-f1d94a83-c0ed-4120-84e5-283ad2b448a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345698170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.345698170 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2037570372 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 83429511732 ps |
| CPU time | 858.32 seconds |
| Started | Jun 30 08:05:25 PM PDT 24 |
| Finished | Jun 30 08:19:44 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-72f17274-13bf-4798-8343-a83cf5d9df1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037570372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2037570372 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.4052687355 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 39367712436 ps |
| CPU time | 653.6 seconds |
| Started | Jun 30 08:05:22 PM PDT 24 |
| Finished | Jun 30 08:16:16 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-e9f5d683-11d1-45fe-bd48-cc720bd3a06d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052687355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.4052687355 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3552422635 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 42046663 ps |
| CPU time | 8.08 seconds |
| Started | Jun 30 08:05:27 PM PDT 24 |
| Finished | Jun 30 08:05:35 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-4bc7d01f-ad99-4c33-86b0-f5f6971b4228 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552422635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.3552422635 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.2448119367 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 349560012 ps |
| CPU time | 30.22 seconds |
| Started | Jun 30 08:05:30 PM PDT 24 |
| Finished | Jun 30 08:06:01 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-292180f2-b4ab-484e-98fa-d4fe5f6cc1d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448119367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2448119367 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.2922341070 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 135983925 ps |
| CPU time | 8.05 seconds |
| Started | Jun 30 08:05:15 PM PDT 24 |
| Finished | Jun 30 08:05:24 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-f3e668ca-3e6a-4130-ad77-da037b1c1ab5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922341070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2922341070 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1175008689 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 8939169432 ps |
| CPU time | 103.34 seconds |
| Started | Jun 30 08:05:35 PM PDT 24 |
| Finished | Jun 30 08:07:19 PM PDT 24 |
| Peak memory | 566044 kb |
| Host | smart-31797e12-092e-4408-a093-0164c40a8db0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175008689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1175008689 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1686316714 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 4027189129 ps |
| CPU time | 69.91 seconds |
| Started | Jun 30 08:05:19 PM PDT 24 |
| Finished | Jun 30 08:06:29 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-8ec5e1fd-27b3-460f-bb73-47e57a56a89a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686316714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1686316714 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3476030131 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 56877843 ps |
| CPU time | 7.32 seconds |
| Started | Jun 30 08:05:10 PM PDT 24 |
| Finished | Jun 30 08:05:18 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-5bd1f610-5531-4158-9d9b-4683edc4adb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476030131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .3476030131 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.3472733267 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 619030577 ps |
| CPU time | 70.18 seconds |
| Started | Jun 30 08:05:40 PM PDT 24 |
| Finished | Jun 30 08:06:51 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-f4c64374-6d49-48b6-ac08-d477c86fc3ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472733267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3472733267 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.403950554 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 8815863129 ps |
| CPU time | 383.89 seconds |
| Started | Jun 30 08:05:41 PM PDT 24 |
| Finished | Jun 30 08:12:05 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-eac84a6c-8a8c-4ca9-8b2e-325efaa42df0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403950554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.403950554 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1173444733 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 2723788714 ps |
| CPU time | 611.51 seconds |
| Started | Jun 30 08:05:53 PM PDT 24 |
| Finished | Jun 30 08:16:05 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-e07fe132-d63d-4611-ace7-2263e8ef6538 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173444733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.1173444733 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2995626536 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 568566956 ps |
| CPU time | 189.57 seconds |
| Started | Jun 30 08:05:39 PM PDT 24 |
| Finished | Jun 30 08:08:49 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-f5129098-d076-4bd3-8381-83b9ba39e5c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995626536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.2995626536 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.4071691893 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 219676763 ps |
| CPU time | 29.23 seconds |
| Started | Jun 30 08:05:31 PM PDT 24 |
| Finished | Jun 30 08:06:00 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-24a3702e-c071-4008-bd01-30c73e6f75fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071691893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.4071691893 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.107672350 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 4142657790 ps |
| CPU time | 348.08 seconds |
| Started | Jun 30 08:11:45 PM PDT 24 |
| Finished | Jun 30 08:17:33 PM PDT 24 |
| Peak memory | 595816 kb |
| Host | smart-8115ac3f-6736-4f81-acb2-307e84930b52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107672350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.107672350 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.709074577 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 15072900559 ps |
| CPU time | 1648.56 seconds |
| Started | Jun 30 08:11:21 PM PDT 24 |
| Finished | Jun 30 08:38:50 PM PDT 24 |
| Peak memory | 591796 kb |
| Host | smart-15758b0c-35fe-4e32-ba8e-fcd89fab9216 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709074577 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 10.chip_same_csr_outstanding.709074577 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.3092663672 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 2215779706 ps |
| CPU time | 97.48 seconds |
| Started | Jun 30 08:11:33 PM PDT 24 |
| Finished | Jun 30 08:13:11 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-4197ff1f-021b-4030-a6d8-17f3115213f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092663672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .3092663672 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2415879518 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 127773022559 ps |
| CPU time | 2150.08 seconds |
| Started | Jun 30 08:11:32 PM PDT 24 |
| Finished | Jun 30 08:47:23 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-a9f991d0-3a4d-44ca-861e-f9cb01f04789 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415879518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.2415879518 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1505355529 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 334029832 ps |
| CPU time | 17.17 seconds |
| Started | Jun 30 08:11:39 PM PDT 24 |
| Finished | Jun 30 08:11:57 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-46611631-ad48-4160-918e-88671b64c919 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505355529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.1505355529 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.3750912556 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 143228316 ps |
| CPU time | 9.12 seconds |
| Started | Jun 30 08:11:40 PM PDT 24 |
| Finished | Jun 30 08:11:49 PM PDT 24 |
| Peak memory | 565964 kb |
| Host | smart-6c408b84-26bf-4e12-89e7-b030fd899403 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750912556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3750912556 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.3753746756 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 314448553 ps |
| CPU time | 34.69 seconds |
| Started | Jun 30 08:11:27 PM PDT 24 |
| Finished | Jun 30 08:12:02 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-d15129c0-a241-4600-b96d-aac35c8a4dea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753746756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.3753746756 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2768563992 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 58452361856 ps |
| CPU time | 599 seconds |
| Started | Jun 30 08:11:25 PM PDT 24 |
| Finished | Jun 30 08:21:25 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-d39aa210-8f5f-4865-af42-13fe7ae15337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768563992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2768563992 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.254549297 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 3735917846 ps |
| CPU time | 68.26 seconds |
| Started | Jun 30 08:11:27 PM PDT 24 |
| Finished | Jun 30 08:12:36 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-b4e5320b-4c4f-4971-ac3f-56f6c88653af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254549297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.254549297 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2054397109 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 468942061 ps |
| CPU time | 47.92 seconds |
| Started | Jun 30 08:11:27 PM PDT 24 |
| Finished | Jun 30 08:12:16 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-ec28ec81-f2b4-4a6f-9d35-1c29304bfaf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054397109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.2054397109 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.3551675239 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 1719008089 ps |
| CPU time | 55.63 seconds |
| Started | Jun 30 08:11:37 PM PDT 24 |
| Finished | Jun 30 08:12:33 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-c1a55d7a-ff0f-4aa0-8118-b0c415818c21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551675239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3551675239 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.936610043 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 44717513 ps |
| CPU time | 6.19 seconds |
| Started | Jun 30 08:11:20 PM PDT 24 |
| Finished | Jun 30 08:11:27 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-8e62aa49-de45-4947-bb6d-fa9a964c3e48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936610043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.936610043 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3207296746 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 9660174358 ps |
| CPU time | 108.4 seconds |
| Started | Jun 30 08:11:28 PM PDT 24 |
| Finished | Jun 30 08:13:17 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-ce24776e-cc55-4c0e-888c-2984d561d45f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207296746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3207296746 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.387966911 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 5713807491 ps |
| CPU time | 104.01 seconds |
| Started | Jun 30 08:11:28 PM PDT 24 |
| Finished | Jun 30 08:13:13 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-8b41a7c7-9024-4a66-a66a-f14e3b548f26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387966911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.387966911 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2854937785 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 37450314 ps |
| CPU time | 6.27 seconds |
| Started | Jun 30 08:11:25 PM PDT 24 |
| Finished | Jun 30 08:11:31 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-f6874728-ca9b-41f9-84a4-56eeca3fd677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854937785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.2854937785 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.1610918630 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 5769841818 ps |
| CPU time | 235.06 seconds |
| Started | Jun 30 08:11:38 PM PDT 24 |
| Finished | Jun 30 08:15:34 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-723cef79-4428-4696-ae3d-be692a8773d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610918630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1610918630 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2039584274 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 2897409270 ps |
| CPU time | 235.14 seconds |
| Started | Jun 30 08:11:43 PM PDT 24 |
| Finished | Jun 30 08:15:39 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-efc9134c-c49c-42ee-a99c-776468bba10e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039584274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2039584274 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1324628512 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 219686810 ps |
| CPU time | 134.05 seconds |
| Started | Jun 30 08:11:37 PM PDT 24 |
| Finished | Jun 30 08:13:52 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-a17ec1d3-dac9-4201-a378-ab44ae654d9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324628512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.1324628512 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.778709680 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 474011642 ps |
| CPU time | 86.32 seconds |
| Started | Jun 30 08:11:44 PM PDT 24 |
| Finished | Jun 30 08:13:11 PM PDT 24 |
| Peak memory | 576388 kb |
| Host | smart-fea7d113-942d-46aa-81b6-f63cd763364e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778709680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_reset_error.778709680 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.754392791 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 238368914 ps |
| CPU time | 14.98 seconds |
| Started | Jun 30 08:11:38 PM PDT 24 |
| Finished | Jun 30 08:11:54 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-d907429a-96b0-4cbc-8896-283bb87f9a41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754392791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.754392791 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.3757993979 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 6318774312 ps |
| CPU time | 639.13 seconds |
| Started | Jun 30 08:12:13 PM PDT 24 |
| Finished | Jun 30 08:22:52 PM PDT 24 |
| Peak memory | 597988 kb |
| Host | smart-2160807b-fae5-4812-9e17-84041b2cdeae |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757993979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.3757993979 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.213354967 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 16418472977 ps |
| CPU time | 1998.1 seconds |
| Started | Jun 30 08:11:46 PM PDT 24 |
| Finished | Jun 30 08:45:05 PM PDT 24 |
| Peak memory | 590716 kb |
| Host | smart-72fb7190-cf19-443b-8fd0-5a8fc94ff186 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213354967 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.chip_same_csr_outstanding.213354967 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.989955327 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 2588662156 ps |
| CPU time | 109.39 seconds |
| Started | Jun 30 08:11:49 PM PDT 24 |
| Finished | Jun 30 08:13:39 PM PDT 24 |
| Peak memory | 603600 kb |
| Host | smart-b99dc758-82f9-48f7-a349-f4874210672a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989955327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.989955327 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.954484978 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 43600792393 ps |
| CPU time | 841.24 seconds |
| Started | Jun 30 08:12:00 PM PDT 24 |
| Finished | Jun 30 08:26:02 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-91909824-4d35-42f6-b0d5-6382455397c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954484978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_d evice_slow_rsp.954484978 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3244942221 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 39442219 ps |
| CPU time | 7.43 seconds |
| Started | Jun 30 08:12:09 PM PDT 24 |
| Finished | Jun 30 08:12:17 PM PDT 24 |
| Peak memory | 565988 kb |
| Host | smart-82b30b4a-559f-42e6-b419-d982db44abc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244942221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.3244942221 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.2735121160 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 640451388 ps |
| CPU time | 61.7 seconds |
| Started | Jun 30 08:12:01 PM PDT 24 |
| Finished | Jun 30 08:13:03 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-7d546284-8e50-466d-9185-4a356dbe2faa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735121160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2735121160 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.1064363997 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 383329390 ps |
| CPU time | 39.3 seconds |
| Started | Jun 30 08:11:57 PM PDT 24 |
| Finished | Jun 30 08:12:36 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-95ead20a-ee04-4882-b084-13512e5e7ea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064363997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.1064363997 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.4246409549 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 79801865834 ps |
| CPU time | 860.12 seconds |
| Started | Jun 30 08:12:02 PM PDT 24 |
| Finished | Jun 30 08:26:23 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-23832cde-1e99-4d6c-bdce-40e2f21f92d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246409549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.4246409549 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.655769507 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 28653716546 ps |
| CPU time | 543.58 seconds |
| Started | Jun 30 08:12:01 PM PDT 24 |
| Finished | Jun 30 08:21:05 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-c78d40da-7c96-4d20-9243-b1d07a9de393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655769507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.655769507 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2503325431 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 271902402 ps |
| CPU time | 28.62 seconds |
| Started | Jun 30 08:11:55 PM PDT 24 |
| Finished | Jun 30 08:12:24 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-015ce750-eb7e-403e-9ea4-3be5940d413a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503325431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.2503325431 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.3157202899 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 2296374517 ps |
| CPU time | 81.95 seconds |
| Started | Jun 30 08:12:02 PM PDT 24 |
| Finished | Jun 30 08:13:24 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-945c222d-13be-4972-8ea5-cb82513de2d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157202899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3157202899 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.279986689 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 186240912 ps |
| CPU time | 9.47 seconds |
| Started | Jun 30 08:11:48 PM PDT 24 |
| Finished | Jun 30 08:11:58 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-881fd67d-a390-49e9-885c-bc66120559f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279986689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.279986689 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2046873296 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 7536454542 ps |
| CPU time | 83.12 seconds |
| Started | Jun 30 08:11:57 PM PDT 24 |
| Finished | Jun 30 08:13:21 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-d3951ff3-b75d-45f7-9c2e-bb6a7a1d9a61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046873296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2046873296 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.394709349 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 4942516990 ps |
| CPU time | 87.85 seconds |
| Started | Jun 30 08:11:53 PM PDT 24 |
| Finished | Jun 30 08:13:21 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-9a19e32f-d6f0-437f-80b1-3cbca30f5ac0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394709349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.394709349 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.4041023997 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 44446776 ps |
| CPU time | 6.53 seconds |
| Started | Jun 30 08:11:50 PM PDT 24 |
| Finished | Jun 30 08:11:57 PM PDT 24 |
| Peak memory | 565892 kb |
| Host | smart-15225329-25ef-4f19-98af-b21aeff2d1af |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041023997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.4041023997 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.4179809691 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 2927823498 ps |
| CPU time | 287.92 seconds |
| Started | Jun 30 08:12:07 PM PDT 24 |
| Finished | Jun 30 08:16:55 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-ea8307ae-dc7a-4806-b772-1c822eaa93b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179809691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.4179809691 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.4197371119 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 10916708534 ps |
| CPU time | 444.15 seconds |
| Started | Jun 30 08:12:06 PM PDT 24 |
| Finished | Jun 30 08:19:31 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-120c1460-6c81-4b07-a048-4af9a2d10148 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197371119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.4197371119 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3842984537 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 345286520 ps |
| CPU time | 134.17 seconds |
| Started | Jun 30 08:12:06 PM PDT 24 |
| Finished | Jun 30 08:14:20 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-c5146391-0fe0-4e1a-8ecb-3a66eb761c32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842984537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.3842984537 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3659914 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 1711524864 ps |
| CPU time | 234.09 seconds |
| Started | Jun 30 08:12:07 PM PDT 24 |
| Finished | Jun 30 08:16:01 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-28840e6d-38bd-4f99-9307-641c83e75a08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_w ith_reset_error.3659914 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.647919525 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 114857605 ps |
| CPU time | 17.52 seconds |
| Started | Jun 30 08:12:07 PM PDT 24 |
| Finished | Jun 30 08:12:25 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-87119c07-c802-44ab-806f-c90e06e5cf36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647919525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.647919525 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.604054936 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 4474850082 ps |
| CPU time | 375.7 seconds |
| Started | Jun 30 08:12:29 PM PDT 24 |
| Finished | Jun 30 08:18:46 PM PDT 24 |
| Peak memory | 596200 kb |
| Host | smart-f91e69ce-c05d-49a5-9070-cc46bbf7abb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604054936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.604054936 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2305850678 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 28976906829 ps |
| CPU time | 3472.35 seconds |
| Started | Jun 30 08:12:11 PM PDT 24 |
| Finished | Jun 30 09:10:04 PM PDT 24 |
| Peak memory | 591832 kb |
| Host | smart-0bfa815d-c18b-415a-baf7-1c0a53a077dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305850678 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.2305850678 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.718787516 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 4311017356 ps |
| CPU time | 397.43 seconds |
| Started | Jun 30 08:12:16 PM PDT 24 |
| Finished | Jun 30 08:18:54 PM PDT 24 |
| Peak memory | 597424 kb |
| Host | smart-da9dd2d5-9e6e-4c84-bdfa-22f374b61dc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718787516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.718787516 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.4104756527 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 84596295 ps |
| CPU time | 16.5 seconds |
| Started | Jun 30 08:12:28 PM PDT 24 |
| Finished | Jun 30 08:12:45 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-2b47c612-f49f-4e07-99ce-0123cd42771e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104756527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .4104756527 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3832823027 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 157547812 ps |
| CPU time | 10.61 seconds |
| Started | Jun 30 08:12:24 PM PDT 24 |
| Finished | Jun 30 08:12:35 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-7af676ed-235e-48c3-af40-a59fbd81f93e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832823027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.3832823027 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.3059635043 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 1613253891 ps |
| CPU time | 57.12 seconds |
| Started | Jun 30 08:12:29 PM PDT 24 |
| Finished | Jun 30 08:13:26 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-ab014101-0a05-4ec4-b4d0-937a18689a7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059635043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3059635043 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.1340741396 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 65616528 ps |
| CPU time | 9.17 seconds |
| Started | Jun 30 08:12:19 PM PDT 24 |
| Finished | Jun 30 08:12:29 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-8224f80b-1ee8-434f-92f4-9fe09290afba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340741396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.1340741396 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.190064732 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 14339234592 ps |
| CPU time | 156 seconds |
| Started | Jun 30 08:12:25 PM PDT 24 |
| Finished | Jun 30 08:15:01 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-916e1777-7a57-418c-85ec-702086a631a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190064732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.190064732 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.4077516012 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 22323645451 ps |
| CPU time | 399.25 seconds |
| Started | Jun 30 08:12:25 PM PDT 24 |
| Finished | Jun 30 08:19:05 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-45181512-79db-4ed1-a43e-a6b031a8a685 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077516012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.4077516012 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1814316117 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 223593733 ps |
| CPU time | 22.96 seconds |
| Started | Jun 30 08:12:19 PM PDT 24 |
| Finished | Jun 30 08:12:42 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-0e242699-90b6-44be-8bf4-0cc285ca7c6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814316117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.1814316117 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.3106902091 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 979365197 ps |
| CPU time | 32.82 seconds |
| Started | Jun 30 08:12:25 PM PDT 24 |
| Finished | Jun 30 08:12:59 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-366152f7-891c-4377-a881-79f0f7e16d70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106902091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3106902091 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.1584478673 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 221189937 ps |
| CPU time | 10.37 seconds |
| Started | Jun 30 08:12:12 PM PDT 24 |
| Finished | Jun 30 08:12:23 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-2ea8740f-5842-4720-a92e-d50f7abe91a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584478673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1584478673 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1673653185 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 8374282987 ps |
| CPU time | 95.34 seconds |
| Started | Jun 30 08:12:24 PM PDT 24 |
| Finished | Jun 30 08:13:59 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-3fb1ed1a-accc-4ee6-b0f2-cb5696a0fef8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673653185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1673653185 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.69878541 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 5313045011 ps |
| CPU time | 91.62 seconds |
| Started | Jun 30 08:12:20 PM PDT 24 |
| Finished | Jun 30 08:13:52 PM PDT 24 |
| Peak memory | 565996 kb |
| Host | smart-66586275-7271-40b6-a961-b84db62a083b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69878541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.69878541 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1317824662 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 52529333 ps |
| CPU time | 6.83 seconds |
| Started | Jun 30 08:12:18 PM PDT 24 |
| Finished | Jun 30 08:12:25 PM PDT 24 |
| Peak memory | 565920 kb |
| Host | smart-bc955513-225e-4951-9291-bce98c0bee24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317824662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.1317824662 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.337476311 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1701030587 ps |
| CPU time | 175.85 seconds |
| Started | Jun 30 08:12:32 PM PDT 24 |
| Finished | Jun 30 08:15:28 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-7087f582-0d97-47cb-9803-7251c4826451 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337476311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.337476311 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1818456161 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 5451882520 ps |
| CPU time | 202.78 seconds |
| Started | Jun 30 08:12:30 PM PDT 24 |
| Finished | Jun 30 08:15:54 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-f67fafc5-6cd1-4306-9444-7ddda156465e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818456161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1818456161 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1113208014 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 668859754 ps |
| CPU time | 221.24 seconds |
| Started | Jun 30 08:12:33 PM PDT 24 |
| Finished | Jun 30 08:16:15 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-75ab50f2-1e42-4888-aea1-00dea475e610 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113208014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.1113208014 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3300438490 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 2513355866 ps |
| CPU time | 293.99 seconds |
| Started | Jun 30 08:12:32 PM PDT 24 |
| Finished | Jun 30 08:17:26 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-02be6d88-ae6d-40d3-bfd2-d447122512fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300438490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.3300438490 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.868035915 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 282694125 ps |
| CPU time | 37.14 seconds |
| Started | Jun 30 08:12:25 PM PDT 24 |
| Finished | Jun 30 08:13:03 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-fa21e1b3-9163-403e-b2fd-e746a4caf1dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868035915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.868035915 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.2109503194 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 4619486522 ps |
| CPU time | 317.74 seconds |
| Started | Jun 30 08:13:05 PM PDT 24 |
| Finished | Jun 30 08:18:23 PM PDT 24 |
| Peak memory | 595632 kb |
| Host | smart-2ab65672-c8ab-481c-8093-849b94571b41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109503194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.2109503194 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3082985217 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 15439506648 ps |
| CPU time | 1972.12 seconds |
| Started | Jun 30 08:12:31 PM PDT 24 |
| Finished | Jun 30 08:45:24 PM PDT 24 |
| Peak memory | 591764 kb |
| Host | smart-6cc3dcc3-b8e2-4358-935c-36d675c08640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082985217 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.3082985217 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.566973852 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 1866686332 ps |
| CPU time | 84.43 seconds |
| Started | Jun 30 08:12:43 PM PDT 24 |
| Finished | Jun 30 08:14:08 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-26116d24-8740-4cac-860a-5701237fcf28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566973852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device. 566973852 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1516844593 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 148516895244 ps |
| CPU time | 2671.43 seconds |
| Started | Jun 30 08:12:42 PM PDT 24 |
| Finished | Jun 30 08:57:14 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-353746b4-763f-4c4e-b331-5df1846f4feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516844593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.1516844593 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3084424402 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 757865807 ps |
| CPU time | 35.84 seconds |
| Started | Jun 30 08:12:50 PM PDT 24 |
| Finished | Jun 30 08:13:27 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-c6e8f709-a86b-428a-95de-4b1c66f9fb84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084424402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.3084424402 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.1642047660 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 549885498 ps |
| CPU time | 47.88 seconds |
| Started | Jun 30 08:12:50 PM PDT 24 |
| Finished | Jun 30 08:13:38 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-be8ec32a-1144-4895-853f-8ebdd55ff5d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642047660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1642047660 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.2978836845 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 272134802 ps |
| CPU time | 26.79 seconds |
| Started | Jun 30 08:12:40 PM PDT 24 |
| Finished | Jun 30 08:13:08 PM PDT 24 |
| Peak memory | 575184 kb |
| Host | smart-1d1f1735-e471-4963-973c-503cb89671e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978836845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.2978836845 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3475621540 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 75895081743 ps |
| CPU time | 809.31 seconds |
| Started | Jun 30 08:12:41 PM PDT 24 |
| Finished | Jun 30 08:26:11 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-a17703d7-78fa-4fc8-8552-88568c8a7fd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475621540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3475621540 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1703997636 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 41074431482 ps |
| CPU time | 751.91 seconds |
| Started | Jun 30 08:12:42 PM PDT 24 |
| Finished | Jun 30 08:25:15 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-1dcbf7fa-68ae-492c-a98a-4d91f8317fed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703997636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1703997636 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3815005984 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 250639773 ps |
| CPU time | 26.24 seconds |
| Started | Jun 30 08:12:39 PM PDT 24 |
| Finished | Jun 30 08:13:06 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-76790392-e8c2-447c-adf4-14a946015de6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815005984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.3815005984 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.1018342040 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 2654075138 ps |
| CPU time | 92.77 seconds |
| Started | Jun 30 08:12:50 PM PDT 24 |
| Finished | Jun 30 08:14:23 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-45347de6-7352-4269-80ef-9ebfc991b4b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018342040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1018342040 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.673106258 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 237663760 ps |
| CPU time | 11.64 seconds |
| Started | Jun 30 08:12:35 PM PDT 24 |
| Finished | Jun 30 08:12:48 PM PDT 24 |
| Peak memory | 565968 kb |
| Host | smart-884a304b-5028-4ae2-8aa4-00e071ed43f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673106258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.673106258 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2489162068 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 10527583038 ps |
| CPU time | 108.19 seconds |
| Started | Jun 30 08:12:36 PM PDT 24 |
| Finished | Jun 30 08:14:25 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-aad52be3-b974-420f-827a-9a0c47dd1957 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489162068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2489162068 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1452006342 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 6423889280 ps |
| CPU time | 111.45 seconds |
| Started | Jun 30 08:12:36 PM PDT 24 |
| Finished | Jun 30 08:14:28 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-671929ec-2829-4c6b-9f54-22c4f404d735 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452006342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1452006342 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2066300502 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 52222555 ps |
| CPU time | 6.89 seconds |
| Started | Jun 30 08:12:36 PM PDT 24 |
| Finished | Jun 30 08:12:44 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-8728d12e-e32f-49f5-9d51-4e93cfa0dd2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066300502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.2066300502 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.731950245 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1579173249 ps |
| CPU time | 134.58 seconds |
| Started | Jun 30 08:12:54 PM PDT 24 |
| Finished | Jun 30 08:15:08 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-094b632f-992e-46d5-8f7d-fe153fe04fb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731950245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.731950245 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2227077259 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 4501148128 ps |
| CPU time | 171.9 seconds |
| Started | Jun 30 08:12:55 PM PDT 24 |
| Finished | Jun 30 08:15:47 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-95007ed7-3557-44d3-9d94-188220b1c0ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227077259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2227077259 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1284752627 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 3863590933 ps |
| CPU time | 555.6 seconds |
| Started | Jun 30 08:12:55 PM PDT 24 |
| Finished | Jun 30 08:22:11 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-b9d31a98-7c6f-4c89-93a5-4e9be396577d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284752627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.1284752627 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2864567006 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 2047483443 ps |
| CPU time | 210.79 seconds |
| Started | Jun 30 08:13:00 PM PDT 24 |
| Finished | Jun 30 08:16:32 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-bb3170da-3ae4-4653-a6b4-a0c8b123b8b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864567006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.2864567006 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.3053076587 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 392012783 ps |
| CPU time | 20.6 seconds |
| Started | Jun 30 08:12:48 PM PDT 24 |
| Finished | Jun 30 08:13:09 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-9290c942-672b-4169-86fe-e29f1e91e657 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053076587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3053076587 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.2833903037 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 5490549560 ps |
| CPU time | 720.91 seconds |
| Started | Jun 30 08:13:18 PM PDT 24 |
| Finished | Jun 30 08:25:19 PM PDT 24 |
| Peak memory | 597208 kb |
| Host | smart-1d015ed1-a5ae-497d-a18f-50ed992a58ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833903037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.2833903037 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.18225005 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 2346276867 ps |
| CPU time | 102.73 seconds |
| Started | Jun 30 08:13:07 PM PDT 24 |
| Finished | Jun 30 08:14:50 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-c4dfb625-8d5a-41dc-961b-febbabb90890 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18225005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.18225005 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.303758278 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 10218891711 ps |
| CPU time | 166.21 seconds |
| Started | Jun 30 08:13:06 PM PDT 24 |
| Finished | Jun 30 08:15:53 PM PDT 24 |
| Peak memory | 566044 kb |
| Host | smart-c7ebbf46-460a-4993-bdf4-e6e210bfeb45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303758278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_d evice_slow_rsp.303758278 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3102721489 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 64037654 ps |
| CPU time | 6.2 seconds |
| Started | Jun 30 08:13:15 PM PDT 24 |
| Finished | Jun 30 08:13:21 PM PDT 24 |
| Peak memory | 565956 kb |
| Host | smart-78bc5abd-35e5-4827-96ca-6d84bd863bc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102721489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.3102721489 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.994693064 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 305068676 ps |
| CPU time | 28.78 seconds |
| Started | Jun 30 08:13:12 PM PDT 24 |
| Finished | Jun 30 08:13:41 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-04a24b30-98c6-4724-992d-9516b9611eb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994693064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.994693064 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.2631234640 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 614496737 ps |
| CPU time | 58.06 seconds |
| Started | Jun 30 08:13:06 PM PDT 24 |
| Finished | Jun 30 08:14:05 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-0f8c6510-dd0c-48e2-a6c9-163753b149a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631234640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.2631234640 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2603666826 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 21129393849 ps |
| CPU time | 252.19 seconds |
| Started | Jun 30 08:13:06 PM PDT 24 |
| Finished | Jun 30 08:17:19 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-e12cb267-9fea-4bdc-8dde-18dee95fdbdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603666826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2603666826 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.3909163276 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 47790259578 ps |
| CPU time | 837.29 seconds |
| Started | Jun 30 08:13:06 PM PDT 24 |
| Finished | Jun 30 08:27:04 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-6fc498af-eb7d-4546-b104-3289f702eb0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909163276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3909163276 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.4224190127 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 41359978 ps |
| CPU time | 7.35 seconds |
| Started | Jun 30 08:13:06 PM PDT 24 |
| Finished | Jun 30 08:13:14 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-fd62c88d-419a-4645-9915-d05c616f8b72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224190127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.4224190127 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.472754937 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 389424296 ps |
| CPU time | 33.84 seconds |
| Started | Jun 30 08:13:06 PM PDT 24 |
| Finished | Jun 30 08:13:41 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-dddb89cd-df51-4fd7-9472-242e6c68787e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472754937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.472754937 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.3495552393 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 185739534 ps |
| CPU time | 9.59 seconds |
| Started | Jun 30 08:13:00 PM PDT 24 |
| Finished | Jun 30 08:13:11 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-7225a898-c48c-4794-a444-5d9260bc9c79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495552393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3495552393 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.1233025685 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 8217431047 ps |
| CPU time | 89.23 seconds |
| Started | Jun 30 08:13:03 PM PDT 24 |
| Finished | Jun 30 08:14:33 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-d824ac2e-4d68-4c05-9b3f-4591826b2329 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233025685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1233025685 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2967522948 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 6134885623 ps |
| CPU time | 108.86 seconds |
| Started | Jun 30 08:13:00 PM PDT 24 |
| Finished | Jun 30 08:14:49 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-b15ac093-f422-41b6-8d2c-a08428bc263d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967522948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2967522948 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.733848146 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 54156752 ps |
| CPU time | 6.75 seconds |
| Started | Jun 30 08:13:02 PM PDT 24 |
| Finished | Jun 30 08:13:10 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-85aa9f81-e9e2-4527-acc7-b44dbef5b640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733848146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays .733848146 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.2270852000 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 9948976199 ps |
| CPU time | 435.05 seconds |
| Started | Jun 30 08:13:14 PM PDT 24 |
| Finished | Jun 30 08:20:29 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-2e1bfc42-6f2a-4b66-8080-2ec89e9da1be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270852000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2270852000 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.3059224429 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 1113924528 ps |
| CPU time | 43.37 seconds |
| Started | Jun 30 08:13:16 PM PDT 24 |
| Finished | Jun 30 08:14:00 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-9d6dbedb-3715-4355-b6d2-ef9661fee767 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059224429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3059224429 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1199670073 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 2275343320 ps |
| CPU time | 301.65 seconds |
| Started | Jun 30 08:13:13 PM PDT 24 |
| Finished | Jun 30 08:18:15 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-c27ef793-4dde-4d77-bed5-459c454de5b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199670073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.1199670073 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3445682953 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 501828891 ps |
| CPU time | 213.67 seconds |
| Started | Jun 30 08:13:17 PM PDT 24 |
| Finished | Jun 30 08:16:51 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-ca85eb5a-9660-4312-8726-1aa80b5e8063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445682953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.3445682953 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.828756428 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 387714843 ps |
| CPU time | 19.94 seconds |
| Started | Jun 30 08:13:13 PM PDT 24 |
| Finished | Jun 30 08:13:33 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-5628830a-c057-47fa-a365-7838d0187af4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828756428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.828756428 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.474996968 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 4870433435 ps |
| CPU time | 357.1 seconds |
| Started | Jun 30 08:13:41 PM PDT 24 |
| Finished | Jun 30 08:19:38 PM PDT 24 |
| Peak memory | 596112 kb |
| Host | smart-9b270eea-9249-464b-be72-7aebe20e701b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474996968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.474996968 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3359922904 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 26662417344 ps |
| CPU time | 3669.97 seconds |
| Started | Jun 30 08:13:18 PM PDT 24 |
| Finished | Jun 30 09:14:29 PM PDT 24 |
| Peak memory | 591852 kb |
| Host | smart-0e525ac5-d580-4a3a-8cc8-99483437ce32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359922904 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.3359922904 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.225715474 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 829692364 ps |
| CPU time | 62.15 seconds |
| Started | Jun 30 08:13:28 PM PDT 24 |
| Finished | Jun 30 08:14:31 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-b2250102-6de8-4947-a1b2-a48c75bab1d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225715474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device. 225715474 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3537263555 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 35037346374 ps |
| CPU time | 631.5 seconds |
| Started | Jun 30 08:13:28 PM PDT 24 |
| Finished | Jun 30 08:24:00 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-78c0b020-d46c-4042-9734-3abd15c575be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537263555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.3537263555 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2103864821 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 306424353 ps |
| CPU time | 38.84 seconds |
| Started | Jun 30 08:13:34 PM PDT 24 |
| Finished | Jun 30 08:14:13 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-a241eb90-227f-4531-a65b-9d95e42b72bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103864821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.2103864821 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.2526993056 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 95255467 ps |
| CPU time | 11.5 seconds |
| Started | Jun 30 08:13:37 PM PDT 24 |
| Finished | Jun 30 08:13:48 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-3c3277e9-963b-43d3-b428-679a287da900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526993056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2526993056 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.369531591 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 590743486 ps |
| CPU time | 55.95 seconds |
| Started | Jun 30 08:13:22 PM PDT 24 |
| Finished | Jun 30 08:14:18 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-1b4a841d-92de-4897-9cbd-b8a4e198eab5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369531591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.369531591 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.2423930594 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 21201787723 ps |
| CPU time | 224.95 seconds |
| Started | Jun 30 08:13:27 PM PDT 24 |
| Finished | Jun 30 08:17:12 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-9b1c4e69-7eef-4fdd-9ddd-87385924d25c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423930594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2423930594 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.3780405469 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 8612345782 ps |
| CPU time | 155.07 seconds |
| Started | Jun 30 08:13:28 PM PDT 24 |
| Finished | Jun 30 08:16:04 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-e8318b70-b3c9-4c05-9e1c-4507f9568d6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780405469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3780405469 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.75480965 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 281235751 ps |
| CPU time | 29.04 seconds |
| Started | Jun 30 08:13:21 PM PDT 24 |
| Finished | Jun 30 08:13:51 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-ff8b96ea-b0f7-43f7-a4ce-2b69dc4e1711 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75480965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delay s.75480965 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.2143835850 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 1070943878 ps |
| CPU time | 38.17 seconds |
| Started | Jun 30 08:13:34 PM PDT 24 |
| Finished | Jun 30 08:14:13 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-99a195a7-e145-430c-8852-c39f8f9722c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143835850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2143835850 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.3266359971 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 225550676 ps |
| CPU time | 11.19 seconds |
| Started | Jun 30 08:13:17 PM PDT 24 |
| Finished | Jun 30 08:13:28 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-54c18ab7-7c51-4f1e-b5ea-2d18d1489f06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266359971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3266359971 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.3849987670 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 9535764400 ps |
| CPU time | 105.21 seconds |
| Started | Jun 30 08:13:22 PM PDT 24 |
| Finished | Jun 30 08:15:07 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-d1c83846-bc65-4d2a-9dfd-ba5476538c57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849987670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3849987670 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.820720114 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 5418603611 ps |
| CPU time | 97.5 seconds |
| Started | Jun 30 08:13:22 PM PDT 24 |
| Finished | Jun 30 08:15:00 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-aacc4827-0627-4bd8-ba86-eead42a4e2b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820720114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.820720114 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.465348472 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 52183328 ps |
| CPU time | 7.18 seconds |
| Started | Jun 30 08:13:16 PM PDT 24 |
| Finished | Jun 30 08:13:24 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-a7875ad8-7307-4237-b04e-57f2da0277e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465348472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays .465348472 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.1073796084 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 12758708873 ps |
| CPU time | 519.03 seconds |
| Started | Jun 30 08:13:36 PM PDT 24 |
| Finished | Jun 30 08:22:16 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-d92db430-339e-4de5-91a5-586621bc52a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073796084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1073796084 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.3217852107 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 1711815115 ps |
| CPU time | 77.34 seconds |
| Started | Jun 30 08:13:41 PM PDT 24 |
| Finished | Jun 30 08:14:59 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-d8d0c0bc-c5dd-4e8f-bbbe-bfa18e4fc743 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217852107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3217852107 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1914664540 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 938104090 ps |
| CPU time | 410.47 seconds |
| Started | Jun 30 08:13:33 PM PDT 24 |
| Finished | Jun 30 08:20:24 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-78586db3-6775-4076-a539-9a0e67b94f43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914664540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.1914664540 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.36904523 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 9704529122 ps |
| CPU time | 426.15 seconds |
| Started | Jun 30 08:13:39 PM PDT 24 |
| Finished | Jun 30 08:20:46 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-10311e6d-9d98-45bf-b2e0-d0d76d84d814 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36904523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_ with_reset_error.36904523 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.2376098847 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 877535484 ps |
| CPU time | 40.2 seconds |
| Started | Jun 30 08:13:35 PM PDT 24 |
| Finished | Jun 30 08:14:15 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-44972608-15e7-4f01-8c72-2cc714d09683 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376098847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2376098847 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.1968638808 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 4954727400 ps |
| CPU time | 408.42 seconds |
| Started | Jun 30 08:14:09 PM PDT 24 |
| Finished | Jun 30 08:20:58 PM PDT 24 |
| Peak memory | 595684 kb |
| Host | smart-7eb96a18-2650-403f-8b4c-8cba15d6c5fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968638808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.1968638808 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.1545886200 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 3209123406 ps |
| CPU time | 221.65 seconds |
| Started | Jun 30 08:13:44 PM PDT 24 |
| Finished | Jun 30 08:17:26 PM PDT 24 |
| Peak memory | 597424 kb |
| Host | smart-d63cf0e5-7d3d-4eee-9814-e7cc50f71ee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545886200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.1545886200 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.2317135726 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 529184968 ps |
| CPU time | 22.41 seconds |
| Started | Jun 30 08:13:50 PM PDT 24 |
| Finished | Jun 30 08:14:13 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-667d8428-b849-47bb-b8e6-423e41e086da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317135726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .2317135726 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3892309050 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 59888095187 ps |
| CPU time | 1065.12 seconds |
| Started | Jun 30 08:13:58 PM PDT 24 |
| Finished | Jun 30 08:31:44 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-c7fec766-3285-4383-beef-cda08e51a469 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892309050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.3892309050 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3246209227 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 202267480 ps |
| CPU time | 24.58 seconds |
| Started | Jun 30 08:13:56 PM PDT 24 |
| Finished | Jun 30 08:14:21 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-cf3fbf81-24d7-4c83-aaf3-7fd11e7c7a7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246209227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.3246209227 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.4243356806 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 2707228014 ps |
| CPU time | 103.35 seconds |
| Started | Jun 30 08:13:57 PM PDT 24 |
| Finished | Jun 30 08:15:41 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-e5a4bd4b-667d-4372-b98f-0aee8ce5b4aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243356806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.4243356806 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.461075572 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 2613198735 ps |
| CPU time | 109.75 seconds |
| Started | Jun 30 08:13:45 PM PDT 24 |
| Finished | Jun 30 08:15:35 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-c62d46d3-44bf-4886-9c65-6d4f3d18f60f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461075572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.461075572 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.26425543 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 20737016954 ps |
| CPU time | 227.41 seconds |
| Started | Jun 30 08:13:52 PM PDT 24 |
| Finished | Jun 30 08:17:39 PM PDT 24 |
| Peak memory | 575144 kb |
| Host | smart-f9622643-e158-4e44-a418-c6d56fc7d434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26425543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.26425543 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.4178818494 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 5125398751 ps |
| CPU time | 90.01 seconds |
| Started | Jun 30 08:13:50 PM PDT 24 |
| Finished | Jun 30 08:15:20 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-ed8ccd04-c567-4bda-8145-27aede49a031 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178818494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.4178818494 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.802707081 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 61654850 ps |
| CPU time | 9.69 seconds |
| Started | Jun 30 08:13:44 PM PDT 24 |
| Finished | Jun 30 08:13:54 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-486caf01-62be-40f7-a015-e8df2f1c91de |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802707081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_dela ys.802707081 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.3849041165 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 1923315366 ps |
| CPU time | 65.48 seconds |
| Started | Jun 30 08:13:57 PM PDT 24 |
| Finished | Jun 30 08:15:03 PM PDT 24 |
| Peak memory | 575088 kb |
| Host | smart-289ddd63-30cf-4bc2-b567-9ad8a365c884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849041165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3849041165 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.742865780 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 213035864 ps |
| CPU time | 9.87 seconds |
| Started | Jun 30 08:13:45 PM PDT 24 |
| Finished | Jun 30 08:13:55 PM PDT 24 |
| Peak memory | 565912 kb |
| Host | smart-fadf3c9d-c20e-4d4f-bf1b-18be00d6652c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742865780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.742865780 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.3258048797 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 7678844550 ps |
| CPU time | 86.37 seconds |
| Started | Jun 30 08:13:46 PM PDT 24 |
| Finished | Jun 30 08:15:12 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-72bcc84a-4a27-4c51-a9f9-fc6511444a5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258048797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3258048797 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.404972766 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 6595851637 ps |
| CPU time | 116.77 seconds |
| Started | Jun 30 08:13:43 PM PDT 24 |
| Finished | Jun 30 08:15:40 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-a5e7f5bc-ef29-4fee-a596-73fae868cfef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404972766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.404972766 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2560504782 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 46889128 ps |
| CPU time | 6.97 seconds |
| Started | Jun 30 08:13:46 PM PDT 24 |
| Finished | Jun 30 08:13:53 PM PDT 24 |
| Peak memory | 565864 kb |
| Host | smart-e26409ff-bca4-4596-bad6-7ae6ab26c67a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560504782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.2560504782 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.3443751858 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 11704472268 ps |
| CPU time | 475.33 seconds |
| Started | Jun 30 08:14:09 PM PDT 24 |
| Finished | Jun 30 08:22:05 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-164088f2-6ecc-4562-8b3a-e3e8d6ee8d31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443751858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3443751858 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.2518945010 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 3785494858 ps |
| CPU time | 157.77 seconds |
| Started | Jun 30 08:14:03 PM PDT 24 |
| Finished | Jun 30 08:16:42 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-b4817e3d-3e06-4747-bae9-45bd256a79b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518945010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2518945010 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.1939205053 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 298874247 ps |
| CPU time | 155.07 seconds |
| Started | Jun 30 08:14:02 PM PDT 24 |
| Finished | Jun 30 08:16:38 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-34135ecc-a301-44db-b07c-2ae2e2774adc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939205053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.1939205053 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.2943674302 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 4678508490 ps |
| CPU time | 572.06 seconds |
| Started | Jun 30 08:14:05 PM PDT 24 |
| Finished | Jun 30 08:23:37 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-d9c4fbdf-f83a-4f9f-901f-2ab03e1e3173 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943674302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.2943674302 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.567848467 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 343812468 ps |
| CPU time | 19.53 seconds |
| Started | Jun 30 08:13:55 PM PDT 24 |
| Finished | Jun 30 08:14:15 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-2792b4b0-c4b7-44d7-b317-650ace9e7eac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567848467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.567848467 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.3428937804 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 4183336947 ps |
| CPU time | 362.04 seconds |
| Started | Jun 30 08:14:18 PM PDT 24 |
| Finished | Jun 30 08:20:21 PM PDT 24 |
| Peak memory | 595488 kb |
| Host | smart-30693bc3-93b8-4a85-ba79-dc0f7480b48d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428937804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.3428937804 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.2267478080 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 16296667124 ps |
| CPU time | 1769.21 seconds |
| Started | Jun 30 08:14:10 PM PDT 24 |
| Finished | Jun 30 08:43:40 PM PDT 24 |
| Peak memory | 591456 kb |
| Host | smart-5167c96e-bc04-414b-b0e2-db1897018add |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267478080 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.2267478080 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.1120618659 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 3326281800 ps |
| CPU time | 197.69 seconds |
| Started | Jun 30 08:14:07 PM PDT 24 |
| Finished | Jun 30 08:17:25 PM PDT 24 |
| Peak memory | 603636 kb |
| Host | smart-63546a3f-bbb9-4e8e-80c9-0a16d31f43f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120618659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.1120618659 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.4111453711 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 713409936 ps |
| CPU time | 56.27 seconds |
| Started | Jun 30 08:14:14 PM PDT 24 |
| Finished | Jun 30 08:15:11 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-6f64e806-640e-44b3-8f48-53897a51ea94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111453711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .4111453711 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.241064576 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 99509554134 ps |
| CPU time | 1819.44 seconds |
| Started | Jun 30 08:14:15 PM PDT 24 |
| Finished | Jun 30 08:44:35 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-a5a3f968-d012-477a-b284-72599ac17e65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241064576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_d evice_slow_rsp.241064576 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2482565087 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 173472579 ps |
| CPU time | 21.73 seconds |
| Started | Jun 30 08:14:18 PM PDT 24 |
| Finished | Jun 30 08:14:41 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-560eff37-7d48-4670-8cb8-7cf086e557ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482565087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.2482565087 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.3036512738 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 57756229 ps |
| CPU time | 8.16 seconds |
| Started | Jun 30 08:14:14 PM PDT 24 |
| Finished | Jun 30 08:14:23 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-acfc9c4c-139b-4658-b7bd-ac9f93a7caa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036512738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3036512738 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.1932413168 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 520522185 ps |
| CPU time | 52.91 seconds |
| Started | Jun 30 08:14:13 PM PDT 24 |
| Finished | Jun 30 08:15:06 PM PDT 24 |
| Peak memory | 575200 kb |
| Host | smart-bd51a83c-61a4-468a-a279-2d904936ce6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932413168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.1932413168 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.629362720 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 21762863483 ps |
| CPU time | 217.57 seconds |
| Started | Jun 30 08:14:13 PM PDT 24 |
| Finished | Jun 30 08:17:51 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-1835c4a1-55df-40f2-ba8d-e8c81a817f12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629362720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.629362720 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.697463273 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 28221523496 ps |
| CPU time | 465.71 seconds |
| Started | Jun 30 08:14:16 PM PDT 24 |
| Finished | Jun 30 08:22:02 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-8236a0fe-a970-46f1-af5c-f7533dd42073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697463273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.697463273 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.3263326927 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 32770413 ps |
| CPU time | 7.11 seconds |
| Started | Jun 30 08:14:14 PM PDT 24 |
| Finished | Jun 30 08:14:21 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-fd1c7acf-c7fd-4fc7-9f44-e4a6edf5dfb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263326927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.3263326927 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.754652169 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 546187628 ps |
| CPU time | 19.61 seconds |
| Started | Jun 30 08:14:14 PM PDT 24 |
| Finished | Jun 30 08:14:34 PM PDT 24 |
| Peak memory | 575200 kb |
| Host | smart-bca4fb4b-598a-4b8e-acb6-86c60bd8a8e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754652169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.754652169 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.1981180968 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 211638377 ps |
| CPU time | 9.71 seconds |
| Started | Jun 30 08:14:10 PM PDT 24 |
| Finished | Jun 30 08:14:20 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-71e9246c-4086-4bd6-9501-e0c78d24efae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981180968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1981180968 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1979691658 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 5396750087 ps |
| CPU time | 58.82 seconds |
| Started | Jun 30 08:14:10 PM PDT 24 |
| Finished | Jun 30 08:15:09 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-e2a1b4d3-be0a-4071-8211-12ab1a7fce96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979691658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1979691658 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1175418951 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 5109072373 ps |
| CPU time | 90.45 seconds |
| Started | Jun 30 08:14:08 PM PDT 24 |
| Finished | Jun 30 08:15:39 PM PDT 24 |
| Peak memory | 565992 kb |
| Host | smart-980dcd83-63cf-4082-8093-c4362217bf83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175418951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1175418951 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1231447133 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 43453251 ps |
| CPU time | 6.67 seconds |
| Started | Jun 30 08:14:10 PM PDT 24 |
| Finished | Jun 30 08:14:18 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-0d847c8d-d1d8-4ee3-bd7c-e4272bf9472f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231447133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.1231447133 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.2109755795 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 3423880528 ps |
| CPU time | 142.35 seconds |
| Started | Jun 30 08:14:21 PM PDT 24 |
| Finished | Jun 30 08:16:44 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-ce6eed84-6d6c-4fe1-8907-ebd0869cdd64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109755795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2109755795 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.3530702297 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 2598033243 ps |
| CPU time | 90.96 seconds |
| Started | Jun 30 08:14:19 PM PDT 24 |
| Finished | Jun 30 08:15:50 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-e88841f5-5d54-4046-b280-ea47f484c03f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530702297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3530702297 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.2584950431 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 6304015700 ps |
| CPU time | 702.11 seconds |
| Started | Jun 30 08:14:18 PM PDT 24 |
| Finished | Jun 30 08:26:01 PM PDT 24 |
| Peak memory | 581756 kb |
| Host | smart-f8fc353f-1187-45ce-9a55-e86c43bd3411 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584950431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al l_with_reset_error.2584950431 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.79852714 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 177767175 ps |
| CPU time | 26.25 seconds |
| Started | Jun 30 08:14:18 PM PDT 24 |
| Finished | Jun 30 08:14:45 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-d5707603-1dad-482f-9d17-d58cb31e926b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79852714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.79852714 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.3979504895 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 5926160239 ps |
| CPU time | 782.39 seconds |
| Started | Jun 30 08:14:42 PM PDT 24 |
| Finished | Jun 30 08:27:45 PM PDT 24 |
| Peak memory | 597212 kb |
| Host | smart-942761a6-5dba-4cf0-9683-97b391d4bbd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979504895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.3979504895 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1832419049 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 30943165660 ps |
| CPU time | 3846.63 seconds |
| Started | Jun 30 08:14:22 PM PDT 24 |
| Finished | Jun 30 09:18:29 PM PDT 24 |
| Peak memory | 591768 kb |
| Host | smart-feedc989-9dcd-4416-a557-f3e1ed4655a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832419049 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.1832419049 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.4086902543 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 3613092000 ps |
| CPU time | 184.47 seconds |
| Started | Jun 30 08:14:27 PM PDT 24 |
| Finished | Jun 30 08:17:32 PM PDT 24 |
| Peak memory | 603560 kb |
| Host | smart-34700196-5e28-452e-88a8-6c490cd8b1e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086902543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.4086902543 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.983563965 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 2476376466 ps |
| CPU time | 128.32 seconds |
| Started | Jun 30 08:14:31 PM PDT 24 |
| Finished | Jun 30 08:16:40 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-5822d2c7-9465-4e12-886d-70bf552e95d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983563965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device. 983563965 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.4047779496 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 87815118948 ps |
| CPU time | 1580.13 seconds |
| Started | Jun 30 08:14:32 PM PDT 24 |
| Finished | Jun 30 08:40:52 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-7b152f52-4cd6-440e-a350-b7175488d6a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047779496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.4047779496 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2129030223 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 412440335 ps |
| CPU time | 19.89 seconds |
| Started | Jun 30 08:14:42 PM PDT 24 |
| Finished | Jun 30 08:15:03 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-02c0270e-adc7-4f07-acfe-46bd452d9aad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129030223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.2129030223 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.562033049 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 514552039 ps |
| CPU time | 21.86 seconds |
| Started | Jun 30 08:14:30 PM PDT 24 |
| Finished | Jun 30 08:14:53 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-9b8d666c-f65d-45ae-83df-a4188f801bab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562033049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.562033049 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.1617977209 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 548261000 ps |
| CPU time | 55.09 seconds |
| Started | Jun 30 08:14:27 PM PDT 24 |
| Finished | Jun 30 08:15:22 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-b6f0dde7-a5c5-4ca9-8891-d5586379fc16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617977209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.1617977209 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.3971777236 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 23902995270 ps |
| CPU time | 252.29 seconds |
| Started | Jun 30 08:14:26 PM PDT 24 |
| Finished | Jun 30 08:18:39 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-55c93779-8a47-4899-86ab-adfebd4c8663 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971777236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3971777236 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.2091782226 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 10085347172 ps |
| CPU time | 170.72 seconds |
| Started | Jun 30 08:14:30 PM PDT 24 |
| Finished | Jun 30 08:17:21 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-4c5c12a9-517a-4564-827b-e795f7bae730 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091782226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2091782226 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.1063797628 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 498266748 ps |
| CPU time | 47.86 seconds |
| Started | Jun 30 08:14:26 PM PDT 24 |
| Finished | Jun 30 08:15:15 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-7919f3ba-834c-4729-8964-bfedbe1eb95c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063797628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.1063797628 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.2167312876 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 268149760 ps |
| CPU time | 24.87 seconds |
| Started | Jun 30 08:14:31 PM PDT 24 |
| Finished | Jun 30 08:14:57 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-4048bfe1-c900-401a-90ae-2ca420f1446b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167312876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2167312876 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.17306658 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 46753488 ps |
| CPU time | 6.72 seconds |
| Started | Jun 30 08:14:25 PM PDT 24 |
| Finished | Jun 30 08:14:32 PM PDT 24 |
| Peak memory | 565904 kb |
| Host | smart-5bf1e5bf-69b2-440e-9626-34f5cb26d342 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17306658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.17306658 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.300600845 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 8878388677 ps |
| CPU time | 97.32 seconds |
| Started | Jun 30 08:14:26 PM PDT 24 |
| Finished | Jun 30 08:16:04 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-e4c8dcf7-b850-466a-ab93-c558122e3c17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300600845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.300600845 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2825938174 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 5721142960 ps |
| CPU time | 95.11 seconds |
| Started | Jun 30 08:14:25 PM PDT 24 |
| Finished | Jun 30 08:16:01 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-179cb244-7088-4a5a-a20f-af51473e2304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825938174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2825938174 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.2248358171 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 53049998 ps |
| CPU time | 7.31 seconds |
| Started | Jun 30 08:14:26 PM PDT 24 |
| Finished | Jun 30 08:14:34 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-eb212962-a07d-403b-b615-d5ffe1a91de4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248358171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.2248358171 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.1807718595 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 125248076 ps |
| CPU time | 14.29 seconds |
| Started | Jun 30 08:14:40 PM PDT 24 |
| Finished | Jun 30 08:14:55 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-4fd910dc-b382-4547-8caa-3ae719e3a2d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807718595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1807718595 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.1721649889 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 1582375275 ps |
| CPU time | 129.18 seconds |
| Started | Jun 30 08:14:42 PM PDT 24 |
| Finished | Jun 30 08:16:52 PM PDT 24 |
| Peak memory | 574576 kb |
| Host | smart-f7104184-468b-48a6-bc70-615eb9c6153d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721649889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1721649889 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.459525106 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 6162368008 ps |
| CPU time | 743.8 seconds |
| Started | Jun 30 08:14:36 PM PDT 24 |
| Finished | Jun 30 08:27:00 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-1317ec2f-d151-4ff6-adc8-60c05a45068c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459525106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_ with_rand_reset.459525106 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.713784108 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 3188858024 ps |
| CPU time | 359.37 seconds |
| Started | Jun 30 08:14:39 PM PDT 24 |
| Finished | Jun 30 08:20:38 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-598071f1-019c-4181-9b2f-bafda2aba071 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713784108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_reset_error.713784108 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.2902473723 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 1098525696 ps |
| CPU time | 50.94 seconds |
| Started | Jun 30 08:14:37 PM PDT 24 |
| Finished | Jun 30 08:15:28 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-2686ede7-6636-4247-a57f-b28913c1fd47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902473723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2902473723 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.1057917455 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 3444862415 ps |
| CPU time | 283.75 seconds |
| Started | Jun 30 08:15:00 PM PDT 24 |
| Finished | Jun 30 08:19:44 PM PDT 24 |
| Peak memory | 595676 kb |
| Host | smart-617b0ad3-b044-47a6-a526-0d63dd6edfe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057917455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.1057917455 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.3018191683 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 15558682561 ps |
| CPU time | 1810.14 seconds |
| Started | Jun 30 08:14:44 PM PDT 24 |
| Finished | Jun 30 08:44:55 PM PDT 24 |
| Peak memory | 591756 kb |
| Host | smart-262cb5a8-667f-44d8-92fc-521e314b77f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018191683 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.3018191683 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.1927701193 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 3151380864 ps |
| CPU time | 195.04 seconds |
| Started | Jun 30 08:14:41 PM PDT 24 |
| Finished | Jun 30 08:17:57 PM PDT 24 |
| Peak memory | 603452 kb |
| Host | smart-6b79657e-6581-4501-82b0-b6af43c243ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927701193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.1927701193 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.432967312 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 451777944 ps |
| CPU time | 39.43 seconds |
| Started | Jun 30 08:14:56 PM PDT 24 |
| Finished | Jun 30 08:15:36 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-50826be5-a58c-4c5b-a4b0-f23653d502e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432967312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device. 432967312 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2473589972 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 34881811332 ps |
| CPU time | 657.9 seconds |
| Started | Jun 30 08:14:53 PM PDT 24 |
| Finished | Jun 30 08:25:52 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-fef96b1d-6cdf-444d-9572-b59d6bf74fdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473589972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.2473589972 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1509536203 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 309540854 ps |
| CPU time | 35.43 seconds |
| Started | Jun 30 08:14:55 PM PDT 24 |
| Finished | Jun 30 08:15:31 PM PDT 24 |
| Peak memory | 573844 kb |
| Host | smart-9d899803-296d-40af-973d-6fa3d030364d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509536203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.1509536203 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.3861094673 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 629820304 ps |
| CPU time | 29.39 seconds |
| Started | Jun 30 08:14:54 PM PDT 24 |
| Finished | Jun 30 08:15:24 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-d6d005f3-760d-4e60-8362-df3eb73e3585 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861094673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3861094673 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.2706685953 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 256336350 ps |
| CPU time | 29.01 seconds |
| Started | Jun 30 08:14:42 PM PDT 24 |
| Finished | Jun 30 08:15:11 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-2153d062-aea4-444c-a0e5-d05c6910c373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706685953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.2706685953 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.2636463734 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 43402579308 ps |
| CPU time | 441.51 seconds |
| Started | Jun 30 08:14:47 PM PDT 24 |
| Finished | Jun 30 08:22:09 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-2b79ff26-31cd-48d8-a212-b6790ec99754 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636463734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2636463734 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.3811502892 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 34870211853 ps |
| CPU time | 597.55 seconds |
| Started | Jun 30 08:14:47 PM PDT 24 |
| Finished | Jun 30 08:24:45 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-60c3b5bd-294b-4b56-855a-61bf6258d841 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811502892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3811502892 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.669754289 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 376915215 ps |
| CPU time | 41 seconds |
| Started | Jun 30 08:14:47 PM PDT 24 |
| Finished | Jun 30 08:15:28 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-bc43f97c-d1dd-4587-b986-bc9265830c7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669754289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_dela ys.669754289 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.782999001 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 243551526 ps |
| CPU time | 18.42 seconds |
| Started | Jun 30 08:14:52 PM PDT 24 |
| Finished | Jun 30 08:15:12 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-59724fb0-03d5-4a5d-a6da-eb7df90f975d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782999001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.782999001 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.373009433 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 160873291 ps |
| CPU time | 8.78 seconds |
| Started | Jun 30 08:14:41 PM PDT 24 |
| Finished | Jun 30 08:14:50 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-a4d013ca-0cc5-4eef-9021-e09e87917ed2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373009433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.373009433 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.1778288055 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 8514341633 ps |
| CPU time | 88.01 seconds |
| Started | Jun 30 08:14:42 PM PDT 24 |
| Finished | Jun 30 08:16:10 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-ac4f8e23-1e71-44d8-84e7-01e2f406db33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778288055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1778288055 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3364426330 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 4338526976 ps |
| CPU time | 76.75 seconds |
| Started | Jun 30 08:14:46 PM PDT 24 |
| Finished | Jun 30 08:16:03 PM PDT 24 |
| Peak memory | 565996 kb |
| Host | smart-0ff42f37-f609-41d6-97aa-b48bede8af2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364426330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3364426330 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.1044851198 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 54143849 ps |
| CPU time | 7.37 seconds |
| Started | Jun 30 08:14:41 PM PDT 24 |
| Finished | Jun 30 08:14:49 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-95250d27-aac9-492d-a394-b02ba736a4cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044851198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.1044851198 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.1841664186 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 736868266 ps |
| CPU time | 81.6 seconds |
| Started | Jun 30 08:14:53 PM PDT 24 |
| Finished | Jun 30 08:16:15 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-3423a626-bea7-441f-ac69-8fdf998b28bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841664186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1841664186 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.2045207691 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 11322831263 ps |
| CPU time | 446.19 seconds |
| Started | Jun 30 08:14:53 PM PDT 24 |
| Finished | Jun 30 08:22:20 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-3a74cff1-984e-4244-8e95-40c88de8d6c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045207691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2045207691 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.964206968 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 7080333239 ps |
| CPU time | 330.6 seconds |
| Started | Jun 30 08:14:55 PM PDT 24 |
| Finished | Jun 30 08:20:26 PM PDT 24 |
| Peak memory | 576404 kb |
| Host | smart-6badc6f7-a2c1-4b69-8d80-cc337bfc0396 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964206968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_ with_rand_reset.964206968 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3296623387 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 530415293 ps |
| CPU time | 157.24 seconds |
| Started | Jun 30 08:14:54 PM PDT 24 |
| Finished | Jun 30 08:17:32 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-fda25f1e-fd0d-43fd-af31-f6fabc6deaa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296623387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.3296623387 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.711234595 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 165171196 ps |
| CPU time | 24.19 seconds |
| Started | Jun 30 08:14:55 PM PDT 24 |
| Finished | Jun 30 08:15:20 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-6595369e-016e-438e-9d96-2a473e9136a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711234595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.711234595 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.3752425952 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 11849445744 ps |
| CPU time | 1658.6 seconds |
| Started | Jun 30 08:06:49 PM PDT 24 |
| Finished | Jun 30 08:34:28 PM PDT 24 |
| Peak memory | 590128 kb |
| Host | smart-203654cd-2050-4800-a27f-c48a959bc363 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752425952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.3752425952 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.3213148073 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 4507708431 ps |
| CPU time | 664.82 seconds |
| Started | Jun 30 08:06:43 PM PDT 24 |
| Finished | Jun 30 08:17:49 PM PDT 24 |
| Peak memory | 597688 kb |
| Host | smart-2d851a13-6218-4610-bef5-c56f63169a9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213148073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.3213148073 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.3191022455 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 7396417276 ps |
| CPU time | 363.98 seconds |
| Started | Jun 30 08:06:04 PM PDT 24 |
| Finished | Jun 30 08:12:08 PM PDT 24 |
| Peak memory | 589116 kb |
| Host | smart-401f40cc-3f65-4e29-8e96-50590839f8f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191022455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.3191022455 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1890612931 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 10258792522 ps |
| CPU time | 576.19 seconds |
| Started | Jun 30 08:06:19 PM PDT 24 |
| Finished | Jun 30 08:15:56 PM PDT 24 |
| Peak memory | 590156 kb |
| Host | smart-284689bc-d29a-433f-84b9-1d2b6762551e |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890612931 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.1890612931 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.3762426796 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 15676700407 ps |
| CPU time | 2157.18 seconds |
| Started | Jun 30 08:06:02 PM PDT 24 |
| Finished | Jun 30 08:42:00 PM PDT 24 |
| Peak memory | 591916 kb |
| Host | smart-967a8e30-35ad-4729-8272-f661102bb571 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762426796 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.3762426796 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.421678713 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 3362787258 ps |
| CPU time | 266.76 seconds |
| Started | Jun 30 08:06:06 PM PDT 24 |
| Finished | Jun 30 08:10:33 PM PDT 24 |
| Peak memory | 597428 kb |
| Host | smart-abeefd28-343e-425b-96b9-0af5d1a967ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421678713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.421678713 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.2876493207 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 1026058005 ps |
| CPU time | 59.46 seconds |
| Started | Jun 30 08:06:26 PM PDT 24 |
| Finished | Jun 30 08:07:26 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-6cd5ff0d-2950-4988-84e4-0d4b0cb694fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876493207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 2876493207 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2421893868 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 125019002994 ps |
| CPU time | 1875.84 seconds |
| Started | Jun 30 08:06:28 PM PDT 24 |
| Finished | Jun 30 08:37:44 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-1b6cb580-e43a-4e5d-9c38-ff60c674c142 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421893868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.2421893868 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1625223872 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 1376631492 ps |
| CPU time | 63.57 seconds |
| Started | Jun 30 08:06:47 PM PDT 24 |
| Finished | Jun 30 08:07:51 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-e0f5d3c8-962c-481f-83ce-86f23309e677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625223872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .1625223872 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.3270007204 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 616042413 ps |
| CPU time | 59.97 seconds |
| Started | Jun 30 08:06:25 PM PDT 24 |
| Finished | Jun 30 08:07:25 PM PDT 24 |
| Peak memory | 573804 kb |
| Host | smart-f10968f4-e465-4cf6-bfa9-d8d9aa4fa6da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270007204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3270007204 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.851604383 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 570031554 ps |
| CPU time | 63.66 seconds |
| Started | Jun 30 08:06:27 PM PDT 24 |
| Finished | Jun 30 08:07:31 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-34abfcd1-6532-469a-a50a-36daf2666f5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851604383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.851604383 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.743084616 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 99905775818 ps |
| CPU time | 1060.38 seconds |
| Started | Jun 30 08:06:24 PM PDT 24 |
| Finished | Jun 30 08:24:04 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-2baa8a1a-7b80-4edc-96e9-129f43a5fb94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743084616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.743084616 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.3003532721 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 44455286889 ps |
| CPU time | 765.23 seconds |
| Started | Jun 30 08:06:24 PM PDT 24 |
| Finished | Jun 30 08:19:09 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-595de85d-26cc-47eb-950f-32dd730d162d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003532721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3003532721 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.2370337724 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 357371536 ps |
| CPU time | 37.6 seconds |
| Started | Jun 30 08:06:27 PM PDT 24 |
| Finished | Jun 30 08:07:05 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-314dd773-a981-45f0-bab4-dee483282679 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370337724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.2370337724 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.4247760129 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 409964237 ps |
| CPU time | 34.03 seconds |
| Started | Jun 30 08:06:30 PM PDT 24 |
| Finished | Jun 30 08:07:04 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-01a9598a-237c-4ec3-b10e-35ea9b361dba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247760129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.4247760129 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.2993441865 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 203342768 ps |
| CPU time | 10.05 seconds |
| Started | Jun 30 08:06:12 PM PDT 24 |
| Finished | Jun 30 08:06:22 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-7d452945-7d1c-4dce-a4a8-d44b5eeb3e17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993441865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2993441865 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.1598013503 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 8029527547 ps |
| CPU time | 83.7 seconds |
| Started | Jun 30 08:06:12 PM PDT 24 |
| Finished | Jun 30 08:07:36 PM PDT 24 |
| Peak memory | 565848 kb |
| Host | smart-4442bdcd-a142-42cf-8f67-eef4437c219a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598013503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1598013503 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.3297298324 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 2819606822 ps |
| CPU time | 54.62 seconds |
| Started | Jun 30 08:06:38 PM PDT 24 |
| Finished | Jun 30 08:07:34 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-e5da721b-59a0-4b0a-92bd-b53c1052c783 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297298324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3297298324 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.269096204 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 47888557 ps |
| CPU time | 7.56 seconds |
| Started | Jun 30 08:06:23 PM PDT 24 |
| Finished | Jun 30 08:06:31 PM PDT 24 |
| Peak memory | 565904 kb |
| Host | smart-7b179b1d-e642-4ee0-9f0f-0c34ff810aef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269096204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays. 269096204 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.214350823 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 1589778854 ps |
| CPU time | 143.44 seconds |
| Started | Jun 30 08:06:38 PM PDT 24 |
| Finished | Jun 30 08:09:03 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-cc1fcd7c-ee44-466f-8b94-dfea764edb0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214350823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.214350823 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.1970483711 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 12897912989 ps |
| CPU time | 461.96 seconds |
| Started | Jun 30 08:06:41 PM PDT 24 |
| Finished | Jun 30 08:14:23 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-3ae4dfc2-da3b-4680-9aa5-3c3491d9f990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970483711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1970483711 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.3197578076 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 5421835838 ps |
| CPU time | 588.32 seconds |
| Started | Jun 30 08:07:02 PM PDT 24 |
| Finished | Jun 30 08:16:51 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-3e5fbe1d-c159-43be-a4ff-aca5c8cc2bb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197578076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.3197578076 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.1858814924 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 2023460624 ps |
| CPU time | 255.6 seconds |
| Started | Jun 30 08:06:42 PM PDT 24 |
| Finished | Jun 30 08:10:58 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-088ad8a2-3986-4b76-9d96-1956f9ac8cc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858814924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.1858814924 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.307137656 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 85641082 ps |
| CPU time | 13.75 seconds |
| Started | Jun 30 08:06:40 PM PDT 24 |
| Finished | Jun 30 08:06:54 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-291c45f3-cf76-41d8-87d3-f270e8abbf66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307137656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.307137656 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.2672580073 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 4900526095 ps |
| CPU time | 498.52 seconds |
| Started | Jun 30 08:14:59 PM PDT 24 |
| Finished | Jun 30 08:23:18 PM PDT 24 |
| Peak memory | 596384 kb |
| Host | smart-9c38c309-074f-4bfb-8f26-d9b2d5a5bb65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672580073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.2672580073 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.1740839715 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 136514550 ps |
| CPU time | 18.36 seconds |
| Started | Jun 30 08:15:14 PM PDT 24 |
| Finished | Jun 30 08:15:33 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-1f23cf5c-224f-40bf-84f0-43c7d9a3d7eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740839715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .1740839715 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.1318712562 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 150384722868 ps |
| CPU time | 2572.42 seconds |
| Started | Jun 30 08:15:14 PM PDT 24 |
| Finished | Jun 30 08:58:07 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-a70db9a4-31da-43d9-857e-c943b3d894d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318712562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.1318712562 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.1347438708 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 418567149 ps |
| CPU time | 19.12 seconds |
| Started | Jun 30 08:15:13 PM PDT 24 |
| Finished | Jun 30 08:15:32 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-8dcb7947-d502-4915-92dc-ea48d7105b41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347438708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.1347438708 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.3566622716 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 515840987 ps |
| CPU time | 45.16 seconds |
| Started | Jun 30 08:15:12 PM PDT 24 |
| Finished | Jun 30 08:15:57 PM PDT 24 |
| Peak memory | 573844 kb |
| Host | smart-bd1c638f-8e14-4411-9cce-e110efbf677f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566622716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3566622716 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.1881998731 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 2201554271 ps |
| CPU time | 82.49 seconds |
| Started | Jun 30 08:15:06 PM PDT 24 |
| Finished | Jun 30 08:16:29 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-e409dd1d-5a4b-4c6f-abc1-a36899d05b09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881998731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.1881998731 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.3913533839 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 117705242064 ps |
| CPU time | 1205.88 seconds |
| Started | Jun 30 08:15:05 PM PDT 24 |
| Finished | Jun 30 08:35:12 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-c63fcd33-9ad3-40d2-8768-c6197328952e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913533839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3913533839 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.3214745344 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 11276546276 ps |
| CPU time | 209.24 seconds |
| Started | Jun 30 08:15:14 PM PDT 24 |
| Finished | Jun 30 08:18:43 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-508eb8a4-ed31-4d20-b40e-47609a3b5ecc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214745344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3214745344 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.1401765712 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 239896716 ps |
| CPU time | 23.92 seconds |
| Started | Jun 30 08:15:07 PM PDT 24 |
| Finished | Jun 30 08:15:31 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-e8d4746d-9143-4da2-a76c-269536e17596 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401765712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.1401765712 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.2143487746 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 2281811237 ps |
| CPU time | 83.28 seconds |
| Started | Jun 30 08:15:12 PM PDT 24 |
| Finished | Jun 30 08:16:36 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-2036eb80-78f0-415f-9aba-b5ad9ed17061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143487746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2143487746 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.202994704 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 56453042 ps |
| CPU time | 7.14 seconds |
| Started | Jun 30 08:14:59 PM PDT 24 |
| Finished | Jun 30 08:15:07 PM PDT 24 |
| Peak memory | 565904 kb |
| Host | smart-50d9b481-8fa0-44f0-a254-e5479c29a9a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202994704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.202994704 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.1710575184 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 8948298837 ps |
| CPU time | 95.22 seconds |
| Started | Jun 30 08:15:00 PM PDT 24 |
| Finished | Jun 30 08:16:36 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-a3662d1f-3639-40ab-b973-6d46feb6281d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710575184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1710575184 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2723372547 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 6205153535 ps |
| CPU time | 106.42 seconds |
| Started | Jun 30 08:15:00 PM PDT 24 |
| Finished | Jun 30 08:16:47 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-ea574c62-6177-40a2-81bf-41b24ce6b44e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723372547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2723372547 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.3674257649 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 48537094 ps |
| CPU time | 6.7 seconds |
| Started | Jun 30 08:14:59 PM PDT 24 |
| Finished | Jun 30 08:15:07 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-d044163c-ae42-4751-b73d-1e30a5a9df78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674257649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.3674257649 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.814863211 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 1855314403 ps |
| CPU time | 60.71 seconds |
| Started | Jun 30 08:15:19 PM PDT 24 |
| Finished | Jun 30 08:16:20 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-a28dcf72-9c09-46e2-8c85-84ab6664b029 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814863211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.814863211 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.3240647935 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 10320615956 ps |
| CPU time | 740.3 seconds |
| Started | Jun 30 08:15:20 PM PDT 24 |
| Finished | Jun 30 08:27:41 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-fa065cfa-759f-4f9d-bc24-990907c0b258 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240647935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.3240647935 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.1777812927 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 3385967902 ps |
| CPU time | 325.73 seconds |
| Started | Jun 30 08:15:18 PM PDT 24 |
| Finished | Jun 30 08:20:45 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-f6c4e2c6-a6e7-4166-9abc-7f62a721546b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777812927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.1777812927 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.1710592184 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 325100467 ps |
| CPU time | 43.63 seconds |
| Started | Jun 30 08:15:13 PM PDT 24 |
| Finished | Jun 30 08:15:57 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-53be89db-8996-42e5-88cf-116452a62389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710592184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1710592184 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.3657504778 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 4496675448 ps |
| CPU time | 354.61 seconds |
| Started | Jun 30 08:15:20 PM PDT 24 |
| Finished | Jun 30 08:21:15 PM PDT 24 |
| Peak memory | 603512 kb |
| Host | smart-52cb0594-31ac-4b48-97dc-7622308eda6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657504778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.3657504778 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.820857911 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 2133926624 ps |
| CPU time | 115.7 seconds |
| Started | Jun 30 08:15:25 PM PDT 24 |
| Finished | Jun 30 08:17:21 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-e1896daa-9a40-4fdd-af9c-2e7a6deb9653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820857911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device. 820857911 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1088621233 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 15486455877 ps |
| CPU time | 275.69 seconds |
| Started | Jun 30 08:15:23 PM PDT 24 |
| Finished | Jun 30 08:19:59 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-23ec0f36-5bf9-4d9c-a75c-b88683ab42ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088621233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.1088621233 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.3898153356 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 751264923 ps |
| CPU time | 35.26 seconds |
| Started | Jun 30 08:15:23 PM PDT 24 |
| Finished | Jun 30 08:15:59 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-d3acc389-37e9-4696-b67f-165a3d420a43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898153356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.3898153356 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.3043271809 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 1889383108 ps |
| CPU time | 73.84 seconds |
| Started | Jun 30 08:15:23 PM PDT 24 |
| Finished | Jun 30 08:16:37 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-18131c4a-496d-40bd-aeb7-8b488572d884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043271809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3043271809 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.4014221712 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 584382485 ps |
| CPU time | 49.62 seconds |
| Started | Jun 30 08:15:20 PM PDT 24 |
| Finished | Jun 30 08:16:10 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-943ba750-a47c-425d-a1c1-2d279d161527 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014221712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.4014221712 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.3352058517 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 74381586339 ps |
| CPU time | 739.93 seconds |
| Started | Jun 30 08:15:22 PM PDT 24 |
| Finished | Jun 30 08:27:43 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-fdfdfcde-9e7e-4307-814d-9ecbf5042595 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352058517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3352058517 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.2864860197 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 39718701206 ps |
| CPU time | 716.72 seconds |
| Started | Jun 30 08:15:24 PM PDT 24 |
| Finished | Jun 30 08:27:21 PM PDT 24 |
| Peak memory | 575180 kb |
| Host | smart-921260ef-e9bc-4c95-b579-f44e89c6dd3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864860197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2864860197 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.2022121371 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 464037317 ps |
| CPU time | 42.37 seconds |
| Started | Jun 30 08:15:19 PM PDT 24 |
| Finished | Jun 30 08:16:02 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-f7b2fb36-0903-4236-b89b-59e7e04b5a6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022121371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.2022121371 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.568705797 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 247386125 ps |
| CPU time | 21.87 seconds |
| Started | Jun 30 08:15:24 PM PDT 24 |
| Finished | Jun 30 08:15:46 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-26c89de5-0fcb-44f7-bdfc-b620f4ac5786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568705797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.568705797 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.534724651 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 179895472 ps |
| CPU time | 9.62 seconds |
| Started | Jun 30 08:15:18 PM PDT 24 |
| Finished | Jun 30 08:15:29 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-0bed8fc8-7a10-4b04-9685-e74de9f39ac9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534724651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.534724651 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.164569400 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 8278736949 ps |
| CPU time | 90.28 seconds |
| Started | Jun 30 08:15:19 PM PDT 24 |
| Finished | Jun 30 08:16:50 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-2f9aafce-cd13-4a04-84fa-fa656a084300 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164569400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.164569400 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.18003566 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 6651101854 ps |
| CPU time | 113.88 seconds |
| Started | Jun 30 08:15:17 PM PDT 24 |
| Finished | Jun 30 08:17:11 PM PDT 24 |
| Peak memory | 566020 kb |
| Host | smart-0f9b1f77-c19e-4597-aee7-b9e3df348be5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18003566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.18003566 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3396741881 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 44525004 ps |
| CPU time | 6.38 seconds |
| Started | Jun 30 08:15:18 PM PDT 24 |
| Finished | Jun 30 08:15:25 PM PDT 24 |
| Peak memory | 565824 kb |
| Host | smart-f4c2a249-8bc7-441d-827d-c49cd42b03d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396741881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.3396741881 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.500635155 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 15567821011 ps |
| CPU time | 615.19 seconds |
| Started | Jun 30 08:15:29 PM PDT 24 |
| Finished | Jun 30 08:25:44 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-7b2a92a4-db1b-42e3-a408-36a4d4ec68ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500635155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.500635155 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.729454738 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 6550797485 ps |
| CPU time | 273.42 seconds |
| Started | Jun 30 08:15:29 PM PDT 24 |
| Finished | Jun 30 08:20:03 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-a459fd30-644d-4f5f-aeba-38bc023e5c6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729454738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.729454738 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.2328307989 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 13455949253 ps |
| CPU time | 708.05 seconds |
| Started | Jun 30 08:15:29 PM PDT 24 |
| Finished | Jun 30 08:27:17 PM PDT 24 |
| Peak memory | 576388 kb |
| Host | smart-4692e764-f0ee-4ba3-9532-44e7b47c463d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328307989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.2328307989 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.3452456539 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 195004362 ps |
| CPU time | 24.9 seconds |
| Started | Jun 30 08:15:23 PM PDT 24 |
| Finished | Jun 30 08:15:49 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-9aca80ad-1b22-4442-8877-cbbb285f2ebc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452456539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3452456539 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.3436844469 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 3651782714 ps |
| CPU time | 209.24 seconds |
| Started | Jun 30 08:15:29 PM PDT 24 |
| Finished | Jun 30 08:18:59 PM PDT 24 |
| Peak memory | 597412 kb |
| Host | smart-baf0370c-1d9c-4aec-bdcd-5afd1862bf83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436844469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.3436844469 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.4209086498 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 1702703247 ps |
| CPU time | 78.35 seconds |
| Started | Jun 30 08:15:36 PM PDT 24 |
| Finished | Jun 30 08:16:55 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-64e32c34-e834-477d-b067-a3cb5eb35d37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209086498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device .4209086498 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.1453086105 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 53586438188 ps |
| CPU time | 948.32 seconds |
| Started | Jun 30 08:15:35 PM PDT 24 |
| Finished | Jun 30 08:31:23 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-4613b49e-c706-45b0-a198-b5552d2960af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453086105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.1453086105 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.2854803366 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 68518547 ps |
| CPU time | 6.78 seconds |
| Started | Jun 30 08:15:49 PM PDT 24 |
| Finished | Jun 30 08:15:56 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-21f05b7d-b420-4572-8115-0a60fa31efaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854803366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.2854803366 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.2769615818 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 557550263 ps |
| CPU time | 45.74 seconds |
| Started | Jun 30 08:15:41 PM PDT 24 |
| Finished | Jun 30 08:16:27 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-ef357772-bdc8-45e8-93b7-e28fe0a1688b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769615818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2769615818 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.1782966175 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 412310939 ps |
| CPU time | 38.15 seconds |
| Started | Jun 30 08:15:34 PM PDT 24 |
| Finished | Jun 30 08:16:13 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-5fb78df0-db20-48f2-bcd4-520341469f37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782966175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.1782966175 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.2035931458 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 54668218616 ps |
| CPU time | 595.36 seconds |
| Started | Jun 30 08:15:36 PM PDT 24 |
| Finished | Jun 30 08:25:32 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-24a59c36-1101-4f67-acdf-c24671f50d42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035931458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2035931458 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.712618467 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 13908606684 ps |
| CPU time | 232.95 seconds |
| Started | Jun 30 08:15:36 PM PDT 24 |
| Finished | Jun 30 08:19:29 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-67158ab7-ef78-4eda-ac1a-45da485d14c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712618467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.712618467 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.3936988028 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 170052550 ps |
| CPU time | 17.31 seconds |
| Started | Jun 30 08:15:34 PM PDT 24 |
| Finished | Jun 30 08:15:52 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-04cf2f6f-7f0c-4e16-aec1-1b21ad4219ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936988028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.3936988028 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.583302793 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2732484130 ps |
| CPU time | 101.34 seconds |
| Started | Jun 30 08:15:39 PM PDT 24 |
| Finished | Jun 30 08:17:21 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-0bd45ea3-9b04-4550-b580-f931a5aa9da3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583302793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.583302793 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.2466874946 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 178771730 ps |
| CPU time | 8.51 seconds |
| Started | Jun 30 08:15:29 PM PDT 24 |
| Finished | Jun 30 08:15:38 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-7fbe2640-b7a8-4307-bf6c-f4c7afa0f3da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466874946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2466874946 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.1012051424 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 8555668946 ps |
| CPU time | 91.15 seconds |
| Started | Jun 30 08:15:29 PM PDT 24 |
| Finished | Jun 30 08:17:01 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-4153caf6-62ff-4cd4-b419-52882bf5376d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012051424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1012051424 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.3293566173 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 7242748808 ps |
| CPU time | 122.71 seconds |
| Started | Jun 30 08:15:31 PM PDT 24 |
| Finished | Jun 30 08:17:34 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-f3deafd6-dfdd-417c-9575-f1606c8ddc7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293566173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3293566173 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.1066653512 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 44074648 ps |
| CPU time | 6.66 seconds |
| Started | Jun 30 08:15:28 PM PDT 24 |
| Finished | Jun 30 08:15:35 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-cad13fa3-dde6-4872-9aa4-e3a6da25c9ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066653512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.1066653512 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.1360641662 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 5059304666 ps |
| CPU time | 221.77 seconds |
| Started | Jun 30 08:15:45 PM PDT 24 |
| Finished | Jun 30 08:19:27 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-09ebbfe3-d39c-4fe5-a049-f1ef6fbfd38f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360641662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1360641662 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.941698494 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1417544863 ps |
| CPU time | 337.97 seconds |
| Started | Jun 30 08:15:45 PM PDT 24 |
| Finished | Jun 30 08:21:23 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-37a7e5f2-e95f-4823-b098-57291a91acde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941698494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_ with_rand_reset.941698494 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.2402705041 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 252399721 ps |
| CPU time | 78.73 seconds |
| Started | Jun 30 08:15:45 PM PDT 24 |
| Finished | Jun 30 08:17:04 PM PDT 24 |
| Peak memory | 576392 kb |
| Host | smart-c2fca467-f562-4060-b4d2-be3d5c4fbc3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402705041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.2402705041 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.2708119618 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 1382934305 ps |
| CPU time | 63.59 seconds |
| Started | Jun 30 08:15:40 PM PDT 24 |
| Finished | Jun 30 08:16:44 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-8a581f62-b221-4769-ac32-a71899aba553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708119618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2708119618 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.2787919415 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 3663556658 ps |
| CPU time | 209.81 seconds |
| Started | Jun 30 08:15:46 PM PDT 24 |
| Finished | Jun 30 08:19:17 PM PDT 24 |
| Peak memory | 597468 kb |
| Host | smart-51a67af7-caf4-4085-802e-2c78296a5880 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787919415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.2787919415 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.1536390034 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 2939970202 ps |
| CPU time | 139.76 seconds |
| Started | Jun 30 08:15:52 PM PDT 24 |
| Finished | Jun 30 08:18:12 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-c1e7c986-0532-48b9-bb85-3e05d01e60b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536390034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .1536390034 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2186364207 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 39856519867 ps |
| CPU time | 729.27 seconds |
| Started | Jun 30 08:15:53 PM PDT 24 |
| Finished | Jun 30 08:28:03 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-fc442794-f04f-4286-8e18-a3bf1b94c4b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186364207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.2186364207 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.134473284 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 155320907 ps |
| CPU time | 18.78 seconds |
| Started | Jun 30 08:16:01 PM PDT 24 |
| Finished | Jun 30 08:16:20 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-c508a03a-774e-4a54-a301-a68cffb212ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134473284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr .134473284 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.1235311346 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 36999203 ps |
| CPU time | 6.34 seconds |
| Started | Jun 30 08:15:57 PM PDT 24 |
| Finished | Jun 30 08:16:04 PM PDT 24 |
| Peak memory | 565596 kb |
| Host | smart-d0ac0a1c-5cf9-49bc-8aa0-443619cc9fa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235311346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1235311346 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.2756373542 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 417959138 ps |
| CPU time | 41.71 seconds |
| Started | Jun 30 08:15:54 PM PDT 24 |
| Finished | Jun 30 08:16:36 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-ab2787c4-7ab1-41a1-93bf-e3b98c39c77a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756373542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.2756373542 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.3349396817 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 65521492852 ps |
| CPU time | 755.75 seconds |
| Started | Jun 30 08:15:55 PM PDT 24 |
| Finished | Jun 30 08:28:31 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-131214fb-7e48-4db7-8355-dcaada501af1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349396817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3349396817 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.2959583018 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 40871247298 ps |
| CPU time | 703.96 seconds |
| Started | Jun 30 08:15:51 PM PDT 24 |
| Finished | Jun 30 08:27:36 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-fa5704b2-0619-46d3-9ab2-4fbe453c3021 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959583018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2959583018 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.714034779 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 255784933 ps |
| CPU time | 25.96 seconds |
| Started | Jun 30 08:15:55 PM PDT 24 |
| Finished | Jun 30 08:16:22 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-6b97a10e-647f-4b53-a9bb-361a09509dc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714034779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_dela ys.714034779 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.2692645275 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 857843705 ps |
| CPU time | 29.41 seconds |
| Started | Jun 30 08:15:51 PM PDT 24 |
| Finished | Jun 30 08:16:21 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-6c844014-4063-4111-8f4f-7e4fd0718fc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692645275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2692645275 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.39363140 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 222325213 ps |
| CPU time | 10.87 seconds |
| Started | Jun 30 08:15:56 PM PDT 24 |
| Finished | Jun 30 08:16:07 PM PDT 24 |
| Peak memory | 565908 kb |
| Host | smart-4dee9a1e-46af-4f4e-bf98-6159ec1285d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39363140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.39363140 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.1075285124 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 6137963440 ps |
| CPU time | 63.79 seconds |
| Started | Jun 30 08:15:59 PM PDT 24 |
| Finished | Jun 30 08:17:03 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-6b29f68c-3e59-40fd-8bc2-24195d0cebea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075285124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1075285124 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1985837180 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 4911884934 ps |
| CPU time | 90.53 seconds |
| Started | Jun 30 08:15:53 PM PDT 24 |
| Finished | Jun 30 08:17:24 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-04715119-a97e-43be-b9ff-2c13bac1e33b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985837180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1985837180 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.4063151982 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 47876968 ps |
| CPU time | 6.8 seconds |
| Started | Jun 30 08:15:59 PM PDT 24 |
| Finished | Jun 30 08:16:06 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-86b99d67-d5bf-4c38-8729-452b27d4e6ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063151982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.4063151982 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.1671008648 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 1300919745 ps |
| CPU time | 112.01 seconds |
| Started | Jun 30 08:16:09 PM PDT 24 |
| Finished | Jun 30 08:18:02 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-ae70e54a-12dc-431b-9699-f744dda1684c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671008648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1671008648 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.3221431687 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 2321131457 ps |
| CPU time | 175.71 seconds |
| Started | Jun 30 08:16:01 PM PDT 24 |
| Finished | Jun 30 08:18:57 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-3f6a923a-2aad-433d-89da-1c0d246d3907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221431687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3221431687 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3464416749 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 2714995634 ps |
| CPU time | 564.07 seconds |
| Started | Jun 30 08:15:57 PM PDT 24 |
| Finished | Jun 30 08:25:22 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-4d25c785-9e86-4745-ad3c-952ce88b6715 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464416749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.3464416749 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.848917227 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 690414038 ps |
| CPU time | 32.52 seconds |
| Started | Jun 30 08:16:09 PM PDT 24 |
| Finished | Jun 30 08:16:42 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-75f280a9-13df-4d34-8579-4c4d3523c326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848917227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.848917227 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.819850668 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 3798001758 ps |
| CPU time | 339.68 seconds |
| Started | Jun 30 08:16:09 PM PDT 24 |
| Finished | Jun 30 08:21:49 PM PDT 24 |
| Peak memory | 603556 kb |
| Host | smart-1a029a78-c828-4cf3-aa39-7b0f18e379df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819850668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.819850668 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.421533530 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 1532675183 ps |
| CPU time | 77.85 seconds |
| Started | Jun 30 08:16:06 PM PDT 24 |
| Finished | Jun 30 08:17:24 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-bfd7b2e4-2039-44d0-a61d-137c61941111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421533530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device. 421533530 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.3901436370 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 99855926682 ps |
| CPU time | 1923.04 seconds |
| Started | Jun 30 08:16:10 PM PDT 24 |
| Finished | Jun 30 08:48:14 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-726f0877-a6d6-4558-b639-fbe2541eb92c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901436370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.3901436370 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.3628229853 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 157209455 ps |
| CPU time | 19.12 seconds |
| Started | Jun 30 08:16:10 PM PDT 24 |
| Finished | Jun 30 08:16:30 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-7c5a1616-d817-44ae-8b00-e410256c9c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628229853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.3628229853 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.575142430 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 304937051 ps |
| CPU time | 28.61 seconds |
| Started | Jun 30 08:16:10 PM PDT 24 |
| Finished | Jun 30 08:16:39 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-79bd1c92-115f-47db-ab5b-b5874f2172ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575142430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.575142430 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.2752354743 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 322772388 ps |
| CPU time | 34.27 seconds |
| Started | Jun 30 08:16:05 PM PDT 24 |
| Finished | Jun 30 08:16:39 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-c88c0560-25e9-45b0-9850-f0c09e0b6448 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752354743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.2752354743 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.3920011350 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 38472280698 ps |
| CPU time | 429.21 seconds |
| Started | Jun 30 08:16:04 PM PDT 24 |
| Finished | Jun 30 08:23:14 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-16d6b746-697a-4dc8-8773-21f331bbe211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920011350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3920011350 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.3608719857 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 15862716664 ps |
| CPU time | 261.61 seconds |
| Started | Jun 30 08:16:12 PM PDT 24 |
| Finished | Jun 30 08:20:34 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-fcd321a4-3520-4593-8d03-76607d3f714b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608719857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3608719857 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.744354606 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 270088189 ps |
| CPU time | 30.08 seconds |
| Started | Jun 30 08:16:04 PM PDT 24 |
| Finished | Jun 30 08:16:35 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-3703d441-b29f-4db6-a30c-4a868272de83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744354606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_dela ys.744354606 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.3331241210 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 124674103 ps |
| CPU time | 11.97 seconds |
| Started | Jun 30 08:16:14 PM PDT 24 |
| Finished | Jun 30 08:16:27 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-40ab2dcf-8240-4c69-ac29-df1cd53b00f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331241210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3331241210 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.3356793509 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 176581722 ps |
| CPU time | 9.32 seconds |
| Started | Jun 30 08:16:01 PM PDT 24 |
| Finished | Jun 30 08:16:11 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-432678af-1aec-4ede-b5ba-ea3c54a7c6b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356793509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3356793509 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.3814688995 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 6501947097 ps |
| CPU time | 70.07 seconds |
| Started | Jun 30 08:16:03 PM PDT 24 |
| Finished | Jun 30 08:17:14 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-b6552c23-cc6c-40ce-8d4a-6a71f93dc40a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814688995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3814688995 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.2307935010 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 6010449953 ps |
| CPU time | 110.53 seconds |
| Started | Jun 30 08:16:04 PM PDT 24 |
| Finished | Jun 30 08:17:55 PM PDT 24 |
| Peak memory | 565996 kb |
| Host | smart-50135903-a1f2-4d49-b853-f90bf13e3c12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307935010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2307935010 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.4048876783 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 58679187 ps |
| CPU time | 7.76 seconds |
| Started | Jun 30 08:15:57 PM PDT 24 |
| Finished | Jun 30 08:16:05 PM PDT 24 |
| Peak memory | 565932 kb |
| Host | smart-c94b7d96-ca79-45d5-85b1-d6b647e5f478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048876783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay s.4048876783 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.1734043939 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 1717007091 ps |
| CPU time | 149.05 seconds |
| Started | Jun 30 08:16:10 PM PDT 24 |
| Finished | Jun 30 08:18:39 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-79e36219-fc38-4ad6-98bc-862c1c8cd264 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734043939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1734043939 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.466307533 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 8823805680 ps |
| CPU time | 306.64 seconds |
| Started | Jun 30 08:16:14 PM PDT 24 |
| Finished | Jun 30 08:21:22 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-70aa0993-bc87-45f5-93cb-c2a791dc3930 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466307533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.466307533 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.718168523 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 8312327580 ps |
| CPU time | 529.62 seconds |
| Started | Jun 30 08:16:10 PM PDT 24 |
| Finished | Jun 30 08:25:00 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-0d83899b-c6ea-49bd-8223-8fea07ea215d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718168523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_ with_rand_reset.718168523 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.1634598116 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 18400967025 ps |
| CPU time | 923.49 seconds |
| Started | Jun 30 08:16:10 PM PDT 24 |
| Finished | Jun 30 08:31:34 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-13e446c2-53f9-423d-83e7-c68349c70708 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634598116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.1634598116 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.91907167 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 322272214 ps |
| CPU time | 39.82 seconds |
| Started | Jun 30 08:16:10 PM PDT 24 |
| Finished | Jun 30 08:16:50 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-21a70895-f9fe-468e-9de6-3833294ea6f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91907167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.91907167 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.3233665685 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 3453793070 ps |
| CPU time | 310.15 seconds |
| Started | Jun 30 08:16:17 PM PDT 24 |
| Finished | Jun 30 08:21:27 PM PDT 24 |
| Peak memory | 603492 kb |
| Host | smart-85cd1151-c593-4203-b09e-e63b9b11eca7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233665685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.3233665685 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.341504845 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 971812924 ps |
| CPU time | 79.8 seconds |
| Started | Jun 30 08:16:27 PM PDT 24 |
| Finished | Jun 30 08:17:47 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-c3cf1631-b905-4c3a-951c-1bd3244e7f58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341504845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device. 341504845 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.805156251 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 33148454670 ps |
| CPU time | 553.15 seconds |
| Started | Jun 30 08:16:45 PM PDT 24 |
| Finished | Jun 30 08:25:59 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-ed729e47-307b-42ad-97af-a8a02d7e10c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805156251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_d evice_slow_rsp.805156251 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.287957263 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 366855071 ps |
| CPU time | 18.44 seconds |
| Started | Jun 30 08:16:27 PM PDT 24 |
| Finished | Jun 30 08:16:46 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-8f5800d1-1632-4131-b5e3-a6a4bf7f8408 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287957263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr .287957263 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.2490852931 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 1208255216 ps |
| CPU time | 46.2 seconds |
| Started | Jun 30 08:16:45 PM PDT 24 |
| Finished | Jun 30 08:17:32 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-ef5c738c-3b71-44bd-83db-0bb88f6dd81f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490852931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2490852931 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.2658072979 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 525274609 ps |
| CPU time | 53.27 seconds |
| Started | Jun 30 08:16:22 PM PDT 24 |
| Finished | Jun 30 08:17:15 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-c02731b5-4210-4060-be1e-975eb77077b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658072979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.2658072979 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.3601528952 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 13585578860 ps |
| CPU time | 153.92 seconds |
| Started | Jun 30 08:16:22 PM PDT 24 |
| Finished | Jun 30 08:18:56 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-fece4102-659f-4885-923b-3c256cf90449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601528952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3601528952 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.275990801 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 46081403861 ps |
| CPU time | 790.33 seconds |
| Started | Jun 30 08:16:19 PM PDT 24 |
| Finished | Jun 30 08:29:30 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-0753f301-3f93-4513-8e0c-e7d68177bbc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275990801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.275990801 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.3350752982 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 119096741 ps |
| CPU time | 13.15 seconds |
| Started | Jun 30 08:16:20 PM PDT 24 |
| Finished | Jun 30 08:16:34 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-329f4d0e-8244-4ee9-a0ee-31f1c1274a97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350752982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.3350752982 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.1241584910 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 1925479967 ps |
| CPU time | 59.66 seconds |
| Started | Jun 30 08:16:45 PM PDT 24 |
| Finished | Jun 30 08:17:46 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-7b959f1d-840f-478a-a5a0-548fc5211aba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241584910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1241584910 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.609828508 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 51468495 ps |
| CPU time | 6.88 seconds |
| Started | Jun 30 08:16:15 PM PDT 24 |
| Finished | Jun 30 08:16:22 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-faa3e7db-16da-4197-a2bd-c8b4ef47c66d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609828508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.609828508 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.2163511242 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 7036843414 ps |
| CPU time | 76.02 seconds |
| Started | Jun 30 08:16:20 PM PDT 24 |
| Finished | Jun 30 08:17:36 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-e989d1e2-5f16-4576-a648-ab62f6af2c4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163511242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2163511242 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.3116736211 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 5959479949 ps |
| CPU time | 110.45 seconds |
| Started | Jun 30 08:16:20 PM PDT 24 |
| Finished | Jun 30 08:18:11 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-0ef9f4ea-aa0f-4d24-8aa5-8450afd4f7c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116736211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3116736211 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.1969798911 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 48212332 ps |
| CPU time | 6.73 seconds |
| Started | Jun 30 08:16:17 PM PDT 24 |
| Finished | Jun 30 08:16:24 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-ce1a8ff1-5c8c-4d59-972d-019efdd30fb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969798911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.1969798911 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.390002448 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 592269994 ps |
| CPU time | 69.02 seconds |
| Started | Jun 30 08:16:27 PM PDT 24 |
| Finished | Jun 30 08:17:37 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-8a4273c0-f659-49a9-8680-03b75d88b64b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390002448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.390002448 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1498742907 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 395821478 ps |
| CPU time | 150.36 seconds |
| Started | Jun 30 08:16:46 PM PDT 24 |
| Finished | Jun 30 08:19:17 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-21568f78-9238-4fee-b407-b19cb4e529ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498742907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.1498742907 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3493099600 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 21112538816 ps |
| CPU time | 888.63 seconds |
| Started | Jun 30 08:16:38 PM PDT 24 |
| Finished | Jun 30 08:31:27 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-89bc6d7f-2755-4779-a611-39d7178878c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493099600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.3493099600 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.3528370083 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 1074255528 ps |
| CPU time | 46.19 seconds |
| Started | Jun 30 08:16:45 PM PDT 24 |
| Finished | Jun 30 08:17:32 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-9e04a45c-80a5-4895-88d2-449732f65d18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528370083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3528370083 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.3623561168 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 3056403828 ps |
| CPU time | 240.39 seconds |
| Started | Jun 30 08:16:38 PM PDT 24 |
| Finished | Jun 30 08:20:39 PM PDT 24 |
| Peak memory | 597436 kb |
| Host | smart-350af192-b511-4e1b-933a-defd9e50d93d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623561168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.3623561168 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.1884689860 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 173025865 ps |
| CPU time | 19.54 seconds |
| Started | Jun 30 08:16:38 PM PDT 24 |
| Finished | Jun 30 08:16:58 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-9319172e-5b7d-4503-a8fc-fb69e8026533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884689860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .1884689860 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1638319025 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 561020722 ps |
| CPU time | 21.96 seconds |
| Started | Jun 30 08:16:44 PM PDT 24 |
| Finished | Jun 30 08:17:07 PM PDT 24 |
| Peak memory | 573820 kb |
| Host | smart-e8b7b1af-2537-49f9-b905-23d7fef8839d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638319025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.1638319025 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.2760066162 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 63210977 ps |
| CPU time | 8.22 seconds |
| Started | Jun 30 08:16:38 PM PDT 24 |
| Finished | Jun 30 08:16:47 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-2309d5e2-db00-43f7-80fa-d0210f2c5e72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760066162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2760066162 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.753686764 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 533719911 ps |
| CPU time | 51.48 seconds |
| Started | Jun 30 08:16:37 PM PDT 24 |
| Finished | Jun 30 08:17:29 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-7af3f8ba-c667-4798-b3f2-0eff33608cb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753686764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.753686764 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.426323455 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 103161815221 ps |
| CPU time | 1109.36 seconds |
| Started | Jun 30 08:16:40 PM PDT 24 |
| Finished | Jun 30 08:35:09 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-cad57dcc-8f95-4d8d-aaec-f288839c19c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426323455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.426323455 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.910392336 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 47546170614 ps |
| CPU time | 849.84 seconds |
| Started | Jun 30 08:16:39 PM PDT 24 |
| Finished | Jun 30 08:30:49 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-b6545847-6202-4347-839b-55f8de128208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910392336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.910392336 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.3093302619 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 489674495 ps |
| CPU time | 51.55 seconds |
| Started | Jun 30 08:16:42 PM PDT 24 |
| Finished | Jun 30 08:17:34 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-052f85d8-89e8-4ea9-a0e3-59aac2df6098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093302619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.3093302619 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.1111578461 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 899266018 ps |
| CPU time | 26.52 seconds |
| Started | Jun 30 08:16:53 PM PDT 24 |
| Finished | Jun 30 08:17:20 PM PDT 24 |
| Peak memory | 575196 kb |
| Host | smart-38042989-ddd0-4e15-a666-7385bd79e368 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111578461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1111578461 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.1317440879 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 207457948 ps |
| CPU time | 9.82 seconds |
| Started | Jun 30 08:16:39 PM PDT 24 |
| Finished | Jun 30 08:16:49 PM PDT 24 |
| Peak memory | 565896 kb |
| Host | smart-0cb1d497-ed92-4826-8a3a-671ebb8ed51d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317440879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1317440879 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.179918055 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 8023738885 ps |
| CPU time | 86.02 seconds |
| Started | Jun 30 08:16:37 PM PDT 24 |
| Finished | Jun 30 08:18:04 PM PDT 24 |
| Peak memory | 565992 kb |
| Host | smart-19f6fe5a-be2d-4758-a3ab-d505d8ce5401 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179918055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.179918055 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.3251559279 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 4816523267 ps |
| CPU time | 84.52 seconds |
| Started | Jun 30 08:16:39 PM PDT 24 |
| Finished | Jun 30 08:18:04 PM PDT 24 |
| Peak memory | 566176 kb |
| Host | smart-6416e3ec-8e46-4bb8-9320-6dc34708b732 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251559279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3251559279 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3431857740 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 56805475 ps |
| CPU time | 7.91 seconds |
| Started | Jun 30 08:16:37 PM PDT 24 |
| Finished | Jun 30 08:16:46 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-5c342203-789c-40de-aa42-94c644f96f18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431857740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.3431857740 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.3096440187 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 11704853483 ps |
| CPU time | 430.77 seconds |
| Started | Jun 30 08:16:54 PM PDT 24 |
| Finished | Jun 30 08:24:06 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-2eaed191-edf7-4782-b8d0-6244c99485d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096440187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3096440187 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.154789317 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 2140950907 ps |
| CPU time | 168.62 seconds |
| Started | Jun 30 08:16:55 PM PDT 24 |
| Finished | Jun 30 08:19:44 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-b9a8886f-12b4-40b3-b869-8982b798d978 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154789317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.154789317 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3393876586 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 2557768813 ps |
| CPU time | 259.36 seconds |
| Started | Jun 30 08:16:45 PM PDT 24 |
| Finished | Jun 30 08:21:05 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-8cd0ee24-ec6b-4f21-9754-05b56ac273c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393876586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.3393876586 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.3080342699 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 133828658 ps |
| CPU time | 19.11 seconds |
| Started | Jun 30 08:16:40 PM PDT 24 |
| Finished | Jun 30 08:17:00 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-58b99565-c185-4b96-b733-5628fef5de34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080342699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3080342699 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.236322255 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 1094447848 ps |
| CPU time | 53.01 seconds |
| Started | Jun 30 08:16:56 PM PDT 24 |
| Finished | Jun 30 08:17:49 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-5eb8d5e3-5cc1-4b30-b6a9-12ff7aa30d54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236322255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device. 236322255 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.3480030180 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 41948820626 ps |
| CPU time | 711.31 seconds |
| Started | Jun 30 08:16:57 PM PDT 24 |
| Finished | Jun 30 08:28:49 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-51519f2f-90ef-4b48-b3e1-38dbd0570600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480030180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.3480030180 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.3490649777 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 765486458 ps |
| CPU time | 32.54 seconds |
| Started | Jun 30 08:16:56 PM PDT 24 |
| Finished | Jun 30 08:17:29 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-aa5526e5-745b-4d0e-8c23-cbd7b3465e63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490649777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.3490649777 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.2158784154 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 492579349 ps |
| CPU time | 50.76 seconds |
| Started | Jun 30 08:16:57 PM PDT 24 |
| Finished | Jun 30 08:17:48 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-9b28bd82-b18d-40b4-aec4-924607082a3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158784154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2158784154 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.2465728852 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 888726381 ps |
| CPU time | 36.91 seconds |
| Started | Jun 30 08:16:51 PM PDT 24 |
| Finished | Jun 30 08:17:29 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-e449f88e-51cb-4541-a8b6-ece598af3584 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465728852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.2465728852 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.2971883227 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 88737952936 ps |
| CPU time | 969.97 seconds |
| Started | Jun 30 08:16:49 PM PDT 24 |
| Finished | Jun 30 08:33:01 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-4a77f572-826d-4995-b12f-1d3b9a97426b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971883227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2971883227 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.1114900478 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 48288928920 ps |
| CPU time | 812.26 seconds |
| Started | Jun 30 08:17:03 PM PDT 24 |
| Finished | Jun 30 08:30:36 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-3ea2e048-e2a5-4eff-93b8-89e06fd18ab1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114900478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1114900478 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.3809530702 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 471096748 ps |
| CPU time | 45.53 seconds |
| Started | Jun 30 08:16:50 PM PDT 24 |
| Finished | Jun 30 08:17:37 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-982bf44f-6438-4b80-8cf0-9f303e2887e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809530702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.3809530702 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.1885058592 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 256970267 ps |
| CPU time | 22.01 seconds |
| Started | Jun 30 08:16:56 PM PDT 24 |
| Finished | Jun 30 08:17:18 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-3f9015b9-e966-47f6-9c8b-55ce7667f701 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885058592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1885058592 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.3808765586 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 186045436 ps |
| CPU time | 7.92 seconds |
| Started | Jun 30 08:16:54 PM PDT 24 |
| Finished | Jun 30 08:17:02 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-4c11317f-9fcd-4f7a-9b85-36f4904d01b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808765586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3808765586 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.845766756 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 9696110321 ps |
| CPU time | 101.51 seconds |
| Started | Jun 30 08:16:50 PM PDT 24 |
| Finished | Jun 30 08:18:33 PM PDT 24 |
| Peak memory | 565992 kb |
| Host | smart-617459ad-f479-42b6-a506-7ef4bf7a14ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845766756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.845766756 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.1358946070 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 5473325518 ps |
| CPU time | 90.33 seconds |
| Started | Jun 30 08:16:49 PM PDT 24 |
| Finished | Jun 30 08:18:21 PM PDT 24 |
| Peak memory | 565964 kb |
| Host | smart-5f7454e9-141e-47b0-a71b-48aaf7e0d550 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358946070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1358946070 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.2495923146 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 52856900 ps |
| CPU time | 7.37 seconds |
| Started | Jun 30 08:16:43 PM PDT 24 |
| Finished | Jun 30 08:16:51 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-8c7a820c-850f-45cc-81aa-f32213c8322e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495923146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.2495923146 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.1492008207 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 2326323854 ps |
| CPU time | 242.13 seconds |
| Started | Jun 30 08:17:03 PM PDT 24 |
| Finished | Jun 30 08:21:06 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-00a18ea8-3feb-4a64-b59c-fcc4a20f364e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492008207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1492008207 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.2379549550 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 1147859484 ps |
| CPU time | 107.4 seconds |
| Started | Jun 30 08:17:02 PM PDT 24 |
| Finished | Jun 30 08:18:50 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-4290ea47-7d63-445d-950b-1dcd38549ad5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379549550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2379549550 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.1462439965 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 108740036 ps |
| CPU time | 34.51 seconds |
| Started | Jun 30 08:17:03 PM PDT 24 |
| Finished | Jun 30 08:17:38 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-3a9f3a90-dc2e-44e3-a296-7e4c1e360178 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462439965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.1462439965 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.857416264 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 560158812 ps |
| CPU time | 32.18 seconds |
| Started | Jun 30 08:17:02 PM PDT 24 |
| Finished | Jun 30 08:17:35 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-fd35b330-b67b-428b-9fb3-e5fc93a692f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857416264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.857416264 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.3023019695 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 4470697040 ps |
| CPU time | 325.62 seconds |
| Started | Jun 30 08:17:02 PM PDT 24 |
| Finished | Jun 30 08:22:28 PM PDT 24 |
| Peak memory | 603564 kb |
| Host | smart-c135f483-e4ee-419c-8233-166b18beb653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023019695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.3023019695 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.3501211664 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 2453082237 ps |
| CPU time | 118.77 seconds |
| Started | Jun 30 08:17:06 PM PDT 24 |
| Finished | Jun 30 08:19:06 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-b42d278a-c1da-41c9-ba0a-5f6a20c43bec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501211664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .3501211664 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.110581884 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 37693925012 ps |
| CPU time | 673.59 seconds |
| Started | Jun 30 08:17:07 PM PDT 24 |
| Finished | Jun 30 08:28:21 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-67ee5cae-f01b-43de-a2d1-afc9bb49cb1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110581884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_d evice_slow_rsp.110581884 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2389675844 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 1305975870 ps |
| CPU time | 59.64 seconds |
| Started | Jun 30 08:17:09 PM PDT 24 |
| Finished | Jun 30 08:18:12 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-89004e4c-73a0-441e-8444-98132e0c0347 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389675844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.2389675844 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.4090362623 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 1241385493 ps |
| CPU time | 47.35 seconds |
| Started | Jun 30 08:17:10 PM PDT 24 |
| Finished | Jun 30 08:18:00 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-786de94a-9f6b-4beb-a93d-416426496de5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090362623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.4090362623 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.3291942223 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 1358955002 ps |
| CPU time | 53.99 seconds |
| Started | Jun 30 08:17:02 PM PDT 24 |
| Finished | Jun 30 08:17:57 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-b2b487ea-762f-406f-8110-0dcdc1df89e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291942223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.3291942223 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.540035228 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 59199489480 ps |
| CPU time | 693.63 seconds |
| Started | Jun 30 08:17:04 PM PDT 24 |
| Finished | Jun 30 08:28:39 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-d1377c55-9f55-4c31-94f0-d893ae62068e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540035228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.540035228 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.3167860617 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 39247171604 ps |
| CPU time | 685.12 seconds |
| Started | Jun 30 08:17:10 PM PDT 24 |
| Finished | Jun 30 08:28:39 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-01f1a2d6-1c94-459c-8d41-7507ebd3dcdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167860617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3167860617 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.2708164762 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 568511972 ps |
| CPU time | 48.12 seconds |
| Started | Jun 30 08:17:01 PM PDT 24 |
| Finished | Jun 30 08:17:50 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-cfcc1c7e-193f-43f4-886e-defde281ce60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708164762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.2708164762 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.1089008035 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 473286161 ps |
| CPU time | 16.81 seconds |
| Started | Jun 30 08:17:09 PM PDT 24 |
| Finished | Jun 30 08:17:29 PM PDT 24 |
| Peak memory | 575200 kb |
| Host | smart-5b1e8529-0b86-4397-a3d2-c64fc03ee9e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089008035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1089008035 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.1100217902 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 186453171 ps |
| CPU time | 8.84 seconds |
| Started | Jun 30 08:17:05 PM PDT 24 |
| Finished | Jun 30 08:17:14 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-1b068fb5-ffab-4fed-bbf5-1dd69bd33e40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100217902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1100217902 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.3988449151 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 9767775163 ps |
| CPU time | 103.19 seconds |
| Started | Jun 30 08:17:05 PM PDT 24 |
| Finished | Jun 30 08:18:48 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-30568a46-7882-4c3a-ad1f-9bba0c8068c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988449151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3988449151 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3152841725 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 5210048512 ps |
| CPU time | 89.58 seconds |
| Started | Jun 30 08:17:04 PM PDT 24 |
| Finished | Jun 30 08:18:34 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-97544c93-d2fa-4c71-837b-92cc5d7bd962 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152841725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3152841725 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.3992051021 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 38587126 ps |
| CPU time | 6.32 seconds |
| Started | Jun 30 08:17:04 PM PDT 24 |
| Finished | Jun 30 08:17:11 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-a49bf8b8-3664-4d43-b566-3cfbd99ea437 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992051021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.3992051021 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.2643468749 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 995158333 ps |
| CPU time | 92.63 seconds |
| Started | Jun 30 08:17:09 PM PDT 24 |
| Finished | Jun 30 08:18:43 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-e70fb299-6426-49c8-8c96-0f1f07744fc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643468749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2643468749 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.682041178 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 12923415261 ps |
| CPU time | 490.07 seconds |
| Started | Jun 30 08:17:07 PM PDT 24 |
| Finished | Jun 30 08:25:18 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-5d0d71bb-c238-4f23-9fc0-fe93f7a845f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682041178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.682041178 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1153777171 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 4868161237 ps |
| CPU time | 267.43 seconds |
| Started | Jun 30 08:17:09 PM PDT 24 |
| Finished | Jun 30 08:21:38 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-2de8f57b-a0d1-409a-aad4-bae130a637e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153777171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.1153777171 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.2495136061 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 553741787 ps |
| CPU time | 222.28 seconds |
| Started | Jun 30 08:17:09 PM PDT 24 |
| Finished | Jun 30 08:20:53 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-e07a1299-2100-42c3-84eb-e21ea75bd357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495136061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.2495136061 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.2385563824 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 592579149 ps |
| CPU time | 29.39 seconds |
| Started | Jun 30 08:17:06 PM PDT 24 |
| Finished | Jun 30 08:17:36 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-8edeaf6c-416e-4b39-b1d6-3acc1d090a3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385563824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2385563824 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.4260241041 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 3591595092 ps |
| CPU time | 251.38 seconds |
| Started | Jun 30 08:17:05 PM PDT 24 |
| Finished | Jun 30 08:21:17 PM PDT 24 |
| Peak memory | 597376 kb |
| Host | smart-b950ac56-fd7a-4fe9-9d9d-24c61c7a9ca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260241041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.4260241041 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.202240177 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 2820018536 ps |
| CPU time | 131.55 seconds |
| Started | Jun 30 08:17:18 PM PDT 24 |
| Finished | Jun 30 08:19:38 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-798ce0cf-0033-4802-a1c5-d977e252a664 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202240177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device. 202240177 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.3028184626 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 27189628916 ps |
| CPU time | 492.36 seconds |
| Started | Jun 30 08:17:19 PM PDT 24 |
| Finished | Jun 30 08:25:41 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-c0b3470e-f307-4a3c-8b7a-6e1aef321476 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028184626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.3028184626 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2482175799 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 108995970 ps |
| CPU time | 15.96 seconds |
| Started | Jun 30 08:17:19 PM PDT 24 |
| Finished | Jun 30 08:17:43 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-9a278f6c-c9d1-42eb-bfc4-ff0ff01ff847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482175799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.2482175799 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.2032620595 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 1181730038 ps |
| CPU time | 46.82 seconds |
| Started | Jun 30 08:17:18 PM PDT 24 |
| Finished | Jun 30 08:18:12 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-029702c8-ad26-4844-bbab-7256d6d5c0ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032620595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2032620595 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.1003697461 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 120037120 ps |
| CPU time | 7.8 seconds |
| Started | Jun 30 08:17:14 PM PDT 24 |
| Finished | Jun 30 08:17:26 PM PDT 24 |
| Peak memory | 565912 kb |
| Host | smart-eb8c2341-2373-4a88-bdf8-d6d7aa4b9501 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003697461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.1003697461 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.1302179896 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 55003775343 ps |
| CPU time | 553.25 seconds |
| Started | Jun 30 08:17:13 PM PDT 24 |
| Finished | Jun 30 08:26:31 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-453baa85-e7d0-4ac9-9e8a-9d60261034ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302179896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1302179896 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.1144238874 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 36910843929 ps |
| CPU time | 681.81 seconds |
| Started | Jun 30 08:17:14 PM PDT 24 |
| Finished | Jun 30 08:28:40 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-17f7fcb7-8e45-4bf5-ba3c-fa8e3517c827 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144238874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1144238874 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.4093372532 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 268831721 ps |
| CPU time | 29.92 seconds |
| Started | Jun 30 08:17:14 PM PDT 24 |
| Finished | Jun 30 08:17:49 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-7f1b13fd-94fa-48e7-a737-0b08114065f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093372532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.4093372532 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.1450469811 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 787137986 ps |
| CPU time | 24.84 seconds |
| Started | Jun 30 08:17:17 PM PDT 24 |
| Finished | Jun 30 08:17:50 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-559a917a-63de-4155-b737-40866507f351 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450469811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1450469811 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.4173979661 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 42777467 ps |
| CPU time | 6.66 seconds |
| Started | Jun 30 08:17:08 PM PDT 24 |
| Finished | Jun 30 08:17:17 PM PDT 24 |
| Peak memory | 565972 kb |
| Host | smart-1123f1f6-6aab-4bcc-961c-b1694d956e80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173979661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.4173979661 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.1798591362 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 6119502064 ps |
| CPU time | 65.51 seconds |
| Started | Jun 30 08:17:14 PM PDT 24 |
| Finished | Jun 30 08:18:24 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-f439f2e4-cf0c-4c5a-9456-ae1e5e9c2d69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798591362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1798591362 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.4169513505 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 5790252622 ps |
| CPU time | 95.14 seconds |
| Started | Jun 30 08:17:13 PM PDT 24 |
| Finished | Jun 30 08:18:53 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-817bccac-8573-4021-aca1-c41940b8a071 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169513505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.4169513505 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.1832916139 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 41105296 ps |
| CPU time | 6.81 seconds |
| Started | Jun 30 08:17:13 PM PDT 24 |
| Finished | Jun 30 08:17:25 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-373971ce-5ce8-43ba-9925-0f02607d6384 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832916139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.1832916139 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.2957748323 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 10541993326 ps |
| CPU time | 398.58 seconds |
| Started | Jun 30 08:17:27 PM PDT 24 |
| Finished | Jun 30 08:24:21 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-ce087900-3961-4a00-b9fa-618e2aba9870 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957748323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2957748323 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.1179170174 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 2436381347 ps |
| CPU time | 217.94 seconds |
| Started | Jun 30 08:17:24 PM PDT 24 |
| Finished | Jun 30 08:21:15 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-e523f646-c240-4f94-9785-eaa79f75a73a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179170174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1179170174 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.4221405768 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 16557051825 ps |
| CPU time | 826.3 seconds |
| Started | Jun 30 08:17:24 PM PDT 24 |
| Finished | Jun 30 08:31:22 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-f383da8a-de00-4963-b83d-bf25941d5931 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221405768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.4221405768 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.3723913044 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 570844398 ps |
| CPU time | 166.2 seconds |
| Started | Jun 30 08:17:26 PM PDT 24 |
| Finished | Jun 30 08:20:29 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-05810dd1-5e04-4077-9b8b-6271686fc000 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723913044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.3723913044 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.4290715841 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 1347687130 ps |
| CPU time | 56.24 seconds |
| Started | Jun 30 08:17:21 PM PDT 24 |
| Finished | Jun 30 08:18:27 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-b24da22a-7a11-4335-b0b7-61f02885aaf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290715841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.4290715841 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.1197484753 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 39776383205 ps |
| CPU time | 5468.78 seconds |
| Started | Jun 30 08:06:59 PM PDT 24 |
| Finished | Jun 30 09:38:09 PM PDT 24 |
| Peak memory | 592624 kb |
| Host | smart-2561841f-2aaf-494a-b6dc-67fabf0648cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197484753 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.1197484753 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.3060986212 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 6603799756 ps |
| CPU time | 771.1 seconds |
| Started | Jun 30 08:06:59 PM PDT 24 |
| Finished | Jun 30 08:19:51 PM PDT 24 |
| Peak memory | 589124 kb |
| Host | smart-a12c5822-9408-4b2f-ba7f-f603fac80529 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060986212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.3060986212 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2398663253 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 4534218570 ps |
| CPU time | 283.52 seconds |
| Started | Jun 30 08:07:56 PM PDT 24 |
| Finished | Jun 30 08:12:41 PM PDT 24 |
| Peak memory | 661480 kb |
| Host | smart-76898bea-0b88-408c-b545-4836073778b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398663253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.2398663253 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.424958047 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 4721932234 ps |
| CPU time | 385.45 seconds |
| Started | Jun 30 08:07:57 PM PDT 24 |
| Finished | Jun 30 08:14:23 PM PDT 24 |
| Peak memory | 596964 kb |
| Host | smart-9151068f-cf78-400f-9450-e805f2282f14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424958047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.424958047 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1530836204 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 29950688652 ps |
| CPU time | 3220.71 seconds |
| Started | Jun 30 08:07:04 PM PDT 24 |
| Finished | Jun 30 09:00:45 PM PDT 24 |
| Peak memory | 591928 kb |
| Host | smart-380bd6d3-e7ea-4499-87e5-d7ae70d6fba9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530836204 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.1530836204 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.1528220426 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 4484627000 ps |
| CPU time | 393.44 seconds |
| Started | Jun 30 08:06:59 PM PDT 24 |
| Finished | Jun 30 08:13:33 PM PDT 24 |
| Peak memory | 603464 kb |
| Host | smart-d38ff5e9-cb04-461b-b74d-f8e17a7e6a71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528220426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.1528220426 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.3853156388 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 2300416640 ps |
| CPU time | 105.74 seconds |
| Started | Jun 30 08:07:36 PM PDT 24 |
| Finished | Jun 30 08:09:22 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-bbf844b1-469a-45e2-bcd7-c44d678e52e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853156388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 3853156388 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.311661759 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 42449161593 ps |
| CPU time | 764.62 seconds |
| Started | Jun 30 08:07:28 PM PDT 24 |
| Finished | Jun 30 08:20:13 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-95bc0b8c-2a1b-4644-bbae-ebc216f0844a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311661759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_de vice_slow_rsp.311661759 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.3206041773 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 76436672 ps |
| CPU time | 12.52 seconds |
| Started | Jun 30 08:07:41 PM PDT 24 |
| Finished | Jun 30 08:07:54 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-559577d1-4308-4696-8655-c7d039c2098a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206041773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .3206041773 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.253469646 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 1437680584 ps |
| CPU time | 62.59 seconds |
| Started | Jun 30 08:07:38 PM PDT 24 |
| Finished | Jun 30 08:08:41 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-8cb0ca09-10fa-455d-92de-b841e2477b09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253469646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.253469646 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.1727668032 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 2025608889 ps |
| CPU time | 79.25 seconds |
| Started | Jun 30 08:07:13 PM PDT 24 |
| Finished | Jun 30 08:08:32 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-54c58c72-7298-44d9-9313-8cb45e66fba5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727668032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.1727668032 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.3230266192 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 36646155998 ps |
| CPU time | 684.5 seconds |
| Started | Jun 30 08:07:29 PM PDT 24 |
| Finished | Jun 30 08:18:54 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-22712e53-2916-4e72-8414-a5ca0de82f48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230266192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3230266192 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.52938680 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 502408315 ps |
| CPU time | 44.19 seconds |
| Started | Jun 30 08:07:23 PM PDT 24 |
| Finished | Jun 30 08:08:08 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-8fa42eaf-801e-4c72-b227-f2f72aa26178 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52938680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays .52938680 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.3602945250 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 2058112197 ps |
| CPU time | 61.33 seconds |
| Started | Jun 30 08:07:29 PM PDT 24 |
| Finished | Jun 30 08:08:31 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-3846d277-3658-4db5-b10d-f64eb0e792a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602945250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3602945250 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.386088900 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 192266084 ps |
| CPU time | 9.14 seconds |
| Started | Jun 30 08:07:02 PM PDT 24 |
| Finished | Jun 30 08:07:11 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-07146b5d-436c-4487-b06f-f6948f77dede |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386088900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.386088900 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.4067409037 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 7275856772 ps |
| CPU time | 85.38 seconds |
| Started | Jun 30 08:07:07 PM PDT 24 |
| Finished | Jun 30 08:08:33 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-e40d1993-744e-4eb9-ad35-31792f82b3fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067409037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.4067409037 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2624100495 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 6184780891 ps |
| CPU time | 112.41 seconds |
| Started | Jun 30 08:07:07 PM PDT 24 |
| Finished | Jun 30 08:09:00 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-75447bd8-a3e0-4e40-999e-5d1f12c7f8e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624100495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2624100495 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.4131962268 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 49337903 ps |
| CPU time | 7.96 seconds |
| Started | Jun 30 08:07:11 PM PDT 24 |
| Finished | Jun 30 08:07:20 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-540ace21-9f13-41c9-b384-7c6d5280bc38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131962268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .4131962268 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.2430060802 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 9032961279 ps |
| CPU time | 363.11 seconds |
| Started | Jun 30 08:07:48 PM PDT 24 |
| Finished | Jun 30 08:13:52 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-2c006710-795d-49ff-8d77-3a7507c2b9db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430060802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2430060802 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.1504341637 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 735916658 ps |
| CPU time | 56.82 seconds |
| Started | Jun 30 08:07:47 PM PDT 24 |
| Finished | Jun 30 08:08:44 PM PDT 24 |
| Peak memory | 573804 kb |
| Host | smart-8cfc00a9-34c3-4218-ab52-8bc3695365ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504341637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1504341637 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.3504390171 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 327936471 ps |
| CPU time | 128.42 seconds |
| Started | Jun 30 08:07:46 PM PDT 24 |
| Finished | Jun 30 08:09:55 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-1496a15f-8974-4414-88cf-f218765395ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504390171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.3504390171 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2118178019 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 4535166124 ps |
| CPU time | 306.74 seconds |
| Started | Jun 30 08:07:53 PM PDT 24 |
| Finished | Jun 30 08:13:01 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-38e6b383-8517-49b0-adf9-3b2764266d45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118178019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.2118178019 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.165312849 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 24349698 ps |
| CPU time | 6.44 seconds |
| Started | Jun 30 08:07:37 PM PDT 24 |
| Finished | Jun 30 08:07:44 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-d4b557b5-e27d-413c-a96c-3d645bf01af7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165312849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.165312849 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.1204295292 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 2452012797 ps |
| CPU time | 111.81 seconds |
| Started | Jun 30 08:17:31 PM PDT 24 |
| Finished | Jun 30 08:19:41 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-3a729bc2-fbfc-4de2-8e29-ca5aaecbe975 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204295292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .1204295292 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.1358955099 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 68252476772 ps |
| CPU time | 1219.89 seconds |
| Started | Jun 30 08:17:29 PM PDT 24 |
| Finished | Jun 30 08:38:05 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-1e4cc9b6-b7a1-4023-97a4-c78ed3c6b01f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358955099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.1358955099 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.1727330833 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 486776935 ps |
| CPU time | 21.64 seconds |
| Started | Jun 30 08:17:36 PM PDT 24 |
| Finished | Jun 30 08:18:22 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-a7824774-5351-4e0c-9a4c-fd091b5e022f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727330833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.1727330833 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.1863783356 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 2088333768 ps |
| CPU time | 80.38 seconds |
| Started | Jun 30 08:17:35 PM PDT 24 |
| Finished | Jun 30 08:19:18 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-4269ed57-163a-47a7-af07-9534d29f462b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863783356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1863783356 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.2815878114 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 655836543 ps |
| CPU time | 28.92 seconds |
| Started | Jun 30 08:17:33 PM PDT 24 |
| Finished | Jun 30 08:18:22 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-5fab94a6-5627-41b6-9567-0cf071666e9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815878114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.2815878114 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.116014163 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 73788787307 ps |
| CPU time | 788.6 seconds |
| Started | Jun 30 08:17:30 PM PDT 24 |
| Finished | Jun 30 08:30:55 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-6f6bdfc6-6496-48bf-a255-1acfd61b5803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116014163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.116014163 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.1664515618 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 58139389845 ps |
| CPU time | 1005.12 seconds |
| Started | Jun 30 08:17:33 PM PDT 24 |
| Finished | Jun 30 08:34:38 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-03b2ac4d-0a54-4e70-a1e9-dc567f86734e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664515618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1664515618 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.2568131375 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 552078297 ps |
| CPU time | 55.45 seconds |
| Started | Jun 30 08:17:31 PM PDT 24 |
| Finished | Jun 30 08:18:44 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-3d87a011-0370-48c6-9c4e-8886f12cf354 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568131375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.2568131375 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.1335349429 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 1798139655 ps |
| CPU time | 59.78 seconds |
| Started | Jun 30 08:17:32 PM PDT 24 |
| Finished | Jun 30 08:18:51 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-a400bcb8-dd56-475d-9d29-3f93140dbf72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335349429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1335349429 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.3408270892 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 218183528 ps |
| CPU time | 9.68 seconds |
| Started | Jun 30 08:17:26 PM PDT 24 |
| Finished | Jun 30 08:17:50 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-d6233586-2696-4fd6-991f-553e985d3b80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408270892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3408270892 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.1961089662 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 8733490423 ps |
| CPU time | 95.07 seconds |
| Started | Jun 30 08:17:26 PM PDT 24 |
| Finished | Jun 30 08:19:16 PM PDT 24 |
| Peak memory | 565972 kb |
| Host | smart-56ef2d1d-8e75-4623-8e99-6a2b04b8db36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961089662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1961089662 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.1036749795 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 5542523448 ps |
| CPU time | 93.51 seconds |
| Started | Jun 30 08:17:24 PM PDT 24 |
| Finished | Jun 30 08:19:09 PM PDT 24 |
| Peak memory | 565996 kb |
| Host | smart-4e5ba274-1c14-49f5-b66c-01803e2a69ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036749795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1036749795 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.1081308185 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 45318110 ps |
| CPU time | 7.08 seconds |
| Started | Jun 30 08:17:23 PM PDT 24 |
| Finished | Jun 30 08:17:43 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-5f5de112-2ed5-4083-9b99-a733f5a729a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081308185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.1081308185 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.1298740796 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 18232156685 ps |
| CPU time | 768.44 seconds |
| Started | Jun 30 08:17:35 PM PDT 24 |
| Finished | Jun 30 08:30:46 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-f0e51993-43a4-4e5d-9d63-ec7fe16213dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298740796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1298740796 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.1753205786 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 15015499972 ps |
| CPU time | 590.23 seconds |
| Started | Jun 30 08:17:38 PM PDT 24 |
| Finished | Jun 30 08:27:54 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-0bc3bfd9-d4be-42f9-b1e1-d9bd847f5f13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753205786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1753205786 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1753001312 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 565339642 ps |
| CPU time | 214.33 seconds |
| Started | Jun 30 08:17:34 PM PDT 24 |
| Finished | Jun 30 08:21:30 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-45973e5e-d438-4cc1-9974-f57199da4a22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753001312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.1753001312 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.1164624600 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 738158594 ps |
| CPU time | 32.51 seconds |
| Started | Jun 30 08:17:38 PM PDT 24 |
| Finished | Jun 30 08:18:37 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-14e47233-09bc-4668-9bfb-4818cf4c34b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164624600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1164624600 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.1761549188 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 530650182 ps |
| CPU time | 47.71 seconds |
| Started | Jun 30 08:17:44 PM PDT 24 |
| Finished | Jun 30 08:18:57 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-3857e519-af52-4285-b76f-dfdda430fda3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761549188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .1761549188 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2113739991 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 103126565279 ps |
| CPU time | 1887.27 seconds |
| Started | Jun 30 08:17:45 PM PDT 24 |
| Finished | Jun 30 08:49:38 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-d85b4569-cdfb-40f8-a11d-c8eb62bac7d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113739991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_ device_slow_rsp.2113739991 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3059271958 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 590245467 ps |
| CPU time | 26.99 seconds |
| Started | Jun 30 08:17:42 PM PDT 24 |
| Finished | Jun 30 08:18:35 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-a468c7ba-e4b3-4028-852f-f091ef30913f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059271958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.3059271958 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.3855942278 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 2463339643 ps |
| CPU time | 93.18 seconds |
| Started | Jun 30 08:17:42 PM PDT 24 |
| Finished | Jun 30 08:19:41 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-1bc0e911-3d29-48ca-aa53-59f09442bb32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855942278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3855942278 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.734779944 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 323922503 ps |
| CPU time | 34.8 seconds |
| Started | Jun 30 08:17:37 PM PDT 24 |
| Finished | Jun 30 08:18:38 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-6e552d1c-dc26-4aa5-9337-ebb7fa079ad9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734779944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.734779944 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.1178621129 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 94663838259 ps |
| CPU time | 1004.03 seconds |
| Started | Jun 30 08:17:41 PM PDT 24 |
| Finished | Jun 30 08:34:52 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-d4b78619-4f27-4d6b-a006-6d29384d5595 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178621129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1178621129 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.4052343845 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 57869337942 ps |
| CPU time | 1062.54 seconds |
| Started | Jun 30 08:17:42 PM PDT 24 |
| Finished | Jun 30 08:35:50 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-338a300b-bd3f-4ff8-af3a-6ad52bcf975f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052343845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.4052343845 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.3111123596 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 374494278 ps |
| CPU time | 36.03 seconds |
| Started | Jun 30 08:17:37 PM PDT 24 |
| Finished | Jun 30 08:18:37 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-7a26ff75-1b20-42a7-b414-e988373ac3fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111123596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.3111123596 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.1195724700 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 386939967 ps |
| CPU time | 28.33 seconds |
| Started | Jun 30 08:17:46 PM PDT 24 |
| Finished | Jun 30 08:18:41 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-0476c51e-fadb-41f3-a7df-16735a2f873e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195724700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1195724700 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.4251828848 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 234801055 ps |
| CPU time | 9.87 seconds |
| Started | Jun 30 08:17:34 PM PDT 24 |
| Finished | Jun 30 08:18:06 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-2c2d3c43-885e-437e-8273-598785a0c0d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251828848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.4251828848 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.2018324874 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 5408998622 ps |
| CPU time | 59.12 seconds |
| Started | Jun 30 08:17:35 PM PDT 24 |
| Finished | Jun 30 08:18:57 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-52f74e31-9948-4140-aa0d-e2f8dc6361fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018324874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2018324874 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.495718163 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 6233634588 ps |
| CPU time | 101.54 seconds |
| Started | Jun 30 08:17:35 PM PDT 24 |
| Finished | Jun 30 08:19:40 PM PDT 24 |
| Peak memory | 566000 kb |
| Host | smart-3284fe3a-2fbd-405b-8b28-deabf40ded13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495718163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.495718163 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.682347669 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 43985990 ps |
| CPU time | 6.11 seconds |
| Started | Jun 30 08:17:37 PM PDT 24 |
| Finished | Jun 30 08:18:09 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-a57c6625-2fcb-475c-aae8-58d783f95c7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682347669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays .682347669 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.3174842275 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 17121885886 ps |
| CPU time | 703.9 seconds |
| Started | Jun 30 08:17:44 PM PDT 24 |
| Finished | Jun 30 08:29:53 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-70661cd4-c128-4bc5-9254-e6dde4c59d89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174842275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3174842275 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.3921231742 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 245096620 ps |
| CPU time | 11.2 seconds |
| Started | Jun 30 08:17:47 PM PDT 24 |
| Finished | Jun 30 08:18:25 PM PDT 24 |
| Peak memory | 565624 kb |
| Host | smart-95edc50b-4d87-4254-a388-96ccdf4f327a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921231742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3921231742 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.559456330 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 5819421926 ps |
| CPU time | 769.53 seconds |
| Started | Jun 30 08:17:48 PM PDT 24 |
| Finished | Jun 30 08:31:03 PM PDT 24 |
| Peak memory | 580340 kb |
| Host | smart-bfe96565-5741-4267-901c-7fcee062117f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559456330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_ with_rand_reset.559456330 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2942467732 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 270999126 ps |
| CPU time | 121.37 seconds |
| Started | Jun 30 08:17:47 PM PDT 24 |
| Finished | Jun 30 08:20:15 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-99f0fde4-e137-4237-9b54-e463d5084c9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942467732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.2942467732 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.1458642975 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1348428768 ps |
| CPU time | 60.43 seconds |
| Started | Jun 30 08:17:44 PM PDT 24 |
| Finished | Jun 30 08:19:11 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-817df2b6-8707-4082-ad46-d77539435464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458642975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1458642975 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.627151140 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 2908005765 ps |
| CPU time | 128.83 seconds |
| Started | Jun 30 08:17:53 PM PDT 24 |
| Finished | Jun 30 08:20:27 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-705cc643-4c38-44a0-bb24-ad05d578a715 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627151140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device. 627151140 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.4254784593 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 170766336114 ps |
| CPU time | 2923.09 seconds |
| Started | Jun 30 08:17:53 PM PDT 24 |
| Finished | Jun 30 09:07:01 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-f502c2d5-2d8e-4940-b7e0-938221dd1913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254784593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.4254784593 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.4178151258 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 73347396 ps |
| CPU time | 6.9 seconds |
| Started | Jun 30 08:17:54 PM PDT 24 |
| Finished | Jun 30 08:18:26 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-a086d769-f3ce-43d9-900c-0b02ff0668de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178151258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.4178151258 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.3117166721 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 411947283 ps |
| CPU time | 38.64 seconds |
| Started | Jun 30 08:17:55 PM PDT 24 |
| Finished | Jun 30 08:18:58 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-c212729b-85ba-4f5f-bb32-4bb08c8a3b31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117166721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3117166721 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.13049487 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 768132965 ps |
| CPU time | 34.29 seconds |
| Started | Jun 30 08:17:52 PM PDT 24 |
| Finished | Jun 30 08:18:52 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-208966ed-4f73-49b1-b9e9-b242fcd7678e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13049487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.13049487 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.3499500022 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 30595453800 ps |
| CPU time | 334.06 seconds |
| Started | Jun 30 08:17:54 PM PDT 24 |
| Finished | Jun 30 08:23:53 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-0f754ee5-10fb-484e-b9c3-5aa33dbeaaa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499500022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3499500022 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.1736760466 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 20204473256 ps |
| CPU time | 358.98 seconds |
| Started | Jun 30 08:17:53 PM PDT 24 |
| Finished | Jun 30 08:24:17 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-10ca65d5-fa56-4cff-8d03-fe91f4e057a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736760466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1736760466 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.1785452508 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 209486313 ps |
| CPU time | 21.85 seconds |
| Started | Jun 30 08:17:52 PM PDT 24 |
| Finished | Jun 30 08:18:39 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-fd108a9e-f2f4-4c72-bc4a-e877045e986f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785452508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.1785452508 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.254962788 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 302019532 ps |
| CPU time | 12.35 seconds |
| Started | Jun 30 08:17:53 PM PDT 24 |
| Finished | Jun 30 08:18:31 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-38983980-ecbb-41af-88f3-a0b5bb6c6fcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254962788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.254962788 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.3770418857 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 213381826 ps |
| CPU time | 9.52 seconds |
| Started | Jun 30 08:17:47 PM PDT 24 |
| Finished | Jun 30 08:18:23 PM PDT 24 |
| Peak memory | 565956 kb |
| Host | smart-c2e12e37-2b3a-4316-9db3-e39e885e541c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770418857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3770418857 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.985122539 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 6659440901 ps |
| CPU time | 71.6 seconds |
| Started | Jun 30 08:17:47 PM PDT 24 |
| Finished | Jun 30 08:19:25 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-53bc1950-371f-4cd0-8a1f-2b0a93568122 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985122539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.985122539 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.1765281035 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 3906058570 ps |
| CPU time | 72.7 seconds |
| Started | Jun 30 08:17:47 PM PDT 24 |
| Finished | Jun 30 08:19:26 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-d47cdb2c-8f32-4732-b156-a7ee85111e6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765281035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1765281035 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.1668716742 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 47086342 ps |
| CPU time | 6.98 seconds |
| Started | Jun 30 08:17:46 PM PDT 24 |
| Finished | Jun 30 08:18:19 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-b0c65bdc-8dfa-4e70-9fc3-58afc78736e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668716742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.1668716742 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.2597425914 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 1643317471 ps |
| CPU time | 148.68 seconds |
| Started | Jun 30 08:17:52 PM PDT 24 |
| Finished | Jun 30 08:20:46 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-87cac424-87c5-45a0-8e3e-db24d18a0eb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597425914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2597425914 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.3969480274 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 2697268471 ps |
| CPU time | 235.66 seconds |
| Started | Jun 30 08:17:59 PM PDT 24 |
| Finished | Jun 30 08:22:17 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-8d8b4101-e889-4116-92d0-c076c81df0ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969480274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3969480274 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.337416205 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 466132737 ps |
| CPU time | 234.14 seconds |
| Started | Jun 30 08:17:54 PM PDT 24 |
| Finished | Jun 30 08:22:13 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-6c5ee984-a230-4eeb-b23d-477f426915ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337416205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_ with_rand_reset.337416205 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.471316846 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 36900521 ps |
| CPU time | 7.37 seconds |
| Started | Jun 30 08:17:55 PM PDT 24 |
| Finished | Jun 30 08:18:27 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-7866c545-5948-4443-8889-0117544c584d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471316846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.471316846 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.1190414566 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 930704633 ps |
| CPU time | 36.87 seconds |
| Started | Jun 30 08:18:05 PM PDT 24 |
| Finished | Jun 30 08:19:00 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-f457ad4e-398e-4b3f-b471-9a66c78a278a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190414566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .1190414566 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.2035152991 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 17862045450 ps |
| CPU time | 335.51 seconds |
| Started | Jun 30 08:18:11 PM PDT 24 |
| Finished | Jun 30 08:24:01 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-ce682806-04c7-4b75-b75e-b4b34d33f51e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035152991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.2035152991 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.85992898 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 242108128 ps |
| CPU time | 26.45 seconds |
| Started | Jun 30 08:18:12 PM PDT 24 |
| Finished | Jun 30 08:18:52 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-d89ab4af-9060-45c8-a4d8-e54aebec14d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85992898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.85992898 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.1286366402 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 367814492 ps |
| CPU time | 33.76 seconds |
| Started | Jun 30 08:18:11 PM PDT 24 |
| Finished | Jun 30 08:18:59 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-606b8e33-1195-421e-ab27-c382fbcf561e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286366402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1286366402 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.3803030720 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 35533238271 ps |
| CPU time | 387.16 seconds |
| Started | Jun 30 08:18:06 PM PDT 24 |
| Finished | Jun 30 08:24:51 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-0789b409-7882-404e-994d-860c82eb28f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803030720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3803030720 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.3296182414 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 50805594546 ps |
| CPU time | 863.05 seconds |
| Started | Jun 30 08:18:05 PM PDT 24 |
| Finished | Jun 30 08:32:46 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-5f585851-4c69-4ee0-8feb-9c175c0f7555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296182414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3296182414 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.3193335514 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 203681668 ps |
| CPU time | 20.68 seconds |
| Started | Jun 30 08:18:05 PM PDT 24 |
| Finished | Jun 30 08:18:44 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-35567123-475d-4dba-9fe5-c44fe44707ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193335514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.3193335514 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.924609758 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 1257701078 ps |
| CPU time | 40.52 seconds |
| Started | Jun 30 08:18:12 PM PDT 24 |
| Finished | Jun 30 08:19:06 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-767c2274-8f38-465e-a778-5c5c8fa119c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924609758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.924609758 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.1679301511 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 55241928 ps |
| CPU time | 7.31 seconds |
| Started | Jun 30 08:18:01 PM PDT 24 |
| Finished | Jun 30 08:18:29 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-9fa4afec-b1d3-4ec0-afae-cf0211c25ad5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679301511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1679301511 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.2848396146 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 8741214225 ps |
| CPU time | 91.27 seconds |
| Started | Jun 30 08:18:01 PM PDT 24 |
| Finished | Jun 30 08:19:53 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-0b3cff78-236e-4ea3-a1b2-7d4449bc493f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848396146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2848396146 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1608673053 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 6763517776 ps |
| CPU time | 114.58 seconds |
| Started | Jun 30 08:17:58 PM PDT 24 |
| Finished | Jun 30 08:20:16 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-a6eac60d-59fd-44cd-9409-153f6bdcf007 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608673053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1608673053 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3570386959 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 49758106 ps |
| CPU time | 6.39 seconds |
| Started | Jun 30 08:17:59 PM PDT 24 |
| Finished | Jun 30 08:18:28 PM PDT 24 |
| Peak memory | 565944 kb |
| Host | smart-1a6b7214-149d-4e8a-a2f0-bb65b22cc5b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570386959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.3570386959 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.3079428897 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 995650112 ps |
| CPU time | 80.92 seconds |
| Started | Jun 30 08:18:15 PM PDT 24 |
| Finished | Jun 30 08:19:47 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-cff2531e-9568-4733-bcbf-8a98b17b91e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079428897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3079428897 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.4123803269 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 2188809567 ps |
| CPU time | 96.16 seconds |
| Started | Jun 30 08:18:18 PM PDT 24 |
| Finished | Jun 30 08:20:03 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-01c4b57a-ebe3-431a-be9b-0e9060c7467d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123803269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.4123803269 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2464761203 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 6915022045 ps |
| CPU time | 296.66 seconds |
| Started | Jun 30 08:18:15 PM PDT 24 |
| Finished | Jun 30 08:23:23 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-98a96eac-f3c9-44f6-b1ad-deca871ec4d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464761203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.2464761203 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.3969335739 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 1044639157 ps |
| CPU time | 201.35 seconds |
| Started | Jun 30 08:18:16 PM PDT 24 |
| Finished | Jun 30 08:21:48 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-1c8f0d7d-1267-4b0f-a69a-b9c87aa5849b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969335739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.3969335739 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.220967601 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 113271343 ps |
| CPU time | 17.38 seconds |
| Started | Jun 30 08:18:12 PM PDT 24 |
| Finished | Jun 30 08:18:43 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-679904ec-c1d4-4985-970c-4c2502c4c23a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220967601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.220967601 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1889844216 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 2872757509 ps |
| CPU time | 110.08 seconds |
| Started | Jun 30 08:18:21 PM PDT 24 |
| Finished | Jun 30 08:20:18 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-135fc0b1-3de6-4e2c-91f4-e33fc1574d00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889844216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .1889844216 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.523911173 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 53583402451 ps |
| CPU time | 958.42 seconds |
| Started | Jun 30 08:18:26 PM PDT 24 |
| Finished | Jun 30 08:34:28 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-f42ccdff-5b58-4367-9afd-386866d7c36e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523911173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_d evice_slow_rsp.523911173 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.689883179 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 73771734 ps |
| CPU time | 6.81 seconds |
| Started | Jun 30 08:18:26 PM PDT 24 |
| Finished | Jun 30 08:18:36 PM PDT 24 |
| Peak memory | 565696 kb |
| Host | smart-a5c9dec7-d566-4605-9ff8-60bc1df787bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689883179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr .689883179 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.1407713804 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 357325982 ps |
| CPU time | 30 seconds |
| Started | Jun 30 08:18:26 PM PDT 24 |
| Finished | Jun 30 08:18:59 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-bb4b5321-ef16-4333-ba45-11cced5b28b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407713804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1407713804 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.2160745007 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 124130498 ps |
| CPU time | 8.3 seconds |
| Started | Jun 30 08:18:22 PM PDT 24 |
| Finished | Jun 30 08:18:36 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-4170d0f5-f5ca-474b-8046-af04d9891e35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160745007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.2160745007 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.2073329934 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 112610319623 ps |
| CPU time | 1179.47 seconds |
| Started | Jun 30 08:18:21 PM PDT 24 |
| Finished | Jun 30 08:38:08 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-297e5a0d-f712-4c19-b9eb-759fd2d15c1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073329934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2073329934 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.3597794881 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 57761036006 ps |
| CPU time | 1067.5 seconds |
| Started | Jun 30 08:18:21 PM PDT 24 |
| Finished | Jun 30 08:36:16 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-87f5e349-416f-447b-886f-1254ce78e075 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597794881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3597794881 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.2838389961 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 509132972 ps |
| CPU time | 43.3 seconds |
| Started | Jun 30 08:18:26 PM PDT 24 |
| Finished | Jun 30 08:19:13 PM PDT 24 |
| Peak memory | 575180 kb |
| Host | smart-f8f6007d-1fc6-4d8f-b3d4-ff81871ebd34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838389961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.2838389961 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.4277769410 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 1127132571 ps |
| CPU time | 37.77 seconds |
| Started | Jun 30 08:18:26 PM PDT 24 |
| Finished | Jun 30 08:19:07 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-b0b2cd94-73b0-41f4-a825-5c1e571556c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277769410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.4277769410 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.3769517694 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 186334395 ps |
| CPU time | 9.37 seconds |
| Started | Jun 30 08:18:16 PM PDT 24 |
| Finished | Jun 30 08:18:36 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-2607aa6c-686b-47fe-886b-195e8350b5f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769517694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3769517694 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.3426973967 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 7640632563 ps |
| CPU time | 80.83 seconds |
| Started | Jun 30 08:18:15 PM PDT 24 |
| Finished | Jun 30 08:19:47 PM PDT 24 |
| Peak memory | 566000 kb |
| Host | smart-9afac5a6-e561-44d9-ac21-17b2a1dc603d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426973967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3426973967 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.2851959766 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 4773458201 ps |
| CPU time | 85.69 seconds |
| Started | Jun 30 08:18:22 PM PDT 24 |
| Finished | Jun 30 08:19:54 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-a249a36c-2577-4a63-bd3b-74f96a2da659 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851959766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2851959766 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.1197553905 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 37572905 ps |
| CPU time | 6.5 seconds |
| Started | Jun 30 08:18:16 PM PDT 24 |
| Finished | Jun 30 08:18:33 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-097bf3a4-861f-43d2-8dde-943e894e354d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197553905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.1197553905 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.865505171 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 849262899 ps |
| CPU time | 75.53 seconds |
| Started | Jun 30 08:18:26 PM PDT 24 |
| Finished | Jun 30 08:19:45 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-d8484c6f-7d69-44dd-96a4-e244a8f93259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865505171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.865505171 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.4082427857 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 8238360191 ps |
| CPU time | 285.16 seconds |
| Started | Jun 30 08:18:26 PM PDT 24 |
| Finished | Jun 30 08:23:14 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-8b316d24-1c24-40a7-aab2-e51bef78a937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082427857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.4082427857 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.1154633155 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1464398939 ps |
| CPU time | 252.69 seconds |
| Started | Jun 30 08:18:27 PM PDT 24 |
| Finished | Jun 30 08:22:42 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-624ab7dd-2911-45a4-b13e-211b6fb4e245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154633155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.1154633155 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.1861112535 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 321502525 ps |
| CPU time | 106.34 seconds |
| Started | Jun 30 08:18:26 PM PDT 24 |
| Finished | Jun 30 08:20:16 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-bac7fec7-fc9f-4f20-aa2c-b0343ad81ffa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861112535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.1861112535 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.4189064300 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 665519740 ps |
| CPU time | 29.12 seconds |
| Started | Jun 30 08:18:34 PM PDT 24 |
| Finished | Jun 30 08:19:04 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-7560ffe5-2cfb-4906-b369-3801e6a531bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189064300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.4189064300 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.4211165906 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 1016414493 ps |
| CPU time | 43.54 seconds |
| Started | Jun 30 08:18:41 PM PDT 24 |
| Finished | Jun 30 08:19:25 PM PDT 24 |
| Peak memory | 575180 kb |
| Host | smart-b6f8ca66-74e1-4969-bfac-1cc7c20a65d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211165906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .4211165906 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3467901291 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 131865853557 ps |
| CPU time | 2161.99 seconds |
| Started | Jun 30 08:18:40 PM PDT 24 |
| Finished | Jun 30 08:54:43 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-4ff3ba34-9c6f-4193-96b9-df12a83d78fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467901291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.3467901291 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.872928898 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 93898212 ps |
| CPU time | 6.85 seconds |
| Started | Jun 30 08:18:41 PM PDT 24 |
| Finished | Jun 30 08:18:49 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-53b4b32a-2223-4c80-8740-9a235ad717a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872928898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr .872928898 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.2351542511 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 392588728 ps |
| CPU time | 40.16 seconds |
| Started | Jun 30 08:18:32 PM PDT 24 |
| Finished | Jun 30 08:19:13 PM PDT 24 |
| Peak memory | 573780 kb |
| Host | smart-35463945-4675-47c7-8a38-c54be505a544 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351542511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2351542511 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.722660237 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 1377198550 ps |
| CPU time | 44.09 seconds |
| Started | Jun 30 08:18:35 PM PDT 24 |
| Finished | Jun 30 08:19:20 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-601969db-916d-451d-b74a-9759baa1b145 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722660237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.722660237 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.3960556589 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 3987898474 ps |
| CPU time | 41.78 seconds |
| Started | Jun 30 08:18:32 PM PDT 24 |
| Finished | Jun 30 08:19:15 PM PDT 24 |
| Peak memory | 565988 kb |
| Host | smart-61aa8785-a92e-4ce1-b806-6e21db3ce503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960556589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3960556589 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.3963268251 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 67096816195 ps |
| CPU time | 1154.83 seconds |
| Started | Jun 30 08:18:33 PM PDT 24 |
| Finished | Jun 30 08:37:49 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-8ab42505-9dc9-4d0b-bf80-d9768dc3c234 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963268251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3963268251 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.771478519 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 122602095 ps |
| CPU time | 13.46 seconds |
| Started | Jun 30 08:18:32 PM PDT 24 |
| Finished | Jun 30 08:18:47 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-fd048da4-e98b-4cc5-9d4d-3cdb24443235 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771478519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_dela ys.771478519 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.536775597 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 214507809 ps |
| CPU time | 19.72 seconds |
| Started | Jun 30 08:18:32 PM PDT 24 |
| Finished | Jun 30 08:18:52 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-4e0d33a3-22c9-4968-8c1c-058464c483ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536775597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.536775597 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.3213932571 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 238030022 ps |
| CPU time | 10.8 seconds |
| Started | Jun 30 08:18:27 PM PDT 24 |
| Finished | Jun 30 08:18:40 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-6a91b141-1f8e-4336-8102-e94af5c0c554 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213932571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3213932571 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.3477908985 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 9564502128 ps |
| CPU time | 95.14 seconds |
| Started | Jun 30 08:18:40 PM PDT 24 |
| Finished | Jun 30 08:20:16 PM PDT 24 |
| Peak memory | 565952 kb |
| Host | smart-301a1139-1ffd-4195-b59d-0a7436cc56da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477908985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3477908985 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.441846109 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 5188821372 ps |
| CPU time | 90.89 seconds |
| Started | Jun 30 08:18:33 PM PDT 24 |
| Finished | Jun 30 08:20:05 PM PDT 24 |
| Peak memory | 566040 kb |
| Host | smart-977a29b4-8bcf-49c8-a349-920416a7cda5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441846109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.441846109 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.203238396 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 51754021 ps |
| CPU time | 6.82 seconds |
| Started | Jun 30 08:18:33 PM PDT 24 |
| Finished | Jun 30 08:18:41 PM PDT 24 |
| Peak memory | 565956 kb |
| Host | smart-b2013b28-7064-43d5-926f-669f6bad5ef2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203238396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays .203238396 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.1892043380 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 9067236201 ps |
| CPU time | 393.14 seconds |
| Started | Jun 30 08:18:39 PM PDT 24 |
| Finished | Jun 30 08:25:14 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-3ef2e8be-7dae-43a4-9396-f35d2bb56444 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892043380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1892043380 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.425457502 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 10856833306 ps |
| CPU time | 378.86 seconds |
| Started | Jun 30 08:18:38 PM PDT 24 |
| Finished | Jun 30 08:24:59 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-e0c53761-3ad0-4553-9477-b34853d0c427 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425457502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.425457502 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.2532513377 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1183261270 ps |
| CPU time | 281.64 seconds |
| Started | Jun 30 08:18:36 PM PDT 24 |
| Finished | Jun 30 08:23:19 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-4873837e-efe5-4715-8b6d-811f4ef50bb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532513377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.2532513377 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.28457165 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 7576431610 ps |
| CPU time | 395.15 seconds |
| Started | Jun 30 08:18:37 PM PDT 24 |
| Finished | Jun 30 08:25:13 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-04c5c192-f822-4695-895b-0d2afd378d92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28457165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_ with_reset_error.28457165 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.4132332009 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 86419788 ps |
| CPU time | 7.88 seconds |
| Started | Jun 30 08:18:33 PM PDT 24 |
| Finished | Jun 30 08:18:42 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-be7ea63a-f80a-48b7-837d-5bb93a17c1b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132332009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.4132332009 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.3009000085 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 93121846923 ps |
| CPU time | 1610.8 seconds |
| Started | Jun 30 08:18:55 PM PDT 24 |
| Finished | Jun 30 08:45:46 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-9779ccec-d862-41ee-8b9e-3f373d59bc53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009000085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.3009000085 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.2161150098 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 78192817 ps |
| CPU time | 6.63 seconds |
| Started | Jun 30 08:18:56 PM PDT 24 |
| Finished | Jun 30 08:19:04 PM PDT 24 |
| Peak memory | 565572 kb |
| Host | smart-7aed4381-f476-48b2-a4c9-b65b04b6df65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161150098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.2161150098 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.1537356465 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 2732527200 ps |
| CPU time | 102.14 seconds |
| Started | Jun 30 08:18:49 PM PDT 24 |
| Finished | Jun 30 08:20:32 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-3ff5e418-716b-4c81-a134-a39dde1838c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537356465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1537356465 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.1081757136 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 458845302 ps |
| CPU time | 46.9 seconds |
| Started | Jun 30 08:18:37 PM PDT 24 |
| Finished | Jun 30 08:19:26 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-c6f3170b-a3e5-49a2-ab33-9c510fef6618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081757136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.1081757136 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.576101194 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 69837373568 ps |
| CPU time | 757.12 seconds |
| Started | Jun 30 08:18:43 PM PDT 24 |
| Finished | Jun 30 08:31:21 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-d4cc98bc-62a4-46c4-9ec6-4a8fff246fab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576101194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.576101194 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.3467214620 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 32595518585 ps |
| CPU time | 582.68 seconds |
| Started | Jun 30 08:18:43 PM PDT 24 |
| Finished | Jun 30 08:28:26 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-b418febc-9076-4e2a-a636-a0f0d4bf0c29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467214620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3467214620 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.465612862 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 248706530 ps |
| CPU time | 28.15 seconds |
| Started | Jun 30 08:18:43 PM PDT 24 |
| Finished | Jun 30 08:19:12 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-1a157d3b-b20d-4a3f-aa24-33d651b1cb29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465612862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_dela ys.465612862 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.63304557 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 1700621223 ps |
| CPU time | 47.8 seconds |
| Started | Jun 30 08:18:50 PM PDT 24 |
| Finished | Jun 30 08:19:38 PM PDT 24 |
| Peak memory | 575176 kb |
| Host | smart-1c8fc3c9-378f-4590-9dde-9766224cf152 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63304557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.63304557 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.1139011903 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 51243620 ps |
| CPU time | 6.04 seconds |
| Started | Jun 30 08:18:37 PM PDT 24 |
| Finished | Jun 30 08:18:45 PM PDT 24 |
| Peak memory | 565896 kb |
| Host | smart-352ec334-ee13-4a57-8925-6907be3b8ca7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139011903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1139011903 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.2851784658 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 9930009066 ps |
| CPU time | 95.36 seconds |
| Started | Jun 30 08:18:38 PM PDT 24 |
| Finished | Jun 30 08:20:15 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-bb8a6878-41f9-442a-a97e-370261cd07b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851784658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2851784658 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.4213804928 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 3809597550 ps |
| CPU time | 72.99 seconds |
| Started | Jun 30 08:18:38 PM PDT 24 |
| Finished | Jun 30 08:19:53 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-7b1932e1-88bd-45ad-b429-ee46628740de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213804928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.4213804928 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.3930815256 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 50708264 ps |
| CPU time | 7.16 seconds |
| Started | Jun 30 08:18:37 PM PDT 24 |
| Finished | Jun 30 08:18:45 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-a439e52d-e921-4013-9e6d-5c6fcd7fa6b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930815256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.3930815256 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.2932334470 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 3277904531 ps |
| CPU time | 301.56 seconds |
| Started | Jun 30 08:18:51 PM PDT 24 |
| Finished | Jun 30 08:23:53 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-684bdff6-7193-424c-817a-05a60b7ac152 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932334470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2932334470 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.2290739536 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 1845246950 ps |
| CPU time | 145.77 seconds |
| Started | Jun 30 08:18:49 PM PDT 24 |
| Finished | Jun 30 08:21:16 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-b5c9621a-8338-405d-bf0b-a4ea6262a48a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290739536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2290739536 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.3565055205 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 312357302 ps |
| CPU time | 110.61 seconds |
| Started | Jun 30 08:18:56 PM PDT 24 |
| Finished | Jun 30 08:20:47 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-0836c85c-101f-41d0-80f5-2fe5ebfe86bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565055205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.3565055205 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.2642547980 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 4154519841 ps |
| CPU time | 237.35 seconds |
| Started | Jun 30 08:18:50 PM PDT 24 |
| Finished | Jun 30 08:22:48 PM PDT 24 |
| Peak memory | 577448 kb |
| Host | smart-9681ced9-d889-494d-b2ef-440fc137a945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642547980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.2642547980 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.2269774307 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 833236159 ps |
| CPU time | 37.79 seconds |
| Started | Jun 30 08:18:50 PM PDT 24 |
| Finished | Jun 30 08:19:28 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-dd8fbfd9-3377-4bf5-9977-22b79254f241 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269774307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2269774307 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.3749449209 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 512490471 ps |
| CPU time | 60.17 seconds |
| Started | Jun 30 08:19:03 PM PDT 24 |
| Finished | Jun 30 08:20:04 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-5a92c283-c6c3-4185-8481-506c930a74a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749449209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .3749449209 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.363535729 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 18250656243 ps |
| CPU time | 316.38 seconds |
| Started | Jun 30 08:19:05 PM PDT 24 |
| Finished | Jun 30 08:24:22 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-f5516baa-3b10-46d9-970f-4cfe01ab4fea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363535729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_d evice_slow_rsp.363535729 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.2078314914 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 1190309615 ps |
| CPU time | 48.97 seconds |
| Started | Jun 30 08:19:06 PM PDT 24 |
| Finished | Jun 30 08:19:55 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-ed877916-9733-410f-8925-80df81c53cf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078314914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.2078314914 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.2866692173 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 2420484015 ps |
| CPU time | 95.91 seconds |
| Started | Jun 30 08:19:04 PM PDT 24 |
| Finished | Jun 30 08:20:41 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-269ffa99-de25-460a-bafa-8470d917807c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866692173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2866692173 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.1366014972 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 2349842697 ps |
| CPU time | 99.73 seconds |
| Started | Jun 30 08:18:57 PM PDT 24 |
| Finished | Jun 30 08:20:38 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-2a8277cb-7042-4ef2-afc9-0bd58b904254 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366014972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.1366014972 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.1984597461 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 75822968062 ps |
| CPU time | 790.63 seconds |
| Started | Jun 30 08:19:04 PM PDT 24 |
| Finished | Jun 30 08:32:15 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-618611e0-8c8e-411c-bbc1-c4b42f2caf61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984597461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1984597461 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.4107947498 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 49407519043 ps |
| CPU time | 838.98 seconds |
| Started | Jun 30 08:19:03 PM PDT 24 |
| Finished | Jun 30 08:33:03 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-09c1b3cb-16e0-4d69-8601-97fe63af944d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107947498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.4107947498 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.1898005683 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 135436981 ps |
| CPU time | 14.58 seconds |
| Started | Jun 30 08:19:05 PM PDT 24 |
| Finished | Jun 30 08:19:21 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-7ae5d1a7-c1ef-4d15-978d-81bce3d36303 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898005683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.1898005683 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.2815462963 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 287719148 ps |
| CPU time | 25.58 seconds |
| Started | Jun 30 08:19:04 PM PDT 24 |
| Finished | Jun 30 08:19:30 PM PDT 24 |
| Peak memory | 575192 kb |
| Host | smart-ea5509a5-1652-4f4f-bbde-b52326f3aeba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815462963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2815462963 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.449639476 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 227554020 ps |
| CPU time | 11.16 seconds |
| Started | Jun 30 08:18:49 PM PDT 24 |
| Finished | Jun 30 08:19:01 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-c569010a-af2c-4bb9-9798-8a1b79b2be46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449639476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.449639476 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.3676957023 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 7386231958 ps |
| CPU time | 79.86 seconds |
| Started | Jun 30 08:18:58 PM PDT 24 |
| Finished | Jun 30 08:20:18 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-0f516ba5-244c-4032-8132-4a450fcf4a68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676957023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3676957023 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.1080709104 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 5430133658 ps |
| CPU time | 95.47 seconds |
| Started | Jun 30 08:18:57 PM PDT 24 |
| Finished | Jun 30 08:20:33 PM PDT 24 |
| Peak memory | 566004 kb |
| Host | smart-60eac926-fbcf-418c-9ef5-57871b78bf11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080709104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1080709104 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.201021956 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 38235907 ps |
| CPU time | 6.31 seconds |
| Started | Jun 30 08:18:56 PM PDT 24 |
| Finished | Jun 30 08:19:03 PM PDT 24 |
| Peak memory | 565728 kb |
| Host | smart-d9c3a49e-7f08-4009-ab3e-fe65db8256a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201021956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays .201021956 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.2789542225 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 1102031791 ps |
| CPU time | 104.71 seconds |
| Started | Jun 30 08:19:12 PM PDT 24 |
| Finished | Jun 30 08:20:58 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-af321558-03bd-42cd-8bb1-cbb506813f4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789542225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2789542225 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.1491930860 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 961607606 ps |
| CPU time | 113.14 seconds |
| Started | Jun 30 08:19:10 PM PDT 24 |
| Finished | Jun 30 08:21:04 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-32d34e32-ad1d-411e-8bfe-3ace81ab51de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491930860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1491930860 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.2880177732 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1219885068 ps |
| CPU time | 260.4 seconds |
| Started | Jun 30 08:19:11 PM PDT 24 |
| Finished | Jun 30 08:23:32 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-47386398-a5d6-4e13-a9bc-edd98f0c1df2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880177732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.2880177732 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.1231027898 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 5010118145 ps |
| CPU time | 295.45 seconds |
| Started | Jun 30 08:19:10 PM PDT 24 |
| Finished | Jun 30 08:24:06 PM PDT 24 |
| Peak memory | 574576 kb |
| Host | smart-5cbf0cb0-83d5-43d9-b5fe-3c2ad2d99d4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231027898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.1231027898 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.3945911441 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 833557134 ps |
| CPU time | 41.65 seconds |
| Started | Jun 30 08:19:03 PM PDT 24 |
| Finished | Jun 30 08:19:45 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-7d8a776f-b24b-4a3c-bc59-c2378f9cb633 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945911441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3945911441 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.3892703818 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 653198218 ps |
| CPU time | 32.51 seconds |
| Started | Jun 30 08:19:14 PM PDT 24 |
| Finished | Jun 30 08:19:48 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-96bbdc96-a7aa-44e4-9421-80d707563d49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892703818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .3892703818 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2012121639 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 114617356820 ps |
| CPU time | 1934.56 seconds |
| Started | Jun 30 08:19:26 PM PDT 24 |
| Finished | Jun 30 08:51:41 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-c7979913-1028-4e64-bc3e-ac95db175b65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012121639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.2012121639 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.4244698664 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 293589835 ps |
| CPU time | 33.28 seconds |
| Started | Jun 30 08:19:27 PM PDT 24 |
| Finished | Jun 30 08:20:01 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-95941905-81b6-470d-bc69-c0698e52ecf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244698664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.4244698664 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.1329908332 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 172336407 ps |
| CPU time | 16.86 seconds |
| Started | Jun 30 08:19:29 PM PDT 24 |
| Finished | Jun 30 08:19:47 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-7a4143f5-5447-42d3-9a7d-c18acea6aefc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329908332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1329908332 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.3795225532 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 2381914617 ps |
| CPU time | 97.07 seconds |
| Started | Jun 30 08:19:24 PM PDT 24 |
| Finished | Jun 30 08:21:01 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-16249e2a-f384-4d12-899a-e1e24ad84df5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795225532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.3795225532 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.2947959151 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 24419005855 ps |
| CPU time | 248.88 seconds |
| Started | Jun 30 08:19:20 PM PDT 24 |
| Finished | Jun 30 08:23:30 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-3ebc3241-8711-4acc-a643-d12ef7428c1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947959151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2947959151 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.846418831 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 43088784506 ps |
| CPU time | 775.1 seconds |
| Started | Jun 30 08:19:15 PM PDT 24 |
| Finished | Jun 30 08:32:11 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-84cee870-07cf-4b02-bc90-65c85f3e27bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846418831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.846418831 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.3675548894 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 182189513 ps |
| CPU time | 19 seconds |
| Started | Jun 30 08:19:29 PM PDT 24 |
| Finished | Jun 30 08:19:48 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-50867025-8f2c-4f8e-bf2f-b5a8f6851681 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675548894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.3675548894 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.3765290550 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 506147292 ps |
| CPU time | 37.69 seconds |
| Started | Jun 30 08:19:22 PM PDT 24 |
| Finished | Jun 30 08:20:00 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-2d6b4b98-9dc6-4583-aee1-feebfbd00db9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765290550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3765290550 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.565445546 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 40937195 ps |
| CPU time | 6.66 seconds |
| Started | Jun 30 08:19:12 PM PDT 24 |
| Finished | Jun 30 08:19:19 PM PDT 24 |
| Peak memory | 565964 kb |
| Host | smart-7ef5ac62-0a36-4aaf-b896-67f8c9e8e86b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565445546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.565445546 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.2295426541 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 11297461704 ps |
| CPU time | 119.05 seconds |
| Started | Jun 30 08:19:10 PM PDT 24 |
| Finished | Jun 30 08:21:10 PM PDT 24 |
| Peak memory | 566004 kb |
| Host | smart-2a107682-3822-48f1-9504-01e35a90e7c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295426541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2295426541 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.4137212438 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 3872633501 ps |
| CPU time | 65.33 seconds |
| Started | Jun 30 08:19:16 PM PDT 24 |
| Finished | Jun 30 08:20:23 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-61e632ee-8fa7-4b8a-a480-6be6dd73da64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137212438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.4137212438 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1760088479 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 40977516 ps |
| CPU time | 6.54 seconds |
| Started | Jun 30 08:19:12 PM PDT 24 |
| Finished | Jun 30 08:19:19 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-061d05b0-b300-4d49-a8c2-e04d6dd4f9b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760088479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.1760088479 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.3595612483 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 1861040960 ps |
| CPU time | 182.71 seconds |
| Started | Jun 30 08:19:25 PM PDT 24 |
| Finished | Jun 30 08:22:28 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-6b4f6be3-ddd5-43d4-8f4f-99bbff521df4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595612483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3595612483 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.4074024007 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 2429395653 ps |
| CPU time | 89.79 seconds |
| Started | Jun 30 08:19:21 PM PDT 24 |
| Finished | Jun 30 08:20:51 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-c56e0987-f4a2-4394-a17f-33be4f95fd62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074024007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.4074024007 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.4140090499 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 7927323971 ps |
| CPU time | 339.17 seconds |
| Started | Jun 30 08:19:23 PM PDT 24 |
| Finished | Jun 30 08:25:02 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-ebd73027-7780-449b-af4b-84455ce49ba8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140090499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.4140090499 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.1479781343 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 808407652 ps |
| CPU time | 207.13 seconds |
| Started | Jun 30 08:19:29 PM PDT 24 |
| Finished | Jun 30 08:22:57 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-420337a3-2de9-4bb8-a488-05c75da55661 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479781343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.1479781343 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.2920306052 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 216292594 ps |
| CPU time | 26.56 seconds |
| Started | Jun 30 08:19:32 PM PDT 24 |
| Finished | Jun 30 08:19:59 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-0154675f-f73d-492f-9972-529d70b4710b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920306052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2920306052 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.761799062 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 352109348 ps |
| CPU time | 35.95 seconds |
| Started | Jun 30 08:19:45 PM PDT 24 |
| Finished | Jun 30 08:20:22 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-9909566f-1d87-4454-a64b-5c1675cbd60b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761799062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device. 761799062 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.852078536 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 20907616543 ps |
| CPU time | 368.17 seconds |
| Started | Jun 30 08:19:35 PM PDT 24 |
| Finished | Jun 30 08:25:44 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-69b33b23-e334-427c-9457-3d793ee75e03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852078536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_d evice_slow_rsp.852078536 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.3118033743 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 989933677 ps |
| CPU time | 44.04 seconds |
| Started | Jun 30 08:19:36 PM PDT 24 |
| Finished | Jun 30 08:20:21 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-9f999326-e691-413e-adf0-f1cc5d8c2600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118033743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.3118033743 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.1683066569 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 505725134 ps |
| CPU time | 50.41 seconds |
| Started | Jun 30 08:19:33 PM PDT 24 |
| Finished | Jun 30 08:20:24 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-b2a926fd-e98f-4e33-83a7-f6a00b59fa97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683066569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1683066569 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.2313112670 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 1132222341 ps |
| CPU time | 47.47 seconds |
| Started | Jun 30 08:19:27 PM PDT 24 |
| Finished | Jun 30 08:20:15 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-ef53d835-99bf-47bf-9559-c4326d941555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313112670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.2313112670 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.2998350598 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 65751976440 ps |
| CPU time | 768.68 seconds |
| Started | Jun 30 08:19:27 PM PDT 24 |
| Finished | Jun 30 08:32:16 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-20f6de28-e0ef-48b3-ba18-7124b0073829 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998350598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2998350598 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.4030681382 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 17745851575 ps |
| CPU time | 312.33 seconds |
| Started | Jun 30 08:19:27 PM PDT 24 |
| Finished | Jun 30 08:24:40 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-0f49d013-1c23-4a5d-8899-31484f2e9207 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030681382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.4030681382 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.2374090047 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 151029604 ps |
| CPU time | 17.81 seconds |
| Started | Jun 30 08:19:45 PM PDT 24 |
| Finished | Jun 30 08:20:04 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-9680b2e4-612d-4902-a825-5272b17377d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374090047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del ays.2374090047 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.1138034799 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 781837963 ps |
| CPU time | 27.32 seconds |
| Started | Jun 30 08:19:33 PM PDT 24 |
| Finished | Jun 30 08:20:01 PM PDT 24 |
| Peak memory | 575180 kb |
| Host | smart-00ec856d-311b-48fe-a061-10319cbe7457 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138034799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1138034799 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.1870644014 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 188961298 ps |
| CPU time | 9.34 seconds |
| Started | Jun 30 08:19:31 PM PDT 24 |
| Finished | Jun 30 08:19:40 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-a10c04eb-c07d-4b5d-91bc-5143b19b6bd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870644014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1870644014 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.342103045 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 10461377070 ps |
| CPU time | 120.78 seconds |
| Started | Jun 30 08:19:35 PM PDT 24 |
| Finished | Jun 30 08:21:37 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-cb576b41-e962-47c5-a94d-15521c830faa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342103045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.342103045 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.3777803259 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 5412120233 ps |
| CPU time | 93.85 seconds |
| Started | Jun 30 08:19:27 PM PDT 24 |
| Finished | Jun 30 08:21:01 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-c4b84e00-3c05-431b-b963-088aa8ad505a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777803259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3777803259 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.2387398614 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 36517667 ps |
| CPU time | 6.19 seconds |
| Started | Jun 30 08:19:44 PM PDT 24 |
| Finished | Jun 30 08:19:51 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-03507920-6261-4c3c-9925-b1eaa7a1e973 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387398614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.2387398614 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.2811443651 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 2110957425 ps |
| CPU time | 236.86 seconds |
| Started | Jun 30 08:19:40 PM PDT 24 |
| Finished | Jun 30 08:23:38 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-ca658d68-1969-4f2f-ba86-5781199b6563 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811443651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2811443651 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.2529876060 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 3814629513 ps |
| CPU time | 534.68 seconds |
| Started | Jun 30 08:19:44 PM PDT 24 |
| Finished | Jun 30 08:28:40 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-e5c0018f-1c3f-4ecb-9c03-22440d21eecb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529876060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.2529876060 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.1239241192 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 6519381102 ps |
| CPU time | 709.79 seconds |
| Started | Jun 30 08:19:40 PM PDT 24 |
| Finished | Jun 30 08:31:30 PM PDT 24 |
| Peak memory | 580388 kb |
| Host | smart-6a4001cf-9b94-4f13-89fa-5e6ddc2f4f68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239241192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.1239241192 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.3998046854 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 277901248 ps |
| CPU time | 36.65 seconds |
| Started | Jun 30 08:19:34 PM PDT 24 |
| Finished | Jun 30 08:20:11 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-f28df763-3efa-4291-a1ab-230f42070cc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998046854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3998046854 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.27567468 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 35722597080 ps |
| CPU time | 5207.46 seconds |
| Started | Jun 30 08:08:01 PM PDT 24 |
| Finished | Jun 30 09:34:53 PM PDT 24 |
| Peak memory | 592664 kb |
| Host | smart-77be089f-1f55-4df4-b50c-a472fd4ebac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27567468 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.chip_csr_aliasing.27567468 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.1832877702 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 9067221875 ps |
| CPU time | 1040.64 seconds |
| Started | Jun 30 08:08:00 PM PDT 24 |
| Finished | Jun 30 08:25:25 PM PDT 24 |
| Peak memory | 589144 kb |
| Host | smart-ebc5d96d-fae1-4fe2-bde3-41fbcd8026fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832877702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.1832877702 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.3363937114 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 4370439071 ps |
| CPU time | 425.01 seconds |
| Started | Jun 30 08:08:40 PM PDT 24 |
| Finished | Jun 30 08:15:45 PM PDT 24 |
| Peak memory | 597984 kb |
| Host | smart-ee0167bd-0db9-4616-9edf-2e330ab1f488 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363937114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.3363937114 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.3923840663 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 16782815900 ps |
| CPU time | 2278.19 seconds |
| Started | Jun 30 08:08:01 PM PDT 24 |
| Finished | Jun 30 08:46:04 PM PDT 24 |
| Peak memory | 591856 kb |
| Host | smart-16f1fd02-5b0b-4d2d-947c-95abe72a9773 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923840663 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.3923840663 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.901130514 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3664619396 ps |
| CPU time | 212.29 seconds |
| Started | Jun 30 08:08:02 PM PDT 24 |
| Finished | Jun 30 08:11:39 PM PDT 24 |
| Peak memory | 603412 kb |
| Host | smart-e19abb90-f505-4bcf-8a30-378bafa45389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901130514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.901130514 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.2309538824 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 964958443 ps |
| CPU time | 100.29 seconds |
| Started | Jun 30 08:08:14 PM PDT 24 |
| Finished | Jun 30 08:09:55 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-e98899d8-ebfa-4de8-8952-ef723f84ec38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309538824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 2309538824 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.2544622973 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 11089857908 ps |
| CPU time | 217.47 seconds |
| Started | Jun 30 08:08:31 PM PDT 24 |
| Finished | Jun 30 08:12:09 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-049244a4-6c62-4d91-a635-25bbde5a56b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544622973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.2544622973 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.1071901443 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 101135869 ps |
| CPU time | 15.67 seconds |
| Started | Jun 30 08:08:35 PM PDT 24 |
| Finished | Jun 30 08:08:51 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-3e9e48cb-029d-4ae9-a099-68d919728ca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071901443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .1071901443 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.2790594106 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 1109818930 ps |
| CPU time | 45.04 seconds |
| Started | Jun 30 08:08:26 PM PDT 24 |
| Finished | Jun 30 08:09:11 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-1202c8cb-cef6-4eb5-b6c7-52cb8a219852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790594106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2790594106 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.433939540 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 246855339 ps |
| CPU time | 28.03 seconds |
| Started | Jun 30 08:08:04 PM PDT 24 |
| Finished | Jun 30 08:08:35 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-a9e0681f-98c7-43da-a3c0-ef88818ac7df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433939540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.433939540 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.467284939 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 11204216542 ps |
| CPU time | 119.18 seconds |
| Started | Jun 30 08:08:15 PM PDT 24 |
| Finished | Jun 30 08:10:15 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-fe176d33-64b5-4afb-bea0-ddb03619bdda |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467284939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.467284939 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.266961790 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 25122353843 ps |
| CPU time | 452.41 seconds |
| Started | Jun 30 08:08:10 PM PDT 24 |
| Finished | Jun 30 08:15:43 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-15248c9f-1913-4ac7-9ef4-d0895b083382 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266961790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.266961790 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.3588544391 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 464211279 ps |
| CPU time | 47.81 seconds |
| Started | Jun 30 08:08:17 PM PDT 24 |
| Finished | Jun 30 08:09:05 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-97e49ffd-1c36-4e02-9277-a047c2235043 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588544391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.3588544391 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.4007250169 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 570535082 ps |
| CPU time | 21.19 seconds |
| Started | Jun 30 08:08:23 PM PDT 24 |
| Finished | Jun 30 08:08:45 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-894661cd-f717-467e-9ab0-140c8717396c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007250169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.4007250169 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.1337974392 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 218778391 ps |
| CPU time | 9.56 seconds |
| Started | Jun 30 08:08:03 PM PDT 24 |
| Finished | Jun 30 08:08:16 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-0f335417-e114-4d91-a397-debf43709867 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337974392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1337974392 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.753646494 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 7011915264 ps |
| CPU time | 71.59 seconds |
| Started | Jun 30 08:08:04 PM PDT 24 |
| Finished | Jun 30 08:09:19 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-b3fb9003-4e73-4ce3-83e6-aa92570690e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753646494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.753646494 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2079853395 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 5036103443 ps |
| CPU time | 92.04 seconds |
| Started | Jun 30 08:08:05 PM PDT 24 |
| Finished | Jun 30 08:09:40 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-1b149409-6bc2-4120-9ac4-7d88b30da2b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079853395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2079853395 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.751177460 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 54975045 ps |
| CPU time | 7.29 seconds |
| Started | Jun 30 08:08:06 PM PDT 24 |
| Finished | Jun 30 08:08:15 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-d1b6c6ef-9a27-4e2e-a623-0441fadbd1e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751177460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays. 751177460 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.174514044 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 2777655941 ps |
| CPU time | 148.71 seconds |
| Started | Jun 30 08:08:31 PM PDT 24 |
| Finished | Jun 30 08:11:00 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-1ec88bfa-9878-4b9f-8a7a-135880862bae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174514044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.174514044 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.4133073563 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 4714005552 ps |
| CPU time | 188.73 seconds |
| Started | Jun 30 08:08:28 PM PDT 24 |
| Finished | Jun 30 08:11:37 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-0f028634-0be1-4ce6-ae9c-a8d8924ce5c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133073563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.4133073563 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.1143729420 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 217202711 ps |
| CPU time | 63.86 seconds |
| Started | Jun 30 08:08:29 PM PDT 24 |
| Finished | Jun 30 08:09:33 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-ed21597f-c692-474c-94b2-fe46f8e6f81b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143729420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.1143729420 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.3998060820 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 173698203 ps |
| CPU time | 73.39 seconds |
| Started | Jun 30 08:08:30 PM PDT 24 |
| Finished | Jun 30 08:09:44 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-4ca7841f-3142-42b8-986d-6a0de36d0714 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998060820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.3998060820 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.2264794316 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 896103030 ps |
| CPU time | 47.4 seconds |
| Started | Jun 30 08:08:30 PM PDT 24 |
| Finished | Jun 30 08:09:18 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-4d6d50d7-7c5f-405a-821e-fba1cf8e82b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264794316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2264794316 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.3735911215 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 948042210 ps |
| CPU time | 82.52 seconds |
| Started | Jun 30 08:19:45 PM PDT 24 |
| Finished | Jun 30 08:21:08 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-6f08bd0f-4204-4c52-b33c-7d58e2195a9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735911215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .3735911215 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3240119574 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 23486104660 ps |
| CPU time | 437.55 seconds |
| Started | Jun 30 08:19:40 PM PDT 24 |
| Finished | Jun 30 08:26:58 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-17855cdc-6672-40fe-9588-db92195ffd6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240119574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.3240119574 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.3755788906 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 952533075 ps |
| CPU time | 37.92 seconds |
| Started | Jun 30 08:19:45 PM PDT 24 |
| Finished | Jun 30 08:20:24 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-f66673d0-a3ed-43d6-b2fd-6b20292ad968 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755788906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.3755788906 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.4252828830 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 2641017675 ps |
| CPU time | 104.84 seconds |
| Started | Jun 30 08:19:41 PM PDT 24 |
| Finished | Jun 30 08:21:26 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-1a3815d3-e831-420c-9073-43545abb106d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252828830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.4252828830 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.1955445756 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 2457663982 ps |
| CPU time | 98.47 seconds |
| Started | Jun 30 08:19:48 PM PDT 24 |
| Finished | Jun 30 08:21:27 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-365963c0-a43c-43b8-92d6-185e98819d35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955445756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.1955445756 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.3639066408 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 15133368372 ps |
| CPU time | 169.81 seconds |
| Started | Jun 30 08:19:39 PM PDT 24 |
| Finished | Jun 30 08:22:29 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-437e26c4-bf0e-4f20-9f21-7291ba8489ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639066408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3639066408 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.4172052461 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 51853011283 ps |
| CPU time | 934.4 seconds |
| Started | Jun 30 08:19:42 PM PDT 24 |
| Finished | Jun 30 08:35:17 PM PDT 24 |
| Peak memory | 575160 kb |
| Host | smart-0fc21a2e-73ae-4914-8439-e4049add6a22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172052461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.4172052461 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.2061415044 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 469488242 ps |
| CPU time | 44.12 seconds |
| Started | Jun 30 08:19:44 PM PDT 24 |
| Finished | Jun 30 08:20:29 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-746c064f-6e20-4f42-af73-96512de3bbd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061415044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.2061415044 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.3090655266 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 1206693361 ps |
| CPU time | 38.47 seconds |
| Started | Jun 30 08:19:43 PM PDT 24 |
| Finished | Jun 30 08:20:22 PM PDT 24 |
| Peak memory | 575180 kb |
| Host | smart-a4628a67-fe82-4bd6-a808-36c384255b77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090655266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3090655266 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.3285729980 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 192151835 ps |
| CPU time | 8.88 seconds |
| Started | Jun 30 08:19:45 PM PDT 24 |
| Finished | Jun 30 08:19:54 PM PDT 24 |
| Peak memory | 565896 kb |
| Host | smart-ea38a4f7-4ca3-4751-9674-f704533d221e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285729980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3285729980 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.1576274221 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 8543713157 ps |
| CPU time | 92.95 seconds |
| Started | Jun 30 08:19:42 PM PDT 24 |
| Finished | Jun 30 08:21:15 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-c50d7b24-da82-405c-b699-a4e659f13b27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576274221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1576274221 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.3103703062 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 5619457022 ps |
| CPU time | 99.29 seconds |
| Started | Jun 30 08:19:40 PM PDT 24 |
| Finished | Jun 30 08:21:20 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-6b7fba12-4b10-4233-ab7a-bed2d681e46e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103703062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3103703062 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.1867023 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 46264627 ps |
| CPU time | 6.89 seconds |
| Started | Jun 30 08:19:43 PM PDT 24 |
| Finished | Jun 30 08:19:50 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-c052ece5-bece-4f2f-9264-efce7dc26cf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.1867023 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.3844876422 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 5301604366 ps |
| CPU time | 240.2 seconds |
| Started | Jun 30 08:19:48 PM PDT 24 |
| Finished | Jun 30 08:23:48 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-2d59e9cf-893c-4837-b9cd-64379aeb24f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844876422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3844876422 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.3982438280 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 838310404 ps |
| CPU time | 98.72 seconds |
| Started | Jun 30 08:19:45 PM PDT 24 |
| Finished | Jun 30 08:21:25 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-46d89f9f-468b-4e3f-9bca-e1df14062faa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982438280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3982438280 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3268562913 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 1454771034 ps |
| CPU time | 367.48 seconds |
| Started | Jun 30 08:19:46 PM PDT 24 |
| Finished | Jun 30 08:25:54 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-ace1dfd5-3b2f-4bb4-87b2-ea91280c5ffd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268562913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.3268562913 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2587250345 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 122960924 ps |
| CPU time | 61.43 seconds |
| Started | Jun 30 08:19:49 PM PDT 24 |
| Finished | Jun 30 08:20:52 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-a378df7b-bb91-44f9-9b25-59563e206a9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587250345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.2587250345 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.3671952336 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 766476940 ps |
| CPU time | 36.39 seconds |
| Started | Jun 30 08:19:45 PM PDT 24 |
| Finished | Jun 30 08:20:23 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-65c6327c-16b0-4698-99c8-44c549d7b34a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671952336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3671952336 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.868234885 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 523032756 ps |
| CPU time | 43.59 seconds |
| Started | Jun 30 08:19:56 PM PDT 24 |
| Finished | Jun 30 08:20:40 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-e5743d3b-90f6-471b-8967-183b71f8acd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868234885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device. 868234885 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.3957551243 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 142928881072 ps |
| CPU time | 2611.96 seconds |
| Started | Jun 30 08:19:51 PM PDT 24 |
| Finished | Jun 30 09:03:23 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-2f7ca727-3e63-4aeb-92d9-3c789787d2f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957551243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.3957551243 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.3260223967 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 969722405 ps |
| CPU time | 40.32 seconds |
| Started | Jun 30 08:19:53 PM PDT 24 |
| Finished | Jun 30 08:20:34 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-7c5cec26-d998-457f-ba82-3915be3525b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260223967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.3260223967 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.1341101850 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 186694084 ps |
| CPU time | 9.79 seconds |
| Started | Jun 30 08:19:49 PM PDT 24 |
| Finished | Jun 30 08:20:00 PM PDT 24 |
| Peak memory | 565664 kb |
| Host | smart-34a4afb5-434f-47ab-b38d-d01a4612549c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341101850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1341101850 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.2690716120 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 1862569687 ps |
| CPU time | 72.74 seconds |
| Started | Jun 30 08:19:55 PM PDT 24 |
| Finished | Jun 30 08:21:08 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-97c55912-cef4-475d-83e3-a784dab8a4ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690716120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.2690716120 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.979789481 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 42724731942 ps |
| CPU time | 470.25 seconds |
| Started | Jun 30 08:19:47 PM PDT 24 |
| Finished | Jun 30 08:27:38 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-adbc6493-b569-46fd-8f62-686d63801a1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979789481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.979789481 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.2209570322 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 15878245049 ps |
| CPU time | 263.94 seconds |
| Started | Jun 30 08:19:45 PM PDT 24 |
| Finished | Jun 30 08:24:10 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-f09fc70b-75b5-4ad4-8136-01ff8d91b9c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209570322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2209570322 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.3419054075 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 65114492 ps |
| CPU time | 9.15 seconds |
| Started | Jun 30 08:19:44 PM PDT 24 |
| Finished | Jun 30 08:19:53 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-c8e03d5c-dabd-4f65-9b2e-59af9f1409a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419054075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.3419054075 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.723800428 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 386641325 ps |
| CPU time | 31.89 seconds |
| Started | Jun 30 08:19:52 PM PDT 24 |
| Finished | Jun 30 08:20:24 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-9e08c795-b019-461a-b013-bbcd287ef911 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723800428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.723800428 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.2198844271 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 47266142 ps |
| CPU time | 7.04 seconds |
| Started | Jun 30 08:19:45 PM PDT 24 |
| Finished | Jun 30 08:19:53 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-78b89b6d-c429-42f9-9875-6b29a3be0359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198844271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2198844271 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.3245193800 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 8334427753 ps |
| CPU time | 85.74 seconds |
| Started | Jun 30 08:19:53 PM PDT 24 |
| Finished | Jun 30 08:21:19 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-ec374558-4fc7-4749-afe3-edcee3e3c0e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245193800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3245193800 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.319140339 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 5388338213 ps |
| CPU time | 96.58 seconds |
| Started | Jun 30 08:19:46 PM PDT 24 |
| Finished | Jun 30 08:21:23 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-761f39c9-b7ac-4a3e-9211-f4d459036f06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319140339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.319140339 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.304500718 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 51829244 ps |
| CPU time | 7.14 seconds |
| Started | Jun 30 08:19:52 PM PDT 24 |
| Finished | Jun 30 08:19:59 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-9c84bf22-a81f-4f45-99a1-c0809ed90afa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304500718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays .304500718 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.2380112468 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 13131835962 ps |
| CPU time | 496.26 seconds |
| Started | Jun 30 08:19:54 PM PDT 24 |
| Finished | Jun 30 08:28:10 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-ae5becf9-dc1f-40d0-896f-97569e475f2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380112468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2380112468 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3495707419 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 689712795 ps |
| CPU time | 72.5 seconds |
| Started | Jun 30 08:19:52 PM PDT 24 |
| Finished | Jun 30 08:21:05 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-3acb33a8-a2d9-42fe-b520-9325b28272c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495707419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.3495707419 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.1945880529 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 475862589 ps |
| CPU time | 192.9 seconds |
| Started | Jun 30 08:19:55 PM PDT 24 |
| Finished | Jun 30 08:23:09 PM PDT 24 |
| Peak memory | 577416 kb |
| Host | smart-388de1d8-cf08-4422-bc5f-6bf2f1ad7414 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945880529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.1945880529 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.3588046548 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 1278266313 ps |
| CPU time | 60.59 seconds |
| Started | Jun 30 08:19:55 PM PDT 24 |
| Finished | Jun 30 08:20:56 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-a2ffd8c3-5d37-45b3-bf54-57140c819a98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588046548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3588046548 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.3173651077 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 777007276 ps |
| CPU time | 65.18 seconds |
| Started | Jun 30 08:19:58 PM PDT 24 |
| Finished | Jun 30 08:21:04 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-622730ff-3b66-460f-922d-7ce5e47f9903 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173651077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .3173651077 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.220044917 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 70647230464 ps |
| CPU time | 1227.21 seconds |
| Started | Jun 30 08:19:58 PM PDT 24 |
| Finished | Jun 30 08:40:26 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-28f8f958-2735-4f33-90c5-94e214a67cfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220044917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_d evice_slow_rsp.220044917 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.3167130369 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 173361776 ps |
| CPU time | 17.95 seconds |
| Started | Jun 30 08:19:59 PM PDT 24 |
| Finished | Jun 30 08:20:18 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-0b2e5c44-6ae9-4b1b-8bc2-4a2a5db73bd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167130369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.3167130369 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.2107018062 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 156310200 ps |
| CPU time | 17.63 seconds |
| Started | Jun 30 08:19:57 PM PDT 24 |
| Finished | Jun 30 08:20:15 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-d9ca3b42-21dc-4467-ab23-185653f18604 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107018062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2107018062 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.3081053566 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 266653000 ps |
| CPU time | 30.01 seconds |
| Started | Jun 30 08:19:59 PM PDT 24 |
| Finished | Jun 30 08:20:30 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-b955f480-0905-4848-8470-6d9d945ab015 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081053566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.3081053566 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.4238272237 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 47902552717 ps |
| CPU time | 529.37 seconds |
| Started | Jun 30 08:19:59 PM PDT 24 |
| Finished | Jun 30 08:28:49 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-78a61bea-3492-48d7-ad8f-bd2af7c9eaca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238272237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.4238272237 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.4055236398 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 48011815697 ps |
| CPU time | 831.3 seconds |
| Started | Jun 30 08:20:00 PM PDT 24 |
| Finished | Jun 30 08:33:52 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-9c731cf5-76c9-4bcc-81be-f6201be5c1b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055236398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.4055236398 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.707806332 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 433551148 ps |
| CPU time | 41.19 seconds |
| Started | Jun 30 08:19:58 PM PDT 24 |
| Finished | Jun 30 08:20:40 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-76d26b96-7552-43ca-b98d-cb7f5fe839f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707806332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_dela ys.707806332 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.1432362920 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 1736861379 ps |
| CPU time | 58.65 seconds |
| Started | Jun 30 08:20:01 PM PDT 24 |
| Finished | Jun 30 08:21:00 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-8678dd37-d119-4d78-91d7-66d3a12f2d32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432362920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1432362920 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.1285490821 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 52255841 ps |
| CPU time | 7.13 seconds |
| Started | Jun 30 08:19:52 PM PDT 24 |
| Finished | Jun 30 08:19:59 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-231c409c-cbac-40cb-91b1-0a413047706f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285490821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1285490821 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.3385164147 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 7337004516 ps |
| CPU time | 82.26 seconds |
| Started | Jun 30 08:19:56 PM PDT 24 |
| Finished | Jun 30 08:21:19 PM PDT 24 |
| Peak memory | 566008 kb |
| Host | smart-d4579a6b-0af8-417d-a59a-6e3bae93371d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385164147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3385164147 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.1999517401 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 6213921905 ps |
| CPU time | 107.84 seconds |
| Started | Jun 30 08:19:59 PM PDT 24 |
| Finished | Jun 30 08:21:48 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-8e5808c4-0976-4498-97a9-62f9cfb131d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999517401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1999517401 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.1185693635 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 46374502 ps |
| CPU time | 6.56 seconds |
| Started | Jun 30 08:19:53 PM PDT 24 |
| Finished | Jun 30 08:20:00 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-66994b1c-78c2-486e-b755-1347a4eafbdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185693635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.1185693635 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.1096133911 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 4666773353 ps |
| CPU time | 200.81 seconds |
| Started | Jun 30 08:20:07 PM PDT 24 |
| Finished | Jun 30 08:23:29 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-b84b41c0-15e9-47c8-8ea0-9940517ecf4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096133911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1096133911 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.793176518 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 2836237094 ps |
| CPU time | 298.06 seconds |
| Started | Jun 30 08:20:01 PM PDT 24 |
| Finished | Jun 30 08:25:00 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-538a357e-805e-41a2-bcec-612a4e495fd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793176518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.793176518 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.2557006285 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 353118778 ps |
| CPU time | 116.64 seconds |
| Started | Jun 30 08:20:04 PM PDT 24 |
| Finished | Jun 30 08:22:01 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-4e81c9d7-72e8-4fca-ac62-1e95a1820d90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557006285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.2557006285 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.2678765636 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 508068463 ps |
| CPU time | 22.57 seconds |
| Started | Jun 30 08:20:01 PM PDT 24 |
| Finished | Jun 30 08:20:24 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-ed67dc1b-e9a1-454a-a36c-44c1ca2dcfc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678765636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2678765636 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.296896716 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 1888353933 ps |
| CPU time | 89.2 seconds |
| Started | Jun 30 08:20:04 PM PDT 24 |
| Finished | Jun 30 08:21:34 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-782be14d-2472-4825-ab68-39044bf77764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296896716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device. 296896716 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1176722826 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 68728594104 ps |
| CPU time | 1166.88 seconds |
| Started | Jun 30 08:20:08 PM PDT 24 |
| Finished | Jun 30 08:39:36 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-0f7480d3-9f7b-43d6-b12a-43fc8d6935d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176722826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.1176722826 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.2222531871 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 1364977437 ps |
| CPU time | 62.47 seconds |
| Started | Jun 30 08:20:08 PM PDT 24 |
| Finished | Jun 30 08:21:11 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-81fbde4f-a3d7-4fba-8ffb-519099237488 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222531871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.2222531871 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.633690901 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 2395732607 ps |
| CPU time | 91.78 seconds |
| Started | Jun 30 08:20:08 PM PDT 24 |
| Finished | Jun 30 08:21:40 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-a39f9a1c-a73e-4798-a9f9-1e386d4ba40d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633690901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.633690901 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.750002620 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 1399063432 ps |
| CPU time | 57.54 seconds |
| Started | Jun 30 08:20:02 PM PDT 24 |
| Finished | Jun 30 08:21:00 PM PDT 24 |
| Peak memory | 575128 kb |
| Host | smart-a54981d0-4c36-4b80-91eb-736e2446ce78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750002620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.750002620 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.1672257021 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 85223723860 ps |
| CPU time | 962.08 seconds |
| Started | Jun 30 08:20:04 PM PDT 24 |
| Finished | Jun 30 08:36:07 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-9ad0b806-5294-408b-802b-46004fc10873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672257021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1672257021 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.550802737 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 11767742457 ps |
| CPU time | 211.48 seconds |
| Started | Jun 30 08:20:07 PM PDT 24 |
| Finished | Jun 30 08:23:39 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-ca2e1712-e6ba-4dba-905e-bbc359423ba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550802737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.550802737 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.3517393174 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 429125853 ps |
| CPU time | 46.47 seconds |
| Started | Jun 30 08:20:03 PM PDT 24 |
| Finished | Jun 30 08:20:50 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-bb18384f-2b23-4e89-8167-a648e1818e27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517393174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.3517393174 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.3207570232 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 2118801694 ps |
| CPU time | 65.66 seconds |
| Started | Jun 30 08:20:11 PM PDT 24 |
| Finished | Jun 30 08:21:17 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-71a10552-5348-48fd-9f92-bb0320a8c731 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207570232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3207570232 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.230389656 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 233214048 ps |
| CPU time | 10.42 seconds |
| Started | Jun 30 08:20:08 PM PDT 24 |
| Finished | Jun 30 08:20:19 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-7539c43d-d02a-4368-af99-68ecfbdc6f95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230389656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.230389656 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.321925534 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 9721275913 ps |
| CPU time | 101.49 seconds |
| Started | Jun 30 08:20:04 PM PDT 24 |
| Finished | Jun 30 08:21:46 PM PDT 24 |
| Peak memory | 566036 kb |
| Host | smart-841d3216-769b-48bb-82cd-a8ad99c65bbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321925534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.321925534 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.3507471341 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 6119836501 ps |
| CPU time | 100.13 seconds |
| Started | Jun 30 08:20:05 PM PDT 24 |
| Finished | Jun 30 08:21:46 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-ee85db7c-ccca-410d-af67-3f873dcd79e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507471341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3507471341 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.1157749132 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 48039299 ps |
| CPU time | 6.6 seconds |
| Started | Jun 30 08:20:07 PM PDT 24 |
| Finished | Jun 30 08:20:14 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-cea586c1-9059-4be5-af2b-eb00260bdda9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157749132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.1157749132 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.50320304 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 3398455333 ps |
| CPU time | 121.83 seconds |
| Started | Jun 30 08:20:09 PM PDT 24 |
| Finished | Jun 30 08:22:11 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-bf8fa6a1-d8bb-4b53-98ae-6822dc8a412c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50320304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.50320304 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.2484062379 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 229971876 ps |
| CPU time | 13.39 seconds |
| Started | Jun 30 08:20:08 PM PDT 24 |
| Finished | Jun 30 08:20:22 PM PDT 24 |
| Peak memory | 565604 kb |
| Host | smart-d6609ccc-b387-4fe9-bb73-dffd2b4d7078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484062379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2484062379 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.2513112833 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 571147331 ps |
| CPU time | 168.82 seconds |
| Started | Jun 30 08:20:13 PM PDT 24 |
| Finished | Jun 30 08:23:02 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-e704a3ee-0d20-49c0-af12-045182392627 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513112833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.2513112833 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.2009789764 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 726652202 ps |
| CPU time | 36.62 seconds |
| Started | Jun 30 08:20:10 PM PDT 24 |
| Finished | Jun 30 08:20:47 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-6f6f4e9f-7ccf-49f3-88a5-38206e6ab033 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009789764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2009789764 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.221010115 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 2407071607 ps |
| CPU time | 106.42 seconds |
| Started | Jun 30 08:20:18 PM PDT 24 |
| Finished | Jun 30 08:22:05 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-6dba1384-40df-49c1-ad7a-10fd0ffcd90d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221010115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device. 221010115 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3867126369 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 83603483 ps |
| CPU time | 11.98 seconds |
| Started | Jun 30 08:20:20 PM PDT 24 |
| Finished | Jun 30 08:20:33 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-96c33fa8-ff04-4dca-b0fb-3c9bc69e02a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867126369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.3867126369 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.3685061378 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 155342298 ps |
| CPU time | 17.23 seconds |
| Started | Jun 30 08:20:20 PM PDT 24 |
| Finished | Jun 30 08:20:37 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-b007a536-7796-4df5-8d56-141dd660a900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685061378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3685061378 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.695895103 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1429236156 ps |
| CPU time | 60.39 seconds |
| Started | Jun 30 08:20:15 PM PDT 24 |
| Finished | Jun 30 08:21:16 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-92da12f3-d176-4f26-8b5f-19505cda5666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695895103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.695895103 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.3032330495 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 58119478601 ps |
| CPU time | 601.24 seconds |
| Started | Jun 30 08:20:15 PM PDT 24 |
| Finished | Jun 30 08:30:17 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-821c16d2-632d-4d73-b5c3-a189f293325f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032330495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3032330495 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.3979668436 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 8699767959 ps |
| CPU time | 152.64 seconds |
| Started | Jun 30 08:20:16 PM PDT 24 |
| Finished | Jun 30 08:22:49 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-1dc14ff4-f583-4595-8e6b-92cdd36e61db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979668436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3979668436 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.235228930 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 279063028 ps |
| CPU time | 28.97 seconds |
| Started | Jun 30 08:20:16 PM PDT 24 |
| Finished | Jun 30 08:20:45 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-c76792c9-cbdc-4058-b741-f208fa2534bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235228930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_dela ys.235228930 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.2153449793 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 1353952176 ps |
| CPU time | 45.3 seconds |
| Started | Jun 30 08:20:20 PM PDT 24 |
| Finished | Jun 30 08:21:06 PM PDT 24 |
| Peak memory | 575192 kb |
| Host | smart-6c0cdbef-c78e-4d58-91ca-9d25748bc21e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153449793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2153449793 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.3995147198 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 199092541 ps |
| CPU time | 10.01 seconds |
| Started | Jun 30 08:20:14 PM PDT 24 |
| Finished | Jun 30 08:20:25 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-9763f578-3ff9-4bc8-9421-a7bf45a01374 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995147198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3995147198 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.256181526 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 8681935494 ps |
| CPU time | 90.82 seconds |
| Started | Jun 30 08:20:14 PM PDT 24 |
| Finished | Jun 30 08:21:45 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-52789b13-3e74-4f1a-ba45-237d9fc8002d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256181526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.256181526 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.2303773249 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 6949374796 ps |
| CPU time | 124.22 seconds |
| Started | Jun 30 08:20:15 PM PDT 24 |
| Finished | Jun 30 08:22:20 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-3a7c045b-a562-4e4e-a478-a873ed66475a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303773249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2303773249 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1530313882 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 45558436 ps |
| CPU time | 7.29 seconds |
| Started | Jun 30 08:20:18 PM PDT 24 |
| Finished | Jun 30 08:20:26 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-6ee985b4-cad8-4813-b245-58dfea480cf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530313882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.1530313882 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.2942126550 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 4799594560 ps |
| CPU time | 203.1 seconds |
| Started | Jun 30 08:20:21 PM PDT 24 |
| Finished | Jun 30 08:23:44 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-0443e3e3-12d2-48c9-8c23-4612b3447d0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942126550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2942126550 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.4271926879 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 870144552 ps |
| CPU time | 85.4 seconds |
| Started | Jun 30 08:20:24 PM PDT 24 |
| Finished | Jun 30 08:21:51 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-c2bb1ccd-c055-4f3e-bc5c-e5c12b802a44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271926879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.4271926879 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.3378273741 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 359145821 ps |
| CPU time | 96.34 seconds |
| Started | Jun 30 08:20:22 PM PDT 24 |
| Finished | Jun 30 08:21:59 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-087ab00d-57fc-4189-9791-4e1d6f9dadd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378273741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.3378273741 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3860383771 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 49563867 ps |
| CPU time | 19.06 seconds |
| Started | Jun 30 08:20:26 PM PDT 24 |
| Finished | Jun 30 08:20:46 PM PDT 24 |
| Peak memory | 565912 kb |
| Host | smart-3c532640-6f40-4b40-951b-125203a5be33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860383771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.3860383771 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.2629013250 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 1417007812 ps |
| CPU time | 63.22 seconds |
| Started | Jun 30 08:20:23 PM PDT 24 |
| Finished | Jun 30 08:21:26 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-5f608060-6953-4b52-8c5e-dd63c581b581 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629013250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2629013250 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.1832326218 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 600320697 ps |
| CPU time | 47.66 seconds |
| Started | Jun 30 08:20:33 PM PDT 24 |
| Finished | Jun 30 08:21:21 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-6eeb763b-908f-413c-9187-7ad6e9b128bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832326218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .1832326218 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.435946453 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 52693281690 ps |
| CPU time | 922.73 seconds |
| Started | Jun 30 08:20:32 PM PDT 24 |
| Finished | Jun 30 08:35:56 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-8e151d0f-14e4-467a-b498-cba827ef4482 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435946453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_d evice_slow_rsp.435946453 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2816858337 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 642149505 ps |
| CPU time | 30.17 seconds |
| Started | Jun 30 08:20:31 PM PDT 24 |
| Finished | Jun 30 08:21:02 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-0cd1aca1-e9f5-4e98-85a1-db2583def059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816858337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.2816858337 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.3889532745 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 628884198 ps |
| CPU time | 23.51 seconds |
| Started | Jun 30 08:20:32 PM PDT 24 |
| Finished | Jun 30 08:20:57 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-16659427-07a3-469a-adf9-958e466aaf1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889532745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3889532745 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.942751683 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 223968873 ps |
| CPU time | 23.6 seconds |
| Started | Jun 30 08:20:29 PM PDT 24 |
| Finished | Jun 30 08:20:53 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-37b3eaae-7902-4707-8d46-9061943acd16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942751683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.942751683 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.2817099952 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 21088011562 ps |
| CPU time | 227.52 seconds |
| Started | Jun 30 08:20:27 PM PDT 24 |
| Finished | Jun 30 08:24:15 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-908103d2-d69f-45bd-a572-683077f043aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817099952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2817099952 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.2452425242 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 4260537300 ps |
| CPU time | 69.74 seconds |
| Started | Jun 30 08:20:26 PM PDT 24 |
| Finished | Jun 30 08:21:36 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-a174ff19-9f01-4680-9cf7-a2182a3e7362 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452425242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2452425242 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.1687905831 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 146658420 ps |
| CPU time | 17.24 seconds |
| Started | Jun 30 08:20:29 PM PDT 24 |
| Finished | Jun 30 08:20:47 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-34d732d1-64a2-4681-879b-0b00d5fd29a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687905831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.1687905831 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.1857953608 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 2742215760 ps |
| CPU time | 81.63 seconds |
| Started | Jun 30 08:20:34 PM PDT 24 |
| Finished | Jun 30 08:21:57 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-1faddce2-bd6e-49d9-a56c-a7f38f5674d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857953608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1857953608 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.3764225143 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 209489011 ps |
| CPU time | 9.95 seconds |
| Started | Jun 30 08:20:28 PM PDT 24 |
| Finished | Jun 30 08:20:39 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-6f18943a-4a3b-4b76-bc89-fc22b5dda409 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764225143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.3764225143 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.3269645203 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 10431787793 ps |
| CPU time | 113.98 seconds |
| Started | Jun 30 08:20:27 PM PDT 24 |
| Finished | Jun 30 08:22:22 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-96b0f9bb-77ca-4047-8b40-b1bf5e936812 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269645203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3269645203 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.2099904429 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 4336152262 ps |
| CPU time | 79.86 seconds |
| Started | Jun 30 08:20:27 PM PDT 24 |
| Finished | Jun 30 08:21:47 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-6f228630-55b9-4b23-9bc2-2e1280ea212d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099904429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2099904429 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.2988924470 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 62232116 ps |
| CPU time | 7.38 seconds |
| Started | Jun 30 08:20:25 PM PDT 24 |
| Finished | Jun 30 08:20:33 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-47247eb0-3291-409b-9f2b-5fa9fa0df81d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988924470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.2988924470 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.4022288984 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 2862808219 ps |
| CPU time | 270.66 seconds |
| Started | Jun 30 08:20:41 PM PDT 24 |
| Finished | Jun 30 08:25:13 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-a2cb1064-5280-40e4-b8fb-d74c556d744c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022288984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.4022288984 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.3237543318 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 3321502344 ps |
| CPU time | 243.28 seconds |
| Started | Jun 30 08:20:40 PM PDT 24 |
| Finished | Jun 30 08:24:44 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-c961f116-2acd-44dc-96a8-66464162a963 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237543318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3237543318 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.1697335979 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 430391266 ps |
| CPU time | 160.37 seconds |
| Started | Jun 30 08:20:40 PM PDT 24 |
| Finished | Jun 30 08:23:21 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-5cc2fc9a-a4cf-4d67-b28a-e8570b3fc6a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697335979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.1697335979 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3069475464 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 13041000224 ps |
| CPU time | 644.91 seconds |
| Started | Jun 30 08:20:37 PM PDT 24 |
| Finished | Jun 30 08:31:23 PM PDT 24 |
| Peak memory | 577464 kb |
| Host | smart-07df1bd5-00d8-4bb7-8010-bb55e3a4f350 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069475464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.3069475464 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.1677279596 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 134081160 ps |
| CPU time | 9.92 seconds |
| Started | Jun 30 08:20:32 PM PDT 24 |
| Finished | Jun 30 08:20:43 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-6de8b2ab-4742-466d-91d8-16eaf3193a72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677279596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1677279596 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.2549799962 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 781937380 ps |
| CPU time | 78.77 seconds |
| Started | Jun 30 08:20:44 PM PDT 24 |
| Finished | Jun 30 08:22:04 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-266af752-2f76-4b08-8c66-6b15105fd4f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549799962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .2549799962 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.2542672132 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 384432696 ps |
| CPU time | 18.07 seconds |
| Started | Jun 30 08:20:48 PM PDT 24 |
| Finished | Jun 30 08:21:07 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-b07e7daf-d410-409d-91f1-5339e6344abe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542672132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.2542672132 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.2367905012 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 297948516 ps |
| CPU time | 15.65 seconds |
| Started | Jun 30 08:20:43 PM PDT 24 |
| Finished | Jun 30 08:20:59 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-baee3211-dbb6-49b0-901d-0b6bc8084c03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367905012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2367905012 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.1998107327 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 468143572 ps |
| CPU time | 42.04 seconds |
| Started | Jun 30 08:20:44 PM PDT 24 |
| Finished | Jun 30 08:21:27 PM PDT 24 |
| Peak memory | 575120 kb |
| Host | smart-e0550b11-fefe-4da8-88fa-a94d002df42b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998107327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.1998107327 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.2563411088 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 108358139966 ps |
| CPU time | 1071.6 seconds |
| Started | Jun 30 08:20:42 PM PDT 24 |
| Finished | Jun 30 08:38:34 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-213bbe5b-cb28-4c18-a933-29cc73467c48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563411088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2563411088 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.2488186600 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 46130321147 ps |
| CPU time | 814.17 seconds |
| Started | Jun 30 08:20:44 PM PDT 24 |
| Finished | Jun 30 08:34:19 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-56682fe5-0d87-437e-a63e-627764a0a64d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488186600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2488186600 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.826062244 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 403445897 ps |
| CPU time | 41.86 seconds |
| Started | Jun 30 08:20:42 PM PDT 24 |
| Finished | Jun 30 08:21:25 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-b07974f6-2536-4173-ad9b-d49ce5d9561f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826062244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_dela ys.826062244 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.1642931501 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 2103536194 ps |
| CPU time | 71.79 seconds |
| Started | Jun 30 08:20:45 PM PDT 24 |
| Finished | Jun 30 08:21:57 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-33672d5b-5d03-4333-a281-f3e9f719885b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642931501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1642931501 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.2831532144 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 212839908 ps |
| CPU time | 9.17 seconds |
| Started | Jun 30 08:20:37 PM PDT 24 |
| Finished | Jun 30 08:20:48 PM PDT 24 |
| Peak memory | 565888 kb |
| Host | smart-082a7d94-72bc-48bc-b24d-417dd1693282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831532144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2831532144 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.1774144731 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 7498062118 ps |
| CPU time | 78.51 seconds |
| Started | Jun 30 08:20:41 PM PDT 24 |
| Finished | Jun 30 08:22:01 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-2b21b73e-125e-4be2-a34a-508c9564c124 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774144731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1774144731 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.2181989354 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 3243277897 ps |
| CPU time | 54.06 seconds |
| Started | Jun 30 08:20:38 PM PDT 24 |
| Finished | Jun 30 08:21:34 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-5b49866e-bc99-4cea-8067-844026c8073a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181989354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2181989354 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.3319706476 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 45257462 ps |
| CPU time | 6.51 seconds |
| Started | Jun 30 08:20:41 PM PDT 24 |
| Finished | Jun 30 08:20:48 PM PDT 24 |
| Peak memory | 565860 kb |
| Host | smart-6dd27886-795b-4122-89a3-43a7e7e16b52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319706476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.3319706476 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.2144136301 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 283376907 ps |
| CPU time | 33.97 seconds |
| Started | Jun 30 08:20:48 PM PDT 24 |
| Finished | Jun 30 08:21:22 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-c0a4a23b-8b48-4b5d-9b76-fa249431a907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144136301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2144136301 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.249287534 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 1847793179 ps |
| CPU time | 79.77 seconds |
| Started | Jun 30 08:20:49 PM PDT 24 |
| Finished | Jun 30 08:22:10 PM PDT 24 |
| Peak memory | 573844 kb |
| Host | smart-47535ac6-b790-4109-90f3-dbdb9f277d4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249287534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.249287534 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3385466399 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 2616804659 ps |
| CPU time | 286.92 seconds |
| Started | Jun 30 08:20:48 PM PDT 24 |
| Finished | Jun 30 08:25:36 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-0f57aba9-bfe0-44e7-8ec8-1543800b4746 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385466399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.3385466399 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.615899805 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 5229378990 ps |
| CPU time | 281.62 seconds |
| Started | Jun 30 08:20:51 PM PDT 24 |
| Finished | Jun 30 08:25:33 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-6fd70eb8-0b5f-4a57-b2df-a34e4c3edac5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615899805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_reset_error.615899805 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.1528788418 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 937135394 ps |
| CPU time | 46.73 seconds |
| Started | Jun 30 08:20:49 PM PDT 24 |
| Finished | Jun 30 08:21:36 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-8e25dd64-299e-4958-85fc-6594db2ed1f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528788418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1528788418 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.578075036 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 499989410 ps |
| CPU time | 39.81 seconds |
| Started | Jun 30 08:20:55 PM PDT 24 |
| Finished | Jun 30 08:21:35 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-f2c5d517-64fc-46fb-9391-c62780033b8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578075036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device. 578075036 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.3268396284 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 107020629118 ps |
| CPU time | 1911.72 seconds |
| Started | Jun 30 08:20:53 PM PDT 24 |
| Finished | Jun 30 08:52:45 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-522bdc77-8312-4dac-817a-fb83c798e103 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268396284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.3268396284 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.3487970414 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 756568246 ps |
| CPU time | 35.99 seconds |
| Started | Jun 30 08:20:59 PM PDT 24 |
| Finished | Jun 30 08:21:36 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-51a2443c-f12a-4459-8763-49a9e60604dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487970414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.3487970414 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.1799387074 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 250681890 ps |
| CPU time | 12.39 seconds |
| Started | Jun 30 08:20:54 PM PDT 24 |
| Finished | Jun 30 08:21:06 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-cfcc8a5e-6fd1-4003-baa6-886f3df58808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799387074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1799387074 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.999846249 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 424318546 ps |
| CPU time | 17.81 seconds |
| Started | Jun 30 08:20:48 PM PDT 24 |
| Finished | Jun 30 08:21:07 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-d3012483-8631-402a-b5d9-97903941a9f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999846249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.999846249 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.3770909894 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 103643879819 ps |
| CPU time | 1189.56 seconds |
| Started | Jun 30 08:20:53 PM PDT 24 |
| Finished | Jun 30 08:40:43 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-43e7968f-4c85-40ed-8657-35b39c8bf185 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770909894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3770909894 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.987434371 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 9069610562 ps |
| CPU time | 152.16 seconds |
| Started | Jun 30 08:20:52 PM PDT 24 |
| Finished | Jun 30 08:23:25 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-ae72be54-1a83-4841-8918-e1ecf9276a27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987434371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.987434371 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.396230074 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 497418926 ps |
| CPU time | 46.15 seconds |
| Started | Jun 30 08:20:52 PM PDT 24 |
| Finished | Jun 30 08:21:39 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-f2feda94-2a5d-4dd4-b981-980b69dc49fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396230074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_dela ys.396230074 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.1528659358 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 1159397604 ps |
| CPU time | 40.4 seconds |
| Started | Jun 30 08:20:53 PM PDT 24 |
| Finished | Jun 30 08:21:34 PM PDT 24 |
| Peak memory | 575176 kb |
| Host | smart-8a316eca-06fe-4495-92bd-39183b70de64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528659358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1528659358 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.1243533543 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 146055382 ps |
| CPU time | 8.57 seconds |
| Started | Jun 30 08:20:49 PM PDT 24 |
| Finished | Jun 30 08:20:59 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-db8112b2-161c-4c58-ad51-300fd7abafe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243533543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1243533543 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.27645198 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 6709108455 ps |
| CPU time | 70 seconds |
| Started | Jun 30 08:20:48 PM PDT 24 |
| Finished | Jun 30 08:21:59 PM PDT 24 |
| Peak memory | 566008 kb |
| Host | smart-ab70fc8b-a5ca-40f1-80c6-e924768de0a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27645198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.27645198 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.2637903764 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 5286155110 ps |
| CPU time | 95.46 seconds |
| Started | Jun 30 08:20:48 PM PDT 24 |
| Finished | Jun 30 08:22:24 PM PDT 24 |
| Peak memory | 566008 kb |
| Host | smart-80372b7f-a61c-49ea-96b0-675328808592 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637903764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2637903764 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.1375525506 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 48060432 ps |
| CPU time | 7.27 seconds |
| Started | Jun 30 08:20:47 PM PDT 24 |
| Finished | Jun 30 08:20:55 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-235fb8ea-e108-4858-a22a-96674096e491 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375525506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.1375525506 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.1788304739 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 8106944434 ps |
| CPU time | 340.55 seconds |
| Started | Jun 30 08:21:01 PM PDT 24 |
| Finished | Jun 30 08:26:42 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-6f878a2f-e080-4940-b0cb-6f7321205762 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788304739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1788304739 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.921909385 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 14383516732 ps |
| CPU time | 498.59 seconds |
| Started | Jun 30 08:21:01 PM PDT 24 |
| Finished | Jun 30 08:29:20 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-27345bfe-e28d-498f-ae57-99f437e287d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921909385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.921909385 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.3654223647 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 11586206470 ps |
| CPU time | 648.24 seconds |
| Started | Jun 30 08:21:03 PM PDT 24 |
| Finished | Jun 30 08:31:52 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-f25a9bb1-5bf7-42e2-8a56-c6ecb40b501a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654223647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.3654223647 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.817326454 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 3692816525 ps |
| CPU time | 341.06 seconds |
| Started | Jun 30 08:20:59 PM PDT 24 |
| Finished | Jun 30 08:26:41 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-4c0fa6e7-6b4f-4089-9439-30a698cc1fd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817326454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_reset_error.817326454 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.420446459 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 349012634 ps |
| CPU time | 17.58 seconds |
| Started | Jun 30 08:20:54 PM PDT 24 |
| Finished | Jun 30 08:21:11 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-cb3468c4-8396-4b15-b08d-bc25dfb605e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420446459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.420446459 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.1939406261 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 628440000 ps |
| CPU time | 27.62 seconds |
| Started | Jun 30 08:21:06 PM PDT 24 |
| Finished | Jun 30 08:21:34 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-876961c4-90d0-44fb-b0d5-6916626e7feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939406261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .1939406261 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1857708580 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 18998056 ps |
| CPU time | 5.25 seconds |
| Started | Jun 30 08:21:16 PM PDT 24 |
| Finished | Jun 30 08:21:22 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-e1d62c54-08ab-4fb2-ac23-51c2eca25e77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857708580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.1857708580 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.1223306791 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 156734018 ps |
| CPU time | 8.97 seconds |
| Started | Jun 30 08:21:12 PM PDT 24 |
| Finished | Jun 30 08:21:22 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-c2a93356-fc00-48d2-b090-bfee4453b62a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223306791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1223306791 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.2768824224 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 627096444 ps |
| CPU time | 28.41 seconds |
| Started | Jun 30 08:21:08 PM PDT 24 |
| Finished | Jun 30 08:21:37 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-32f19f23-5c1e-4b6d-b25b-c7e94cd92265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768824224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.2768824224 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.2469879651 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 102198318076 ps |
| CPU time | 1058.48 seconds |
| Started | Jun 30 08:21:06 PM PDT 24 |
| Finished | Jun 30 08:38:45 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-405460cb-b85f-4a17-a0f8-168ed98989bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469879651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2469879651 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.300439441 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 72730333136 ps |
| CPU time | 1212.16 seconds |
| Started | Jun 30 08:21:07 PM PDT 24 |
| Finished | Jun 30 08:41:20 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-b4d0b63d-94ee-47d9-9546-abaa498f05fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300439441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.300439441 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.4088042827 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 282891629 ps |
| CPU time | 30.63 seconds |
| Started | Jun 30 08:21:05 PM PDT 24 |
| Finished | Jun 30 08:21:36 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-65741879-a0de-42b0-8014-5ee11811077e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088042827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.4088042827 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.1749461260 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 520676568 ps |
| CPU time | 18.02 seconds |
| Started | Jun 30 08:21:08 PM PDT 24 |
| Finished | Jun 30 08:21:27 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-0f26f38f-2f64-455d-9df5-cd82a5efe6ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749461260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1749461260 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.3255289373 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 51277075 ps |
| CPU time | 7 seconds |
| Started | Jun 30 08:21:00 PM PDT 24 |
| Finished | Jun 30 08:21:07 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-4b41d3cb-ec4f-447d-b83d-497a1e3ee696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255289373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3255289373 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.2813305621 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 8311660468 ps |
| CPU time | 87.7 seconds |
| Started | Jun 30 08:21:04 PM PDT 24 |
| Finished | Jun 30 08:22:33 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-93d4d146-c2c8-4173-91be-b1f5ef3d75e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813305621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2813305621 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3603372129 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 4977603803 ps |
| CPU time | 91.47 seconds |
| Started | Jun 30 08:21:00 PM PDT 24 |
| Finished | Jun 30 08:22:32 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-fc28f7e2-a022-4dd8-bb49-f617ccfc68a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603372129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3603372129 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.870306930 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 40896918 ps |
| CPU time | 6.44 seconds |
| Started | Jun 30 08:21:03 PM PDT 24 |
| Finished | Jun 30 08:21:10 PM PDT 24 |
| Peak memory | 566032 kb |
| Host | smart-63482f1c-8537-4cbb-a5fa-4b1661f7148b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870306930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays .870306930 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.3173837165 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 1078356826 ps |
| CPU time | 136.39 seconds |
| Started | Jun 30 08:21:13 PM PDT 24 |
| Finished | Jun 30 08:23:30 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-c4e3e685-516d-4533-971d-caa531e7075d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173837165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3173837165 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.1626294926 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 5293123794 ps |
| CPU time | 225.02 seconds |
| Started | Jun 30 08:21:14 PM PDT 24 |
| Finished | Jun 30 08:25:00 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-811ef80d-272c-4f0b-bd1a-03bfccfae3cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626294926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1626294926 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.4051865782 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 3706985602 ps |
| CPU time | 432.9 seconds |
| Started | Jun 30 08:21:16 PM PDT 24 |
| Finished | Jun 30 08:28:29 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-dc27a1fd-2d2a-4c2a-9b67-de2e4e21cbf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051865782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.4051865782 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.1413450151 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 9323801229 ps |
| CPU time | 479.78 seconds |
| Started | Jun 30 08:21:17 PM PDT 24 |
| Finished | Jun 30 08:29:18 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-24439407-ae9f-45fc-a280-4f266c8b1e70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413450151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.1413450151 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.2186752756 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 626674784 ps |
| CPU time | 33.9 seconds |
| Started | Jun 30 08:21:13 PM PDT 24 |
| Finished | Jun 30 08:21:47 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-988b78bd-6bfd-4a90-bc19-519e18fa2ed0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186752756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2186752756 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.3626847475 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 472046920 ps |
| CPU time | 48.77 seconds |
| Started | Jun 30 08:21:23 PM PDT 24 |
| Finished | Jun 30 08:22:13 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-e5a67d8c-a81e-4049-94a6-0a639568ed01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626847475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .3626847475 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.672879803 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 132078341371 ps |
| CPU time | 2149.78 seconds |
| Started | Jun 30 08:21:17 PM PDT 24 |
| Finished | Jun 30 08:57:08 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-b1402dfd-60a8-4005-b217-70283aa1e545 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672879803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_d evice_slow_rsp.672879803 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1177171032 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 588064580 ps |
| CPU time | 23.44 seconds |
| Started | Jun 30 08:21:28 PM PDT 24 |
| Finished | Jun 30 08:21:53 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-2ec5b911-72b5-4c8e-b2a1-9c0c94716aa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177171032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.1177171032 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.874130152 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 572531446 ps |
| CPU time | 55.14 seconds |
| Started | Jun 30 08:21:26 PM PDT 24 |
| Finished | Jun 30 08:22:22 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-bb7ea6b3-2961-401d-813c-4c57eaf5a4ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874130152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.874130152 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.3527640097 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 303426825 ps |
| CPU time | 29.22 seconds |
| Started | Jun 30 08:21:18 PM PDT 24 |
| Finished | Jun 30 08:21:48 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-4f27e7ba-f74d-44a5-9b1f-7206bfd0c23f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527640097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.3527640097 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.2854956124 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 16778373709 ps |
| CPU time | 178.71 seconds |
| Started | Jun 30 08:21:17 PM PDT 24 |
| Finished | Jun 30 08:24:16 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-b8a11fdc-c8bc-4eb5-b3f8-91115a8a77db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854956124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2854956124 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.79526646 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 10402022331 ps |
| CPU time | 185.71 seconds |
| Started | Jun 30 08:21:20 PM PDT 24 |
| Finished | Jun 30 08:24:26 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-9b34a74a-e877-4fe0-8808-8cf82db2805b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79526646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.79526646 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.2621064726 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 520807951 ps |
| CPU time | 49.54 seconds |
| Started | Jun 30 08:21:19 PM PDT 24 |
| Finished | Jun 30 08:22:09 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-b8d1fe9a-f5b4-440e-a151-6cbcd0123b99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621064726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.2621064726 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.3234611334 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 467612236 ps |
| CPU time | 37.54 seconds |
| Started | Jun 30 08:21:16 PM PDT 24 |
| Finished | Jun 30 08:21:54 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-1a47f1d1-1261-49e4-b043-91af802179c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234611334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3234611334 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.504959689 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 274751562 ps |
| CPU time | 11.74 seconds |
| Started | Jun 30 08:21:20 PM PDT 24 |
| Finished | Jun 30 08:21:32 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-e893e224-17dc-446a-994c-0ef3105fbbc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504959689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.504959689 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.2788060462 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 9423002196 ps |
| CPU time | 101.15 seconds |
| Started | Jun 30 08:21:19 PM PDT 24 |
| Finished | Jun 30 08:23:01 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-f5d4465b-ee9b-4ac9-81b8-000b0d68b588 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788060462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2788060462 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3089329036 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 6194577197 ps |
| CPU time | 104.09 seconds |
| Started | Jun 30 08:21:22 PM PDT 24 |
| Finished | Jun 30 08:23:07 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-9e11005b-8cc4-4e27-948c-7ef7be02adee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089329036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3089329036 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1556143515 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 46515726 ps |
| CPU time | 6.69 seconds |
| Started | Jun 30 08:21:17 PM PDT 24 |
| Finished | Jun 30 08:21:24 PM PDT 24 |
| Peak memory | 565960 kb |
| Host | smart-4711c1da-69d3-4dbc-b11e-d61dfe24994f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556143515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.1556143515 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.381114844 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 4210544365 ps |
| CPU time | 159.12 seconds |
| Started | Jun 30 08:21:22 PM PDT 24 |
| Finished | Jun 30 08:24:02 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-8d041304-4a86-4f22-9cae-22aa40206bfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381114844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.381114844 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.447387763 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 4959561341 ps |
| CPU time | 192.04 seconds |
| Started | Jun 30 08:21:23 PM PDT 24 |
| Finished | Jun 30 08:24:36 PM PDT 24 |
| Peak memory | 574712 kb |
| Host | smart-732e424f-86ce-4777-b79f-c4ffce2abcec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447387763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.447387763 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.4014731605 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 3474001605 ps |
| CPU time | 439.43 seconds |
| Started | Jun 30 08:21:24 PM PDT 24 |
| Finished | Jun 30 08:28:45 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-2b7498a8-31dc-4fb5-8dbf-522ddd286bf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014731605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.4014731605 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.1897863717 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 1896522523 ps |
| CPU time | 178.74 seconds |
| Started | Jun 30 08:21:29 PM PDT 24 |
| Finished | Jun 30 08:24:29 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-4f8f3fa3-2255-464d-a6f1-34bca1ddf0a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897863717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.1897863717 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.1331578237 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 671686640 ps |
| CPU time | 30.97 seconds |
| Started | Jun 30 08:21:23 PM PDT 24 |
| Finished | Jun 30 08:21:55 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-d6b1ea0e-4655-4d9e-8793-721c14c626e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331578237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1331578237 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.2940434764 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 4187937932 ps |
| CPU time | 300.01 seconds |
| Started | Jun 30 08:09:11 PM PDT 24 |
| Finished | Jun 30 08:14:12 PM PDT 24 |
| Peak memory | 596172 kb |
| Host | smart-9e25219b-969d-439e-9b30-58cc35e837fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940434764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.2940434764 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.1156978597 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 29093259922 ps |
| CPU time | 3642.77 seconds |
| Started | Jun 30 08:08:41 PM PDT 24 |
| Finished | Jun 30 09:09:24 PM PDT 24 |
| Peak memory | 592236 kb |
| Host | smart-c568f606-f858-450d-85b3-353925aa7144 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156978597 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.1156978597 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.1657647609 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 2746363736 ps |
| CPU time | 275.63 seconds |
| Started | Jun 30 08:08:41 PM PDT 24 |
| Finished | Jun 30 08:13:17 PM PDT 24 |
| Peak memory | 589248 kb |
| Host | smart-3349314e-ca5c-4b28-8774-f0d68c57190c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657647609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.1657647609 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.3670613789 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 115126439 ps |
| CPU time | 14.68 seconds |
| Started | Jun 30 08:08:52 PM PDT 24 |
| Finished | Jun 30 08:09:07 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-e94dd10b-902a-4416-9a0d-4a6bb3419c52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670613789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 3670613789 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.34693618 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 22962073511 ps |
| CPU time | 412.05 seconds |
| Started | Jun 30 08:08:55 PM PDT 24 |
| Finished | Jun 30 08:15:47 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-5adc1bda-1cd9-4d75-9920-4541c57eaea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34693618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_dev ice_slow_rsp.34693618 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.2159025735 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 208774417 ps |
| CPU time | 25.43 seconds |
| Started | Jun 30 08:09:06 PM PDT 24 |
| Finished | Jun 30 08:09:31 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-9d8fd33c-4fd8-499c-bab4-891f72cfeac4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159025735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .2159025735 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.2202163305 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 41240492 ps |
| CPU time | 6.91 seconds |
| Started | Jun 30 08:08:53 PM PDT 24 |
| Finished | Jun 30 08:09:00 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-41c148b5-5488-4bc9-9c52-1b94198a8a03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202163305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2202163305 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.1113213461 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 76677835 ps |
| CPU time | 10.14 seconds |
| Started | Jun 30 08:08:46 PM PDT 24 |
| Finished | Jun 30 08:08:56 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-e1265e4e-1c79-43fb-9f47-79db23b75399 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113213461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.1113213461 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.99685067 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 97439848407 ps |
| CPU time | 1112.22 seconds |
| Started | Jun 30 08:08:51 PM PDT 24 |
| Finished | Jun 30 08:27:23 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-330a5bd2-b2da-4bfd-8fad-8475a5f89884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99685067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.99685067 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.1917561876 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 9634936684 ps |
| CPU time | 183.79 seconds |
| Started | Jun 30 08:08:47 PM PDT 24 |
| Finished | Jun 30 08:11:51 PM PDT 24 |
| Peak memory | 575108 kb |
| Host | smart-678cbd80-47e8-4e53-a937-838eb9913626 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917561876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1917561876 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.302329182 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 381384318 ps |
| CPU time | 42.4 seconds |
| Started | Jun 30 08:08:50 PM PDT 24 |
| Finished | Jun 30 08:09:33 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-9547be6d-b1c1-45e3-9168-7f3892a07b7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302329182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delay s.302329182 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.4206014141 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 158779838 ps |
| CPU time | 9.08 seconds |
| Started | Jun 30 08:08:55 PM PDT 24 |
| Finished | Jun 30 08:09:05 PM PDT 24 |
| Peak memory | 565864 kb |
| Host | smart-2e158ad9-5eb4-4a6b-ac71-0d9882053fb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206014141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.4206014141 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.3255971179 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 48784182 ps |
| CPU time | 7.16 seconds |
| Started | Jun 30 08:08:36 PM PDT 24 |
| Finished | Jun 30 08:08:44 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-460f7905-b6ae-420c-962d-fdd2caf85d73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255971179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3255971179 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.3032605516 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 10474856710 ps |
| CPU time | 113.01 seconds |
| Started | Jun 30 08:08:42 PM PDT 24 |
| Finished | Jun 30 08:10:36 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-e0372b51-c1a9-4547-9416-dba11c2721e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032605516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3032605516 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1980348901 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 5511550837 ps |
| CPU time | 98.21 seconds |
| Started | Jun 30 08:08:40 PM PDT 24 |
| Finished | Jun 30 08:10:18 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-a611df3e-6c13-4d0c-99b4-0ed76fc3cdc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980348901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1980348901 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.3240257 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 52683980 ps |
| CPU time | 7.86 seconds |
| Started | Jun 30 08:08:43 PM PDT 24 |
| Finished | Jun 30 08:08:52 PM PDT 24 |
| Peak memory | 565968 kb |
| Host | smart-335648e6-6c48-4118-ac00-3cd74877c1ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.3240257 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.3528802685 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 1814823867 ps |
| CPU time | 149.77 seconds |
| Started | Jun 30 08:09:07 PM PDT 24 |
| Finished | Jun 30 08:11:37 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-272a7e9d-0efb-4f79-acf7-f54255ee4897 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528802685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3528802685 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.728948353 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 1792989347 ps |
| CPU time | 131.24 seconds |
| Started | Jun 30 08:09:15 PM PDT 24 |
| Finished | Jun 30 08:11:26 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-c926bc49-3f35-4abd-b039-b7845d09e89a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728948353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.728948353 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3442262131 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 2253056298 ps |
| CPU time | 333.51 seconds |
| Started | Jun 30 08:09:12 PM PDT 24 |
| Finished | Jun 30 08:14:46 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-0757c8ec-53ea-4f4d-b252-01d8f8f93d59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442262131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.3442262131 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.3735435495 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 2720596159 ps |
| CPU time | 296.51 seconds |
| Started | Jun 30 08:09:14 PM PDT 24 |
| Finished | Jun 30 08:14:11 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-64e93497-2343-4c19-922c-9a6859cd95dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735435495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.3735435495 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.830761302 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1541831865 ps |
| CPU time | 70.78 seconds |
| Started | Jun 30 08:09:02 PM PDT 24 |
| Finished | Jun 30 08:10:13 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-464dbb23-32da-4efe-8d5b-5079eda71a9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830761302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.830761302 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.3712406572 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 874125375 ps |
| CPU time | 64.74 seconds |
| Started | Jun 30 08:21:24 PM PDT 24 |
| Finished | Jun 30 08:22:30 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-6669ffe4-7064-4064-bf99-ce99e09c4457 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712406572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .3712406572 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2303854383 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 36462133374 ps |
| CPU time | 643.12 seconds |
| Started | Jun 30 08:21:23 PM PDT 24 |
| Finished | Jun 30 08:32:07 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-e04f8c76-cf23-4f40-9f1b-e0556c6114aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303854383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.2303854383 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.2836711700 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 1184772772 ps |
| CPU time | 54.26 seconds |
| Started | Jun 30 08:21:29 PM PDT 24 |
| Finished | Jun 30 08:22:24 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-88414212-194d-4ede-96ff-27530c0be25d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836711700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.2836711700 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.769181359 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 611131813 ps |
| CPU time | 23.58 seconds |
| Started | Jun 30 08:21:28 PM PDT 24 |
| Finished | Jun 30 08:21:52 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-75135413-cc98-4bff-877d-45efcbe972f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769181359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.769181359 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.3715539553 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 35548088 ps |
| CPU time | 7.4 seconds |
| Started | Jun 30 08:21:25 PM PDT 24 |
| Finished | Jun 30 08:21:34 PM PDT 24 |
| Peak memory | 565884 kb |
| Host | smart-fe0a20f0-d0d4-44d2-b35f-b3cd9c14ae1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715539553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.3715539553 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.1011138069 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 50424291723 ps |
| CPU time | 556.24 seconds |
| Started | Jun 30 08:21:24 PM PDT 24 |
| Finished | Jun 30 08:30:42 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-d844d0ab-3413-452c-8528-d7f0dd38aec6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011138069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.1011138069 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.4070514682 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 47038891015 ps |
| CPU time | 822.46 seconds |
| Started | Jun 30 08:21:24 PM PDT 24 |
| Finished | Jun 30 08:35:08 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-6cce6cca-6ac0-4efb-bde2-239eed20df03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070514682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.4070514682 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.2700647304 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 121625367 ps |
| CPU time | 15.2 seconds |
| Started | Jun 30 08:21:23 PM PDT 24 |
| Finished | Jun 30 08:21:39 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-31d5028b-f50c-445e-b1de-8022f05930d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700647304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.2700647304 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.1149108992 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 392891722 ps |
| CPU time | 34.36 seconds |
| Started | Jun 30 08:21:27 PM PDT 24 |
| Finished | Jun 30 08:22:02 PM PDT 24 |
| Peak memory | 575184 kb |
| Host | smart-6ddd37cf-ba79-42ce-9258-37b4b6ad1fff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149108992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.1149108992 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.1265806348 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 220000825 ps |
| CPU time | 10.09 seconds |
| Started | Jun 30 08:21:22 PM PDT 24 |
| Finished | Jun 30 08:21:33 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-83e311e4-c52f-47d8-9cf3-29044307f351 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265806348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.1265806348 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.809304375 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 7590687194 ps |
| CPU time | 77.41 seconds |
| Started | Jun 30 08:21:22 PM PDT 24 |
| Finished | Jun 30 08:22:41 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-40f8ed5c-27ba-4b34-bbd0-082b9d768c2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809304375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.809304375 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.3937934452 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 5694333405 ps |
| CPU time | 103.55 seconds |
| Started | Jun 30 08:21:23 PM PDT 24 |
| Finished | Jun 30 08:23:07 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-8d5395ee-f439-4b7d-a46d-b9fc8ef123d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937934452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.3937934452 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.1654121703 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 49671105 ps |
| CPU time | 6.2 seconds |
| Started | Jun 30 08:21:29 PM PDT 24 |
| Finished | Jun 30 08:21:37 PM PDT 24 |
| Peak memory | 565928 kb |
| Host | smart-09c718f1-d031-4146-baec-97357b778913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654121703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.1654121703 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.3751092690 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 397232003 ps |
| CPU time | 39.97 seconds |
| Started | Jun 30 08:21:29 PM PDT 24 |
| Finished | Jun 30 08:22:09 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-095ba642-7aa3-42a6-977d-6c28de11427f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751092690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.3751092690 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.1409502132 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 3311932552 ps |
| CPU time | 307.6 seconds |
| Started | Jun 30 08:21:30 PM PDT 24 |
| Finished | Jun 30 08:26:39 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-3e756941-1d06-49af-9d56-56fbf07ab38b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409502132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.1409502132 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.2825629179 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 3985997527 ps |
| CPU time | 533.1 seconds |
| Started | Jun 30 08:21:28 PM PDT 24 |
| Finished | Jun 30 08:30:22 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-9a1718d6-c8c3-4ae7-91aa-1fb3da777581 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825629179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.2825629179 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.1150307453 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 242693585 ps |
| CPU time | 14.18 seconds |
| Started | Jun 30 08:21:29 PM PDT 24 |
| Finished | Jun 30 08:21:44 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-c7474e98-9847-414d-bf69-0d26c00458d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150307453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.1150307453 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.3147912056 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 728745939 ps |
| CPU time | 69.22 seconds |
| Started | Jun 30 08:21:40 PM PDT 24 |
| Finished | Jun 30 08:22:50 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-a7784c4f-d7ea-473d-af44-7b20035610f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147912056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .3147912056 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.109345290 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 12960720534 ps |
| CPU time | 217.19 seconds |
| Started | Jun 30 08:21:40 PM PDT 24 |
| Finished | Jun 30 08:25:18 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-232fc05a-2441-46cd-a25d-f3fdf47856d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109345290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_d evice_slow_rsp.109345290 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.2149877362 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 224256722 ps |
| CPU time | 13.6 seconds |
| Started | Jun 30 08:21:41 PM PDT 24 |
| Finished | Jun 30 08:21:55 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-0b791fa8-5e76-434c-840f-55c1c4ca5879 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149877362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.2149877362 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.4135247650 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 407927921 ps |
| CPU time | 15.03 seconds |
| Started | Jun 30 08:21:47 PM PDT 24 |
| Finished | Jun 30 08:22:04 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-1f6216d8-a0d2-43cc-9ecc-2716b789c1de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135247650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.4135247650 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.252935998 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 1055974572 ps |
| CPU time | 45.22 seconds |
| Started | Jun 30 08:21:36 PM PDT 24 |
| Finished | Jun 30 08:22:21 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-f130f953-c3a7-48d6-b210-0fc9c28d2f10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252935998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.252935998 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.450614057 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 56811266485 ps |
| CPU time | 578.39 seconds |
| Started | Jun 30 08:21:33 PM PDT 24 |
| Finished | Jun 30 08:31:12 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-87af8c5c-6740-4619-966d-76a8b887e548 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450614057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.450614057 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.3844283412 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 8534165048 ps |
| CPU time | 151.79 seconds |
| Started | Jun 30 08:21:34 PM PDT 24 |
| Finished | Jun 30 08:24:07 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-933e37f4-8191-4aad-bc83-e8f9114efc86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844283412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.3844283412 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.3042470525 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 377731146 ps |
| CPU time | 30.36 seconds |
| Started | Jun 30 08:21:36 PM PDT 24 |
| Finished | Jun 30 08:22:07 PM PDT 24 |
| Peak memory | 575200 kb |
| Host | smart-1d13a25e-b794-482f-a431-dd3d8138cc2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042470525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.3042470525 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.2797858379 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 388812834 ps |
| CPU time | 15.24 seconds |
| Started | Jun 30 08:21:47 PM PDT 24 |
| Finished | Jun 30 08:22:04 PM PDT 24 |
| Peak memory | 575192 kb |
| Host | smart-1e8b507a-10aa-4ce5-b5da-8c9e2793a0e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797858379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.2797858379 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.1569031335 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 233304176 ps |
| CPU time | 10.99 seconds |
| Started | Jun 30 08:21:33 PM PDT 24 |
| Finished | Jun 30 08:21:45 PM PDT 24 |
| Peak memory | 565944 kb |
| Host | smart-23498279-a150-4f66-b60e-f8d79869080f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569031335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.1569031335 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.2564641245 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 5511947938 ps |
| CPU time | 63.28 seconds |
| Started | Jun 30 08:21:39 PM PDT 24 |
| Finished | Jun 30 08:22:44 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-fe3c36d5-d808-4977-a52b-34755bab36d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564641245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.2564641245 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.2533512410 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 5214115398 ps |
| CPU time | 92.03 seconds |
| Started | Jun 30 08:21:34 PM PDT 24 |
| Finished | Jun 30 08:23:07 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-723413e2-b5d2-4ade-9d8e-6485f2f5af9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533512410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.2533512410 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.310360907 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 49370207 ps |
| CPU time | 7.02 seconds |
| Started | Jun 30 08:21:35 PM PDT 24 |
| Finished | Jun 30 08:21:42 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-213ef53e-1752-43fa-ae1f-82a5dd5c90c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310360907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delays .310360907 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.3747223519 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 1496194248 ps |
| CPU time | 72.33 seconds |
| Started | Jun 30 08:21:41 PM PDT 24 |
| Finished | Jun 30 08:22:53 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-fbe5f4a4-8116-4455-8cef-386f8b10320d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747223519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.3747223519 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.754238324 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 1544054758 ps |
| CPU time | 111.49 seconds |
| Started | Jun 30 08:21:46 PM PDT 24 |
| Finished | Jun 30 08:23:39 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-2331be49-b4f6-4e75-88d0-2a080e7191a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754238324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.754238324 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1252365877 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 289643961 ps |
| CPU time | 69.57 seconds |
| Started | Jun 30 08:21:41 PM PDT 24 |
| Finished | Jun 30 08:22:51 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-341163b4-6bbc-4baa-a9ef-00128feb597a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252365877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.1252365877 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.4193402239 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 411576014 ps |
| CPU time | 90.84 seconds |
| Started | Jun 30 08:21:48 PM PDT 24 |
| Finished | Jun 30 08:23:20 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-ded0e711-b5a0-41ef-a2ba-0871f9166bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193402239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.4193402239 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.2632738139 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 641167883 ps |
| CPU time | 36.92 seconds |
| Started | Jun 30 08:21:40 PM PDT 24 |
| Finished | Jun 30 08:22:18 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-387104d0-e813-402d-bcbd-afb3c7477b30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632738139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.2632738139 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.947211188 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 99582249 ps |
| CPU time | 10.1 seconds |
| Started | Jun 30 08:21:49 PM PDT 24 |
| Finished | Jun 30 08:22:01 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-68225649-ef51-412e-aef3-e4ae8ddfed2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947211188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device. 947211188 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.872105460 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 84155639 ps |
| CPU time | 6.87 seconds |
| Started | Jun 30 08:21:51 PM PDT 24 |
| Finished | Jun 30 08:21:59 PM PDT 24 |
| Peak memory | 565984 kb |
| Host | smart-8f15eba2-fddf-41b0-9030-251a7e86732c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872105460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_addr .872105460 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.1057398624 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 406457798 ps |
| CPU time | 39.19 seconds |
| Started | Jun 30 08:21:52 PM PDT 24 |
| Finished | Jun 30 08:22:32 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-73bc92c0-2fa7-475a-a59a-c6f1f248e150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057398624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.1057398624 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.1290259598 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 816106102 ps |
| CPU time | 35.76 seconds |
| Started | Jun 30 08:21:46 PM PDT 24 |
| Finished | Jun 30 08:22:22 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-cd094fec-a3ca-4dd6-8853-944b87aad042 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290259598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.1290259598 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.1610619099 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 16994403411 ps |
| CPU time | 187.72 seconds |
| Started | Jun 30 08:21:49 PM PDT 24 |
| Finished | Jun 30 08:24:58 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-09e8e38e-7201-40e9-b753-2208411baca5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610619099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.1610619099 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.4032960095 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 57789472335 ps |
| CPU time | 1019.86 seconds |
| Started | Jun 30 08:21:46 PM PDT 24 |
| Finished | Jun 30 08:38:46 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-e07d8ed0-0193-443b-8394-f0bf65400ecd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032960095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.4032960095 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.98782873 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 140186793 ps |
| CPU time | 15.52 seconds |
| Started | Jun 30 08:21:46 PM PDT 24 |
| Finished | Jun 30 08:22:03 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-08a243c6-1dc1-45c7-9537-abd0ad446772 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98782873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_delay s.98782873 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.3274983461 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 2109665173 ps |
| CPU time | 66.86 seconds |
| Started | Jun 30 08:21:52 PM PDT 24 |
| Finished | Jun 30 08:22:59 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-d5df04c3-8ed9-4348-8e7e-efd94a0314ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274983461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.3274983461 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.2531078028 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 209787986 ps |
| CPU time | 9.63 seconds |
| Started | Jun 30 08:21:47 PM PDT 24 |
| Finished | Jun 30 08:21:58 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-477c9459-121d-4c4d-bf17-f1a460e4d8dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531078028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.2531078028 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.3775247178 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 8653225353 ps |
| CPU time | 90.75 seconds |
| Started | Jun 30 08:21:47 PM PDT 24 |
| Finished | Jun 30 08:23:19 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-bf25c136-03dc-4253-aef1-bc059a2c0c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775247178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.3775247178 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.16095981 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 5612299587 ps |
| CPU time | 98.72 seconds |
| Started | Jun 30 08:21:49 PM PDT 24 |
| Finished | Jun 30 08:23:29 PM PDT 24 |
| Peak memory | 566020 kb |
| Host | smart-67fa7b78-fdc5-48e9-a486-465ad4f84196 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16095981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.16095981 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.3305396020 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 44549159 ps |
| CPU time | 6.75 seconds |
| Started | Jun 30 08:21:48 PM PDT 24 |
| Finished | Jun 30 08:21:56 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-37bbe4fa-10b4-43c4-89b1-be3aaca8b3c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305396020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.3305396020 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.2250263378 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 4778405380 ps |
| CPU time | 443.66 seconds |
| Started | Jun 30 08:21:52 PM PDT 24 |
| Finished | Jun 30 08:29:17 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-fcde6884-07da-4b4c-bb8d-25cec4e78043 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250263378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.2250263378 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.3815362667 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 2365649719 ps |
| CPU time | 187.9 seconds |
| Started | Jun 30 08:22:01 PM PDT 24 |
| Finished | Jun 30 08:25:09 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-73509ecd-d0b2-4c77-9a41-b9092c313422 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815362667 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.3815362667 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.4270290518 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 7934780558 ps |
| CPU time | 487.06 seconds |
| Started | Jun 30 08:21:54 PM PDT 24 |
| Finished | Jun 30 08:30:02 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-09000ec6-bc54-4338-8581-39f3df6324e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270290518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.4270290518 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.4207068011 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 13664028 ps |
| CPU time | 10.36 seconds |
| Started | Jun 30 08:21:56 PM PDT 24 |
| Finished | Jun 30 08:22:07 PM PDT 24 |
| Peak memory | 566052 kb |
| Host | smart-810d01c0-6f76-4b11-8fa9-a199608f48ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207068011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.4207068011 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.1245757211 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 529706110 ps |
| CPU time | 25.54 seconds |
| Started | Jun 30 08:21:52 PM PDT 24 |
| Finished | Jun 30 08:22:18 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-57275888-f907-4812-b675-928e580dcbef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245757211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.1245757211 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.1710636427 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 2625492081 ps |
| CPU time | 112.41 seconds |
| Started | Jun 30 08:22:03 PM PDT 24 |
| Finished | Jun 30 08:23:55 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-66ffe393-06d6-45c5-9c6b-6636cb3e414a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710636427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .1710636427 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2082346819 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 287972291 ps |
| CPU time | 37.21 seconds |
| Started | Jun 30 08:22:02 PM PDT 24 |
| Finished | Jun 30 08:22:39 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-46ce3f1d-1974-426c-a5ac-3439e4448829 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082346819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.2082346819 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.164875725 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 2057471150 ps |
| CPU time | 77.28 seconds |
| Started | Jun 30 08:22:02 PM PDT 24 |
| Finished | Jun 30 08:23:20 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-fc09ecb7-997d-4f67-aac1-482167567cb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164875725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.164875725 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.3723951493 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 775874775 ps |
| CPU time | 31.65 seconds |
| Started | Jun 30 08:21:56 PM PDT 24 |
| Finished | Jun 30 08:22:29 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-7b73bff3-ec19-4d6d-977f-b727b9ee082b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723951493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.3723951493 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.2426824920 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 67023499643 ps |
| CPU time | 671.66 seconds |
| Started | Jun 30 08:22:02 PM PDT 24 |
| Finished | Jun 30 08:33:14 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-a347f5bb-583b-411b-b519-e76e6f994586 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426824920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.2426824920 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.823982634 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 34202004685 ps |
| CPU time | 614.96 seconds |
| Started | Jun 30 08:22:04 PM PDT 24 |
| Finished | Jun 30 08:32:19 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-b3a5dedb-a71c-4f52-be17-83e9d614cda9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823982634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.823982634 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.3376734802 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 161831960 ps |
| CPU time | 16.79 seconds |
| Started | Jun 30 08:21:56 PM PDT 24 |
| Finished | Jun 30 08:22:14 PM PDT 24 |
| Peak memory | 575164 kb |
| Host | smart-58119d62-f4a3-42dc-a243-d3ea10bb1389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376734802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.3376734802 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.3868721815 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 327287099 ps |
| CPU time | 13.36 seconds |
| Started | Jun 30 08:22:03 PM PDT 24 |
| Finished | Jun 30 08:22:17 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-c32041ab-705b-487a-aefc-7090702e3143 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868721815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.3868721815 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.412723739 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 50971525 ps |
| CPU time | 6.68 seconds |
| Started | Jun 30 08:21:59 PM PDT 24 |
| Finished | Jun 30 08:22:06 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-71178933-2735-4494-90c6-b2816045eb2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412723739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.412723739 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.317635674 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 9251835424 ps |
| CPU time | 100.5 seconds |
| Started | Jun 30 08:21:57 PM PDT 24 |
| Finished | Jun 30 08:23:38 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-d21b58bf-f629-450f-be98-8183846a140b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317635674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.317635674 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.2301736609 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 4322465739 ps |
| CPU time | 75.2 seconds |
| Started | Jun 30 08:22:00 PM PDT 24 |
| Finished | Jun 30 08:23:16 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-3238e42b-a945-4585-97dc-1d79f3331c97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301736609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.2301736609 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2432555126 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 45871949 ps |
| CPU time | 6.46 seconds |
| Started | Jun 30 08:21:59 PM PDT 24 |
| Finished | Jun 30 08:22:06 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-7b260995-0812-4ba0-b677-c008e6f5af4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432555126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.2432555126 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.4063883266 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 8243568008 ps |
| CPU time | 385.62 seconds |
| Started | Jun 30 08:22:03 PM PDT 24 |
| Finished | Jun 30 08:28:29 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-23d858be-b543-4c26-ac7d-1668d0d65736 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063883266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.4063883266 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.182161615 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 16814513988 ps |
| CPU time | 579.34 seconds |
| Started | Jun 30 08:22:04 PM PDT 24 |
| Finished | Jun 30 08:31:44 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-93117632-8515-4c3c-be0d-0ccd7b67d141 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182161615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.182161615 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1300714072 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 3351447858 ps |
| CPU time | 308.92 seconds |
| Started | Jun 30 08:22:01 PM PDT 24 |
| Finished | Jun 30 08:27:11 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-a4ecf77d-f1b0-4e7e-bb78-70fa2be93d1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300714072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.1300714072 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.171486059 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 640507519 ps |
| CPU time | 275.36 seconds |
| Started | Jun 30 08:22:09 PM PDT 24 |
| Finished | Jun 30 08:26:45 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-16fceca6-f0f6-431e-a006-a7b6cc7146a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171486059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_reset_error.171486059 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.4290347593 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 633311250 ps |
| CPU time | 28.31 seconds |
| Started | Jun 30 08:22:05 PM PDT 24 |
| Finished | Jun 30 08:22:34 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-08499e48-908b-4a11-b65c-3aa6207d0ad8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290347593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.4290347593 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.745580098 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 2006223306 ps |
| CPU time | 97.17 seconds |
| Started | Jun 30 08:22:14 PM PDT 24 |
| Finished | Jun 30 08:23:51 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-81fcb3b6-109c-462d-9a85-4cfa5fb37d85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745580098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device. 745580098 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.1626234265 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 13196316516 ps |
| CPU time | 239.6 seconds |
| Started | Jun 30 08:22:19 PM PDT 24 |
| Finished | Jun 30 08:26:19 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-115f58f7-4802-4bb5-a905-a3d1d88a57ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626234265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.1626234265 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.2122784576 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 220836312 ps |
| CPU time | 24.8 seconds |
| Started | Jun 30 08:22:15 PM PDT 24 |
| Finished | Jun 30 08:22:40 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-5184187e-d6f4-473c-85c1-25aae157d7de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122784576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.2122784576 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.3546079585 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 357459077 ps |
| CPU time | 16.37 seconds |
| Started | Jun 30 08:22:15 PM PDT 24 |
| Finished | Jun 30 08:22:32 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-47feb4b0-198a-462c-a1a1-65df4c167308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546079585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.3546079585 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.2013861498 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1407144489 ps |
| CPU time | 53.95 seconds |
| Started | Jun 30 08:22:08 PM PDT 24 |
| Finished | Jun 30 08:23:03 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-9666a453-ff2f-4b0e-bc91-c9c69944ef2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013861498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.2013861498 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.2151937363 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 94601833291 ps |
| CPU time | 1028.26 seconds |
| Started | Jun 30 08:22:09 PM PDT 24 |
| Finished | Jun 30 08:39:18 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-590525d4-e0a7-4a77-bd55-02a2d8922d5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151937363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.2151937363 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.1903051643 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 52360459548 ps |
| CPU time | 928.62 seconds |
| Started | Jun 30 08:22:19 PM PDT 24 |
| Finished | Jun 30 08:37:48 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-10e06098-52e0-4ca5-9a4c-bc5c5728d577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903051643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.1903051643 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.2133120363 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 214372799 ps |
| CPU time | 21.64 seconds |
| Started | Jun 30 08:22:07 PM PDT 24 |
| Finished | Jun 30 08:22:29 PM PDT 24 |
| Peak memory | 575188 kb |
| Host | smart-25874931-48a6-4d5d-9186-cb6b7e43dab9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133120363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.2133120363 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.992307329 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 2728013429 ps |
| CPU time | 82.21 seconds |
| Started | Jun 30 08:22:18 PM PDT 24 |
| Finished | Jun 30 08:23:41 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-8a280596-582e-463f-b9ff-cc4430988a89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992307329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.992307329 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.176013068 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 218514797 ps |
| CPU time | 9.92 seconds |
| Started | Jun 30 08:22:10 PM PDT 24 |
| Finished | Jun 30 08:22:21 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-196765ba-25f5-4dfc-9a75-94111cb9b9e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176013068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.176013068 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.2536759962 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 8019541593 ps |
| CPU time | 90.68 seconds |
| Started | Jun 30 08:22:07 PM PDT 24 |
| Finished | Jun 30 08:23:38 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-b73a2594-bc92-4a6d-89ad-81503eb53f11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536759962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.2536759962 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.4169911534 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 3983846311 ps |
| CPU time | 69.48 seconds |
| Started | Jun 30 08:22:08 PM PDT 24 |
| Finished | Jun 30 08:23:19 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-e90e199c-b8fa-4650-8e38-4818d2e1ff52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169911534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.4169911534 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1471331484 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 36269025 ps |
| CPU time | 6.28 seconds |
| Started | Jun 30 08:22:08 PM PDT 24 |
| Finished | Jun 30 08:22:16 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-a149dc97-a1ac-40ce-8a8d-0937a9a03b6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471331484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.1471331484 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.1699191935 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 9099373933 ps |
| CPU time | 415.65 seconds |
| Started | Jun 30 08:22:16 PM PDT 24 |
| Finished | Jun 30 08:29:12 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-efa038a5-c95b-4e6f-9fa2-dce71af079fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699191935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.1699191935 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.1306738675 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 3862439620 ps |
| CPU time | 277.04 seconds |
| Started | Jun 30 08:22:23 PM PDT 24 |
| Finished | Jun 30 08:27:01 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-8b7bb67d-1334-4b90-a21c-075a11a0b62e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306738675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.1306738675 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.644941471 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 285895473 ps |
| CPU time | 85.75 seconds |
| Started | Jun 30 08:22:19 PM PDT 24 |
| Finished | Jun 30 08:23:46 PM PDT 24 |
| Peak memory | 577408 kb |
| Host | smart-ba583290-029e-4400-ab1b-ed7d5856895c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644941471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_ with_rand_reset.644941471 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3068788072 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 6419613411 ps |
| CPU time | 223.08 seconds |
| Started | Jun 30 08:22:18 PM PDT 24 |
| Finished | Jun 30 08:26:02 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-570e7d0e-3703-4422-9954-d17f26cadbff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068788072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.3068788072 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.2105041320 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 686135370 ps |
| CPU time | 32.44 seconds |
| Started | Jun 30 08:22:12 PM PDT 24 |
| Finished | Jun 30 08:22:45 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-0e679a15-751c-4498-bdb7-0828102b81c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105041320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.2105041320 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.4230664404 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 1166371968 ps |
| CPU time | 92.58 seconds |
| Started | Jun 30 08:22:25 PM PDT 24 |
| Finished | Jun 30 08:23:58 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-4cea1645-85bb-4286-9e7b-62b8d9743487 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230664404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .4230664404 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.1279415406 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 97743908239 ps |
| CPU time | 1651.57 seconds |
| Started | Jun 30 08:22:25 PM PDT 24 |
| Finished | Jun 30 08:49:58 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-65b968f0-4691-44d0-bb78-dffa478b6f8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279415406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.1279415406 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.1175473332 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 344963525 ps |
| CPU time | 37.82 seconds |
| Started | Jun 30 08:22:28 PM PDT 24 |
| Finished | Jun 30 08:23:07 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-257feccb-f811-4a3e-81d8-d185861242e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175473332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add r.1175473332 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.2660835624 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 1751620947 ps |
| CPU time | 57.59 seconds |
| Started | Jun 30 08:22:26 PM PDT 24 |
| Finished | Jun 30 08:23:25 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-d532b83c-cabf-42d6-9c1e-77ddbb0195a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660835624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.2660835624 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.3493224729 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 1884697003 ps |
| CPU time | 73.78 seconds |
| Started | Jun 30 08:22:19 PM PDT 24 |
| Finished | Jun 30 08:23:34 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-6743b2f7-e97c-4535-9dc6-e3749ec04cad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493224729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.3493224729 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.638861277 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 54259779179 ps |
| CPU time | 628.27 seconds |
| Started | Jun 30 08:22:25 PM PDT 24 |
| Finished | Jun 30 08:32:54 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-ee0c27e2-6979-48ee-b952-83fbcd0f66b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638861277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.638861277 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.1695873759 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 56835067388 ps |
| CPU time | 1037.18 seconds |
| Started | Jun 30 08:22:25 PM PDT 24 |
| Finished | Jun 30 08:39:43 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-9602a738-ed14-4173-a3bf-217fa569ade0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695873759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.1695873759 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.1714166256 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 506037156 ps |
| CPU time | 44.24 seconds |
| Started | Jun 30 08:22:25 PM PDT 24 |
| Finished | Jun 30 08:23:10 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-f5bd7c13-bf52-48ef-8a7a-d1f813a8ddfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714166256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.1714166256 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.3415297678 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 1857289418 ps |
| CPU time | 61.99 seconds |
| Started | Jun 30 08:22:24 PM PDT 24 |
| Finished | Jun 30 08:23:27 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-f0b8d1e7-179d-4cd6-8a96-c4d7286e3c29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415297678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.3415297678 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.1095232874 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 59091127 ps |
| CPU time | 7.11 seconds |
| Started | Jun 30 08:22:18 PM PDT 24 |
| Finished | Jun 30 08:22:26 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-b6362e36-db90-4890-b388-feab6b71586b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095232874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.1095232874 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.4038348084 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 6907352731 ps |
| CPU time | 74.22 seconds |
| Started | Jun 30 08:22:17 PM PDT 24 |
| Finished | Jun 30 08:23:32 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-34b352bb-36a4-433e-a1e4-9ddcb5c2c1c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038348084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.4038348084 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.34701720 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 5237987948 ps |
| CPU time | 96.61 seconds |
| Started | Jun 30 08:22:22 PM PDT 24 |
| Finished | Jun 30 08:23:59 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-8c511643-4af8-4302-8d36-0abb3345f06a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34701720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.34701720 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.935348568 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 40568968 ps |
| CPU time | 6.13 seconds |
| Started | Jun 30 08:22:22 PM PDT 24 |
| Finished | Jun 30 08:22:29 PM PDT 24 |
| Peak memory | 565868 kb |
| Host | smart-955e9145-81e9-4d35-9f24-d52105318671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935348568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delays .935348568 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.1956996062 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1944173728 ps |
| CPU time | 177.92 seconds |
| Started | Jun 30 08:22:29 PM PDT 24 |
| Finished | Jun 30 08:25:27 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-97d688cc-654e-42ed-82ca-d0f8eb96818d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956996062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.1956996062 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.2083930855 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 1937586486 ps |
| CPU time | 188.8 seconds |
| Started | Jun 30 08:22:29 PM PDT 24 |
| Finished | Jun 30 08:25:38 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-4f141375-2752-41f8-9c4d-3bd47fb6d935 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083930855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.2083930855 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3196171383 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 8042537472 ps |
| CPU time | 420.03 seconds |
| Started | Jun 30 08:22:27 PM PDT 24 |
| Finished | Jun 30 08:29:27 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-8f66a1cb-7623-4b8c-919b-0241fe9e0028 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196171383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.3196171383 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.304183188 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 5401822496 ps |
| CPU time | 388.16 seconds |
| Started | Jun 30 08:22:25 PM PDT 24 |
| Finished | Jun 30 08:28:54 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-838ac8d4-817d-4761-b93f-a2719da19a69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304183188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_reset_error.304183188 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.3362961859 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 182757924 ps |
| CPU time | 21.42 seconds |
| Started | Jun 30 08:22:26 PM PDT 24 |
| Finished | Jun 30 08:22:48 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-3d274574-8493-46c6-ba05-4638f1ecfcfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362961859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.3362961859 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.2284952971 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 204763117 ps |
| CPU time | 16.45 seconds |
| Started | Jun 30 08:22:32 PM PDT 24 |
| Finished | Jun 30 08:22:49 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-ab246676-bb31-4beb-ad84-ef43589360a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284952971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .2284952971 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1088941131 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 100041153646 ps |
| CPU time | 1735.51 seconds |
| Started | Jun 30 08:22:35 PM PDT 24 |
| Finished | Jun 30 08:51:32 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-658e2acb-3890-4717-9615-51e8d8d819d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088941131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.1088941131 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.989991381 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 477864976 ps |
| CPU time | 25.86 seconds |
| Started | Jun 30 08:22:37 PM PDT 24 |
| Finished | Jun 30 08:23:04 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-d0cd522e-7cc9-4c66-8484-ed374e5c46a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989991381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_addr .989991381 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.2602804594 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 393256926 ps |
| CPU time | 19.3 seconds |
| Started | Jun 30 08:22:35 PM PDT 24 |
| Finished | Jun 30 08:22:55 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-ad04c0c4-0d8d-4dff-989c-653b534e5516 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602804594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.2602804594 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.587860615 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 1001774762 ps |
| CPU time | 38.77 seconds |
| Started | Jun 30 08:22:32 PM PDT 24 |
| Finished | Jun 30 08:23:12 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-32956289-986a-4751-aa5b-f29f0c29f1e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587860615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.587860615 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.649581603 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 6364469978 ps |
| CPU time | 70.94 seconds |
| Started | Jun 30 08:22:33 PM PDT 24 |
| Finished | Jun 30 08:23:45 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-02e4dc64-7e1b-43c9-836b-71941c0243a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649581603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.649581603 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.2978956410 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 8361871081 ps |
| CPU time | 154.59 seconds |
| Started | Jun 30 08:22:31 PM PDT 24 |
| Finished | Jun 30 08:25:06 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-5af28e5f-a83e-457d-b17d-71c4b5ec6125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978956410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.2978956410 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.1696254679 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 559513574 ps |
| CPU time | 47.01 seconds |
| Started | Jun 30 08:22:31 PM PDT 24 |
| Finished | Jun 30 08:23:19 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-220ebc3f-f9fa-4ff7-b8fd-64bb3702235e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696254679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.1696254679 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.1064392130 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 561403655 ps |
| CPU time | 42.4 seconds |
| Started | Jun 30 08:22:34 PM PDT 24 |
| Finished | Jun 30 08:23:17 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-def999be-7857-4c59-884a-b6b408932b9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064392130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.1064392130 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.2086095614 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 138112241 ps |
| CPU time | 8.09 seconds |
| Started | Jun 30 08:22:25 PM PDT 24 |
| Finished | Jun 30 08:22:35 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-cab122f4-c40d-471e-852f-7c78273a3a9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086095614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.2086095614 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.255033961 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 6198124916 ps |
| CPU time | 65.96 seconds |
| Started | Jun 30 08:22:28 PM PDT 24 |
| Finished | Jun 30 08:23:35 PM PDT 24 |
| Peak memory | 565972 kb |
| Host | smart-c8fb911e-1bda-42f5-9692-269c3f58adfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255033961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.255033961 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.1541383160 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 6227335220 ps |
| CPU time | 105.1 seconds |
| Started | Jun 30 08:22:31 PM PDT 24 |
| Finished | Jun 30 08:24:16 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-eba8ef45-92dd-4332-80e9-73a974eefa27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541383160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.1541383160 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.845010034 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 46320419 ps |
| CPU time | 6.22 seconds |
| Started | Jun 30 08:22:29 PM PDT 24 |
| Finished | Jun 30 08:22:36 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-69e156c2-b5f9-4f25-bb07-8d59a426dd69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845010034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delays .845010034 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.1126977969 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 7415550613 ps |
| CPU time | 280.06 seconds |
| Started | Jun 30 08:22:36 PM PDT 24 |
| Finished | Jun 30 08:27:17 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-63375289-1a1f-4916-9bd6-eddf0bcf24dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126977969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.1126977969 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.3321572243 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 14394528900 ps |
| CPU time | 642.07 seconds |
| Started | Jun 30 08:22:40 PM PDT 24 |
| Finished | Jun 30 08:33:22 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-c897ccaa-b0c8-4fed-ba48-c75094063778 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321572243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.3321572243 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.3510167167 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 5674890108 ps |
| CPU time | 520.26 seconds |
| Started | Jun 30 08:22:35 PM PDT 24 |
| Finished | Jun 30 08:31:16 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-950ce15c-f543-4e9b-a317-07b4386a8112 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510167167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.3510167167 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.144987058 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 9593106 ps |
| CPU time | 22.9 seconds |
| Started | Jun 30 08:22:37 PM PDT 24 |
| Finished | Jun 30 08:23:01 PM PDT 24 |
| Peak memory | 566052 kb |
| Host | smart-6a59eba6-8712-41ab-8858-61cc1542bdb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144987058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_reset_error.144987058 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.2387820747 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 528790522 ps |
| CPU time | 27.01 seconds |
| Started | Jun 30 08:22:34 PM PDT 24 |
| Finished | Jun 30 08:23:02 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-5a9b7cca-2bed-409f-a245-9c55b3e92f60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387820747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.2387820747 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.796129495 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 152699282 ps |
| CPU time | 18.49 seconds |
| Started | Jun 30 08:22:36 PM PDT 24 |
| Finished | Jun 30 08:22:55 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-7b3f670c-1d4b-42d3-ae9a-4ff348e6d64a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796129495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device. 796129495 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.2154861427 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 39615372140 ps |
| CPU time | 723.62 seconds |
| Started | Jun 30 08:22:42 PM PDT 24 |
| Finished | Jun 30 08:34:46 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-82554be8-8e17-49ee-addb-d1051db04bc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154861427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.2154861427 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.2601946658 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 1127351246 ps |
| CPU time | 47.26 seconds |
| Started | Jun 30 08:22:42 PM PDT 24 |
| Finished | Jun 30 08:23:30 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-eb7ed78f-4812-4897-9430-3ae2c6022b61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601946658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.2601946658 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.3271396930 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 1550067916 ps |
| CPU time | 53.95 seconds |
| Started | Jun 30 08:22:42 PM PDT 24 |
| Finished | Jun 30 08:23:37 PM PDT 24 |
| Peak memory | 573808 kb |
| Host | smart-08ac770a-fec6-4af7-a084-0e20a10f3c42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271396930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.3271396930 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.3669033434 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1307660454 ps |
| CPU time | 51.62 seconds |
| Started | Jun 30 08:22:37 PM PDT 24 |
| Finished | Jun 30 08:23:29 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-e1390c5c-f732-4c79-8a1e-1b6943d2cc83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669033434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.3669033434 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.2214505276 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 51337837955 ps |
| CPU time | 547.1 seconds |
| Started | Jun 30 08:22:36 PM PDT 24 |
| Finished | Jun 30 08:31:44 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-41a1abcf-5fc9-4e9c-9baa-5bdd5700fb1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214505276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.2214505276 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.4232395296 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 32054775156 ps |
| CPU time | 540.43 seconds |
| Started | Jun 30 08:22:39 PM PDT 24 |
| Finished | Jun 30 08:31:40 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-0dc485bb-e393-46f2-b3fb-1aff22ecff81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232395296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.4232395296 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.634204049 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 538281428 ps |
| CPU time | 51.08 seconds |
| Started | Jun 30 08:22:35 PM PDT 24 |
| Finished | Jun 30 08:23:27 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-a0417af2-2357-44ed-a082-b70a93782f05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634204049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_dela ys.634204049 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.2796723007 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 1731709735 ps |
| CPU time | 55.37 seconds |
| Started | Jun 30 08:22:40 PM PDT 24 |
| Finished | Jun 30 08:23:36 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-72b7865e-3ea4-4a55-a67f-3198f1c25614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796723007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.2796723007 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.2114838693 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 174277836 ps |
| CPU time | 8.69 seconds |
| Started | Jun 30 08:22:37 PM PDT 24 |
| Finished | Jun 30 08:22:46 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-acbfd5b1-0637-4b25-9a8f-c2923e01b8fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114838693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.2114838693 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.1253822000 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 6352783792 ps |
| CPU time | 68.09 seconds |
| Started | Jun 30 08:22:36 PM PDT 24 |
| Finished | Jun 30 08:23:45 PM PDT 24 |
| Peak memory | 566004 kb |
| Host | smart-cdbe7e3b-95ea-4e09-8dd1-e45e5498b0bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253822000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.1253822000 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.3717015133 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 2940765638 ps |
| CPU time | 50.27 seconds |
| Started | Jun 30 08:22:35 PM PDT 24 |
| Finished | Jun 30 08:23:26 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-c5992b5d-535f-4e7c-95db-2a697e1feb87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717015133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.3717015133 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.463003843 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 50556000 ps |
| CPU time | 6.76 seconds |
| Started | Jun 30 08:22:35 PM PDT 24 |
| Finished | Jun 30 08:22:42 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-cf55fb04-1573-4021-b8d2-fb7ed575ca53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463003843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delays .463003843 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.2077085022 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 3633643461 ps |
| CPU time | 155.83 seconds |
| Started | Jun 30 08:22:41 PM PDT 24 |
| Finished | Jun 30 08:25:18 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-b56cb012-d085-4194-9579-5d562c2421c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077085022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.2077085022 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2790096769 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 2385624002 ps |
| CPU time | 170.51 seconds |
| Started | Jun 30 08:22:49 PM PDT 24 |
| Finished | Jun 30 08:25:40 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-8333b0cd-42e3-4e72-b20b-ff91c4a2ea31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790096769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.2790096769 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.364292375 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 3034942056 ps |
| CPU time | 348.77 seconds |
| Started | Jun 30 08:22:46 PM PDT 24 |
| Finished | Jun 30 08:28:35 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-855353c9-c8d4-4a9a-9450-5ad8067dd21f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364292375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_reset_error.364292375 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.2155726945 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 247259599 ps |
| CPU time | 13.2 seconds |
| Started | Jun 30 08:22:41 PM PDT 24 |
| Finished | Jun 30 08:22:55 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-9387966d-a14a-4dfb-98a3-89e7bd54f6a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155726945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.2155726945 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.3168347039 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 128994214 ps |
| CPU time | 11.39 seconds |
| Started | Jun 30 08:22:46 PM PDT 24 |
| Finished | Jun 30 08:22:58 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-f74c49b2-b568-49e8-b9fe-c3c1672ca698 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168347039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .3168347039 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3049594806 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 105535585160 ps |
| CPU time | 1817.96 seconds |
| Started | Jun 30 08:22:53 PM PDT 24 |
| Finished | Jun 30 08:53:12 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-ad9534ae-3453-40f1-be50-41e7bb49d583 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049594806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.3049594806 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.2709352101 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 1226550608 ps |
| CPU time | 51.53 seconds |
| Started | Jun 30 08:22:52 PM PDT 24 |
| Finished | Jun 30 08:23:44 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-8d63906c-9312-4f9b-ad51-aa8034ce3bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709352101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.2709352101 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.3070588627 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 1748292161 ps |
| CPU time | 64.41 seconds |
| Started | Jun 30 08:22:53 PM PDT 24 |
| Finished | Jun 30 08:23:58 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-a35eae8c-1346-4ae4-a27f-a173a3094a4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070588627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.3070588627 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.1519895760 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 226756510 ps |
| CPU time | 25.04 seconds |
| Started | Jun 30 08:22:47 PM PDT 24 |
| Finished | Jun 30 08:23:13 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-e12430da-2f74-4602-80ff-ff1c48860f35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519895760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.1519895760 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.2509120635 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 69802238408 ps |
| CPU time | 744.47 seconds |
| Started | Jun 30 08:22:48 PM PDT 24 |
| Finished | Jun 30 08:35:13 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-f5762ed8-d5c0-4ad2-8657-e5054e738564 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509120635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.2509120635 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.2666636751 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 50182401454 ps |
| CPU time | 864.89 seconds |
| Started | Jun 30 08:22:47 PM PDT 24 |
| Finished | Jun 30 08:37:13 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-c0a06015-e598-4a76-9193-a7836e2b8ae4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666636751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.2666636751 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.2691711305 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 553312248 ps |
| CPU time | 57.95 seconds |
| Started | Jun 30 08:22:46 PM PDT 24 |
| Finished | Jun 30 08:23:45 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-60c9dd89-dd80-4c38-852a-7c7bb7d51986 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691711305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.2691711305 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.3221884997 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 1099380664 ps |
| CPU time | 30.28 seconds |
| Started | Jun 30 08:22:52 PM PDT 24 |
| Finished | Jun 30 08:23:23 PM PDT 24 |
| Peak memory | 575184 kb |
| Host | smart-6c7dbdf5-d736-47f9-87c7-a4dfa4897579 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221884997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.3221884997 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.606992111 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 210034810 ps |
| CPU time | 9.42 seconds |
| Started | Jun 30 08:22:46 PM PDT 24 |
| Finished | Jun 30 08:22:56 PM PDT 24 |
| Peak memory | 565952 kb |
| Host | smart-528d8b59-b33f-43f7-9792-a7ef6d77a557 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606992111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.606992111 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.4022200307 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 5845677563 ps |
| CPU time | 60.19 seconds |
| Started | Jun 30 08:22:47 PM PDT 24 |
| Finished | Jun 30 08:23:49 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-27e74e0a-e7ab-4cfe-aa8b-8236fa4eae04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022200307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.4022200307 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.821829841 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 3867204433 ps |
| CPU time | 65.14 seconds |
| Started | Jun 30 08:22:47 PM PDT 24 |
| Finished | Jun 30 08:23:53 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-fc0f1350-8b1b-40f3-895e-a8a3388c4866 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821829841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.821829841 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.3259592214 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 50078376 ps |
| CPU time | 6.89 seconds |
| Started | Jun 30 08:22:46 PM PDT 24 |
| Finished | Jun 30 08:22:54 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-7f9a8ce1-b401-4911-976e-f742dedf4efe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259592214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.3259592214 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.600695063 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 2006228860 ps |
| CPU time | 74.1 seconds |
| Started | Jun 30 08:23:13 PM PDT 24 |
| Finished | Jun 30 08:24:28 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-7a5cf352-1b8c-4777-8fd8-52fd9487e7b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600695063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.600695063 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.1290953732 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 5071237424 ps |
| CPU time | 366.41 seconds |
| Started | Jun 30 08:22:59 PM PDT 24 |
| Finished | Jun 30 08:29:06 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-d3400fdc-d8c5-4a52-be26-9f42f7601216 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290953732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.1290953732 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.3109238461 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 521031220 ps |
| CPU time | 145.72 seconds |
| Started | Jun 30 08:22:58 PM PDT 24 |
| Finished | Jun 30 08:25:24 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-a51fa988-2339-4c0f-b749-6ee81c5b50e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109238461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.3109238461 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.1458405512 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 264011220 ps |
| CPU time | 15.62 seconds |
| Started | Jun 30 08:22:52 PM PDT 24 |
| Finished | Jun 30 08:23:08 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-cc0ff757-e522-4fce-8037-46af3f3f1ad6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458405512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.1458405512 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.2553705605 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 509186013 ps |
| CPU time | 21.26 seconds |
| Started | Jun 30 08:23:04 PM PDT 24 |
| Finished | Jun 30 08:23:26 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-4a101e92-5e42-4ffb-8875-3229731f793f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553705605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .2553705605 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3143756910 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 134248748667 ps |
| CPU time | 2275.85 seconds |
| Started | Jun 30 08:23:00 PM PDT 24 |
| Finished | Jun 30 09:00:57 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-6ddd0ef8-a5db-47d1-b0b1-52e2477168cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143756910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.3143756910 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.573902197 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 958826300 ps |
| CPU time | 39 seconds |
| Started | Jun 30 08:23:02 PM PDT 24 |
| Finished | Jun 30 08:23:42 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-e3d5f5b7-148a-4107-9683-a3b3b42b51f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573902197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_addr .573902197 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.2646137915 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 2045993353 ps |
| CPU time | 77.22 seconds |
| Started | Jun 30 08:23:01 PM PDT 24 |
| Finished | Jun 30 08:24:20 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-29182319-4c47-4962-8e10-538bbae590b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646137915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.2646137915 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.88094215 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 90857059 ps |
| CPU time | 12.27 seconds |
| Started | Jun 30 08:22:57 PM PDT 24 |
| Finished | Jun 30 08:23:10 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-3e6bf77b-bd9c-49c7-99f5-654f79e4ec6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88094215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.88094215 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.3417951384 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 45739924016 ps |
| CPU time | 470.08 seconds |
| Started | Jun 30 08:23:02 PM PDT 24 |
| Finished | Jun 30 08:30:53 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-5f27b8f2-1120-4c89-8e18-95cb43de2417 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417951384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.3417951384 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.397409756 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 10936514852 ps |
| CPU time | 201.12 seconds |
| Started | Jun 30 08:23:02 PM PDT 24 |
| Finished | Jun 30 08:26:24 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-4509bb0e-f0b5-4f67-b02a-b57bb843bcbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397409756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.397409756 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.2730063199 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 75108709 ps |
| CPU time | 9.84 seconds |
| Started | Jun 30 08:22:56 PM PDT 24 |
| Finished | Jun 30 08:23:06 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-8f8fb765-1377-451b-a6c8-ee4704ed22fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730063199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.2730063199 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.3907842821 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 1593243773 ps |
| CPU time | 51.53 seconds |
| Started | Jun 30 08:23:02 PM PDT 24 |
| Finished | Jun 30 08:23:55 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-9363353b-7b8a-47f6-9136-b13cd8a41e54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907842821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.3907842821 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.3038407997 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 163930757 ps |
| CPU time | 8.61 seconds |
| Started | Jun 30 08:22:57 PM PDT 24 |
| Finished | Jun 30 08:23:06 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-e614c3fb-5b63-4aeb-a60b-55e22c40b735 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038407997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.3038407997 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.610377397 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 6888709415 ps |
| CPU time | 74.18 seconds |
| Started | Jun 30 08:22:54 PM PDT 24 |
| Finished | Jun 30 08:24:09 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-88396ca1-ffae-419c-87cc-f60773ec03fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610377397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.610377397 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.1749840807 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 4622211843 ps |
| CPU time | 77.06 seconds |
| Started | Jun 30 08:22:57 PM PDT 24 |
| Finished | Jun 30 08:24:15 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-5e07025c-df58-46de-9539-cc7d7576ce40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749840807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.1749840807 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.72025884 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 50331149 ps |
| CPU time | 7.3 seconds |
| Started | Jun 30 08:22:56 PM PDT 24 |
| Finished | Jun 30 08:23:04 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-a12430d9-040a-4f3c-ac3b-a110100b0b8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72025884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delays.72025884 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.2628248106 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 1489391398 ps |
| CPU time | 133.12 seconds |
| Started | Jun 30 08:23:02 PM PDT 24 |
| Finished | Jun 30 08:25:16 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-8a982106-6953-4d37-9eff-d0636f06b0c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628248106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.2628248106 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.3093530775 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 45979526 ps |
| CPU time | 6.14 seconds |
| Started | Jun 30 08:23:03 PM PDT 24 |
| Finished | Jun 30 08:23:09 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-8ba840a2-5efa-4454-9e20-8a1c3c16a144 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093530775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.3093530775 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3935210546 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 5481160530 ps |
| CPU time | 348.49 seconds |
| Started | Jun 30 08:23:05 PM PDT 24 |
| Finished | Jun 30 08:28:54 PM PDT 24 |
| Peak memory | 577448 kb |
| Host | smart-0a004715-fc81-45d9-b584-cb1b5013eb2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935210546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.3935210546 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1451639337 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 68995912 ps |
| CPU time | 32.65 seconds |
| Started | Jun 30 08:23:04 PM PDT 24 |
| Finished | Jun 30 08:23:38 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-8da8c5b6-7698-4469-9fa6-a2a269b9a294 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451639337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.1451639337 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.120843998 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 175596028 ps |
| CPU time | 24.41 seconds |
| Started | Jun 30 08:23:02 PM PDT 24 |
| Finished | Jun 30 08:23:27 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-b1e1a5de-ea1f-458d-a27b-3eca04eb8aa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120843998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.120843998 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.1735561632 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 3818996701 ps |
| CPU time | 370.49 seconds |
| Started | Jun 30 08:09:58 PM PDT 24 |
| Finished | Jun 30 08:16:09 PM PDT 24 |
| Peak memory | 596220 kb |
| Host | smart-cfcb9f5e-5c5c-4cd1-8847-8bacb0ad8268 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735561632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.1735561632 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3892977941 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 28906013436 ps |
| CPU time | 3420.9 seconds |
| Started | Jun 30 08:09:18 PM PDT 24 |
| Finished | Jun 30 09:06:19 PM PDT 24 |
| Peak memory | 591976 kb |
| Host | smart-8a459eb9-e2f2-4e55-ae26-c5dd734ebb3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892977941 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.3892977941 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.4281116472 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 3984401037 ps |
| CPU time | 327.27 seconds |
| Started | Jun 30 08:09:29 PM PDT 24 |
| Finished | Jun 30 08:14:56 PM PDT 24 |
| Peak memory | 597436 kb |
| Host | smart-99d4a497-d531-477c-8c52-26058814b808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281116472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.4281116472 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.2768393251 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1822692916 ps |
| CPU time | 87.27 seconds |
| Started | Jun 30 08:09:44 PM PDT 24 |
| Finished | Jun 30 08:11:12 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-d1b39f63-849e-4c1f-9e4c-9cef6904d52c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768393251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 2768393251 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.2439290903 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 285831653 ps |
| CPU time | 13.13 seconds |
| Started | Jun 30 08:09:54 PM PDT 24 |
| Finished | Jun 30 08:10:08 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-82bf71a8-6ee4-4811-ac83-dd34c3074e24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439290903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .2439290903 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.2791413603 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 850762663 ps |
| CPU time | 33.4 seconds |
| Started | Jun 30 08:09:47 PM PDT 24 |
| Finished | Jun 30 08:10:21 PM PDT 24 |
| Peak memory | 573832 kb |
| Host | smart-c34b4fea-85b7-464c-9894-59ae61fa07af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791413603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2791413603 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.1793697243 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 159413038 ps |
| CPU time | 17.1 seconds |
| Started | Jun 30 08:09:36 PM PDT 24 |
| Finished | Jun 30 08:09:53 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-fdc4a527-d48d-440a-9d78-056ccc81f78b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793697243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.1793697243 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.261817462 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 62485155215 ps |
| CPU time | 681.52 seconds |
| Started | Jun 30 08:09:49 PM PDT 24 |
| Finished | Jun 30 08:21:12 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-2c989396-3785-470a-bf9c-519c9c0b00b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261817462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.261817462 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.54412420 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 34590243565 ps |
| CPU time | 625.59 seconds |
| Started | Jun 30 08:09:42 PM PDT 24 |
| Finished | Jun 30 08:20:08 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-af8a5fe4-8ba2-4ead-bffb-be25743df3f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54412420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.54412420 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.2353803477 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 190262015 ps |
| CPU time | 20.79 seconds |
| Started | Jun 30 08:09:42 PM PDT 24 |
| Finished | Jun 30 08:10:03 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-bd53aa7f-9e22-4c69-a8be-ffe5fac2bbfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353803477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.2353803477 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.2178209955 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 2452115860 ps |
| CPU time | 81.53 seconds |
| Started | Jun 30 08:09:47 PM PDT 24 |
| Finished | Jun 30 08:11:09 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-8409ccdf-4a82-4341-a6ec-e50604965093 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178209955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2178209955 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.2052024424 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 166320375 ps |
| CPU time | 8.96 seconds |
| Started | Jun 30 08:09:30 PM PDT 24 |
| Finished | Jun 30 08:09:40 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-4fe1f313-a313-41a3-8a3d-497ca17d3c67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052024424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2052024424 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.176968842 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 8941783895 ps |
| CPU time | 95.37 seconds |
| Started | Jun 30 08:09:36 PM PDT 24 |
| Finished | Jun 30 08:11:12 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-767feeef-3503-474b-b1ce-5b83b7786532 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176968842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.176968842 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.4154070716 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 4589842860 ps |
| CPU time | 77.28 seconds |
| Started | Jun 30 08:09:36 PM PDT 24 |
| Finished | Jun 30 08:10:54 PM PDT 24 |
| Peak memory | 566004 kb |
| Host | smart-8110a24e-52ca-4be7-8a55-9706e422c9f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154070716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.4154070716 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.1513407816 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 46900179 ps |
| CPU time | 6.86 seconds |
| Started | Jun 30 08:09:32 PM PDT 24 |
| Finished | Jun 30 08:09:39 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-c21aada1-094a-49d3-9575-1c464e09041c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513407816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .1513407816 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.3539618672 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 4508590041 ps |
| CPU time | 179.13 seconds |
| Started | Jun 30 08:09:49 PM PDT 24 |
| Finished | Jun 30 08:12:49 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-0d87450b-8f79-4256-aa8b-6d6e49598817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539618672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3539618672 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.1021886008 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 871347129 ps |
| CPU time | 82.34 seconds |
| Started | Jun 30 08:09:52 PM PDT 24 |
| Finished | Jun 30 08:11:15 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-c152cc23-ffd6-41ef-8022-c82f3294882d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021886008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1021886008 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.800563381 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 1283999860 ps |
| CPU time | 89.66 seconds |
| Started | Jun 30 08:09:50 PM PDT 24 |
| Finished | Jun 30 08:11:20 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-432433f5-fafb-4783-9f7a-2653d6ba3a10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800563381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_w ith_rand_reset.800563381 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3051165586 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 490456619 ps |
| CPU time | 76.92 seconds |
| Started | Jun 30 08:09:57 PM PDT 24 |
| Finished | Jun 30 08:11:14 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-7d818a02-d4f8-4926-9148-34ec2f54d766 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051165586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.3051165586 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.42547702 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 150543931 ps |
| CPU time | 20.74 seconds |
| Started | Jun 30 08:09:46 PM PDT 24 |
| Finished | Jun 30 08:10:07 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-1c53cdd2-dde6-4087-999f-348ceb332747 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42547702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.42547702 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.2925216472 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 2066313978 ps |
| CPU time | 91.21 seconds |
| Started | Jun 30 08:23:09 PM PDT 24 |
| Finished | Jun 30 08:24:41 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-ca1fa5f3-9be2-486c-a62c-c1d04fb4ba3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925216472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .2925216472 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.3726702269 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 160068872228 ps |
| CPU time | 2707.86 seconds |
| Started | Jun 30 08:23:08 PM PDT 24 |
| Finished | Jun 30 09:08:17 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-713de241-65f4-4583-9a1f-0884989aa044 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726702269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.3726702269 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.2399595451 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 33548648 ps |
| CPU time | 6.64 seconds |
| Started | Jun 30 08:23:15 PM PDT 24 |
| Finished | Jun 30 08:23:22 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-0b118d14-cc06-4d2d-887f-8a0131f6b612 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399595451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.2399595451 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.729895460 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 510905524 ps |
| CPU time | 40.14 seconds |
| Started | Jun 30 08:23:14 PM PDT 24 |
| Finished | Jun 30 08:23:55 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-01ff709f-15ba-44fd-88d9-8b334365a043 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729895460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.729895460 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.3540300687 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 1627907812 ps |
| CPU time | 61.12 seconds |
| Started | Jun 30 08:23:12 PM PDT 24 |
| Finished | Jun 30 08:24:14 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-de34751b-e02d-4259-a8a6-0ca2e05036e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540300687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.3540300687 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.3504626933 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 87912662969 ps |
| CPU time | 907.85 seconds |
| Started | Jun 30 08:23:08 PM PDT 24 |
| Finished | Jun 30 08:38:17 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-639a9ec9-b0e3-44f8-b380-46beb8eac178 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504626933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.3504626933 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1871168978 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 52867277944 ps |
| CPU time | 912.77 seconds |
| Started | Jun 30 08:23:09 PM PDT 24 |
| Finished | Jun 30 08:38:22 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-7fa97761-729d-4e62-90d9-a9511b81cd7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871168978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.1871168978 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.1066437532 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 346174757 ps |
| CPU time | 35.07 seconds |
| Started | Jun 30 08:23:08 PM PDT 24 |
| Finished | Jun 30 08:23:44 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-e48954ae-aeac-4c8f-8ff3-3d94a575bbc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066437532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.1066437532 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.3652788581 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 574165988 ps |
| CPU time | 41.33 seconds |
| Started | Jun 30 08:23:10 PM PDT 24 |
| Finished | Jun 30 08:23:52 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-7b12c10a-e010-4770-8923-d8a2d4a5164c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652788581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.3652788581 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.1488465496 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 203958442 ps |
| CPU time | 8.66 seconds |
| Started | Jun 30 08:23:04 PM PDT 24 |
| Finished | Jun 30 08:23:13 PM PDT 24 |
| Peak memory | 565872 kb |
| Host | smart-560f0d18-5c42-41e5-95e1-e7d8146608da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488465496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.1488465496 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.56743511 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 8870220218 ps |
| CPU time | 92.52 seconds |
| Started | Jun 30 08:23:08 PM PDT 24 |
| Finished | Jun 30 08:24:41 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-c3c3e3c4-7bf4-4c0a-a0fd-68c2ae593eb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56743511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.56743511 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.938083672 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 4750578753 ps |
| CPU time | 82.28 seconds |
| Started | Jun 30 08:23:12 PM PDT 24 |
| Finished | Jun 30 08:24:35 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-706bf3a5-172f-4c78-8a7f-fa8a12e6802b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938083672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.938083672 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3518785241 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 49710423 ps |
| CPU time | 6.94 seconds |
| Started | Jun 30 08:23:02 PM PDT 24 |
| Finished | Jun 30 08:23:10 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-fcf51562-4d65-4a8e-8cd1-81f74a223d7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518785241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.3518785241 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.2252401682 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 13982835688 ps |
| CPU time | 530.45 seconds |
| Started | Jun 30 08:23:13 PM PDT 24 |
| Finished | Jun 30 08:32:04 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-b9686aa6-285c-4f73-bd51-be10f4477b8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252401682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.2252401682 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.944026683 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 7762485168 ps |
| CPU time | 292.61 seconds |
| Started | Jun 30 08:23:12 PM PDT 24 |
| Finished | Jun 30 08:28:05 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-6b63c2ba-236c-4e32-acf4-eb3eaf60f56d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944026683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.944026683 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.3602313465 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 8731621322 ps |
| CPU time | 517.53 seconds |
| Started | Jun 30 08:23:13 PM PDT 24 |
| Finished | Jun 30 08:31:51 PM PDT 24 |
| Peak memory | 576436 kb |
| Host | smart-31dfcc8a-537a-4dd9-9e39-866c4ddd8a5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602313465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.3602313465 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.2942210980 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 590361045 ps |
| CPU time | 255.1 seconds |
| Started | Jun 30 08:23:16 PM PDT 24 |
| Finished | Jun 30 08:27:32 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-a1f571c1-7216-43af-a288-05b64b39f2ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942210980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.2942210980 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.1823518286 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 166666779 ps |
| CPU time | 10.25 seconds |
| Started | Jun 30 08:23:12 PM PDT 24 |
| Finished | Jun 30 08:23:22 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-2f014644-4e52-4007-ac31-d0d742bd612e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823518286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.1823518286 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.566179239 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 954713746 ps |
| CPU time | 81.65 seconds |
| Started | Jun 30 08:23:21 PM PDT 24 |
| Finished | Jun 30 08:24:43 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-c0fdd9dd-d77a-435c-8a4b-2015f55d0608 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566179239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device. 566179239 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.2038492453 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 65292274282 ps |
| CPU time | 1141.4 seconds |
| Started | Jun 30 08:23:18 PM PDT 24 |
| Finished | Jun 30 08:42:20 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-a0bdb892-e398-4c5b-9303-a93745cd1117 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038492453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.2038492453 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3142901964 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 811194281 ps |
| CPU time | 38.72 seconds |
| Started | Jun 30 08:23:25 PM PDT 24 |
| Finished | Jun 30 08:24:04 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-c1e18680-579b-41de-989e-327247687be1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142901964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.3142901964 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.3414763918 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 2077595912 ps |
| CPU time | 80.78 seconds |
| Started | Jun 30 08:23:19 PM PDT 24 |
| Finished | Jun 30 08:24:41 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-673fe094-9887-43e6-9b3f-e9ae8cf5bb1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414763918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.3414763918 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.2395017628 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 73251568 ps |
| CPU time | 9.2 seconds |
| Started | Jun 30 08:23:19 PM PDT 24 |
| Finished | Jun 30 08:23:29 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-1f256ed0-8cff-4833-b116-2ac71c9db9be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395017628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.2395017628 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.3965641658 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 72009751001 ps |
| CPU time | 706.49 seconds |
| Started | Jun 30 08:23:19 PM PDT 24 |
| Finished | Jun 30 08:35:07 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-6b591965-c86c-41f5-a60f-69a28264f8c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965641658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.3965641658 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.3762008326 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 49838476871 ps |
| CPU time | 843.31 seconds |
| Started | Jun 30 08:23:21 PM PDT 24 |
| Finished | Jun 30 08:37:25 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-56ccad97-46fd-4964-acfa-a924de027f90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762008326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.3762008326 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.273933768 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 298151753 ps |
| CPU time | 31.58 seconds |
| Started | Jun 30 08:23:19 PM PDT 24 |
| Finished | Jun 30 08:23:51 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-37cdc244-63eb-4ef4-b2c5-1dc0518c79a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273933768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_dela ys.273933768 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.2790824772 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 1284389757 ps |
| CPU time | 37.6 seconds |
| Started | Jun 30 08:23:19 PM PDT 24 |
| Finished | Jun 30 08:23:58 PM PDT 24 |
| Peak memory | 575184 kb |
| Host | smart-ac77c842-058c-4f62-ac2b-b7bffd16c87b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790824772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.2790824772 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.3330239287 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 184306551 ps |
| CPU time | 9.78 seconds |
| Started | Jun 30 08:23:19 PM PDT 24 |
| Finished | Jun 30 08:23:29 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-48ba448a-12df-48c7-a417-67801e72cc20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330239287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.3330239287 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.903789933 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 6000801876 ps |
| CPU time | 65.76 seconds |
| Started | Jun 30 08:23:18 PM PDT 24 |
| Finished | Jun 30 08:24:24 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-ccbb4008-aa60-4d6c-82a8-31f760ecf430 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903789933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.903789933 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.3234337024 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 4651912913 ps |
| CPU time | 81.8 seconds |
| Started | Jun 30 08:23:20 PM PDT 24 |
| Finished | Jun 30 08:24:43 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-bd0cb4bd-9ba4-4d53-955b-9248900fe42e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234337024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.3234337024 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.1699162077 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 52441100 ps |
| CPU time | 6.67 seconds |
| Started | Jun 30 08:23:18 PM PDT 24 |
| Finished | Jun 30 08:23:25 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-bd7b84ee-23e9-47be-ad6f-e823c9e8c0bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699162077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.1699162077 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.2706156759 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 9642911222 ps |
| CPU time | 389.39 seconds |
| Started | Jun 30 08:23:23 PM PDT 24 |
| Finished | Jun 30 08:29:53 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-98ed06b7-0fa6-4f7d-a5a8-9cff9e5712d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706156759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.2706156759 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.1123075519 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 2080014277 ps |
| CPU time | 143.96 seconds |
| Started | Jun 30 08:23:32 PM PDT 24 |
| Finished | Jun 30 08:25:56 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-110c1cb5-1950-407e-9360-e56002a11651 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123075519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.1123075519 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.1923454043 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 2174435343 ps |
| CPU time | 315.7 seconds |
| Started | Jun 30 08:23:30 PM PDT 24 |
| Finished | Jun 30 08:28:46 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-00dbdcd8-0d24-499b-a9f7-ce372cc744eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923454043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.1923454043 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.1343572252 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 4221158784 ps |
| CPU time | 257.91 seconds |
| Started | Jun 30 08:23:29 PM PDT 24 |
| Finished | Jun 30 08:27:48 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-91d932ab-d53c-4c4c-ae9d-5e2622e93958 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343572252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.1343572252 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.3358029241 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 1349770865 ps |
| CPU time | 66.08 seconds |
| Started | Jun 30 08:23:24 PM PDT 24 |
| Finished | Jun 30 08:24:30 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-e3423d6c-c6b7-463b-96bb-7b5346349eeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358029241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.3358029241 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.2915786521 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 1412320034 ps |
| CPU time | 64.74 seconds |
| Started | Jun 30 08:23:29 PM PDT 24 |
| Finished | Jun 30 08:24:35 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-d2df188b-0d18-4a74-8c5b-e3646dbb29f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915786521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .2915786521 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.1458295692 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 59472173340 ps |
| CPU time | 1017.33 seconds |
| Started | Jun 30 08:23:36 PM PDT 24 |
| Finished | Jun 30 08:40:34 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-fa151fcb-3165-4e7b-abbd-067f652f3813 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458295692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.1458295692 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.3204385811 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 120462409 ps |
| CPU time | 9.83 seconds |
| Started | Jun 30 08:23:35 PM PDT 24 |
| Finished | Jun 30 08:23:45 PM PDT 24 |
| Peak memory | 565816 kb |
| Host | smart-e3778503-5128-447f-9ccd-e39aca0909bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204385811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.3204385811 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.3928355722 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 67206360 ps |
| CPU time | 8.75 seconds |
| Started | Jun 30 08:23:36 PM PDT 24 |
| Finished | Jun 30 08:23:46 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-e7158bcb-1a08-4843-a4ec-874a8a0f0714 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928355722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.3928355722 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.3854752862 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 2152637053 ps |
| CPU time | 81.12 seconds |
| Started | Jun 30 08:23:30 PM PDT 24 |
| Finished | Jun 30 08:24:52 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-1335825f-ce8d-4886-b120-add839e8e1d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854752862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.3854752862 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.2037542016 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 94787897792 ps |
| CPU time | 986.89 seconds |
| Started | Jun 30 08:23:33 PM PDT 24 |
| Finished | Jun 30 08:40:00 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-d912c921-427b-4b2c-b8ec-10a99802e8eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037542016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.2037542016 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.3102912671 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 60841555842 ps |
| CPU time | 1065.87 seconds |
| Started | Jun 30 08:23:33 PM PDT 24 |
| Finished | Jun 30 08:41:19 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-07298183-f25d-44f2-a13e-07681c0be2e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102912671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.3102912671 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.3905099635 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 509364788 ps |
| CPU time | 43.86 seconds |
| Started | Jun 30 08:23:28 PM PDT 24 |
| Finished | Jun 30 08:24:12 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-cff9950e-ac96-4b2c-85b9-4457c3be034d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905099635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.3905099635 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.1239112945 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 748183181 ps |
| CPU time | 23.03 seconds |
| Started | Jun 30 08:23:36 PM PDT 24 |
| Finished | Jun 30 08:24:00 PM PDT 24 |
| Peak memory | 575192 kb |
| Host | smart-b9024457-042c-40f9-a078-7052428feffe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239112945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.1239112945 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.3193873661 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 199270791 ps |
| CPU time | 8.65 seconds |
| Started | Jun 30 08:23:30 PM PDT 24 |
| Finished | Jun 30 08:23:39 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-7e692f37-2e54-4c36-ab1e-cb4a8e8eca82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193873661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.3193873661 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.3520296717 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 6433042106 ps |
| CPU time | 74.98 seconds |
| Started | Jun 30 08:23:29 PM PDT 24 |
| Finished | Jun 30 08:24:45 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-d602de1e-f7ec-48fc-803b-01c03eaa731c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520296717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.3520296717 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.1096899926 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 5275356789 ps |
| CPU time | 90.21 seconds |
| Started | Jun 30 08:23:29 PM PDT 24 |
| Finished | Jun 30 08:25:00 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-c4cf4776-a973-4b52-965f-83c8de0c30fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096899926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.1096899926 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.3752000662 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 54110534 ps |
| CPU time | 7.5 seconds |
| Started | Jun 30 08:23:30 PM PDT 24 |
| Finished | Jun 30 08:23:38 PM PDT 24 |
| Peak memory | 565916 kb |
| Host | smart-d5b3cfa5-ad23-4e52-a028-0df865f357ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752000662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.3752000662 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.2395900906 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 12186771164 ps |
| CPU time | 511.35 seconds |
| Started | Jun 30 08:23:37 PM PDT 24 |
| Finished | Jun 30 08:32:10 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-ea94d457-565e-44f2-a4ea-0b865122b700 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395900906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.2395900906 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.2695538804 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 2711486078 ps |
| CPU time | 224.81 seconds |
| Started | Jun 30 08:23:44 PM PDT 24 |
| Finished | Jun 30 08:27:30 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-d8dd46c4-7b93-4046-a9bb-01cca95c8719 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695538804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.2695538804 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.803567309 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 543655918 ps |
| CPU time | 150.66 seconds |
| Started | Jun 30 08:23:41 PM PDT 24 |
| Finished | Jun 30 08:26:12 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-ce193267-f8b5-4cde-b0ef-479fc3ea66b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803567309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_ with_rand_reset.803567309 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.2645786358 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 606083637 ps |
| CPU time | 30.98 seconds |
| Started | Jun 30 08:23:35 PM PDT 24 |
| Finished | Jun 30 08:24:07 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-466a4b07-f5ff-4746-a564-72a94d4aa211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645786358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.2645786358 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.1620684153 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 2546451546 ps |
| CPU time | 128.77 seconds |
| Started | Jun 30 08:23:47 PM PDT 24 |
| Finished | Jun 30 08:25:56 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-198a1abb-7b56-43ec-a8ab-2d8750a6085b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620684153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .1620684153 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1660638107 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 92023316385 ps |
| CPU time | 1609.21 seconds |
| Started | Jun 30 08:23:53 PM PDT 24 |
| Finished | Jun 30 08:50:43 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-36c3ad2d-7318-41ad-94d1-05020d9a5500 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660638107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.1660638107 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.520693199 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 242197352 ps |
| CPU time | 30.26 seconds |
| Started | Jun 30 08:23:53 PM PDT 24 |
| Finished | Jun 30 08:24:24 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-0d53caf3-bbcc-42a4-9374-f2e749415599 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520693199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_addr .520693199 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.1604011404 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 563330195 ps |
| CPU time | 47.94 seconds |
| Started | Jun 30 08:23:52 PM PDT 24 |
| Finished | Jun 30 08:24:41 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-b27255c3-9716-41ac-a999-62339883c681 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604011404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.1604011404 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.4089368009 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 613156410 ps |
| CPU time | 66.34 seconds |
| Started | Jun 30 08:23:47 PM PDT 24 |
| Finished | Jun 30 08:24:54 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-367f7499-bb78-4e3d-b95b-8e4b403da761 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089368009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.4089368009 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.2764393534 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 19790660195 ps |
| CPU time | 216.96 seconds |
| Started | Jun 30 08:23:47 PM PDT 24 |
| Finished | Jun 30 08:27:25 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-9b0bb27b-4f5b-4747-ad6d-469db4d382c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764393534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.2764393534 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.2854112353 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 38266953740 ps |
| CPU time | 651.26 seconds |
| Started | Jun 30 08:23:47 PM PDT 24 |
| Finished | Jun 30 08:34:39 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-eca6a48c-da94-4723-a89f-4e37e3cb4fa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854112353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.2854112353 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.483340093 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 241599578 ps |
| CPU time | 23.08 seconds |
| Started | Jun 30 08:23:49 PM PDT 24 |
| Finished | Jun 30 08:24:12 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-a3bb42be-6086-459a-af87-b83dda630170 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483340093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_dela ys.483340093 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.2266898527 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 2219031190 ps |
| CPU time | 74.99 seconds |
| Started | Jun 30 08:23:52 PM PDT 24 |
| Finished | Jun 30 08:25:08 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-49220af3-f519-453c-8a71-3b820a80ec20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266898527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.2266898527 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.1345915483 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 171510867 ps |
| CPU time | 9.02 seconds |
| Started | Jun 30 08:23:44 PM PDT 24 |
| Finished | Jun 30 08:23:54 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-77b8dd11-82ed-41e3-9258-5909568d9b6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345915483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.1345915483 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.665277874 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 8222902689 ps |
| CPU time | 85.35 seconds |
| Started | Jun 30 08:23:41 PM PDT 24 |
| Finished | Jun 30 08:25:07 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-693330da-5b1a-46b8-b10f-8cc0d838c33f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665277874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.665277874 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.1149787065 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 6285211103 ps |
| CPU time | 108.54 seconds |
| Started | Jun 30 08:23:48 PM PDT 24 |
| Finished | Jun 30 08:25:37 PM PDT 24 |
| Peak memory | 565992 kb |
| Host | smart-fd562df2-7eb6-440c-9e0e-94e1d407a2fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149787065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.1149787065 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2633718165 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 48295849 ps |
| CPU time | 7.15 seconds |
| Started | Jun 30 08:23:41 PM PDT 24 |
| Finished | Jun 30 08:23:49 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-b00ff5f3-71ec-4900-b049-4be44e76bda2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633718165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.2633718165 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.2959449920 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 5654418729 ps |
| CPU time | 232.82 seconds |
| Started | Jun 30 08:23:57 PM PDT 24 |
| Finished | Jun 30 08:27:51 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-28d01359-bd59-4de4-bc0b-1d2053d746db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959449920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.2959449920 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.3807097557 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 1357652093 ps |
| CPU time | 55.16 seconds |
| Started | Jun 30 08:23:52 PM PDT 24 |
| Finished | Jun 30 08:24:48 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-87dbc77f-9c68-4381-8031-fc1724a32362 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807097557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.3807097557 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.2663064514 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 15020664778 ps |
| CPU time | 813.47 seconds |
| Started | Jun 30 08:23:52 PM PDT 24 |
| Finished | Jun 30 08:37:26 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-80ab57c7-26fb-4300-946e-ff4a24e8312c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663064514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.2663064514 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3660449212 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 38307621 ps |
| CPU time | 14.85 seconds |
| Started | Jun 30 08:23:57 PM PDT 24 |
| Finished | Jun 30 08:24:12 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-b52cf8a5-6108-4ad9-8623-3c2bf254118e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660449212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.3660449212 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.2495429583 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 1065029706 ps |
| CPU time | 53.52 seconds |
| Started | Jun 30 08:23:53 PM PDT 24 |
| Finished | Jun 30 08:24:47 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-e816b761-197a-472d-b22f-58d45687ada0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495429583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.2495429583 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.3680922542 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 1595148196 ps |
| CPU time | 67.94 seconds |
| Started | Jun 30 08:24:04 PM PDT 24 |
| Finished | Jun 30 08:25:13 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-3569c693-b2f5-419c-ade5-b4e93f5d079f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680922542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .3680922542 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3309314779 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 116490924642 ps |
| CPU time | 1954.32 seconds |
| Started | Jun 30 08:24:06 PM PDT 24 |
| Finished | Jun 30 08:56:41 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-364d1694-d8ab-43eb-9893-620740222915 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309314779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.3309314779 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.127690640 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 1268009930 ps |
| CPU time | 49.59 seconds |
| Started | Jun 30 08:24:10 PM PDT 24 |
| Finished | Jun 30 08:25:00 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-6329d476-5949-4019-a399-fb48db9673a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127690640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_addr .127690640 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.4236330068 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 446124047 ps |
| CPU time | 46.64 seconds |
| Started | Jun 30 08:24:05 PM PDT 24 |
| Finished | Jun 30 08:24:53 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-36de72a1-6d6f-40a4-9325-0c8dca728c53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236330068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.4236330068 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.3263429162 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 513079593 ps |
| CPU time | 46.71 seconds |
| Started | Jun 30 08:23:58 PM PDT 24 |
| Finished | Jun 30 08:24:45 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-accd3041-39ce-45cd-b08b-eb03a28d69e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263429162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.3263429162 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.3189060003 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 42963802376 ps |
| CPU time | 467.17 seconds |
| Started | Jun 30 08:23:59 PM PDT 24 |
| Finished | Jun 30 08:31:46 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-5471b87e-8545-4951-a3ce-1497920dffb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189060003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.3189060003 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.2421533673 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 44727317366 ps |
| CPU time | 779.7 seconds |
| Started | Jun 30 08:24:05 PM PDT 24 |
| Finished | Jun 30 08:37:05 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-990af79b-faec-451a-876b-cb618e23f2c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421533673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.2421533673 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.682383399 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 52778383 ps |
| CPU time | 8.53 seconds |
| Started | Jun 30 08:23:58 PM PDT 24 |
| Finished | Jun 30 08:24:07 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-464e30e7-e21c-4e03-ae82-b5dfa15bb7be |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682383399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_dela ys.682383399 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.3475363653 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 141318838 ps |
| CPU time | 13.71 seconds |
| Started | Jun 30 08:24:05 PM PDT 24 |
| Finished | Jun 30 08:24:20 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-50a9aacb-8103-40df-b06d-ad65dd93f9b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475363653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.3475363653 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.4159318265 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 52270542 ps |
| CPU time | 6.8 seconds |
| Started | Jun 30 08:24:00 PM PDT 24 |
| Finished | Jun 30 08:24:07 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-cb9b1191-e253-4150-ae12-9d099307da63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159318265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.4159318265 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.1355131305 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 9550336503 ps |
| CPU time | 106.62 seconds |
| Started | Jun 30 08:23:58 PM PDT 24 |
| Finished | Jun 30 08:25:45 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-356eebd5-b731-4e00-965f-d75eb9594b31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355131305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.1355131305 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.509927535 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 3990481962 ps |
| CPU time | 75.51 seconds |
| Started | Jun 30 08:23:58 PM PDT 24 |
| Finished | Jun 30 08:25:14 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-ffd8fd9c-7c18-413b-b1ab-72201e45eac4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509927535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.509927535 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.2388300133 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 45389085 ps |
| CPU time | 7.06 seconds |
| Started | Jun 30 08:23:58 PM PDT 24 |
| Finished | Jun 30 08:24:06 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-d0de79e2-d0a9-4bdf-a20f-2ba50db2ce05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388300133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.2388300133 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.1570760969 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1350185105 ps |
| CPU time | 146.59 seconds |
| Started | Jun 30 08:24:05 PM PDT 24 |
| Finished | Jun 30 08:26:33 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-9ff0c0c4-6d20-45df-aa3d-1fe80b6d6480 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570760969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.1570760969 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.2901736516 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 323386680 ps |
| CPU time | 16.68 seconds |
| Started | Jun 30 08:24:04 PM PDT 24 |
| Finished | Jun 30 08:24:21 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-9402feb2-901b-4736-9a99-419f683636e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901736516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.2901736516 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.2049546125 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 10028892936 ps |
| CPU time | 546.98 seconds |
| Started | Jun 30 08:24:07 PM PDT 24 |
| Finished | Jun 30 08:33:14 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-153f8dbf-d711-406f-acc0-52144752a9a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049546125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_rand_reset.2049546125 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.2980151457 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 161461210 ps |
| CPU time | 55.67 seconds |
| Started | Jun 30 08:24:05 PM PDT 24 |
| Finished | Jun 30 08:25:01 PM PDT 24 |
| Peak memory | 576416 kb |
| Host | smart-77c30439-078a-4df6-8a77-e101b6a5eeb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980151457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.2980151457 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.3464100842 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 50568160 ps |
| CPU time | 5.98 seconds |
| Started | Jun 30 08:24:10 PM PDT 24 |
| Finished | Jun 30 08:24:16 PM PDT 24 |
| Peak memory | 565932 kb |
| Host | smart-d918167c-74a8-4c51-a43f-1486ad58edeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464100842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.3464100842 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.1395299510 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 1031746006 ps |
| CPU time | 91.48 seconds |
| Started | Jun 30 08:24:10 PM PDT 24 |
| Finished | Jun 30 08:25:42 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-497dfb9a-c650-458d-bdde-2b911011d7f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395299510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .1395299510 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.265912463 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 35979230950 ps |
| CPU time | 657.07 seconds |
| Started | Jun 30 08:24:09 PM PDT 24 |
| Finished | Jun 30 08:35:06 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-d39e04c9-e955-4b01-a1d1-029e4d1cb94a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265912463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_d evice_slow_rsp.265912463 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.649759478 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 111876000 ps |
| CPU time | 15.31 seconds |
| Started | Jun 30 08:24:14 PM PDT 24 |
| Finished | Jun 30 08:24:30 PM PDT 24 |
| Peak memory | 573864 kb |
| Host | smart-acc8682b-fd9e-4e0e-a1e8-a9a202ddb01a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649759478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr .649759478 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.1542664689 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 235629633 ps |
| CPU time | 11.97 seconds |
| Started | Jun 30 08:24:16 PM PDT 24 |
| Finished | Jun 30 08:24:29 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-d0e832a0-ece0-4b0a-bda6-731621388977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542664689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.1542664689 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.1647365818 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 1710367994 ps |
| CPU time | 65.83 seconds |
| Started | Jun 30 08:24:13 PM PDT 24 |
| Finished | Jun 30 08:25:19 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-8e27e509-2852-4a7b-99b7-0578c66a9473 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647365818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.1647365818 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.920363773 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 38960549508 ps |
| CPU time | 405.99 seconds |
| Started | Jun 30 08:24:10 PM PDT 24 |
| Finished | Jun 30 08:30:57 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-2f6b48fc-7b12-4f8a-a3ea-e7d606054f25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920363773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.920363773 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.2804973591 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 3665318407 ps |
| CPU time | 63.53 seconds |
| Started | Jun 30 08:24:12 PM PDT 24 |
| Finished | Jun 30 08:25:16 PM PDT 24 |
| Peak memory | 565996 kb |
| Host | smart-3865bf34-c775-497a-99f4-a0c696e00bc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804973591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.2804973591 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.2890716405 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 526589888 ps |
| CPU time | 50.87 seconds |
| Started | Jun 30 08:24:11 PM PDT 24 |
| Finished | Jun 30 08:25:02 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-18dd60ea-13b6-4d16-b7c8-9ee4ebd70225 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890716405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.2890716405 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.462631595 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 210657938 ps |
| CPU time | 18.38 seconds |
| Started | Jun 30 08:24:19 PM PDT 24 |
| Finished | Jun 30 08:24:38 PM PDT 24 |
| Peak memory | 575172 kb |
| Host | smart-fa98674a-9b93-47d4-a5b8-a0d0ae14fe30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462631595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.462631595 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.2655214885 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 57427601 ps |
| CPU time | 7.69 seconds |
| Started | Jun 30 08:24:06 PM PDT 24 |
| Finished | Jun 30 08:24:14 PM PDT 24 |
| Peak memory | 565888 kb |
| Host | smart-25e8a55d-2d2a-4300-9879-f683f2b336ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655214885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.2655214885 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.3384354171 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 8374317163 ps |
| CPU time | 86.9 seconds |
| Started | Jun 30 08:24:10 PM PDT 24 |
| Finished | Jun 30 08:25:38 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-4a40868f-253b-4382-964b-1997294bfdf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384354171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.3384354171 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.2763920012 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 5566894017 ps |
| CPU time | 105.1 seconds |
| Started | Jun 30 08:24:10 PM PDT 24 |
| Finished | Jun 30 08:25:56 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-cb6a06b8-4e84-45ba-a619-f58ecbb6341a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763920012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.2763920012 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2111231792 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 43818189 ps |
| CPU time | 6.33 seconds |
| Started | Jun 30 08:24:10 PM PDT 24 |
| Finished | Jun 30 08:24:16 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-0d34051a-d287-48d5-8dbc-3741081317ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111231792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.2111231792 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.4129848007 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 5350395021 ps |
| CPU time | 227.25 seconds |
| Started | Jun 30 08:24:15 PM PDT 24 |
| Finished | Jun 30 08:28:03 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-2eca637a-3a4d-4083-b793-a0b938470954 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129848007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.4129848007 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.2538872043 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 1776669178 ps |
| CPU time | 60.77 seconds |
| Started | Jun 30 08:24:19 PM PDT 24 |
| Finished | Jun 30 08:25:20 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-52657d08-4017-4fc5-9b9f-441b08e0852b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538872043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.2538872043 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.599338849 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 3373803873 ps |
| CPU time | 350.13 seconds |
| Started | Jun 30 08:24:15 PM PDT 24 |
| Finished | Jun 30 08:30:05 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-370650c9-4f9d-492a-a017-37a03ef2456f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599338849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_ with_rand_reset.599338849 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1438835847 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 102111624 ps |
| CPU time | 13.63 seconds |
| Started | Jun 30 08:24:15 PM PDT 24 |
| Finished | Jun 30 08:24:29 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-02ddd868-e286-4f67-ae98-98b10e9c6606 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438835847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.1438835847 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.2828960660 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 217520088 ps |
| CPU time | 20.26 seconds |
| Started | Jun 30 08:24:23 PM PDT 24 |
| Finished | Jun 30 08:24:44 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-63e7d57a-a655-41a1-9050-266ba7646b04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828960660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .2828960660 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.1707969984 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 11916318663 ps |
| CPU time | 202.27 seconds |
| Started | Jun 30 08:24:20 PM PDT 24 |
| Finished | Jun 30 08:27:43 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-1068bb53-85bf-4f90-b01e-d3d8274eef39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707969984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.1707969984 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.3222939982 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 1353635879 ps |
| CPU time | 58.47 seconds |
| Started | Jun 30 08:24:24 PM PDT 24 |
| Finished | Jun 30 08:25:23 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-2560a66d-708e-4991-a3c4-21d603b20a48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222939982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.3222939982 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.4179413189 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 1661180078 ps |
| CPU time | 59.29 seconds |
| Started | Jun 30 08:24:27 PM PDT 24 |
| Finished | Jun 30 08:25:27 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-d63a4910-bff0-454b-9ab1-8dd865f45e4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179413189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.4179413189 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.2243988172 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 201290135 ps |
| CPU time | 11.69 seconds |
| Started | Jun 30 08:24:20 PM PDT 24 |
| Finished | Jun 30 08:24:32 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-a36f8073-1ab4-4426-a21c-6ec5eecf4c43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243988172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.2243988172 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.674995947 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 73276694902 ps |
| CPU time | 766.44 seconds |
| Started | Jun 30 08:24:26 PM PDT 24 |
| Finished | Jun 30 08:37:13 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-5c76533e-34df-43a2-9981-e57be1678fdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674995947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.674995947 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.1160346353 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 7285711108 ps |
| CPU time | 120.89 seconds |
| Started | Jun 30 08:24:26 PM PDT 24 |
| Finished | Jun 30 08:26:28 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-8790c195-0080-49fd-a2c8-88e780bedabb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160346353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.1160346353 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.1296625883 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 585428465 ps |
| CPU time | 53.2 seconds |
| Started | Jun 30 08:24:21 PM PDT 24 |
| Finished | Jun 30 08:25:15 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-d33976a7-9190-49a5-8efe-fc5a64dca746 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296625883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.1296625883 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.3971047269 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 299814778 ps |
| CPU time | 27.55 seconds |
| Started | Jun 30 08:24:29 PM PDT 24 |
| Finished | Jun 30 08:24:57 PM PDT 24 |
| Peak memory | 575148 kb |
| Host | smart-9f8e451a-3072-455a-9e86-692d64db8fad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971047269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.3971047269 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.368021691 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 256828876 ps |
| CPU time | 11.84 seconds |
| Started | Jun 30 08:24:22 PM PDT 24 |
| Finished | Jun 30 08:24:35 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-571fce70-611b-4183-823b-f9e962af11bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368021691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.368021691 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.1818537504 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 6258170718 ps |
| CPU time | 68.99 seconds |
| Started | Jun 30 08:24:22 PM PDT 24 |
| Finished | Jun 30 08:25:32 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-fb510d86-d900-4e22-9ae7-542994cfdd7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818537504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.1818537504 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.3453625172 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 3899233906 ps |
| CPU time | 66.48 seconds |
| Started | Jun 30 08:24:22 PM PDT 24 |
| Finished | Jun 30 08:25:29 PM PDT 24 |
| Peak memory | 566148 kb |
| Host | smart-46881bb2-a6df-41f8-a6d6-57ba260ab197 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453625172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.3453625172 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.4131501728 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 55685967 ps |
| CPU time | 7.4 seconds |
| Started | Jun 30 08:24:21 PM PDT 24 |
| Finished | Jun 30 08:24:28 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-59a52c37-6c87-4d93-82ac-f4bfe7a1ef02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131501728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.4131501728 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.1710842678 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 7624178528 ps |
| CPU time | 307.36 seconds |
| Started | Jun 30 08:24:26 PM PDT 24 |
| Finished | Jun 30 08:29:34 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-1e92e393-e6eb-4756-be33-fad888e8b95f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710842678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.1710842678 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.2950023644 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 10740826676 ps |
| CPU time | 404.38 seconds |
| Started | Jun 30 08:24:36 PM PDT 24 |
| Finished | Jun 30 08:31:21 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-6abcd212-cc4d-484e-9208-2b794abdbf29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950023644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.2950023644 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.2063758649 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 74988545 ps |
| CPU time | 46.52 seconds |
| Started | Jun 30 08:24:26 PM PDT 24 |
| Finished | Jun 30 08:25:13 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-58673f4d-b413-4341-a6db-192c0d044a66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063758649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.2063758649 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.1441051211 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 923022499 ps |
| CPU time | 222.18 seconds |
| Started | Jun 30 08:24:36 PM PDT 24 |
| Finished | Jun 30 08:28:19 PM PDT 24 |
| Peak memory | 576392 kb |
| Host | smart-4a78ea9c-df49-4959-9198-0c9790ca3381 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441051211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.1441051211 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.1237500596 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 285843219 ps |
| CPU time | 40.84 seconds |
| Started | Jun 30 08:24:30 PM PDT 24 |
| Finished | Jun 30 08:25:11 PM PDT 24 |
| Peak memory | 575196 kb |
| Host | smart-c2144da4-080f-49bc-8cd2-82d5d358476b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237500596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.1237500596 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.2799104162 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 313238067 ps |
| CPU time | 23.88 seconds |
| Started | Jun 30 08:24:36 PM PDT 24 |
| Finished | Jun 30 08:25:00 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-80640dca-5539-4231-8762-fc2bcc4b3b02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799104162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .2799104162 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.1423894516 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 48372757627 ps |
| CPU time | 872.24 seconds |
| Started | Jun 30 08:24:37 PM PDT 24 |
| Finished | Jun 30 08:39:10 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-c7ca8464-4590-4b31-9f51-5cbacb4fac1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423894516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.1423894516 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.2452663709 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 537626970 ps |
| CPU time | 21.69 seconds |
| Started | Jun 30 08:24:36 PM PDT 24 |
| Finished | Jun 30 08:24:58 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-d36ec467-ff1b-4e37-910a-6a34e9be80b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452663709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.2452663709 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.579003251 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 293931339 ps |
| CPU time | 25.37 seconds |
| Started | Jun 30 08:24:35 PM PDT 24 |
| Finished | Jun 30 08:25:01 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-15750d11-2449-4444-8fff-dad1c73cc9ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579003251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.579003251 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.3906673650 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 78816436 ps |
| CPU time | 9.98 seconds |
| Started | Jun 30 08:24:26 PM PDT 24 |
| Finished | Jun 30 08:24:36 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-63540bb2-c5a0-4d45-8dc6-74abfa92ac97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906673650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.3906673650 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.782431078 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 78906765710 ps |
| CPU time | 805.1 seconds |
| Started | Jun 30 08:24:27 PM PDT 24 |
| Finished | Jun 30 08:37:52 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-fbd33ad9-7f7f-4193-9f24-c06f5a3690fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782431078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.782431078 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.1678349659 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 66391115234 ps |
| CPU time | 1143.55 seconds |
| Started | Jun 30 08:24:34 PM PDT 24 |
| Finished | Jun 30 08:43:38 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-c5818eb5-b9a1-4f92-ad85-dd13d54fdbb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678349659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.1678349659 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.3236657393 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 103348072 ps |
| CPU time | 12.48 seconds |
| Started | Jun 30 08:24:34 PM PDT 24 |
| Finished | Jun 30 08:24:47 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-0f00ffcc-c3b7-4af6-aecf-b8b5716f0ab1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236657393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.3236657393 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.2551113364 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 660989690 ps |
| CPU time | 23.18 seconds |
| Started | Jun 30 08:24:36 PM PDT 24 |
| Finished | Jun 30 08:25:00 PM PDT 24 |
| Peak memory | 575188 kb |
| Host | smart-156e5a29-7df7-4219-bfa7-c46e02d3d8de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551113364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.2551113364 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.3139460359 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 174467474 ps |
| CPU time | 9.14 seconds |
| Started | Jun 30 08:24:26 PM PDT 24 |
| Finished | Jun 30 08:24:36 PM PDT 24 |
| Peak memory | 565944 kb |
| Host | smart-5940b71d-b8ec-495e-b85f-0e056e031817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139460359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.3139460359 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.2532811445 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 8224647926 ps |
| CPU time | 86.28 seconds |
| Started | Jun 30 08:24:27 PM PDT 24 |
| Finished | Jun 30 08:25:54 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-4a08f931-4a4a-4b67-b3aa-283d9d199a20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532811445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.2532811445 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.1881695435 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 5240879999 ps |
| CPU time | 94.95 seconds |
| Started | Jun 30 08:24:34 PM PDT 24 |
| Finished | Jun 30 08:26:09 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-a8074e06-8272-4eb2-baef-6acfbdd7eee8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881695435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.1881695435 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.4264319566 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 47214285 ps |
| CPU time | 6.33 seconds |
| Started | Jun 30 08:24:28 PM PDT 24 |
| Finished | Jun 30 08:24:35 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-808842eb-d05e-48bf-95ff-e31b97cb3d56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264319566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.4264319566 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.1480493750 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 14634313311 ps |
| CPU time | 519.61 seconds |
| Started | Jun 30 08:24:38 PM PDT 24 |
| Finished | Jun 30 08:33:18 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-bb2ae16b-38aa-4496-8222-b49b08fc52e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480493750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.1480493750 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.3233207013 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 1716094720 ps |
| CPU time | 57.61 seconds |
| Started | Jun 30 08:24:39 PM PDT 24 |
| Finished | Jun 30 08:25:37 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-86acd7fc-b3e1-4e1a-83ab-5078d6bfe538 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233207013 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.3233207013 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3645591811 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 2547209961 ps |
| CPU time | 341.04 seconds |
| Started | Jun 30 08:24:37 PM PDT 24 |
| Finished | Jun 30 08:30:19 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-0bff8a57-a531-453c-bf09-201e5e70ecee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645591811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.3645591811 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3900531941 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 116710580 ps |
| CPU time | 81.62 seconds |
| Started | Jun 30 08:24:37 PM PDT 24 |
| Finished | Jun 30 08:25:59 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-a29ef27b-38b4-4b7f-a923-e5cfccd1e7bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900531941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.3900531941 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.291502259 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1380463007 ps |
| CPU time | 65.44 seconds |
| Started | Jun 30 08:24:36 PM PDT 24 |
| Finished | Jun 30 08:25:42 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-469b3131-2b9b-4b0e-bbf1-680990c8972a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291502259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.291502259 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.3310779167 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 2612100879 ps |
| CPU time | 121.63 seconds |
| Started | Jun 30 08:24:40 PM PDT 24 |
| Finished | Jun 30 08:26:42 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-9f3965d8-7f69-49e1-80a4-1a54adf8494e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310779167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .3310779167 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.2271327306 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 42064258764 ps |
| CPU time | 692.66 seconds |
| Started | Jun 30 08:24:47 PM PDT 24 |
| Finished | Jun 30 08:36:21 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-7bd1227f-8d63-4124-b56a-e6919d2c441d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271327306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.2271327306 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2178647652 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 264251642 ps |
| CPU time | 30.07 seconds |
| Started | Jun 30 08:24:46 PM PDT 24 |
| Finished | Jun 30 08:25:16 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-d01b3572-9f41-47db-80f2-979aff07566c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178647652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.2178647652 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.2967525880 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 2447442555 ps |
| CPU time | 83.05 seconds |
| Started | Jun 30 08:24:46 PM PDT 24 |
| Finished | Jun 30 08:26:09 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-9bc4e23d-14ab-42af-96ee-1fa2c32f34d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967525880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.2967525880 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.3585305201 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 435306362 ps |
| CPU time | 19.46 seconds |
| Started | Jun 30 08:24:38 PM PDT 24 |
| Finished | Jun 30 08:24:58 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-a5ac35cb-cdf5-4d2c-a6a2-49a28826d285 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585305201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.3585305201 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.137138303 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 24159826010 ps |
| CPU time | 261.01 seconds |
| Started | Jun 30 08:24:38 PM PDT 24 |
| Finished | Jun 30 08:29:00 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-794090a2-bbb6-4125-a516-5604c5e9ef7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137138303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.137138303 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.3397038132 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 67445243236 ps |
| CPU time | 1170.63 seconds |
| Started | Jun 30 08:24:36 PM PDT 24 |
| Finished | Jun 30 08:44:08 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-c29b3486-0939-46ce-919b-16119663c723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397038132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.3397038132 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.604181728 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 329136580 ps |
| CPU time | 32.57 seconds |
| Started | Jun 30 08:24:47 PM PDT 24 |
| Finished | Jun 30 08:25:21 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-cf4f730b-fc0e-4d1d-a9a6-6cd441ebb8c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604181728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_dela ys.604181728 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.2295691275 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 2182219286 ps |
| CPU time | 72.32 seconds |
| Started | Jun 30 08:24:38 PM PDT 24 |
| Finished | Jun 30 08:25:51 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-f2a69cb0-488b-427b-819c-a436cd3d3dcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295691275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.2295691275 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.2582428387 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 208137535 ps |
| CPU time | 8.83 seconds |
| Started | Jun 30 08:24:47 PM PDT 24 |
| Finished | Jun 30 08:24:57 PM PDT 24 |
| Peak memory | 565896 kb |
| Host | smart-8db55473-176a-40a4-8071-12b85ad21380 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582428387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.2582428387 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.4012743438 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 7680471958 ps |
| CPU time | 85.9 seconds |
| Started | Jun 30 08:24:47 PM PDT 24 |
| Finished | Jun 30 08:26:14 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-1be07aed-3692-4797-b3cc-86ec061d1c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012743438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.4012743438 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.2893112274 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 5428818875 ps |
| CPU time | 93.36 seconds |
| Started | Jun 30 08:24:37 PM PDT 24 |
| Finished | Jun 30 08:26:11 PM PDT 24 |
| Peak memory | 566000 kb |
| Host | smart-49e8a653-c1a9-4c19-ae45-45b2d375bf3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893112274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.2893112274 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.26244813 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 44171883 ps |
| CPU time | 6.97 seconds |
| Started | Jun 30 08:24:39 PM PDT 24 |
| Finished | Jun 30 08:24:47 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-92bdfa63-8640-41d1-a3c9-fb46ce0e61f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26244813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays.26244813 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.2472715186 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 3744167249 ps |
| CPU time | 153.48 seconds |
| Started | Jun 30 08:24:43 PM PDT 24 |
| Finished | Jun 30 08:27:17 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-a73c0c44-633c-46cf-8c6c-7e6742256919 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472715186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.2472715186 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.495887059 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 21124063711 ps |
| CPU time | 808.06 seconds |
| Started | Jun 30 08:24:47 PM PDT 24 |
| Finished | Jun 30 08:38:16 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-9665243c-0577-463d-beb2-5712caf734d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495887059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.495887059 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3257122877 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 5922550665 ps |
| CPU time | 659.52 seconds |
| Started | Jun 30 08:24:45 PM PDT 24 |
| Finished | Jun 30 08:35:45 PM PDT 24 |
| Peak memory | 576432 kb |
| Host | smart-52c0c68c-ed19-41f9-b97c-25ac3d1f1610 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257122877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.3257122877 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.2222881602 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 135522701 ps |
| CPU time | 18.54 seconds |
| Started | Jun 30 08:24:46 PM PDT 24 |
| Finished | Jun 30 08:25:05 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-0d0970a1-2061-4ad4-9d1f-c1eea7c3d091 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222881602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.2222881602 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.3721969204 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 2736595797 ps |
| CPU time | 107.38 seconds |
| Started | Jun 30 08:24:50 PM PDT 24 |
| Finished | Jun 30 08:26:38 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-7dff6b53-d90e-414f-9c8d-607fc4a6be91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721969204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .3721969204 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.1868452845 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 84214844774 ps |
| CPU time | 1437.44 seconds |
| Started | Jun 30 08:24:50 PM PDT 24 |
| Finished | Jun 30 08:48:48 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-ac0dee50-7b08-4093-9865-337f5e6777fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868452845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.1868452845 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.970745299 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 284552401 ps |
| CPU time | 15.98 seconds |
| Started | Jun 30 08:24:56 PM PDT 24 |
| Finished | Jun 30 08:25:12 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-8e9782c0-8f0b-4bac-a975-80e338b9c047 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970745299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr .970745299 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.3930338907 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 264934847 ps |
| CPU time | 28.41 seconds |
| Started | Jun 30 08:24:56 PM PDT 24 |
| Finished | Jun 30 08:25:25 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-34dde486-4d5a-4459-b9a6-dab356172c97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930338907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.3930338907 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.2378557000 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 2479753745 ps |
| CPU time | 96.07 seconds |
| Started | Jun 30 08:24:51 PM PDT 24 |
| Finished | Jun 30 08:26:27 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-a1a6d94c-f5d3-489a-9f3f-b246b8d79c5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378557000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2378557000 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.4182657802 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 74713451334 ps |
| CPU time | 737.1 seconds |
| Started | Jun 30 08:24:50 PM PDT 24 |
| Finished | Jun 30 08:37:07 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-764381ce-46c5-4945-a515-00f7cf4f780a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182657802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.4182657802 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.4114908458 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 43274231276 ps |
| CPU time | 763.56 seconds |
| Started | Jun 30 08:24:51 PM PDT 24 |
| Finished | Jun 30 08:37:35 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-df4056bf-a675-4402-b41a-40b0eb5b803c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114908458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.4114908458 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.3404590385 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 496020755 ps |
| CPU time | 51.43 seconds |
| Started | Jun 30 08:24:49 PM PDT 24 |
| Finished | Jun 30 08:25:41 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-cb5c319e-92ed-43f3-b70a-4fa78d0bdffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404590385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.3404590385 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.4243483824 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 2289623305 ps |
| CPU time | 72.93 seconds |
| Started | Jun 30 08:24:57 PM PDT 24 |
| Finished | Jun 30 08:26:11 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-c108bad0-eacb-407e-ac98-b3b144c63f19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243483824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.4243483824 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.3529602301 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 188229938 ps |
| CPU time | 8.92 seconds |
| Started | Jun 30 08:24:46 PM PDT 24 |
| Finished | Jun 30 08:24:55 PM PDT 24 |
| Peak memory | 565916 kb |
| Host | smart-7ef65f2b-2fae-46f2-bd34-8c95c366be56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529602301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.3529602301 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.1410322088 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 8312831154 ps |
| CPU time | 86.03 seconds |
| Started | Jun 30 08:24:43 PM PDT 24 |
| Finished | Jun 30 08:26:10 PM PDT 24 |
| Peak memory | 566008 kb |
| Host | smart-dfaf3060-541f-48eb-b487-cbdd31dcc856 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410322088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.1410322088 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.1406453466 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 3563241349 ps |
| CPU time | 67.03 seconds |
| Started | Jun 30 08:24:43 PM PDT 24 |
| Finished | Jun 30 08:25:51 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-120defc6-5885-4aba-af0e-075ae3e42466 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406453466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.1406453466 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.3519389094 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 39328146 ps |
| CPU time | 6.04 seconds |
| Started | Jun 30 08:24:43 PM PDT 24 |
| Finished | Jun 30 08:24:50 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-50afc550-ac7a-47b5-9ec8-c059c89af46f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519389094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.3519389094 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.1190449149 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 13870227314 ps |
| CPU time | 584.78 seconds |
| Started | Jun 30 08:24:57 PM PDT 24 |
| Finished | Jun 30 08:34:43 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-9c17a2b6-f5f0-4d27-b99b-18f529f234e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190449149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.1190449149 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.1769800163 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 11221114117 ps |
| CPU time | 518.7 seconds |
| Started | Jun 30 08:24:58 PM PDT 24 |
| Finished | Jun 30 08:33:38 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-475f0f65-6c31-495a-895a-a6fc736b6737 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769800163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.1769800163 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.4116991893 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2175606844 ps |
| CPU time | 302.03 seconds |
| Started | Jun 30 08:24:57 PM PDT 24 |
| Finished | Jun 30 08:29:59 PM PDT 24 |
| Peak memory | 576436 kb |
| Host | smart-423a11ff-cdf7-419a-bd7e-1ec1296c0453 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116991893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.4116991893 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.4261318987 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 5475893625 ps |
| CPU time | 389.82 seconds |
| Started | Jun 30 08:24:57 PM PDT 24 |
| Finished | Jun 30 08:31:27 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-85ff5f16-5253-4e80-8cd5-2dd88e82b558 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261318987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.4261318987 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.1188870311 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 177480877 ps |
| CPU time | 23.99 seconds |
| Started | Jun 30 08:24:57 PM PDT 24 |
| Finished | Jun 30 08:25:22 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-b8d33261-68e6-4235-a0d7-ea50b4753415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188870311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.1188870311 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.1599911986 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 4367366980 ps |
| CPU time | 356.65 seconds |
| Started | Jun 30 08:10:27 PM PDT 24 |
| Finished | Jun 30 08:16:24 PM PDT 24 |
| Peak memory | 596548 kb |
| Host | smart-5d34e464-3e17-4927-a884-d80b15e2b0d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599911986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.1599911986 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2515636763 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 31058497617 ps |
| CPU time | 3617 seconds |
| Started | Jun 30 08:10:04 PM PDT 24 |
| Finished | Jun 30 09:10:21 PM PDT 24 |
| Peak memory | 591860 kb |
| Host | smart-5519c419-f7a5-49d7-a986-cbf4b7263e19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515636763 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.2515636763 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.2459009028 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 3989009266 ps |
| CPU time | 280.62 seconds |
| Started | Jun 30 08:10:07 PM PDT 24 |
| Finished | Jun 30 08:14:48 PM PDT 24 |
| Peak memory | 603592 kb |
| Host | smart-d6102cb3-a8eb-46d5-b47d-8ad7f4877f02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459009028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.2459009028 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.4103732252 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 1013573953 ps |
| CPU time | 91.27 seconds |
| Started | Jun 30 08:10:09 PM PDT 24 |
| Finished | Jun 30 08:11:41 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-f0b867cd-f93a-428a-99e4-01dca7cdcb78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103732252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 4103732252 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2630769453 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 128679713225 ps |
| CPU time | 2222.8 seconds |
| Started | Jun 30 08:10:11 PM PDT 24 |
| Finished | Jun 30 08:47:15 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-5e60a8f9-1c21-4fef-948a-2fcc99fa74c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630769453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.2630769453 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.1941812091 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 1373324367 ps |
| CPU time | 65.4 seconds |
| Started | Jun 30 08:10:21 PM PDT 24 |
| Finished | Jun 30 08:11:27 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-223467b3-aee0-4ad3-ad5c-ed89cfd90175 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941812091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .1941812091 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.2253579564 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 1511833639 ps |
| CPU time | 55.61 seconds |
| Started | Jun 30 08:10:13 PM PDT 24 |
| Finished | Jun 30 08:11:09 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-45371ffe-71f9-42d0-b486-44f2ba6a850f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253579564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2253579564 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.4075823482 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 1185383336 ps |
| CPU time | 53.9 seconds |
| Started | Jun 30 08:10:06 PM PDT 24 |
| Finished | Jun 30 08:11:00 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-3176bb70-344c-4a7f-b676-c915890d477f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075823482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.4075823482 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.2133745324 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 75034783785 ps |
| CPU time | 881.08 seconds |
| Started | Jun 30 08:10:10 PM PDT 24 |
| Finished | Jun 30 08:24:51 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-24333550-8483-4ece-ab60-6e5f8fb584f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133745324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2133745324 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.1323355291 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 36628914223 ps |
| CPU time | 642.17 seconds |
| Started | Jun 30 08:10:11 PM PDT 24 |
| Finished | Jun 30 08:20:54 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-1c4cefd9-8e7a-4bed-bb63-f6852f29823e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323355291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1323355291 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.576433166 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 122081161 ps |
| CPU time | 15.48 seconds |
| Started | Jun 30 08:10:08 PM PDT 24 |
| Finished | Jun 30 08:10:24 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-02b946a2-cad5-4582-87a8-afe7957fe162 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576433166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delay s.576433166 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.4065175724 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 684881362 ps |
| CPU time | 25.27 seconds |
| Started | Jun 30 08:10:12 PM PDT 24 |
| Finished | Jun 30 08:10:37 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-bdabea84-0add-45ef-b473-0f520a73c056 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065175724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.4065175724 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.614029074 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 223316468 ps |
| CPU time | 10.53 seconds |
| Started | Jun 30 08:10:08 PM PDT 24 |
| Finished | Jun 30 08:10:19 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-593a92db-1c5a-4740-b0c8-ac0837601746 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614029074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.614029074 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.460662386 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 8467107810 ps |
| CPU time | 90.87 seconds |
| Started | Jun 30 08:10:06 PM PDT 24 |
| Finished | Jun 30 08:11:37 PM PDT 24 |
| Peak memory | 566028 kb |
| Host | smart-e2fa610f-d2e7-48cb-9462-e8620602407e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460662386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.460662386 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.4212652185 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 6535182442 ps |
| CPU time | 113.1 seconds |
| Started | Jun 30 08:10:03 PM PDT 24 |
| Finished | Jun 30 08:11:57 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-68ba41ab-0954-4deb-86d8-080e50bf01c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212652185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.4212652185 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.1244066386 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 55294695 ps |
| CPU time | 7.42 seconds |
| Started | Jun 30 08:10:05 PM PDT 24 |
| Finished | Jun 30 08:10:12 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-98b96752-f928-480b-b038-58a7696e8e54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244066386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays .1244066386 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.431880622 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 1565145447 ps |
| CPU time | 152.72 seconds |
| Started | Jun 30 08:10:24 PM PDT 24 |
| Finished | Jun 30 08:12:57 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-93ee3e1b-eaae-4e56-b8ba-78077bcf5a9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431880622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.431880622 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.1233176018 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 3673574510 ps |
| CPU time | 339.83 seconds |
| Started | Jun 30 08:10:23 PM PDT 24 |
| Finished | Jun 30 08:16:04 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-0e82a710-3961-4254-9278-98e215362443 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233176018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1233176018 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.1201536918 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 7948899701 ps |
| CPU time | 539.9 seconds |
| Started | Jun 30 08:10:21 PM PDT 24 |
| Finished | Jun 30 08:19:21 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-dd5116ea-f3c2-4c5a-aeb3-b797b5cb9703 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201536918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.1201536918 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3399764082 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 3464528131 ps |
| CPU time | 499.67 seconds |
| Started | Jun 30 08:10:23 PM PDT 24 |
| Finished | Jun 30 08:18:44 PM PDT 24 |
| Peak memory | 577452 kb |
| Host | smart-07bed13b-9081-470d-a9eb-f74e3518306c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399764082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.3399764082 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.3168087958 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 79119381 ps |
| CPU time | 7.85 seconds |
| Started | Jun 30 08:10:17 PM PDT 24 |
| Finished | Jun 30 08:10:25 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-416b1ea3-95b6-4d50-885d-887842657aa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168087958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3168087958 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.1238731370 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 899836911 ps |
| CPU time | 81.46 seconds |
| Started | Jun 30 08:25:04 PM PDT 24 |
| Finished | Jun 30 08:26:26 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-bd661bae-d04d-447d-a237-0cf755f7c982 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238731370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .1238731370 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.1143670647 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 65224713081 ps |
| CPU time | 1192.18 seconds |
| Started | Jun 30 08:25:05 PM PDT 24 |
| Finished | Jun 30 08:44:58 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-ef3dce9f-0692-4196-ac64-de33c007780c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143670647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.1143670647 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.3331797979 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 128325473 ps |
| CPU time | 8.52 seconds |
| Started | Jun 30 08:25:10 PM PDT 24 |
| Finished | Jun 30 08:25:19 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-31bcb4f8-83f7-41cc-9236-cc5b658f9a6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331797979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.3331797979 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.2496695546 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 566671131 ps |
| CPU time | 52.63 seconds |
| Started | Jun 30 08:25:03 PM PDT 24 |
| Finished | Jun 30 08:25:56 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-fcc6781d-ad31-4120-aa54-b2c7888d77f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496695546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.2496695546 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.4104378052 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 2124262979 ps |
| CPU time | 92.87 seconds |
| Started | Jun 30 08:25:02 PM PDT 24 |
| Finished | Jun 30 08:26:35 PM PDT 24 |
| Peak memory | 575152 kb |
| Host | smart-8a771bb1-db02-4a98-bae1-b086e24de71a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104378052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.4104378052 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.1292156914 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 35455045690 ps |
| CPU time | 389.1 seconds |
| Started | Jun 30 08:25:03 PM PDT 24 |
| Finished | Jun 30 08:31:33 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-b10abc5b-ee53-47a6-b267-267d6c3f018d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292156914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.1292156914 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.1155517011 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 44609074501 ps |
| CPU time | 786.36 seconds |
| Started | Jun 30 08:25:03 PM PDT 24 |
| Finished | Jun 30 08:38:10 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-f80df56a-a71c-4ab6-8ab9-49d7ebefa5b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155517011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.1155517011 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.921014551 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 267592718 ps |
| CPU time | 28.74 seconds |
| Started | Jun 30 08:25:03 PM PDT 24 |
| Finished | Jun 30 08:25:32 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-cbf90a0e-203e-4afc-b91b-2f17658f92cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921014551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_dela ys.921014551 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.4060852537 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 516940551 ps |
| CPU time | 42.17 seconds |
| Started | Jun 30 08:25:04 PM PDT 24 |
| Finished | Jun 30 08:25:47 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-07973122-0751-4917-8bcb-e3d09c8c0b0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060852537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.4060852537 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.416851794 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 228699187 ps |
| CPU time | 10.4 seconds |
| Started | Jun 30 08:24:56 PM PDT 24 |
| Finished | Jun 30 08:25:07 PM PDT 24 |
| Peak memory | 565948 kb |
| Host | smart-5790b94d-53f2-4058-a3ed-a0747c276861 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416851794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.416851794 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.2083413625 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 7929939135 ps |
| CPU time | 81.19 seconds |
| Started | Jun 30 08:25:02 PM PDT 24 |
| Finished | Jun 30 08:26:24 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-3a3e20df-6635-4621-9f7c-c70ee0674ef5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083413625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.2083413625 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.81436362 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 5329189763 ps |
| CPU time | 87.64 seconds |
| Started | Jun 30 08:25:03 PM PDT 24 |
| Finished | Jun 30 08:26:32 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-403a23c3-b90c-48d8-8762-bb71a550fff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81436362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.81436362 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1650859797 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 48763365 ps |
| CPU time | 6.45 seconds |
| Started | Jun 30 08:24:57 PM PDT 24 |
| Finished | Jun 30 08:25:04 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-8ab00d02-8b91-4d92-839f-8434fefdc093 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650859797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.1650859797 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.414069303 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 389149099 ps |
| CPU time | 40.9 seconds |
| Started | Jun 30 08:25:14 PM PDT 24 |
| Finished | Jun 30 08:25:56 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-caf9b062-db0d-4878-ab8e-df24703d53cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414069303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.414069303 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.3095230777 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 2444875130 ps |
| CPU time | 220.39 seconds |
| Started | Jun 30 08:25:10 PM PDT 24 |
| Finished | Jun 30 08:28:51 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-e06134d2-2812-414d-99c5-a879e4b4fb5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095230777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.3095230777 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3800509137 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 13292150298 ps |
| CPU time | 654 seconds |
| Started | Jun 30 08:25:14 PM PDT 24 |
| Finished | Jun 30 08:36:09 PM PDT 24 |
| Peak memory | 576412 kb |
| Host | smart-71a8655f-377d-4e73-9d64-21e6b8eafc18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800509137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.3800509137 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.4007282858 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 215361818 ps |
| CPU time | 53.93 seconds |
| Started | Jun 30 08:25:11 PM PDT 24 |
| Finished | Jun 30 08:26:05 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-b6af537f-1168-44e0-b4ba-ab8061eb9cb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007282858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.4007282858 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.3354400373 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 632705771 ps |
| CPU time | 32.32 seconds |
| Started | Jun 30 08:25:10 PM PDT 24 |
| Finished | Jun 30 08:25:43 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-e398704b-67d9-4ed4-ad24-93b103d48729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354400373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.3354400373 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.1989047932 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 1034511010 ps |
| CPU time | 77.88 seconds |
| Started | Jun 30 08:25:19 PM PDT 24 |
| Finished | Jun 30 08:26:37 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-d4885922-93bc-4dc8-b54a-44b6179e7d89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989047932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .1989047932 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.499807031 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 22460100099 ps |
| CPU time | 435.66 seconds |
| Started | Jun 30 08:25:18 PM PDT 24 |
| Finished | Jun 30 08:32:34 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-229c20cb-4933-482b-9904-df9284566125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499807031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_d evice_slow_rsp.499807031 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.3101025618 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 637329872 ps |
| CPU time | 29.29 seconds |
| Started | Jun 30 08:25:17 PM PDT 24 |
| Finished | Jun 30 08:25:46 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-680b1d53-842f-4d46-9c99-52f398d43d51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101025618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.3101025618 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.3707015710 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 371490376 ps |
| CPU time | 15.86 seconds |
| Started | Jun 30 08:25:19 PM PDT 24 |
| Finished | Jun 30 08:25:35 PM PDT 24 |
| Peak memory | 573804 kb |
| Host | smart-194db5f0-664b-47b7-98aa-c0b79f4970fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707015710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.3707015710 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.1511378204 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 1027875582 ps |
| CPU time | 36.09 seconds |
| Started | Jun 30 08:25:09 PM PDT 24 |
| Finished | Jun 30 08:25:45 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-55fc1274-4388-4257-b4b0-badba59165a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511378204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.1511378204 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.492453115 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 24143018578 ps |
| CPU time | 257.82 seconds |
| Started | Jun 30 08:25:10 PM PDT 24 |
| Finished | Jun 30 08:29:28 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-a3825daf-0cb3-45a4-9e4e-739ed6077d47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492453115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.492453115 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.629919405 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 22171074296 ps |
| CPU time | 390.71 seconds |
| Started | Jun 30 08:25:11 PM PDT 24 |
| Finished | Jun 30 08:31:42 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-4bdcd3ba-7aff-4673-b47a-1d13f9a8befe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629919405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.629919405 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.50685166 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 432906723 ps |
| CPU time | 36.78 seconds |
| Started | Jun 30 08:25:15 PM PDT 24 |
| Finished | Jun 30 08:25:52 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-c0e5106e-94b5-4a73-8ef7-90a23b4d10e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50685166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_delay s.50685166 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.3953916329 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 265187544 ps |
| CPU time | 21.65 seconds |
| Started | Jun 30 08:25:18 PM PDT 24 |
| Finished | Jun 30 08:25:40 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-6f54cd80-b790-40c3-9c18-9c5084723e64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953916329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.3953916329 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.1266623974 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 158285733 ps |
| CPU time | 8.03 seconds |
| Started | Jun 30 08:25:11 PM PDT 24 |
| Finished | Jun 30 08:25:19 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-54ce3f24-4f33-4021-b1d7-dc8f881d3619 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266623974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.1266623974 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.3057431482 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 6054029205 ps |
| CPU time | 62.9 seconds |
| Started | Jun 30 08:25:10 PM PDT 24 |
| Finished | Jun 30 08:26:14 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-58a70d7d-3aee-444b-a724-e59d753b9023 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057431482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.3057431482 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.984434027 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 5051812892 ps |
| CPU time | 89.48 seconds |
| Started | Jun 30 08:25:09 PM PDT 24 |
| Finished | Jun 30 08:26:39 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-93e3a1de-71f5-4d05-83e7-a5d7dfb082bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984434027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.984434027 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.945883620 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 42081483 ps |
| CPU time | 6.88 seconds |
| Started | Jun 30 08:25:14 PM PDT 24 |
| Finished | Jun 30 08:25:21 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-a1912655-a285-48c7-ba5f-77a6ab5aa0fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945883620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delays .945883620 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.936222669 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 7529411938 ps |
| CPU time | 298.29 seconds |
| Started | Jun 30 08:25:19 PM PDT 24 |
| Finished | Jun 30 08:30:18 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-8c0d7ac3-32b9-44f4-b4e0-b89ebf818686 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936222669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.936222669 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.2611844715 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 10207795874 ps |
| CPU time | 382.1 seconds |
| Started | Jun 30 08:25:18 PM PDT 24 |
| Finished | Jun 30 08:31:41 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-6feb8dd0-d548-44b3-bf69-6e90a614a4f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611844715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.2611844715 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.1934839725 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 8919632648 ps |
| CPU time | 448.35 seconds |
| Started | Jun 30 08:25:19 PM PDT 24 |
| Finished | Jun 30 08:32:48 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-e37468fa-0aec-472c-9ed5-b2e8a08ae13a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934839725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.1934839725 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.3880529759 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 486515764 ps |
| CPU time | 145.06 seconds |
| Started | Jun 30 08:25:17 PM PDT 24 |
| Finished | Jun 30 08:27:42 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-095a7a43-581d-43a3-b9e4-e119263ec113 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880529759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.3880529759 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.4213584817 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 220103294 ps |
| CPU time | 25.3 seconds |
| Started | Jun 30 08:25:19 PM PDT 24 |
| Finished | Jun 30 08:25:45 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-94624d63-2e10-4fbd-a345-ee3c402a5665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213584817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.4213584817 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.2754422836 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 554419014 ps |
| CPU time | 48.29 seconds |
| Started | Jun 30 08:25:25 PM PDT 24 |
| Finished | Jun 30 08:26:14 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-4dcf0f1c-6537-42ad-9acc-836cca35ea8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754422836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .2754422836 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1647541860 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 3056313847 ps |
| CPU time | 59.53 seconds |
| Started | Jun 30 08:25:24 PM PDT 24 |
| Finished | Jun 30 08:26:24 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-49544326-0440-4f7a-b4f3-e17f63446c49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647541860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.1647541860 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3907456522 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 42656161 ps |
| CPU time | 7.12 seconds |
| Started | Jun 30 08:25:32 PM PDT 24 |
| Finished | Jun 30 08:25:39 PM PDT 24 |
| Peak memory | 565988 kb |
| Host | smart-8571e59c-59d4-4486-8348-60a5dbae6788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907456522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.3907456522 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.2545835371 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 2603940454 ps |
| CPU time | 99.75 seconds |
| Started | Jun 30 08:25:29 PM PDT 24 |
| Finished | Jun 30 08:27:09 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-c35c4e63-f879-4c9b-a76b-281c1d6941f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545835371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.2545835371 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.388687066 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 341490068 ps |
| CPU time | 32.35 seconds |
| Started | Jun 30 08:25:26 PM PDT 24 |
| Finished | Jun 30 08:25:58 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-06311673-d24f-411e-a200-bef5e8f16975 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388687066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.388687066 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.2630877539 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 118028038672 ps |
| CPU time | 1233.56 seconds |
| Started | Jun 30 08:25:29 PM PDT 24 |
| Finished | Jun 30 08:46:03 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-b83714f3-28f6-4b99-8cc1-2f3825778a6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630877539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.2630877539 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.1156178750 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 9651555466 ps |
| CPU time | 177.88 seconds |
| Started | Jun 30 08:25:29 PM PDT 24 |
| Finished | Jun 30 08:28:27 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-8dfbd78d-e89d-40d5-bad5-e89d4eb52341 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156178750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.1156178750 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.525008878 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 500315742 ps |
| CPU time | 42.9 seconds |
| Started | Jun 30 08:25:26 PM PDT 24 |
| Finished | Jun 30 08:26:09 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-5f2d7135-c0e4-4fce-b22c-30d7e7ff5b22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525008878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_dela ys.525008878 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.958964830 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 514624389 ps |
| CPU time | 43 seconds |
| Started | Jun 30 08:25:25 PM PDT 24 |
| Finished | Jun 30 08:26:08 PM PDT 24 |
| Peak memory | 575180 kb |
| Host | smart-deba63b6-0855-4920-9f98-b91e9403879d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958964830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.958964830 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.2682835444 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 39391012 ps |
| CPU time | 6.52 seconds |
| Started | Jun 30 08:25:17 PM PDT 24 |
| Finished | Jun 30 08:25:24 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-6664efdb-a682-4f36-8262-fb44c7ac723d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682835444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.2682835444 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.2198495399 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 6074507193 ps |
| CPU time | 62.56 seconds |
| Started | Jun 30 08:25:19 PM PDT 24 |
| Finished | Jun 30 08:26:22 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-2d0069d1-ca5b-4972-b770-f185be0f49c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198495399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.2198495399 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.1070963488 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 5616646063 ps |
| CPU time | 102.99 seconds |
| Started | Jun 30 08:25:25 PM PDT 24 |
| Finished | Jun 30 08:27:09 PM PDT 24 |
| Peak memory | 565972 kb |
| Host | smart-4ccd1afc-6d57-48f4-b4f7-dfead5199377 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070963488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.1070963488 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.3686667815 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 51384856 ps |
| CPU time | 6.78 seconds |
| Started | Jun 30 08:25:18 PM PDT 24 |
| Finished | Jun 30 08:25:26 PM PDT 24 |
| Peak memory | 566060 kb |
| Host | smart-90db45d5-6b3d-4496-90c7-421b2a82a46e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686667815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.3686667815 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.4203060631 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 2410232341 ps |
| CPU time | 101.25 seconds |
| Started | Jun 30 08:25:33 PM PDT 24 |
| Finished | Jun 30 08:27:15 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-523e9bc5-8fc6-450e-bb9d-d582c72fe10f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203060631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.4203060631 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.3842822177 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 2219597543 ps |
| CPU time | 168.34 seconds |
| Started | Jun 30 08:25:33 PM PDT 24 |
| Finished | Jun 30 08:28:22 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-f9edc8cf-8665-429e-a0eb-0e62b0fa6e4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842822177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.3842822177 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.3553141623 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 5109577738 ps |
| CPU time | 373.38 seconds |
| Started | Jun 30 08:25:33 PM PDT 24 |
| Finished | Jun 30 08:31:47 PM PDT 24 |
| Peak memory | 576452 kb |
| Host | smart-3eb7254e-3ab2-42f7-a44a-e45029b9e5ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553141623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.3553141623 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.1159252589 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 178955817 ps |
| CPU time | 22.4 seconds |
| Started | Jun 30 08:25:31 PM PDT 24 |
| Finished | Jun 30 08:25:54 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-f39ebb6e-c4a6-4339-bd07-4078a4a5edb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159252589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.1159252589 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.1486643722 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 562389864 ps |
| CPU time | 53.17 seconds |
| Started | Jun 30 08:25:39 PM PDT 24 |
| Finished | Jun 30 08:26:33 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-ead42b42-05a3-4458-af50-a07bc1b9e53d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486643722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .1486643722 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2851847811 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 55693996370 ps |
| CPU time | 1036.86 seconds |
| Started | Jun 30 08:25:40 PM PDT 24 |
| Finished | Jun 30 08:42:57 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-f7c7df86-60e5-48b7-a203-0bcc4d810256 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851847811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.2851847811 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.2863521000 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 1013019836 ps |
| CPU time | 43.09 seconds |
| Started | Jun 30 08:25:39 PM PDT 24 |
| Finished | Jun 30 08:26:22 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-7b5377ac-c4b6-4e73-8cc9-92122c2f7453 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863521000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.2863521000 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.2736717063 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 2598973480 ps |
| CPU time | 93.65 seconds |
| Started | Jun 30 08:25:39 PM PDT 24 |
| Finished | Jun 30 08:27:13 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-83231b3d-8b33-4084-858f-e0f2effcf176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736717063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.2736717063 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.191135884 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 259430361 ps |
| CPU time | 12.49 seconds |
| Started | Jun 30 08:25:38 PM PDT 24 |
| Finished | Jun 30 08:25:51 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-c5dc973a-40fd-412b-b27d-b93495b216fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191135884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.191135884 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.288335487 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 22807336714 ps |
| CPU time | 229.86 seconds |
| Started | Jun 30 08:25:47 PM PDT 24 |
| Finished | Jun 30 08:29:37 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-4094268d-a8e9-4412-aede-cf3d56a12f8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288335487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.288335487 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.1657422960 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 35058866252 ps |
| CPU time | 598.42 seconds |
| Started | Jun 30 08:25:41 PM PDT 24 |
| Finished | Jun 30 08:35:40 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-91351279-b1d7-45e8-b97a-d541c2647903 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657422960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.1657422960 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.1142623500 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 68796274 ps |
| CPU time | 9.61 seconds |
| Started | Jun 30 08:25:38 PM PDT 24 |
| Finished | Jun 30 08:25:48 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-408c39ba-9786-425c-941d-5da006726d4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142623500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.1142623500 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.1165936883 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 470442807 ps |
| CPU time | 38.67 seconds |
| Started | Jun 30 08:25:37 PM PDT 24 |
| Finished | Jun 30 08:26:16 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-373b95b2-a308-40f8-98bb-a9eee9615a22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165936883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.1165936883 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.2216181443 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 184656590 ps |
| CPU time | 8.71 seconds |
| Started | Jun 30 08:25:32 PM PDT 24 |
| Finished | Jun 30 08:25:41 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-4fdc1897-3239-429e-8ea5-42e86682a586 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216181443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.2216181443 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.1505122407 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 8530602368 ps |
| CPU time | 96.4 seconds |
| Started | Jun 30 08:25:38 PM PDT 24 |
| Finished | Jun 30 08:27:15 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-0fa8cf9d-e9e4-48e4-af99-bb91fb880775 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505122407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.1505122407 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.3273083795 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 6313494840 ps |
| CPU time | 109.98 seconds |
| Started | Jun 30 08:25:38 PM PDT 24 |
| Finished | Jun 30 08:27:29 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-dd697093-b41b-47c1-bf26-c5d5b628847a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273083795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.3273083795 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.490781694 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 45227771 ps |
| CPU time | 6.57 seconds |
| Started | Jun 30 08:25:31 PM PDT 24 |
| Finished | Jun 30 08:25:38 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-078dd6ba-fcd6-4937-92ed-df93276de27e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490781694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delays .490781694 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.3338531114 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 16255647503 ps |
| CPU time | 613.59 seconds |
| Started | Jun 30 08:25:47 PM PDT 24 |
| Finished | Jun 30 08:36:01 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-b95ca402-3121-4786-aa6c-7cf829a8c95d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338531114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.3338531114 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.1712340231 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 2340373183 ps |
| CPU time | 96.27 seconds |
| Started | Jun 30 08:25:47 PM PDT 24 |
| Finished | Jun 30 08:27:24 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-5a719b78-9759-4a44-9d05-fb2ebaebfc6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712340231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.1712340231 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.2121298822 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 1017517372 ps |
| CPU time | 257.32 seconds |
| Started | Jun 30 08:25:47 PM PDT 24 |
| Finished | Jun 30 08:30:05 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-ab7c49de-65d9-4a24-8f92-8ea8c41324f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121298822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.2121298822 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.190057485 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 11761881146 ps |
| CPU time | 509.19 seconds |
| Started | Jun 30 08:25:46 PM PDT 24 |
| Finished | Jun 30 08:34:16 PM PDT 24 |
| Peak memory | 576440 kb |
| Host | smart-78f69447-bedc-4f6d-8e21-19c73f4000fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190057485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_reset_error.190057485 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.926603378 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 752150708 ps |
| CPU time | 35.91 seconds |
| Started | Jun 30 08:25:42 PM PDT 24 |
| Finished | Jun 30 08:26:18 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-5d75af01-914e-4aaa-ae33-c21340e0f321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926603378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.926603378 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.3045275496 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 978574620 ps |
| CPU time | 87.36 seconds |
| Started | Jun 30 08:25:45 PM PDT 24 |
| Finished | Jun 30 08:27:13 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-aae93fe7-5bfd-4cd1-8608-b5db6f8c6824 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045275496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .3045275496 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.2728274848 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 42764878875 ps |
| CPU time | 763.24 seconds |
| Started | Jun 30 08:25:46 PM PDT 24 |
| Finished | Jun 30 08:38:30 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-ff673340-327e-4644-bebc-49905db1a946 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728274848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.2728274848 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3706722185 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 104764693 ps |
| CPU time | 13.74 seconds |
| Started | Jun 30 08:25:46 PM PDT 24 |
| Finished | Jun 30 08:26:00 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-3d5ccbb0-0542-49f1-9465-2fef3c95cab3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706722185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.3706722185 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.3212751205 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 157350773 ps |
| CPU time | 16.85 seconds |
| Started | Jun 30 08:25:49 PM PDT 24 |
| Finished | Jun 30 08:26:07 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-855b12f8-efeb-4514-b6d4-25edfd05952a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212751205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.3212751205 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.4116699271 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 210414286 ps |
| CPU time | 22.67 seconds |
| Started | Jun 30 08:25:46 PM PDT 24 |
| Finished | Jun 30 08:26:09 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-edfa1038-24f1-481a-afc7-5f9fc533fdd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116699271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.4116699271 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.2860375609 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 12989585676 ps |
| CPU time | 136.11 seconds |
| Started | Jun 30 08:25:47 PM PDT 24 |
| Finished | Jun 30 08:28:04 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-8a8f9a6b-1eaa-4f03-bf54-9ebda734d8a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860375609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.2860375609 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.1386827561 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 67264079263 ps |
| CPU time | 1108.87 seconds |
| Started | Jun 30 08:25:49 PM PDT 24 |
| Finished | Jun 30 08:44:19 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-7638695f-8b99-4b2c-abcd-92a9bfcbbb61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386827561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.1386827561 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.2354849804 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 312905538 ps |
| CPU time | 30.81 seconds |
| Started | Jun 30 08:25:46 PM PDT 24 |
| Finished | Jun 30 08:26:17 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-c766f2cc-744c-4a6d-a842-13e4064937e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354849804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.2354849804 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.1259128704 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 2464009703 ps |
| CPU time | 74.09 seconds |
| Started | Jun 30 08:25:51 PM PDT 24 |
| Finished | Jun 30 08:27:05 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-079377eb-6bca-48da-ae09-bb04a131cf1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259128704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.1259128704 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.117143449 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 173540652 ps |
| CPU time | 8.31 seconds |
| Started | Jun 30 08:25:49 PM PDT 24 |
| Finished | Jun 30 08:25:58 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-8eb8c4d9-b902-46f7-89b0-eddf29fb220d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117143449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.117143449 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.2845877572 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 8290707314 ps |
| CPU time | 89.63 seconds |
| Started | Jun 30 08:25:48 PM PDT 24 |
| Finished | Jun 30 08:27:18 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-53c1f999-7f4c-4300-954f-fc322b6ea3d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845877572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.2845877572 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.980378266 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 5018797633 ps |
| CPU time | 82.34 seconds |
| Started | Jun 30 08:25:51 PM PDT 24 |
| Finished | Jun 30 08:27:13 PM PDT 24 |
| Peak memory | 566028 kb |
| Host | smart-e22d5b45-6dcf-4adc-b5ed-e2d32c680c61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980378266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.980378266 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.2226302580 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 51544590 ps |
| CPU time | 7.1 seconds |
| Started | Jun 30 08:25:47 PM PDT 24 |
| Finished | Jun 30 08:25:55 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-f015816b-6e52-4df3-87c5-f10aa2bebf90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226302580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.2226302580 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.223432972 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 4744021780 ps |
| CPU time | 152.17 seconds |
| Started | Jun 30 08:25:56 PM PDT 24 |
| Finished | Jun 30 08:28:29 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-3a74f09a-4966-41e4-b13a-a92e4e63a79e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223432972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.223432972 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.2241511574 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 139006720 ps |
| CPU time | 37.81 seconds |
| Started | Jun 30 08:25:53 PM PDT 24 |
| Finished | Jun 30 08:26:31 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-47be3391-dc21-47ec-9684-ded5b0653c8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241511574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.2241511574 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3909523904 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 211175277 ps |
| CPU time | 84.64 seconds |
| Started | Jun 30 08:25:52 PM PDT 24 |
| Finished | Jun 30 08:27:17 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-514cb4db-797c-4646-986c-d64b2508d408 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909523904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.3909523904 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.2313152623 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 334535605 ps |
| CPU time | 19.89 seconds |
| Started | Jun 30 08:25:47 PM PDT 24 |
| Finished | Jun 30 08:26:08 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-f2fa6ab7-6d58-461e-807e-c5f1d5a9b2a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313152623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.2313152623 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.2791994633 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 1177153285 ps |
| CPU time | 47.41 seconds |
| Started | Jun 30 08:26:06 PM PDT 24 |
| Finished | Jun 30 08:26:54 PM PDT 24 |
| Peak memory | 575140 kb |
| Host | smart-6241a614-e352-4aa5-9c75-2551655453cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791994633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device .2791994633 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1985780323 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 112126262921 ps |
| CPU time | 1738.4 seconds |
| Started | Jun 30 08:26:05 PM PDT 24 |
| Finished | Jun 30 08:55:04 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-02768f5f-668c-4430-98e5-3d01d993b2a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985780323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.1985780323 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.2453803472 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 517507507 ps |
| CPU time | 25.66 seconds |
| Started | Jun 30 08:26:04 PM PDT 24 |
| Finished | Jun 30 08:26:31 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-2246d13e-8479-48d0-8dc2-37e037fd98ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453803472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.2453803472 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.1355420902 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 577193300 ps |
| CPU time | 21.37 seconds |
| Started | Jun 30 08:26:02 PM PDT 24 |
| Finished | Jun 30 08:26:24 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-cea4c119-830a-48f0-8243-cd55038c2bdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355420902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.1355420902 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.31510110 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 525522848 ps |
| CPU time | 22.53 seconds |
| Started | Jun 30 08:25:54 PM PDT 24 |
| Finished | Jun 30 08:26:17 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-461492b0-033a-4ade-a4a5-56ae65a14490 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31510110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.31510110 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.2405469326 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 95185828231 ps |
| CPU time | 995.36 seconds |
| Started | Jun 30 08:26:01 PM PDT 24 |
| Finished | Jun 30 08:42:37 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-48ae1de0-c9df-48d5-bfc5-baf302f8b99d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405469326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.2405469326 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.330335962 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 57317538967 ps |
| CPU time | 965.59 seconds |
| Started | Jun 30 08:26:03 PM PDT 24 |
| Finished | Jun 30 08:42:09 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-48340d79-a76c-4f4f-9bee-e9de91edd2fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330335962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.330335962 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.2807356236 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 586606848 ps |
| CPU time | 58.85 seconds |
| Started | Jun 30 08:26:04 PM PDT 24 |
| Finished | Jun 30 08:27:04 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-a6528482-a039-42e9-9ac5-927d8f01c525 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807356236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.2807356236 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.3484885946 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2101042289 ps |
| CPU time | 62.84 seconds |
| Started | Jun 30 08:26:03 PM PDT 24 |
| Finished | Jun 30 08:27:06 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-d5087b53-6f55-4f6c-bf2b-b63ad2bc99a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484885946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.3484885946 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.4186812411 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 137662946 ps |
| CPU time | 7.74 seconds |
| Started | Jun 30 08:25:54 PM PDT 24 |
| Finished | Jun 30 08:26:02 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-b236f746-94a8-46d1-8a23-c5fa739ca8a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186812411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.4186812411 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.3555976852 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 10207128585 ps |
| CPU time | 105.09 seconds |
| Started | Jun 30 08:25:56 PM PDT 24 |
| Finished | Jun 30 08:27:42 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-5987755a-8949-4550-8161-721af3219eb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555976852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.3555976852 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.461653300 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 3569149355 ps |
| CPU time | 63.16 seconds |
| Started | Jun 30 08:25:56 PM PDT 24 |
| Finished | Jun 30 08:27:00 PM PDT 24 |
| Peak memory | 565920 kb |
| Host | smart-f343a107-6b6b-4190-bf06-1b8e67394bac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461653300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.461653300 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.323679426 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 47977594 ps |
| CPU time | 7.44 seconds |
| Started | Jun 30 08:25:53 PM PDT 24 |
| Finished | Jun 30 08:26:01 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-508b0594-2137-48cc-b146-1d97fd1854d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323679426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delays .323679426 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.2402327871 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 209694347 ps |
| CPU time | 24.15 seconds |
| Started | Jun 30 08:26:05 PM PDT 24 |
| Finished | Jun 30 08:26:29 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-12988fbb-c785-4414-a486-31f7d41e2a7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402327871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.2402327871 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.1850218124 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 4547160039 ps |
| CPU time | 185.05 seconds |
| Started | Jun 30 08:26:01 PM PDT 24 |
| Finished | Jun 30 08:29:07 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-a6f987ff-fa8a-4424-9c0d-9e308c1b7cda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850218124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.1850218124 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.592511784 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 3691294974 ps |
| CPU time | 364.92 seconds |
| Started | Jun 30 08:26:03 PM PDT 24 |
| Finished | Jun 30 08:32:09 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-ed145315-4459-4c04-a1ce-9af50fb2c04d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592511784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_ with_rand_reset.592511784 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2294591316 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 3154106727 ps |
| CPU time | 434.3 seconds |
| Started | Jun 30 08:26:03 PM PDT 24 |
| Finished | Jun 30 08:33:18 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-e321f58a-b919-4fdf-94ae-c42eacb87b0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294591316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.2294591316 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.1913925215 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 861902192 ps |
| CPU time | 37.26 seconds |
| Started | Jun 30 08:26:03 PM PDT 24 |
| Finished | Jun 30 08:26:41 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-c10f1514-2e6b-459b-8d08-3fee51c6c5a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913925215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.1913925215 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.314897569 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 64420302 ps |
| CPU time | 7.28 seconds |
| Started | Jun 30 08:26:07 PM PDT 24 |
| Finished | Jun 30 08:26:14 PM PDT 24 |
| Peak memory | 565876 kb |
| Host | smart-af2f3205-3df8-44cb-b7df-6381f5bdddfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314897569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device. 314897569 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.812790636 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 40956738523 ps |
| CPU time | 673.11 seconds |
| Started | Jun 30 08:26:12 PM PDT 24 |
| Finished | Jun 30 08:37:25 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-09d2baac-96fa-42e5-b1f9-12af6cda3095 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812790636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_d evice_slow_rsp.812790636 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.139185980 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 1418598544 ps |
| CPU time | 53.35 seconds |
| Started | Jun 30 08:26:10 PM PDT 24 |
| Finished | Jun 30 08:27:04 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-0dab3b0c-1c87-49ee-9732-c9e6af10e218 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139185980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_addr .139185980 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.243106153 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 1127763713 ps |
| CPU time | 48.33 seconds |
| Started | Jun 30 08:26:13 PM PDT 24 |
| Finished | Jun 30 08:27:02 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-af97eab6-7dd6-437f-b6f8-6680a6256bfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243106153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.243106153 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.1004344120 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 137704288 ps |
| CPU time | 14.21 seconds |
| Started | Jun 30 08:26:06 PM PDT 24 |
| Finished | Jun 30 08:26:21 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-58e5bec5-f383-480f-92cd-ccba68a551ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004344120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.1004344120 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.1038527530 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 34751377169 ps |
| CPU time | 329.58 seconds |
| Started | Jun 30 08:26:07 PM PDT 24 |
| Finished | Jun 30 08:31:37 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-571463e8-dd08-48c1-8c33-0f6de19198de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038527530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.1038527530 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.3730224981 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 47222074856 ps |
| CPU time | 789.58 seconds |
| Started | Jun 30 08:26:11 PM PDT 24 |
| Finished | Jun 30 08:39:21 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-1d01bec2-7389-4ce4-83b7-5dfed57f57b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730224981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.3730224981 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.1860359809 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 278263885 ps |
| CPU time | 29.32 seconds |
| Started | Jun 30 08:26:12 PM PDT 24 |
| Finished | Jun 30 08:26:41 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-262a8d45-b7d1-49ed-8079-139dfc4218eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860359809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.1860359809 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.696585380 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 794770412 ps |
| CPU time | 26.71 seconds |
| Started | Jun 30 08:26:10 PM PDT 24 |
| Finished | Jun 30 08:26:37 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-c5e336ae-76d2-4d71-be43-e9f37ed57c18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696585380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.696585380 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.625880705 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 52734550 ps |
| CPU time | 6.93 seconds |
| Started | Jun 30 08:26:07 PM PDT 24 |
| Finished | Jun 30 08:26:14 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-4a6f7bfc-5586-47c2-8ece-0d66611e95ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625880705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.625880705 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.4132050200 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 8708522082 ps |
| CPU time | 92.52 seconds |
| Started | Jun 30 08:26:03 PM PDT 24 |
| Finished | Jun 30 08:27:36 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-59838a43-25dd-4443-b3af-760b0c7ebf96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132050200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.4132050200 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.3609933236 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 3306483750 ps |
| CPU time | 58.77 seconds |
| Started | Jun 30 08:26:06 PM PDT 24 |
| Finished | Jun 30 08:27:05 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-0ba70f64-0d33-4a75-b315-0258036a5dd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609933236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.3609933236 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.485357823 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 45752554 ps |
| CPU time | 6.4 seconds |
| Started | Jun 30 08:26:06 PM PDT 24 |
| Finished | Jun 30 08:26:13 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-a7afd951-a446-4c56-bac7-aca9217895f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485357823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays .485357823 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.1912564254 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 2363780566 ps |
| CPU time | 247.17 seconds |
| Started | Jun 30 08:26:13 PM PDT 24 |
| Finished | Jun 30 08:30:22 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-b9006f90-de37-4e94-9a10-694e0910fc6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912564254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.1912564254 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.2741180464 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 8147982404 ps |
| CPU time | 295.63 seconds |
| Started | Jun 30 08:26:23 PM PDT 24 |
| Finished | Jun 30 08:31:19 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-8264269c-6bbd-4150-a9a4-4036e0ebcf4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741180464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.2741180464 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.4205962904 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 629447523 ps |
| CPU time | 273.47 seconds |
| Started | Jun 30 08:26:10 PM PDT 24 |
| Finished | Jun 30 08:30:44 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-6cec255d-fd6a-45a7-90b3-34b50d9b07aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205962904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.4205962904 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.972272094 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 520967456 ps |
| CPU time | 176.21 seconds |
| Started | Jun 30 08:26:12 PM PDT 24 |
| Finished | Jun 30 08:29:09 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-6df9aaab-ce4e-475e-8003-6215ad8f84fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972272094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_reset_error.972272094 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.2887238983 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 201004360 ps |
| CPU time | 24.46 seconds |
| Started | Jun 30 08:26:12 PM PDT 24 |
| Finished | Jun 30 08:26:37 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-b8bcf764-fee2-4348-a992-c0b51c7a209d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887238983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.2887238983 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.4173596613 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 217402721 ps |
| CPU time | 17.58 seconds |
| Started | Jun 30 08:26:20 PM PDT 24 |
| Finished | Jun 30 08:26:38 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-a9b977bf-ec6f-4144-8444-0eec12817dfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173596613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .4173596613 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.1478099717 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 20998914009 ps |
| CPU time | 379.45 seconds |
| Started | Jun 30 08:26:19 PM PDT 24 |
| Finished | Jun 30 08:32:39 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-ede452dc-19bf-493f-8915-040323787062 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478099717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.1478099717 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.1659576126 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 50104752 ps |
| CPU time | 9.12 seconds |
| Started | Jun 30 08:26:19 PM PDT 24 |
| Finished | Jun 30 08:26:28 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-cdd54a68-e346-4187-a7bc-957e56adb5c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659576126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.1659576126 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.3598155920 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 807466946 ps |
| CPU time | 28.87 seconds |
| Started | Jun 30 08:26:19 PM PDT 24 |
| Finished | Jun 30 08:26:48 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-ea9ea706-0cce-49d1-91c4-2c7cd8df178f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598155920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.3598155920 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.2312243 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 143553784 ps |
| CPU time | 15.65 seconds |
| Started | Jun 30 08:26:15 PM PDT 24 |
| Finished | Jun 30 08:26:31 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-c007f815-229b-4845-9e84-32b17836b2a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.2312243 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.3849715880 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 88577909622 ps |
| CPU time | 945.47 seconds |
| Started | Jun 30 08:26:19 PM PDT 24 |
| Finished | Jun 30 08:42:05 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-43e11a3a-8358-428f-8a38-6c60716757c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849715880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.3849715880 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.2226090385 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 62419127327 ps |
| CPU time | 999.57 seconds |
| Started | Jun 30 08:26:27 PM PDT 24 |
| Finished | Jun 30 08:43:07 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-785e0a74-84c9-4451-8d6f-be9645e7605e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226090385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.2226090385 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.3661253567 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 458291440 ps |
| CPU time | 42.15 seconds |
| Started | Jun 30 08:26:21 PM PDT 24 |
| Finished | Jun 30 08:27:03 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-4cec09f2-5b37-4839-8440-f12a402b883c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661253567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.3661253567 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.746168197 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 939811764 ps |
| CPU time | 30.09 seconds |
| Started | Jun 30 08:26:26 PM PDT 24 |
| Finished | Jun 30 08:26:57 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-679f96f9-2a26-405b-bd5e-a743ffd08c7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746168197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.746168197 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.3344956256 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 43845452 ps |
| CPU time | 6.17 seconds |
| Started | Jun 30 08:26:11 PM PDT 24 |
| Finished | Jun 30 08:26:18 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-431d0f2b-c496-474d-9ea4-8985539c7e26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344956256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.3344956256 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.3543362548 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 8256190151 ps |
| CPU time | 90.9 seconds |
| Started | Jun 30 08:26:11 PM PDT 24 |
| Finished | Jun 30 08:27:43 PM PDT 24 |
| Peak memory | 566036 kb |
| Host | smart-a435d8ab-4a82-458a-b85e-bf6be168da6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543362548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.3543362548 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.3091281354 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 4105392010 ps |
| CPU time | 67.06 seconds |
| Started | Jun 30 08:26:14 PM PDT 24 |
| Finished | Jun 30 08:27:22 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-33b8c91b-bf1e-4215-9668-87ebaa07d426 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091281354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.3091281354 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.973252134 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 49513321 ps |
| CPU time | 7.21 seconds |
| Started | Jun 30 08:26:13 PM PDT 24 |
| Finished | Jun 30 08:26:22 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-8a4c4938-d9d2-4e48-91f5-ee63827e5add |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973252134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delays .973252134 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.2702863426 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 1605874396 ps |
| CPU time | 59.34 seconds |
| Started | Jun 30 08:26:26 PM PDT 24 |
| Finished | Jun 30 08:27:26 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-e6c8a9fe-7ada-4410-9b25-4cba97c6645e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702863426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.2702863426 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.87532426 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 7364245468 ps |
| CPU time | 267.33 seconds |
| Started | Jun 30 08:26:17 PM PDT 24 |
| Finished | Jun 30 08:30:44 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-592918fd-4672-4660-af2a-f48e8743b038 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87532426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.87532426 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2512597013 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 11985359802 ps |
| CPU time | 570.2 seconds |
| Started | Jun 30 08:26:18 PM PDT 24 |
| Finished | Jun 30 08:35:49 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-fc961acd-552b-44ff-8488-663c1bdbddd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512597013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.2512597013 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.2002388213 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 577689467 ps |
| CPU time | 172.1 seconds |
| Started | Jun 30 08:26:27 PM PDT 24 |
| Finished | Jun 30 08:29:20 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-a4aed049-d5c8-445b-8ef7-8d956d37c7f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002388213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.2002388213 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.1315628967 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 1160668780 ps |
| CPU time | 55.64 seconds |
| Started | Jun 30 08:26:20 PM PDT 24 |
| Finished | Jun 30 08:27:16 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-fee0a274-dbea-4a04-a534-9e06761af535 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315628967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.1315628967 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.2416517334 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 683618522 ps |
| CPU time | 33.1 seconds |
| Started | Jun 30 08:26:25 PM PDT 24 |
| Finished | Jun 30 08:26:58 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-f8aca8cc-e265-464b-843e-5fb89dc8474a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416517334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .2416517334 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2964346259 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 70283998614 ps |
| CPU time | 1269.25 seconds |
| Started | Jun 30 08:26:25 PM PDT 24 |
| Finished | Jun 30 08:47:35 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-b9d2a935-ab40-4235-80f1-8605237e2893 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964346259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.2964346259 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3197324188 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 723213300 ps |
| CPU time | 30.6 seconds |
| Started | Jun 30 08:26:28 PM PDT 24 |
| Finished | Jun 30 08:26:59 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-26bfe94c-ebc6-48c1-95b9-f8799edd678e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197324188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.3197324188 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.3405165148 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 2113790794 ps |
| CPU time | 69.83 seconds |
| Started | Jun 30 08:26:27 PM PDT 24 |
| Finished | Jun 30 08:27:38 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-a63bd68a-bbec-4bfe-9776-0891923347f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405165148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.3405165148 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.1487106899 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 120532017 ps |
| CPU time | 15.07 seconds |
| Started | Jun 30 08:26:21 PM PDT 24 |
| Finished | Jun 30 08:26:36 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-8490a9dd-d526-4039-80b3-5ae3a536b2b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487106899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.1487106899 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.3176989231 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 17455272111 ps |
| CPU time | 184.6 seconds |
| Started | Jun 30 08:26:27 PM PDT 24 |
| Finished | Jun 30 08:29:32 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-8f56865d-c7f6-4aa7-a887-5533b5dd0400 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176989231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.3176989231 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.215782656 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 40709662850 ps |
| CPU time | 722.89 seconds |
| Started | Jun 30 08:26:26 PM PDT 24 |
| Finished | Jun 30 08:38:29 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-317de97e-7ae2-4cd2-8a65-24e77f236cde |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215782656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.215782656 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.627664966 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 542794353 ps |
| CPU time | 47.59 seconds |
| Started | Jun 30 08:26:21 PM PDT 24 |
| Finished | Jun 30 08:27:09 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-5ff10f32-9593-4fac-99c9-442da5e896c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627664966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_dela ys.627664966 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.2018518892 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 423188070 ps |
| CPU time | 15.71 seconds |
| Started | Jun 30 08:26:26 PM PDT 24 |
| Finished | Jun 30 08:26:42 PM PDT 24 |
| Peak memory | 575188 kb |
| Host | smart-9d7a32a2-2031-43b1-acab-9218a5131c8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018518892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.2018518892 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.1858602491 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 48202630 ps |
| CPU time | 6.92 seconds |
| Started | Jun 30 08:26:18 PM PDT 24 |
| Finished | Jun 30 08:26:25 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-fd1d090a-cb44-4eb6-9db8-333f605b4351 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858602491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.1858602491 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.1036048010 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 9462630030 ps |
| CPU time | 102.55 seconds |
| Started | Jun 30 08:26:18 PM PDT 24 |
| Finished | Jun 30 08:28:00 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-82440a17-c1dd-47e2-aeb1-095fb25c5167 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036048010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.1036048010 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.2284655539 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 4293045167 ps |
| CPU time | 77.36 seconds |
| Started | Jun 30 08:26:18 PM PDT 24 |
| Finished | Jun 30 08:27:36 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-0df82715-68aa-4d7a-b441-ce33913f4fde |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284655539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.2284655539 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.4014596913 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 44475365 ps |
| CPU time | 6.62 seconds |
| Started | Jun 30 08:26:18 PM PDT 24 |
| Finished | Jun 30 08:26:25 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-4fb69d1d-a533-437c-a120-dfc5de8f22ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014596913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.4014596913 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.1461545125 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 1151801988 ps |
| CPU time | 47.47 seconds |
| Started | Jun 30 08:26:25 PM PDT 24 |
| Finished | Jun 30 08:27:13 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-df72de7d-c24c-4650-ac3d-207a0fd43f2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461545125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.1461545125 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.4087746844 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 1906766623 ps |
| CPU time | 53.47 seconds |
| Started | Jun 30 08:26:32 PM PDT 24 |
| Finished | Jun 30 08:27:26 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-90bf8351-80b0-4685-8028-3417a81326cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087746844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.4087746844 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.1606919349 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 2587639192 ps |
| CPU time | 392.98 seconds |
| Started | Jun 30 08:26:27 PM PDT 24 |
| Finished | Jun 30 08:33:00 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-270b5eb3-43c0-4fee-ab00-f6182e84deda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606919349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.1606919349 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.668505859 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 7033333 ps |
| CPU time | 16.59 seconds |
| Started | Jun 30 08:26:33 PM PDT 24 |
| Finished | Jun 30 08:26:51 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-7d67d20f-f24b-48e9-b5b4-db9a7def17c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668505859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_reset_error.668505859 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.2185235923 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 203396507 ps |
| CPU time | 30.34 seconds |
| Started | Jun 30 08:26:28 PM PDT 24 |
| Finished | Jun 30 08:26:58 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-c64dd745-c233-407b-be48-62fb5707288e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185235923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.2185235923 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.3094553367 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 772336213 ps |
| CPU time | 66.25 seconds |
| Started | Jun 30 08:26:37 PM PDT 24 |
| Finished | Jun 30 08:27:44 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-ef9e681e-6f66-4f4c-b016-e167f7da3c83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094553367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .3094553367 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.2330307485 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 2741338806 ps |
| CPU time | 50.71 seconds |
| Started | Jun 30 08:26:39 PM PDT 24 |
| Finished | Jun 30 08:27:30 PM PDT 24 |
| Peak memory | 566012 kb |
| Host | smart-b903a5d1-65b4-45bb-913e-5d5145c8aff6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330307485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.2330307485 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.2917237151 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 469106879 ps |
| CPU time | 21.12 seconds |
| Started | Jun 30 08:26:39 PM PDT 24 |
| Finished | Jun 30 08:27:00 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-10973af6-a9a6-4286-9175-e84976f1a8b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917237151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.2917237151 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.644286588 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 2346136147 ps |
| CPU time | 85.93 seconds |
| Started | Jun 30 08:26:38 PM PDT 24 |
| Finished | Jun 30 08:28:04 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-2ed1aa9e-b157-4d23-934f-d9aad7b21a33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644286588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.644286588 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.3468216799 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 1245456832 ps |
| CPU time | 49.46 seconds |
| Started | Jun 30 08:26:31 PM PDT 24 |
| Finished | Jun 30 08:27:21 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-24c2194b-5838-4a3f-8cd3-72617c4728d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468216799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.3468216799 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.247377459 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 58444644804 ps |
| CPU time | 638.56 seconds |
| Started | Jun 30 08:26:40 PM PDT 24 |
| Finished | Jun 30 08:37:19 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-4c7c6737-88bc-41ad-83be-fbc3603597f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247377459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.247377459 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.543247096 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 33027652024 ps |
| CPU time | 573.91 seconds |
| Started | Jun 30 08:26:37 PM PDT 24 |
| Finished | Jun 30 08:36:12 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-afee3c3e-10ba-42b0-a09f-2ca42975dca5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543247096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.543247096 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.4086764707 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 194810677 ps |
| CPU time | 20.79 seconds |
| Started | Jun 30 08:26:38 PM PDT 24 |
| Finished | Jun 30 08:26:59 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-5ab0c31b-463f-4a8f-a240-050b26e5ba89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086764707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.4086764707 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.2219424290 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 176269973 ps |
| CPU time | 16.49 seconds |
| Started | Jun 30 08:26:37 PM PDT 24 |
| Finished | Jun 30 08:26:54 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-548daf4d-dfb4-49ee-8fea-112975bde72e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219424290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.2219424290 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.3152647384 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 44884342 ps |
| CPU time | 6.43 seconds |
| Started | Jun 30 08:26:34 PM PDT 24 |
| Finished | Jun 30 08:26:41 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-7d175743-b220-401e-8d73-0d48393d6b18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152647384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.3152647384 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.1498708783 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 8631735147 ps |
| CPU time | 96.23 seconds |
| Started | Jun 30 08:26:31 PM PDT 24 |
| Finished | Jun 30 08:28:08 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-dd178fb5-9f84-4df0-a9e6-4dcb3e112506 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498708783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.1498708783 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.2980979637 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 4084256760 ps |
| CPU time | 68.73 seconds |
| Started | Jun 30 08:26:32 PM PDT 24 |
| Finished | Jun 30 08:27:41 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-5fe829dd-c844-4eee-8764-9b193ef9d884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980979637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.2980979637 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.1745745424 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 54200778 ps |
| CPU time | 7.77 seconds |
| Started | Jun 30 08:26:31 PM PDT 24 |
| Finished | Jun 30 08:26:39 PM PDT 24 |
| Peak memory | 565912 kb |
| Host | smart-e723607b-5448-4544-b466-bec29a234b13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745745424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.1745745424 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.2549603820 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 10079905889 ps |
| CPU time | 456.3 seconds |
| Started | Jun 30 08:26:36 PM PDT 24 |
| Finished | Jun 30 08:34:13 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-c407eabb-6e02-4c6b-9b63-b35eb76cc679 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549603820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.2549603820 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.2917770585 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 531353011 ps |
| CPU time | 59.25 seconds |
| Started | Jun 30 08:26:39 PM PDT 24 |
| Finished | Jun 30 08:27:38 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-1baa80ac-af45-459f-9915-d8d8aa587ca6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917770585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.2917770585 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1669528850 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 5251822073 ps |
| CPU time | 763.35 seconds |
| Started | Jun 30 08:26:36 PM PDT 24 |
| Finished | Jun 30 08:39:20 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-87a9475c-a9b0-41cf-83c4-209606034ad6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669528850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.1669528850 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.3172968717 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 26198099 ps |
| CPU time | 44.93 seconds |
| Started | Jun 30 08:26:45 PM PDT 24 |
| Finished | Jun 30 08:27:30 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-135f1820-22c5-4cff-9e16-c26d2f005008 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172968717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.3172968717 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.981226080 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 260271710 ps |
| CPU time | 14.55 seconds |
| Started | Jun 30 08:26:37 PM PDT 24 |
| Finished | Jun 30 08:26:52 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-6f563273-73a1-49df-a367-7f98bdde53bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981226080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.981226080 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.1875336090 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 4606183215 ps |
| CPU time | 361.76 seconds |
| Started | Jun 30 08:10:46 PM PDT 24 |
| Finished | Jun 30 08:16:49 PM PDT 24 |
| Peak memory | 596876 kb |
| Host | smart-4d88f257-8792-45ad-bd61-5dd793419b1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875336090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.1875336090 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.3593940153 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 17887252086 ps |
| CPU time | 1978.77 seconds |
| Started | Jun 30 08:10:23 PM PDT 24 |
| Finished | Jun 30 08:43:22 PM PDT 24 |
| Peak memory | 591836 kb |
| Host | smart-5bd1f725-4217-48cd-b9d5-7ef29e955a14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593940153 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.3593940153 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.2415658393 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 935563227 ps |
| CPU time | 73.98 seconds |
| Started | Jun 30 08:10:35 PM PDT 24 |
| Finished | Jun 30 08:11:50 PM PDT 24 |
| Peak memory | 575200 kb |
| Host | smart-864f900d-8e55-483c-ad1d-66a9e1b8a6f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415658393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 2415658393 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.205603538 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 155378938003 ps |
| CPU time | 2823.27 seconds |
| Started | Jun 30 08:10:32 PM PDT 24 |
| Finished | Jun 30 08:57:37 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-3e4004e5-eb71-456c-931d-92cc3faa68f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205603538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_de vice_slow_rsp.205603538 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.1758288508 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 21600583 ps |
| CPU time | 5.81 seconds |
| Started | Jun 30 08:10:39 PM PDT 24 |
| Finished | Jun 30 08:10:46 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-79e63ab3-bbd2-49fc-9103-070e7b07bdee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758288508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .1758288508 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.1818855261 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 2554625927 ps |
| CPU time | 104.55 seconds |
| Started | Jun 30 08:10:41 PM PDT 24 |
| Finished | Jun 30 08:12:26 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-f183b7ae-d42a-44f8-82fa-f34ee1260bef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818855261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1818855261 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.3467703839 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 115785518 ps |
| CPU time | 15.31 seconds |
| Started | Jun 30 08:10:33 PM PDT 24 |
| Finished | Jun 30 08:10:49 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-4272f99a-673a-4aee-8c16-b367b0749ec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467703839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.3467703839 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.938733349 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 32873038627 ps |
| CPU time | 370.44 seconds |
| Started | Jun 30 08:10:33 PM PDT 24 |
| Finished | Jun 30 08:16:44 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-2601f0ea-b46f-41b3-af9b-9018b6de087b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938733349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.938733349 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.3252641693 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 34586003419 ps |
| CPU time | 663.55 seconds |
| Started | Jun 30 08:10:34 PM PDT 24 |
| Finished | Jun 30 08:21:38 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-b8c23b8e-1dfb-4c5c-93b0-fb7a4db6f975 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252641693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3252641693 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.783907340 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 334427240 ps |
| CPU time | 32.41 seconds |
| Started | Jun 30 08:10:36 PM PDT 24 |
| Finished | Jun 30 08:11:09 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-c7f0215d-17c8-4759-b0ea-1f4a8a8d52bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783907340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delay s.783907340 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.1732322708 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 2094050137 ps |
| CPU time | 71.06 seconds |
| Started | Jun 30 08:10:41 PM PDT 24 |
| Finished | Jun 30 08:11:53 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-d2a6de35-9c00-4053-bc7e-8fcd502797a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732322708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1732322708 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.2871292180 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 46954623 ps |
| CPU time | 6.41 seconds |
| Started | Jun 30 08:10:27 PM PDT 24 |
| Finished | Jun 30 08:10:34 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-21f10987-140e-4924-b343-4fbee69511da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871292180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2871292180 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.619649375 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 10160110615 ps |
| CPU time | 105.62 seconds |
| Started | Jun 30 08:10:29 PM PDT 24 |
| Finished | Jun 30 08:12:15 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-fb7bbb09-89b1-4695-9f9b-9a5e0b316597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619649375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.619649375 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.4285359609 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 5164017908 ps |
| CPU time | 90.56 seconds |
| Started | Jun 30 08:10:33 PM PDT 24 |
| Finished | Jun 30 08:12:04 PM PDT 24 |
| Peak memory | 565996 kb |
| Host | smart-0503d1a5-a22b-480c-8f67-cdaaf4d53d04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285359609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.4285359609 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.2241348705 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 45758010 ps |
| CPU time | 7.11 seconds |
| Started | Jun 30 08:10:30 PM PDT 24 |
| Finished | Jun 30 08:10:38 PM PDT 24 |
| Peak memory | 565960 kb |
| Host | smart-fa2b1130-05a1-4d6c-88e0-b2798d9b9d8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241348705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .2241348705 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.3276090160 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 2651393109 ps |
| CPU time | 263.79 seconds |
| Started | Jun 30 08:10:42 PM PDT 24 |
| Finished | Jun 30 08:15:06 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-fc2f884e-1121-4aae-8033-fd31e68b2edf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276090160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3276090160 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.788027230 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 1972816366 ps |
| CPU time | 188.95 seconds |
| Started | Jun 30 08:10:46 PM PDT 24 |
| Finished | Jun 30 08:13:55 PM PDT 24 |
| Peak memory | 574768 kb |
| Host | smart-53208518-1197-4770-8078-77ef37e0e73e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788027230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.788027230 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.3149760431 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 149672950 ps |
| CPU time | 82.47 seconds |
| Started | Jun 30 08:10:48 PM PDT 24 |
| Finished | Jun 30 08:12:11 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-27222f80-c3ae-4e2a-9ad5-9d3421837b46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149760431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.3149760431 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.4186619416 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 468812577 ps |
| CPU time | 208.66 seconds |
| Started | Jun 30 08:10:45 PM PDT 24 |
| Finished | Jun 30 08:14:15 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-b4e43ae5-32e9-478c-9a67-d1b19836d0f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186619416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.4186619416 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.1517558224 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 223808016 ps |
| CPU time | 27.66 seconds |
| Started | Jun 30 08:10:39 PM PDT 24 |
| Finished | Jun 30 08:11:07 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-de8e2a9e-2e19-40b3-b827-4323e4bf301f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517558224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1517558224 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.2600226181 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 1813218344 ps |
| CPU time | 76.3 seconds |
| Started | Jun 30 08:26:47 PM PDT 24 |
| Finished | Jun 30 08:28:04 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-fd4238fa-fea2-43f4-be6d-50bcb465eabf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600226181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .2600226181 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.1475680235 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 99408603198 ps |
| CPU time | 1760.18 seconds |
| Started | Jun 30 08:26:44 PM PDT 24 |
| Finished | Jun 30 08:56:05 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-71f24336-dd6f-4b38-8fcf-f585c6deb580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475680235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.1475680235 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.985814984 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 209238945 ps |
| CPU time | 26.92 seconds |
| Started | Jun 30 08:26:48 PM PDT 24 |
| Finished | Jun 30 08:27:15 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-f09d7cfb-647d-4b52-b92d-031e5abcae0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985814984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr .985814984 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.1267958506 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 187387908 ps |
| CPU time | 19.06 seconds |
| Started | Jun 30 08:26:46 PM PDT 24 |
| Finished | Jun 30 08:27:06 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-3cc28c84-67a3-44ab-8142-7168f5aa019a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267958506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.1267958506 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.1585420765 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 406099780 ps |
| CPU time | 39.64 seconds |
| Started | Jun 30 08:26:48 PM PDT 24 |
| Finished | Jun 30 08:27:28 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-ff5e391c-6b7c-4372-b066-50322cbdb95d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585420765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.1585420765 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.3932830343 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 57750695136 ps |
| CPU time | 593.99 seconds |
| Started | Jun 30 08:26:49 PM PDT 24 |
| Finished | Jun 30 08:36:44 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-5bd5b389-7605-4421-8977-295fdec5049b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932830343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.3932830343 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.2808045871 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 62850721478 ps |
| CPU time | 1086.98 seconds |
| Started | Jun 30 08:26:45 PM PDT 24 |
| Finished | Jun 30 08:44:53 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-21ac14ef-0cf1-4478-a42b-653adb42b8f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808045871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.2808045871 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.1385213558 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 596934813 ps |
| CPU time | 52.65 seconds |
| Started | Jun 30 08:26:47 PM PDT 24 |
| Finished | Jun 30 08:27:40 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-ac6bc15f-8d17-4861-974f-c05d65ce7df9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385213558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.1385213558 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.4075374260 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 130007908 ps |
| CPU time | 12.58 seconds |
| Started | Jun 30 08:26:47 PM PDT 24 |
| Finished | Jun 30 08:27:00 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-18ee1f8e-6f2f-4099-9df8-82a9ca59c8b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075374260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.4075374260 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.3443487466 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 237371969 ps |
| CPU time | 10.67 seconds |
| Started | Jun 30 08:26:47 PM PDT 24 |
| Finished | Jun 30 08:26:59 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-d94d7e66-997b-4525-aeda-2fd289ed5e0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443487466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.3443487466 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.3771296435 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 8752691508 ps |
| CPU time | 91.47 seconds |
| Started | Jun 30 08:26:47 PM PDT 24 |
| Finished | Jun 30 08:28:19 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-e4de08a0-c9d4-4600-b4cd-fc9f36a1f421 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771296435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.3771296435 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.15664657 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 5243176156 ps |
| CPU time | 93.83 seconds |
| Started | Jun 30 08:26:44 PM PDT 24 |
| Finished | Jun 30 08:28:19 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-921f12c3-6185-408a-bb88-2515c8037dcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15664657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.15664657 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.944778132 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 34771015 ps |
| CPU time | 6.13 seconds |
| Started | Jun 30 08:26:47 PM PDT 24 |
| Finished | Jun 30 08:26:54 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-2e4e8244-85f1-446a-a2b6-788e1147f982 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944778132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delays .944778132 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.2289320774 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 1861789021 ps |
| CPU time | 190.99 seconds |
| Started | Jun 30 08:26:53 PM PDT 24 |
| Finished | Jun 30 08:30:05 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-3491cb75-a2ec-48c1-9163-df538237dc75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289320774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.2289320774 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.810455123 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 8775611765 ps |
| CPU time | 324.07 seconds |
| Started | Jun 30 08:26:51 PM PDT 24 |
| Finished | Jun 30 08:32:15 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-64240407-bbbc-4281-8fa3-6eac8a910937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810455123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.810455123 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2155294817 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2091257291 ps |
| CPU time | 279.28 seconds |
| Started | Jun 30 08:26:54 PM PDT 24 |
| Finished | Jun 30 08:31:34 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-de1dfca1-1768-4291-80d4-e6769bba06d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155294817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.2155294817 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.1817338308 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 241733421 ps |
| CPU time | 92.77 seconds |
| Started | Jun 30 08:26:54 PM PDT 24 |
| Finished | Jun 30 08:28:27 PM PDT 24 |
| Peak memory | 577368 kb |
| Host | smart-180c594c-60e7-4e8a-aa8e-60002eb063f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817338308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.1817338308 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.795341348 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 255558404 ps |
| CPU time | 32 seconds |
| Started | Jun 30 08:26:44 PM PDT 24 |
| Finished | Jun 30 08:27:17 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-2bdb495f-914d-45a7-b4f8-aa28871cec25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795341348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.795341348 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.1676587156 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 15208067 ps |
| CPU time | 5.94 seconds |
| Started | Jun 30 08:27:01 PM PDT 24 |
| Finished | Jun 30 08:27:08 PM PDT 24 |
| Peak memory | 565848 kb |
| Host | smart-beb75436-a804-4f90-b503-d04deabbe14c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676587156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .1676587156 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3503583223 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 21113162327 ps |
| CPU time | 347.14 seconds |
| Started | Jun 30 08:27:03 PM PDT 24 |
| Finished | Jun 30 08:32:50 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-bcb36adb-df3a-40f4-9c79-47ea5aee383d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503583223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.3503583223 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1417521824 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 1051419690 ps |
| CPU time | 48.89 seconds |
| Started | Jun 30 08:27:00 PM PDT 24 |
| Finished | Jun 30 08:27:49 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-a9c39c63-65f5-49bf-b236-b24aa7b72123 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417521824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.1417521824 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.2104983165 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 1201888432 ps |
| CPU time | 44.31 seconds |
| Started | Jun 30 08:26:58 PM PDT 24 |
| Finished | Jun 30 08:27:42 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-6b5b253f-18f8-4389-9e94-ad5dbcd2de5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104983165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.2104983165 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.2478431066 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 323427135 ps |
| CPU time | 33.48 seconds |
| Started | Jun 30 08:26:58 PM PDT 24 |
| Finished | Jun 30 08:27:31 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-be7158dd-39b3-4a73-9de3-b689dfb81183 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478431066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.2478431066 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.2256222748 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 20837334193 ps |
| CPU time | 207.38 seconds |
| Started | Jun 30 08:27:02 PM PDT 24 |
| Finished | Jun 30 08:30:30 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-c4ddfa2f-38a4-44ed-b141-5d6ca3df71a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256222748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.2256222748 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.1075123334 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 68519909791 ps |
| CPU time | 1178.35 seconds |
| Started | Jun 30 08:26:59 PM PDT 24 |
| Finished | Jun 30 08:46:38 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-e6d94cc3-27ae-47c4-98d3-456fa2f468e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075123334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.1075123334 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2739462311 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 588141426 ps |
| CPU time | 51.66 seconds |
| Started | Jun 30 08:27:03 PM PDT 24 |
| Finished | Jun 30 08:27:55 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-02240c81-e1ac-47ea-b1c4-ebf378a7716a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739462311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.2739462311 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.2495745300 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 324809803 ps |
| CPU time | 13.49 seconds |
| Started | Jun 30 08:27:00 PM PDT 24 |
| Finished | Jun 30 08:27:14 PM PDT 24 |
| Peak memory | 575180 kb |
| Host | smart-f456013d-3348-4c57-b456-b3dc11e780c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495745300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.2495745300 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.99573066 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 128610516 ps |
| CPU time | 7.73 seconds |
| Started | Jun 30 08:26:53 PM PDT 24 |
| Finished | Jun 30 08:27:01 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-3d1f21c6-b91b-41a7-9711-91fb664d0928 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99573066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.99573066 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.746774299 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 10698099460 ps |
| CPU time | 116.22 seconds |
| Started | Jun 30 08:27:02 PM PDT 24 |
| Finished | Jun 30 08:28:59 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-51ee37d4-6f84-4822-a525-16763d8d1afa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746774299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.746774299 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.1584961730 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 6445509369 ps |
| CPU time | 113.11 seconds |
| Started | Jun 30 08:27:02 PM PDT 24 |
| Finished | Jun 30 08:28:56 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-435555ba-003f-43c2-aab1-98d820347f0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584961730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.1584961730 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.12004209 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 44228681 ps |
| CPU time | 6.81 seconds |
| Started | Jun 30 08:26:55 PM PDT 24 |
| Finished | Jun 30 08:27:02 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-6bed015f-20bb-47c0-afa1-33d26c35cc98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12004209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delays.12004209 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.1873574625 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 9279928415 ps |
| CPU time | 326.25 seconds |
| Started | Jun 30 08:27:01 PM PDT 24 |
| Finished | Jun 30 08:32:28 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-dc4d84ea-4995-48c5-b4fc-8f8c17c80d60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873574625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.1873574625 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.4134898806 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 502116431 ps |
| CPU time | 48.59 seconds |
| Started | Jun 30 08:26:58 PM PDT 24 |
| Finished | Jun 30 08:27:47 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-c175a14c-62aa-4c0e-b56b-142e9f2d4d41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134898806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.4134898806 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.2019236216 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 369251163 ps |
| CPU time | 112.12 seconds |
| Started | Jun 30 08:27:00 PM PDT 24 |
| Finished | Jun 30 08:28:53 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-50124f1e-0747-454f-a9ea-dd9108de6729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019236216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.2019236216 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.3216064436 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 6309159287 ps |
| CPU time | 298.94 seconds |
| Started | Jun 30 08:27:06 PM PDT 24 |
| Finished | Jun 30 08:32:05 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-76346d36-8e55-4abe-8f7a-97b3c37186d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216064436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.3216064436 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.1359675873 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 232746881 ps |
| CPU time | 29.96 seconds |
| Started | Jun 30 08:27:00 PM PDT 24 |
| Finished | Jun 30 08:27:30 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-99743ace-a83c-4bd4-be03-c194a538aa5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359675873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.1359675873 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.1073469219 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 112238960 ps |
| CPU time | 23.87 seconds |
| Started | Jun 30 08:27:16 PM PDT 24 |
| Finished | Jun 30 08:27:41 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-2fe83e1c-489c-4e9d-bcd5-df9e9c621819 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073469219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .1073469219 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1121192802 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 72446508850 ps |
| CPU time | 1246.63 seconds |
| Started | Jun 30 08:27:13 PM PDT 24 |
| Finished | Jun 30 08:48:00 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-0c8fb3f1-0912-46a4-a1fd-93e9b21119f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121192802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.1121192802 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.651395834 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 920580605 ps |
| CPU time | 38.61 seconds |
| Started | Jun 30 08:27:15 PM PDT 24 |
| Finished | Jun 30 08:27:54 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-887ee633-69df-48f2-b324-d721b1436b52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651395834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_addr .651395834 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.1594583931 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 1962399198 ps |
| CPU time | 77.29 seconds |
| Started | Jun 30 08:27:15 PM PDT 24 |
| Finished | Jun 30 08:28:33 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-0214da1c-f01d-494a-bb82-17fea2879873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594583931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.1594583931 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.1120430819 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 746914817 ps |
| CPU time | 31.69 seconds |
| Started | Jun 30 08:27:06 PM PDT 24 |
| Finished | Jun 30 08:27:38 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-ab7b21aa-6a97-46bc-8e98-f9ed14ace9df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120430819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.1120430819 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.514941220 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 57396257099 ps |
| CPU time | 621.07 seconds |
| Started | Jun 30 08:27:15 PM PDT 24 |
| Finished | Jun 30 08:37:36 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-19333792-4c89-4906-a6e6-f77ff8238ebd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514941220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.514941220 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.3543990507 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 23680601028 ps |
| CPU time | 404.85 seconds |
| Started | Jun 30 08:27:16 PM PDT 24 |
| Finished | Jun 30 08:34:01 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-b3e87946-7d88-4f7d-a2c0-12d911320466 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543990507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.3543990507 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.1165475721 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 178919132 ps |
| CPU time | 19.92 seconds |
| Started | Jun 30 08:27:08 PM PDT 24 |
| Finished | Jun 30 08:27:28 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-86035440-f94f-4c5d-b92f-09708f7c6e92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165475721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.1165475721 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.3149113836 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 221821848 ps |
| CPU time | 19.81 seconds |
| Started | Jun 30 08:27:17 PM PDT 24 |
| Finished | Jun 30 08:27:38 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-7cfa5a59-c44f-49e9-accc-80b1d32a77ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149113836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.3149113836 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.2997942387 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 175662388 ps |
| CPU time | 8.41 seconds |
| Started | Jun 30 08:27:08 PM PDT 24 |
| Finished | Jun 30 08:27:17 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-e161cdd8-73be-4ac4-958a-fbe8133e30e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997942387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.2997942387 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.104092393 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 7521507169 ps |
| CPU time | 81.19 seconds |
| Started | Jun 30 08:27:09 PM PDT 24 |
| Finished | Jun 30 08:28:31 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-b6b71367-8fa4-421c-8810-b276ff86df17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104092393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.104092393 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.3247984167 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 4724567704 ps |
| CPU time | 81.08 seconds |
| Started | Jun 30 08:27:06 PM PDT 24 |
| Finished | Jun 30 08:28:28 PM PDT 24 |
| Peak memory | 565996 kb |
| Host | smart-a56bfaba-017f-4897-841a-ac86ad397ab0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247984167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.3247984167 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.1097450071 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 53605197 ps |
| CPU time | 7.31 seconds |
| Started | Jun 30 08:27:07 PM PDT 24 |
| Finished | Jun 30 08:27:15 PM PDT 24 |
| Peak memory | 565872 kb |
| Host | smart-d21d3ea6-983b-4113-a44b-a112d1cdda73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097450071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay s.1097450071 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.1315054879 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 3699803588 ps |
| CPU time | 288.85 seconds |
| Started | Jun 30 08:27:14 PM PDT 24 |
| Finished | Jun 30 08:32:04 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-6e3d29db-2f78-4768-bea6-5479aa42f20b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315054879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.1315054879 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.850326807 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 259224486 ps |
| CPU time | 105.22 seconds |
| Started | Jun 30 08:27:14 PM PDT 24 |
| Finished | Jun 30 08:29:00 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-831c97d8-8a31-45ed-94c9-2311b090a9aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850326807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_ with_rand_reset.850326807 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.189933175 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 839623494 ps |
| CPU time | 308.28 seconds |
| Started | Jun 30 08:27:16 PM PDT 24 |
| Finished | Jun 30 08:32:24 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-9f54f00d-1dab-4237-ae87-034bae8d8b5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189933175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_reset_error.189933175 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.128653133 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 784892145 ps |
| CPU time | 39.07 seconds |
| Started | Jun 30 08:27:15 PM PDT 24 |
| Finished | Jun 30 08:27:54 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-1a8e9d51-389d-41ca-a8ab-7ffb975b6a0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128653133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.128653133 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.2187160804 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 1256503535 ps |
| CPU time | 58.2 seconds |
| Started | Jun 30 08:27:28 PM PDT 24 |
| Finished | Jun 30 08:28:27 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-d4b139c9-e41d-4769-a271-df82c1be140b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187160804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .2187160804 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.2794302141 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 121721272244 ps |
| CPU time | 1949.53 seconds |
| Started | Jun 30 08:27:21 PM PDT 24 |
| Finished | Jun 30 08:59:51 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-7896746f-4907-44b1-9452-06af7ac9055a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794302141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.2794302141 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.305810892 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 319209392 ps |
| CPU time | 39.7 seconds |
| Started | Jun 30 08:27:23 PM PDT 24 |
| Finished | Jun 30 08:28:03 PM PDT 24 |
| Peak memory | 573832 kb |
| Host | smart-e9d29d3a-3546-485f-a20f-191595c69300 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305810892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_addr .305810892 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.554727943 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 697820988 ps |
| CPU time | 30.91 seconds |
| Started | Jun 30 08:27:26 PM PDT 24 |
| Finished | Jun 30 08:27:57 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-2c9242a8-755c-43ed-8fd0-8614186dd555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554727943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.554727943 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.1703447932 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 1922702818 ps |
| CPU time | 69.48 seconds |
| Started | Jun 30 08:27:15 PM PDT 24 |
| Finished | Jun 30 08:28:25 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-eb31a127-cba7-4220-934a-93f46045bb8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703447932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.1703447932 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.645251682 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 73083921955 ps |
| CPU time | 835.23 seconds |
| Started | Jun 30 08:27:22 PM PDT 24 |
| Finished | Jun 30 08:41:17 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-80b82993-3954-4b03-b1b0-dae1aca47a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645251682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.645251682 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.279624777 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 29332921572 ps |
| CPU time | 509.79 seconds |
| Started | Jun 30 08:27:24 PM PDT 24 |
| Finished | Jun 30 08:35:54 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-9d345ab2-56bc-4b72-83fa-4cfa5519c1de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279624777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.279624777 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1970871341 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 466922888 ps |
| CPU time | 43.13 seconds |
| Started | Jun 30 08:27:21 PM PDT 24 |
| Finished | Jun 30 08:28:04 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-76f9da37-197f-41b5-9636-8e116cd8acf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970871341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.1970871341 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.1152120943 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 2595052685 ps |
| CPU time | 93.66 seconds |
| Started | Jun 30 08:27:26 PM PDT 24 |
| Finished | Jun 30 08:29:00 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-756c22fb-b16e-43f8-8b49-113250aecee4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152120943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.1152120943 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.2250344422 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 52026833 ps |
| CPU time | 6.88 seconds |
| Started | Jun 30 08:27:14 PM PDT 24 |
| Finished | Jun 30 08:27:21 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-2b968d8d-fdc4-447a-9c80-af7348182498 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250344422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.2250344422 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.2101004880 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 9592670001 ps |
| CPU time | 98.81 seconds |
| Started | Jun 30 08:27:15 PM PDT 24 |
| Finished | Jun 30 08:28:54 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-7849a98b-9a20-4a60-b849-6e2eb40e17c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101004880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.2101004880 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3034831312 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 4840819616 ps |
| CPU time | 81.7 seconds |
| Started | Jun 30 08:27:15 PM PDT 24 |
| Finished | Jun 30 08:28:37 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-42503c2e-bae8-4c51-a6f9-8eea38c01d0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034831312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.3034831312 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.777343161 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 44299338 ps |
| CPU time | 7.03 seconds |
| Started | Jun 30 08:27:16 PM PDT 24 |
| Finished | Jun 30 08:27:23 PM PDT 24 |
| Peak memory | 565940 kb |
| Host | smart-96981f48-d191-4e7e-8b76-fa48398ec314 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777343161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delays .777343161 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.3715989015 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 6073842074 ps |
| CPU time | 236.34 seconds |
| Started | Jun 30 08:27:23 PM PDT 24 |
| Finished | Jun 30 08:31:20 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-e1c218a9-656b-4bb6-9c01-00da019605c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715989015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.3715989015 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.3817778114 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 3173562720 ps |
| CPU time | 120.47 seconds |
| Started | Jun 30 08:27:23 PM PDT 24 |
| Finished | Jun 30 08:29:24 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-aaf1f6cf-7350-4052-841f-0d6551158476 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817778114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.3817778114 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.2098703819 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 11613620270 ps |
| CPU time | 613.07 seconds |
| Started | Jun 30 08:27:24 PM PDT 24 |
| Finished | Jun 30 08:37:37 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-e5498f61-cc89-4445-bbb2-df2f225f29cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098703819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.2098703819 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.570242037 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 9210151110 ps |
| CPU time | 401.56 seconds |
| Started | Jun 30 08:27:38 PM PDT 24 |
| Finished | Jun 30 08:34:20 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-27c634c5-8d78-4d27-8d82-c47271c7159a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570242037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_reset_error.570242037 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.3924265340 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 394860005 ps |
| CPU time | 20.15 seconds |
| Started | Jun 30 08:27:22 PM PDT 24 |
| Finished | Jun 30 08:27:43 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-ec0dc4f6-7cae-4612-af9b-236bc993b27a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924265340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.3924265340 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.3862375375 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 2475710339 ps |
| CPU time | 112.49 seconds |
| Started | Jun 30 08:27:29 PM PDT 24 |
| Finished | Jun 30 08:29:22 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-5b1f6e1c-567a-4658-822c-8efb9252714c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862375375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .3862375375 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.1105259959 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 15711326183 ps |
| CPU time | 299.33 seconds |
| Started | Jun 30 08:27:32 PM PDT 24 |
| Finished | Jun 30 08:32:32 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-414d6ce5-4afa-48d5-a2e9-1607bd0dac05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105259959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_ device_slow_rsp.1105259959 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.3812139531 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 290372708 ps |
| CPU time | 33.3 seconds |
| Started | Jun 30 08:27:30 PM PDT 24 |
| Finished | Jun 30 08:28:04 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-cc292eae-cfee-4735-8fdc-2cbc792444ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812139531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.3812139531 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.3925795291 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 323813088 ps |
| CPU time | 26.93 seconds |
| Started | Jun 30 08:27:31 PM PDT 24 |
| Finished | Jun 30 08:27:58 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-94938bfe-e056-448f-8c7c-050cee70c8a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925795291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.3925795291 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.3652778268 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 631430509 ps |
| CPU time | 27.59 seconds |
| Started | Jun 30 08:27:29 PM PDT 24 |
| Finished | Jun 30 08:27:58 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-9c6657ff-3ff1-4344-983e-a1f6be253bb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652778268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.3652778268 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.2966213705 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 57356989857 ps |
| CPU time | 595.37 seconds |
| Started | Jun 30 08:27:37 PM PDT 24 |
| Finished | Jun 30 08:37:33 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-9b8a0ad2-ebe1-48f2-8c52-617783710d1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966213705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.2966213705 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.1526835792 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 40159167979 ps |
| CPU time | 689.55 seconds |
| Started | Jun 30 08:27:29 PM PDT 24 |
| Finished | Jun 30 08:38:59 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-cd96c39d-7203-4582-869a-3b67d759aec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526835792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.1526835792 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.3276972055 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 414491525 ps |
| CPU time | 38.05 seconds |
| Started | Jun 30 08:27:29 PM PDT 24 |
| Finished | Jun 30 08:28:08 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-f2fcb38b-5081-44ab-a1e9-08c730b9db64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276972055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.3276972055 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.1681769871 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 246520681 ps |
| CPU time | 18.53 seconds |
| Started | Jun 30 08:27:31 PM PDT 24 |
| Finished | Jun 30 08:27:50 PM PDT 24 |
| Peak memory | 575176 kb |
| Host | smart-9d4f0d13-c632-430b-833f-fffa451fc891 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681769871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.1681769871 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.708858291 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 40731792 ps |
| CPU time | 6.35 seconds |
| Started | Jun 30 08:27:30 PM PDT 24 |
| Finished | Jun 30 08:27:37 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-b6edb8ca-1f43-4d10-bd1f-fd03ad18baaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708858291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.708858291 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.1744270260 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 8896287777 ps |
| CPU time | 100.91 seconds |
| Started | Jun 30 08:27:38 PM PDT 24 |
| Finished | Jun 30 08:29:20 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-3fa0c2d1-cf94-4336-9666-c884bbfb2f82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744270260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.1744270260 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.883363202 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 5442231032 ps |
| CPU time | 98.63 seconds |
| Started | Jun 30 08:27:30 PM PDT 24 |
| Finished | Jun 30 08:29:09 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-928ff21f-0683-4776-bf34-51e0aa760ccd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883363202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.883363202 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.806340897 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 45615156 ps |
| CPU time | 6.71 seconds |
| Started | Jun 30 08:27:38 PM PDT 24 |
| Finished | Jun 30 08:27:46 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-d88ef057-7c6c-494b-a46d-987b0502cf84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806340897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delays .806340897 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.693815282 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 3416255365 ps |
| CPU time | 169.85 seconds |
| Started | Jun 30 08:27:35 PM PDT 24 |
| Finished | Jun 30 08:30:25 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-e0e14202-e1a7-40c3-b285-64117eed11be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693815282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.693815282 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.2222149768 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 582966916 ps |
| CPU time | 46.52 seconds |
| Started | Jun 30 08:27:35 PM PDT 24 |
| Finished | Jun 30 08:28:22 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-a98292f7-a761-486c-880e-2e29e3dfd081 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222149768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.2222149768 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2306775298 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 6220093781 ps |
| CPU time | 658.85 seconds |
| Started | Jun 30 08:27:37 PM PDT 24 |
| Finished | Jun 30 08:38:36 PM PDT 24 |
| Peak memory | 581164 kb |
| Host | smart-6494cefd-0f25-4ef2-bdaf-585b15efad78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306775298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.2306775298 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.2324866447 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 87678119 ps |
| CPU time | 13.72 seconds |
| Started | Jun 30 08:27:32 PM PDT 24 |
| Finished | Jun 30 08:27:46 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-ebcc557c-1110-4c94-833f-f7c105e704de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324866447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.2324866447 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.1862315018 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 941576858 ps |
| CPU time | 80.62 seconds |
| Started | Jun 30 08:27:42 PM PDT 24 |
| Finished | Jun 30 08:29:04 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-ed5c88c5-a555-4313-a697-9aa80be12877 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862315018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .1862315018 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.1172069953 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 13436655390 ps |
| CPU time | 244.8 seconds |
| Started | Jun 30 08:27:43 PM PDT 24 |
| Finished | Jun 30 08:31:49 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-e5858bc6-cf37-4478-a97d-62ae6a989e06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172069953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.1172069953 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.279509438 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 238699674 ps |
| CPU time | 29.46 seconds |
| Started | Jun 30 08:27:42 PM PDT 24 |
| Finished | Jun 30 08:28:12 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-2bbcc51b-c949-4e70-b79b-0afd264c4459 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279509438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_addr .279509438 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.2878497633 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 2257041962 ps |
| CPU time | 71.66 seconds |
| Started | Jun 30 08:27:42 PM PDT 24 |
| Finished | Jun 30 08:28:55 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-b656e93a-ee35-41f4-a16b-4e74422e280d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878497633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.2878497633 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.2897475177 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 1019730233 ps |
| CPU time | 43.92 seconds |
| Started | Jun 30 08:27:36 PM PDT 24 |
| Finished | Jun 30 08:28:20 PM PDT 24 |
| Peak memory | 575168 kb |
| Host | smart-157cc789-dfb0-4a01-9ca2-c100a55429f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897475177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.2897475177 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.3064520496 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 82404046884 ps |
| CPU time | 874.09 seconds |
| Started | Jun 30 08:27:43 PM PDT 24 |
| Finished | Jun 30 08:42:18 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-ab9f943f-91b5-4526-92be-c0a9f2f9ea7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064520496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.3064520496 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.1965981814 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 51198351539 ps |
| CPU time | 821.81 seconds |
| Started | Jun 30 08:27:41 PM PDT 24 |
| Finished | Jun 30 08:41:24 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-63e055c8-6637-4584-b73c-48c5a862da4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965981814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.1965981814 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.3065363966 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 87101926 ps |
| CPU time | 11.65 seconds |
| Started | Jun 30 08:27:43 PM PDT 24 |
| Finished | Jun 30 08:27:56 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-00111a15-3c2a-460a-9825-03222fb2050d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065363966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.3065363966 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.1171618465 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 1415100169 ps |
| CPU time | 46.5 seconds |
| Started | Jun 30 08:27:42 PM PDT 24 |
| Finished | Jun 30 08:28:30 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-d2a5b6d7-4f32-4890-9194-e4be3a745bd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171618465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.1171618465 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.1907429608 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 50171773 ps |
| CPU time | 6.63 seconds |
| Started | Jun 30 08:27:39 PM PDT 24 |
| Finished | Jun 30 08:27:46 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-b52a2760-07fb-4be7-bd22-3eb47b504205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907429608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.1907429608 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.3058817649 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 5827838731 ps |
| CPU time | 61.47 seconds |
| Started | Jun 30 08:27:36 PM PDT 24 |
| Finished | Jun 30 08:28:38 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-bb7c7dc9-b023-4cfe-aff5-5fe9b019584a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058817649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.3058817649 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.3133379164 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 5437716151 ps |
| CPU time | 96.71 seconds |
| Started | Jun 30 08:27:36 PM PDT 24 |
| Finished | Jun 30 08:29:13 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-3f5751e9-e4a6-4d89-9a29-4cc751cc49f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133379164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.3133379164 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.844992057 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 37783718 ps |
| CPU time | 6.11 seconds |
| Started | Jun 30 08:27:37 PM PDT 24 |
| Finished | Jun 30 08:27:43 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-852e327e-8f22-4a0a-938c-89eda0e563b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844992057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delays .844992057 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.854803261 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 1020487345 ps |
| CPU time | 89.22 seconds |
| Started | Jun 30 08:27:43 PM PDT 24 |
| Finished | Jun 30 08:29:13 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-9117fa89-d0c2-4662-bf1e-e2cc9afa150e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854803261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.854803261 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.3578925909 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 6495405314 ps |
| CPU time | 261.37 seconds |
| Started | Jun 30 08:27:42 PM PDT 24 |
| Finished | Jun 30 08:32:04 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-0edb1c2a-2e4a-4f46-bb27-b228781b7b68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578925909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.3578925909 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.2234951529 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 400201731 ps |
| CPU time | 136.01 seconds |
| Started | Jun 30 08:27:43 PM PDT 24 |
| Finished | Jun 30 08:30:00 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-3ceb645f-8749-41cd-a4fe-d13ff770d84b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234951529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.2234951529 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.1937063341 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 7769002 ps |
| CPU time | 17.04 seconds |
| Started | Jun 30 08:28:04 PM PDT 24 |
| Finished | Jun 30 08:28:21 PM PDT 24 |
| Peak memory | 565872 kb |
| Host | smart-1783fc9d-e02d-462d-9fd9-ed29114eb656 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937063341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.1937063341 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.4125051034 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 313258873 ps |
| CPU time | 37.56 seconds |
| Started | Jun 30 08:27:44 PM PDT 24 |
| Finished | Jun 30 08:28:22 PM PDT 24 |
| Peak memory | 575200 kb |
| Host | smart-273a9731-50ce-47b9-9337-b8bea68bb386 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125051034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.4125051034 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.2132455328 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 401983854 ps |
| CPU time | 25.61 seconds |
| Started | Jun 30 08:28:04 PM PDT 24 |
| Finished | Jun 30 08:28:30 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-de8a9a34-4f4c-4630-95e8-a029eb5c22f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132455328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .2132455328 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1712922889 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 2647609945 ps |
| CPU time | 47.25 seconds |
| Started | Jun 30 08:27:55 PM PDT 24 |
| Finished | Jun 30 08:28:43 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-06b6c1da-f262-4a9f-8f1f-6aff1854a1b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712922889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.1712922889 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.2227489145 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 109537212 ps |
| CPU time | 15.36 seconds |
| Started | Jun 30 08:28:03 PM PDT 24 |
| Finished | Jun 30 08:28:19 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-f6b1dd3c-2a1f-43e4-b826-2981c648bb9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227489145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.2227489145 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.4008416168 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 2320638884 ps |
| CPU time | 56.83 seconds |
| Started | Jun 30 08:29:13 PM PDT 24 |
| Finished | Jun 30 08:30:11 PM PDT 24 |
| Peak memory | 573376 kb |
| Host | smart-10177d46-89de-4edf-913b-14038e2f2119 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008416168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.4008416168 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.2299619942 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 935452693 ps |
| CPU time | 34.06 seconds |
| Started | Jun 30 08:27:55 PM PDT 24 |
| Finished | Jun 30 08:28:30 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-2af35bd3-fde0-4825-b43f-8c88c84490ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299619942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.2299619942 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.4123159762 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 97868807231 ps |
| CPU time | 995.5 seconds |
| Started | Jun 30 08:28:04 PM PDT 24 |
| Finished | Jun 30 08:44:40 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-c5c199ce-9b2b-4a05-b943-5726e7530e18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123159762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.4123159762 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.198780238 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 53483311249 ps |
| CPU time | 979.89 seconds |
| Started | Jun 30 08:27:55 PM PDT 24 |
| Finished | Jun 30 08:44:15 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-45742242-3535-41de-9b40-b7aa1393d732 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198780238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.198780238 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.2976261853 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 458129103 ps |
| CPU time | 47.22 seconds |
| Started | Jun 30 08:28:04 PM PDT 24 |
| Finished | Jun 30 08:28:52 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-b1790829-77d4-40b5-9680-f4bdcc00d611 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976261853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.2976261853 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.1179372953 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 924402970 ps |
| CPU time | 31 seconds |
| Started | Jun 30 08:28:00 PM PDT 24 |
| Finished | Jun 30 08:28:32 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-a0a8d47e-e0f0-406c-a71a-132697dd0942 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179372953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.1179372953 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.1004841197 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 196429646 ps |
| CPU time | 8.71 seconds |
| Started | Jun 30 08:28:00 PM PDT 24 |
| Finished | Jun 30 08:28:09 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-b3bb2109-c6c7-4466-9459-43de3d21e8f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004841197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.1004841197 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.2304589904 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 5515690468 ps |
| CPU time | 60.65 seconds |
| Started | Jun 30 08:27:50 PM PDT 24 |
| Finished | Jun 30 08:28:51 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-b4f46223-b753-41d1-9938-975c7a9e44f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304589904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.2304589904 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.3506374148 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 6788332727 ps |
| CPU time | 117.5 seconds |
| Started | Jun 30 08:27:50 PM PDT 24 |
| Finished | Jun 30 08:29:48 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-26c2b6a7-656e-431b-9c7d-fc19cc9356e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506374148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.3506374148 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.1495534102 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 50029248 ps |
| CPU time | 6.63 seconds |
| Started | Jun 30 08:28:00 PM PDT 24 |
| Finished | Jun 30 08:28:07 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-9c9ab0db-a7ad-4a3a-aaa4-37bc2db26684 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495534102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.1495534102 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.2920503840 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 2241386372 ps |
| CPU time | 150.53 seconds |
| Started | Jun 30 08:28:04 PM PDT 24 |
| Finished | Jun 30 08:30:35 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-a68fd226-acd3-4fc8-bbd3-ba72887e30f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920503840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.2920503840 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.1302084752 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 62611497 ps |
| CPU time | 8.49 seconds |
| Started | Jun 30 08:28:02 PM PDT 24 |
| Finished | Jun 30 08:28:11 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-a0cbb1dc-60b2-4a8e-a5d8-57028d054fff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302084752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.1302084752 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.3087958711 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 2068907071 ps |
| CPU time | 225.39 seconds |
| Started | Jun 30 08:29:07 PM PDT 24 |
| Finished | Jun 30 08:32:53 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-c71f875b-4a7d-456a-89a4-ca1f2acf8247 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087958711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_rand_reset.3087958711 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.75532374 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 333996774 ps |
| CPU time | 172.19 seconds |
| Started | Jun 30 08:28:02 PM PDT 24 |
| Finished | Jun 30 08:30:55 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-2c3a8b46-5b70-414d-ae71-db4b2c007ae5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75532374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_ with_reset_error.75532374 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.4024865103 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 725433560 ps |
| CPU time | 35.53 seconds |
| Started | Jun 30 08:28:01 PM PDT 24 |
| Finished | Jun 30 08:28:37 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-c0b03aac-114b-40f6-83e3-a9fed1a3d58a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024865103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.4024865103 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.1451711139 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 777662603 ps |
| CPU time | 38.34 seconds |
| Started | Jun 30 08:28:07 PM PDT 24 |
| Finished | Jun 30 08:28:46 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-d723d5aa-c1fb-4dd3-b352-eb83499f8100 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451711139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .1451711139 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2714356797 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 49964065193 ps |
| CPU time | 937.23 seconds |
| Started | Jun 30 08:28:09 PM PDT 24 |
| Finished | Jun 30 08:43:47 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-85241eb4-614c-45d5-9f5d-f20690e3c52c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714356797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.2714356797 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.3474232185 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 223203286 ps |
| CPU time | 27.23 seconds |
| Started | Jun 30 08:28:09 PM PDT 24 |
| Finished | Jun 30 08:28:36 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-f260d7d9-e6ff-4aa3-a621-379ec59f1539 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474232185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.3474232185 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.2168879887 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 458501651 ps |
| CPU time | 21.79 seconds |
| Started | Jun 30 08:28:10 PM PDT 24 |
| Finished | Jun 30 08:28:32 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-9a5f5ccb-9ddc-4394-b55f-fb6548353676 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168879887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.2168879887 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.2329366502 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 190488599 ps |
| CPU time | 21.68 seconds |
| Started | Jun 30 08:28:02 PM PDT 24 |
| Finished | Jun 30 08:28:24 PM PDT 24 |
| Peak memory | 575200 kb |
| Host | smart-2d1987d6-d884-4490-b0b3-710c8f3c9a86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329366502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.2329366502 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.1388938961 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 89259308244 ps |
| CPU time | 824.62 seconds |
| Started | Jun 30 08:29:13 PM PDT 24 |
| Finished | Jun 30 08:42:59 PM PDT 24 |
| Peak memory | 574924 kb |
| Host | smart-212c414d-3a6e-4861-a13d-49c4bffcdc09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388938961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.1388938961 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.718891739 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 6424879011 ps |
| CPU time | 111.27 seconds |
| Started | Jun 30 08:28:02 PM PDT 24 |
| Finished | Jun 30 08:29:54 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-00aff26a-ecc3-46b9-9b5c-d74669b2ee49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718891739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.718891739 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.793190922 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 174929926 ps |
| CPU time | 18.83 seconds |
| Started | Jun 30 08:28:02 PM PDT 24 |
| Finished | Jun 30 08:28:21 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-284d6575-f73e-473d-9c11-c35128a841a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793190922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_dela ys.793190922 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.1162296490 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 575810044 ps |
| CPU time | 46.78 seconds |
| Started | Jun 30 08:28:08 PM PDT 24 |
| Finished | Jun 30 08:28:55 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-8e1aeada-9e16-4b77-845f-0bce42b510c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162296490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.1162296490 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.1623608926 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 42590201 ps |
| CPU time | 6.63 seconds |
| Started | Jun 30 08:28:02 PM PDT 24 |
| Finished | Jun 30 08:28:09 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-b5f515cc-5b1e-4ad5-a934-061821a332b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623608926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.1623608926 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.552314260 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 7658068687 ps |
| CPU time | 90.64 seconds |
| Started | Jun 30 08:28:05 PM PDT 24 |
| Finished | Jun 30 08:29:36 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-5bb05deb-eeb0-472d-8bc9-ce14e088be5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552314260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.552314260 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.40112397 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 5102261833 ps |
| CPU time | 93.31 seconds |
| Started | Jun 30 08:27:59 PM PDT 24 |
| Finished | Jun 30 08:29:33 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-cc3995ba-2c44-4a82-950b-952f2c636c51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40112397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.40112397 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3182357260 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 37668942 ps |
| CPU time | 6.07 seconds |
| Started | Jun 30 08:28:02 PM PDT 24 |
| Finished | Jun 30 08:28:09 PM PDT 24 |
| Peak memory | 565948 kb |
| Host | smart-0db4b5f7-f5ee-4bfe-bcd6-9b44cb613620 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182357260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.3182357260 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.3388334379 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 1597109417 ps |
| CPU time | 140.11 seconds |
| Started | Jun 30 08:28:08 PM PDT 24 |
| Finished | Jun 30 08:30:29 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-f020986e-32bf-47fe-b4ce-70ec3cd3fd97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388334379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.3388334379 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.3604726707 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 12272541692 ps |
| CPU time | 438.27 seconds |
| Started | Jun 30 08:28:09 PM PDT 24 |
| Finished | Jun 30 08:35:28 PM PDT 24 |
| Peak memory | 574812 kb |
| Host | smart-eb57846b-1ae6-41bb-830b-f5cbb47ff584 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604726707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.3604726707 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.592219844 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 115421395 ps |
| CPU time | 28.84 seconds |
| Started | Jun 30 08:28:07 PM PDT 24 |
| Finished | Jun 30 08:28:36 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-f7f25a13-54cf-479e-87bd-e82c0e0740d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592219844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_ with_rand_reset.592219844 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3561045002 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 1292048028 ps |
| CPU time | 163.18 seconds |
| Started | Jun 30 08:28:11 PM PDT 24 |
| Finished | Jun 30 08:30:54 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-9683f7eb-9d90-49c3-8475-0d65702da798 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561045002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.3561045002 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.1160187779 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 209596475 ps |
| CPU time | 27.9 seconds |
| Started | Jun 30 08:28:08 PM PDT 24 |
| Finished | Jun 30 08:28:36 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-7ff9310f-f292-45f7-af67-06dd9cb002e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160187779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.1160187779 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.3080683056 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 747537191 ps |
| CPU time | 31.43 seconds |
| Started | Jun 30 08:28:14 PM PDT 24 |
| Finished | Jun 30 08:28:46 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-bb521903-7511-4735-aca1-299d6041020a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080683056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .3080683056 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.2143467093 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 82563688359 ps |
| CPU time | 1442.35 seconds |
| Started | Jun 30 08:28:17 PM PDT 24 |
| Finished | Jun 30 08:52:20 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-bfdd292f-15d2-4bf5-a25e-c9508582aaae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143467093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.2143467093 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.2296206633 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 1310873602 ps |
| CPU time | 51.65 seconds |
| Started | Jun 30 08:28:17 PM PDT 24 |
| Finished | Jun 30 08:29:09 PM PDT 24 |
| Peak memory | 573848 kb |
| Host | smart-fc69ffba-f7d1-419a-8ff4-49453f394a59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296206633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.2296206633 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.1849485085 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 1056898042 ps |
| CPU time | 43.67 seconds |
| Started | Jun 30 08:28:14 PM PDT 24 |
| Finished | Jun 30 08:28:58 PM PDT 24 |
| Peak memory | 573756 kb |
| Host | smart-f529696a-e5d1-4a39-b6f8-0005e4cd15ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849485085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.1849485085 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.845370483 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 410403046 ps |
| CPU time | 36.66 seconds |
| Started | Jun 30 08:28:17 PM PDT 24 |
| Finished | Jun 30 08:28:54 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-075f5334-4fe2-411f-87ca-1af1fc497c10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845370483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.845370483 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.3805314217 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 44503290377 ps |
| CPU time | 469.42 seconds |
| Started | Jun 30 08:28:21 PM PDT 24 |
| Finished | Jun 30 08:36:11 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-b7a1925c-d7c8-4792-8d83-0aaf25c891d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805314217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.3805314217 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.20561946 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 66070128331 ps |
| CPU time | 1081.61 seconds |
| Started | Jun 30 08:28:13 PM PDT 24 |
| Finished | Jun 30 08:46:15 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-885b7862-2f5b-4be9-9a25-9925c5b6faa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20561946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.20561946 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.4264714518 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 39317551 ps |
| CPU time | 6.63 seconds |
| Started | Jun 30 08:28:22 PM PDT 24 |
| Finished | Jun 30 08:28:29 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-7af38a1a-4a14-4b34-8704-599f13e73be5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264714518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.4264714518 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.232599671 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 757206188 ps |
| CPU time | 24.67 seconds |
| Started | Jun 30 08:28:16 PM PDT 24 |
| Finished | Jun 30 08:28:42 PM PDT 24 |
| Peak memory | 575184 kb |
| Host | smart-70dbf502-ed06-41d0-a7e7-4e3e0b18e6f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232599671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.232599671 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.3236648988 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 43888753 ps |
| CPU time | 6.47 seconds |
| Started | Jun 30 08:28:07 PM PDT 24 |
| Finished | Jun 30 08:28:14 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-56e77868-425c-484c-9e86-eefb613addc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236648988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.3236648988 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.345557096 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 6816770864 ps |
| CPU time | 73.66 seconds |
| Started | Jun 30 08:28:16 PM PDT 24 |
| Finished | Jun 30 08:29:31 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-5a93aaa9-58b3-415e-baa9-0576f25ddb78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345557096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.345557096 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1546706549 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 4015678777 ps |
| CPU time | 70.77 seconds |
| Started | Jun 30 08:28:15 PM PDT 24 |
| Finished | Jun 30 08:29:26 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-b410b5a9-4fdd-4e11-9fad-7a0d703439e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546706549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.1546706549 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.2718390082 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 35746292 ps |
| CPU time | 5.66 seconds |
| Started | Jun 30 08:28:16 PM PDT 24 |
| Finished | Jun 30 08:28:22 PM PDT 24 |
| Peak memory | 565812 kb |
| Host | smart-918cacc5-b371-452c-a375-a7c382d57631 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718390082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.2718390082 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.186057873 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 2812233073 ps |
| CPU time | 105.36 seconds |
| Started | Jun 30 08:28:20 PM PDT 24 |
| Finished | Jun 30 08:30:05 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-a9891314-2d5a-4764-a1e0-ea5485831341 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186057873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.186057873 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.3366117802 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 7340930646 ps |
| CPU time | 294.05 seconds |
| Started | Jun 30 08:28:21 PM PDT 24 |
| Finished | Jun 30 08:33:16 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-fa15934b-bc2a-4c4c-85fd-2027c99f8d57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366117802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.3366117802 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.3066449041 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 3493370497 ps |
| CPU time | 228.43 seconds |
| Started | Jun 30 08:28:18 PM PDT 24 |
| Finished | Jun 30 08:32:07 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-abc53c78-fb36-4810-9eb3-b96228831e6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066449041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.3066449041 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.2647079769 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 16655012889 ps |
| CPU time | 578.32 seconds |
| Started | Jun 30 08:28:18 PM PDT 24 |
| Finished | Jun 30 08:37:58 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-b178d081-570e-49a4-9df1-58f0be902397 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647079769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.2647079769 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.2158373506 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 88143589 ps |
| CPU time | 13.29 seconds |
| Started | Jun 30 08:28:21 PM PDT 24 |
| Finished | Jun 30 08:28:35 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-45483bdc-93be-436a-8f38-a276dd1bc9a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158373506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.2158373506 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.1965931676 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 1018437179 ps |
| CPU time | 82.93 seconds |
| Started | Jun 30 08:28:20 PM PDT 24 |
| Finished | Jun 30 08:29:43 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-28c8485e-9081-4a82-a705-ca1af664acfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965931676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .1965931676 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.2865864762 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 42674743069 ps |
| CPU time | 723.73 seconds |
| Started | Jun 30 08:28:26 PM PDT 24 |
| Finished | Jun 30 08:40:31 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-7a084dba-499b-4188-a811-5eeed0b6d1fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865864762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.2865864762 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.3256966884 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 378466962 ps |
| CPU time | 17.97 seconds |
| Started | Jun 30 08:28:26 PM PDT 24 |
| Finished | Jun 30 08:28:44 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-1d90a075-d031-408f-b0d3-fc832d74341f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256966884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.3256966884 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.1329471356 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 176434451 ps |
| CPU time | 10.22 seconds |
| Started | Jun 30 08:28:26 PM PDT 24 |
| Finished | Jun 30 08:28:36 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-d23b2f2f-faa0-4864-82b4-b9d0df1ae98f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329471356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.1329471356 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.3714505107 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 2387801180 ps |
| CPU time | 91.25 seconds |
| Started | Jun 30 08:28:19 PM PDT 24 |
| Finished | Jun 30 08:29:51 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-1bdc6269-5b6f-4eb0-9b7f-0c80b3efca32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714505107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.3714505107 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.1484589769 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 50880827736 ps |
| CPU time | 525.18 seconds |
| Started | Jun 30 08:28:18 PM PDT 24 |
| Finished | Jun 30 08:37:04 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-595d33d3-829e-46f9-aa18-fdfca0dd8b78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484589769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.1484589769 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.1852350099 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 56789355326 ps |
| CPU time | 970.36 seconds |
| Started | Jun 30 08:28:20 PM PDT 24 |
| Finished | Jun 30 08:44:32 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-f3ed2e05-1ab8-4597-86ae-6ac6b8e88fff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852350099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.1852350099 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.231840916 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 418378226 ps |
| CPU time | 37.79 seconds |
| Started | Jun 30 08:28:19 PM PDT 24 |
| Finished | Jun 30 08:28:57 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-80c358c5-956f-469e-a5c5-4acb2f4a9efa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231840916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_dela ys.231840916 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.2881055998 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 257762978 ps |
| CPU time | 21.51 seconds |
| Started | Jun 30 08:28:25 PM PDT 24 |
| Finished | Jun 30 08:28:47 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-8c54b70b-ad8d-4370-940c-3391fb2a1c36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881055998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.2881055998 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.1444208490 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 172791339 ps |
| CPU time | 8.26 seconds |
| Started | Jun 30 08:28:18 PM PDT 24 |
| Finished | Jun 30 08:28:27 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-bd649adb-aff5-4f38-a899-95927835a7d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444208490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.1444208490 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.3784987390 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 8120432106 ps |
| CPU time | 86.31 seconds |
| Started | Jun 30 08:28:21 PM PDT 24 |
| Finished | Jun 30 08:29:48 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-2eddb158-ac62-4b35-a77a-ad185aafdbdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784987390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.3784987390 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.278082117 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 5044070702 ps |
| CPU time | 92.38 seconds |
| Started | Jun 30 08:28:21 PM PDT 24 |
| Finished | Jun 30 08:29:54 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-1c87eda9-5024-4b3e-944a-aed2c7aa8c8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278082117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.278082117 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.4146684573 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 50119365 ps |
| CPU time | 6.77 seconds |
| Started | Jun 30 08:28:21 PM PDT 24 |
| Finished | Jun 30 08:28:28 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-bb6a441c-35e6-499e-8556-0edffcb96b3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146684573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.4146684573 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.3517775089 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 5307298772 ps |
| CPU time | 208.28 seconds |
| Started | Jun 30 08:28:26 PM PDT 24 |
| Finished | Jun 30 08:31:55 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-d9a9cca4-55eb-49b1-a801-2650d8d032e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517775089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.3517775089 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.294113879 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 5994934087 ps |
| CPU time | 244.68 seconds |
| Started | Jun 30 08:28:27 PM PDT 24 |
| Finished | Jun 30 08:32:32 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-0753d4e0-dba0-4916-8d62-5196a8301fb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294113879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.294113879 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.1028317275 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 12438378188 ps |
| CPU time | 755.69 seconds |
| Started | Jun 30 08:28:26 PM PDT 24 |
| Finished | Jun 30 08:41:02 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-124a6ea2-2085-4001-abbe-70a0875fbe14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028317275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.1028317275 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.194000673 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 80461555 ps |
| CPU time | 17.39 seconds |
| Started | Jun 30 08:28:26 PM PDT 24 |
| Finished | Jun 30 08:28:44 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-9290d919-c9e7-4451-9a6d-7e374afdd476 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194000673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_reset_error.194000673 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.2686221038 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 245985607 ps |
| CPU time | 34.13 seconds |
| Started | Jun 30 08:28:26 PM PDT 24 |
| Finished | Jun 30 08:29:01 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-7d2b6744-40de-4780-b253-4141c532dc5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686221038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.2686221038 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.1999209648 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 28559788616 ps |
| CPU time | 3363.69 seconds |
| Started | Jun 30 08:10:52 PM PDT 24 |
| Finished | Jun 30 09:06:57 PM PDT 24 |
| Peak memory | 592348 kb |
| Host | smart-6ed0d905-22e5-4c18-b4f8-b6bebdbfed73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999209648 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.1999209648 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.3813306363 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 4093237000 ps |
| CPU time | 430.74 seconds |
| Started | Jun 30 08:10:58 PM PDT 24 |
| Finished | Jun 30 08:18:09 PM PDT 24 |
| Peak memory | 603460 kb |
| Host | smart-9bc80719-b5e3-4a26-b5fe-632951a4f4aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813306363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.3813306363 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.2570933136 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 1260968391 ps |
| CPU time | 102.8 seconds |
| Started | Jun 30 08:11:12 PM PDT 24 |
| Finished | Jun 30 08:12:55 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-7e261d0a-ed5d-48a3-987b-f14e077a67a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570933136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 2570933136 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2681618038 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 91717466597 ps |
| CPU time | 1522.9 seconds |
| Started | Jun 30 08:11:08 PM PDT 24 |
| Finished | Jun 30 08:36:32 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-f5c4fa1b-9030-4a42-ad53-dd9a26fc1971 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681618038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.2681618038 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2183917961 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 705123821 ps |
| CPU time | 29.95 seconds |
| Started | Jun 30 08:11:15 PM PDT 24 |
| Finished | Jun 30 08:11:46 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-7e2cbd31-9450-424b-8c03-222a385f8f61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183917961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .2183917961 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.3639371172 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 98228601 ps |
| CPU time | 12.8 seconds |
| Started | Jun 30 08:11:15 PM PDT 24 |
| Finished | Jun 30 08:11:28 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-166410dc-76cb-49da-b167-b86bdec9172c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639371172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3639371172 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.281977867 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 432085306 ps |
| CPU time | 44.6 seconds |
| Started | Jun 30 08:11:03 PM PDT 24 |
| Finished | Jun 30 08:11:49 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-414765f9-85ee-4ea6-bdcd-5ab858992162 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281977867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.281977867 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.2806854350 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 51334022914 ps |
| CPU time | 535.71 seconds |
| Started | Jun 30 08:11:10 PM PDT 24 |
| Finished | Jun 30 08:20:07 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-e64b6224-6924-408f-a50c-0b429d97c3cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806854350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2806854350 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.3137664541 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 56201485851 ps |
| CPU time | 966.36 seconds |
| Started | Jun 30 08:11:09 PM PDT 24 |
| Finished | Jun 30 08:27:16 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-262bbe47-00ce-4bcc-83bc-7e26e0ff7114 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137664541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3137664541 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.2843842268 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 252640336 ps |
| CPU time | 25.21 seconds |
| Started | Jun 30 08:11:09 PM PDT 24 |
| Finished | Jun 30 08:11:34 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-973a18e0-520e-4f42-8686-e467d57c0c77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843842268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.2843842268 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.2647026408 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 1421501018 ps |
| CPU time | 46.59 seconds |
| Started | Jun 30 08:11:15 PM PDT 24 |
| Finished | Jun 30 08:12:02 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-5b5e5e91-df20-4bed-85bf-5ffeab77023e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647026408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2647026408 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.2374874657 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 209602460 ps |
| CPU time | 9.55 seconds |
| Started | Jun 30 08:10:58 PM PDT 24 |
| Finished | Jun 30 08:11:08 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-7b08a1dc-a6e0-4ef3-9798-815a85222ba4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374874657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2374874657 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.1898835477 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 6094019152 ps |
| CPU time | 65.93 seconds |
| Started | Jun 30 08:11:07 PM PDT 24 |
| Finished | Jun 30 08:12:14 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-54fcc7bf-10b9-42ce-9f3c-20c1778cd93b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898835477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1898835477 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.993809086 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 3985538780 ps |
| CPU time | 67.47 seconds |
| Started | Jun 30 08:11:01 PM PDT 24 |
| Finished | Jun 30 08:12:08 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-bcdb2587-9116-40a0-be32-cdca83966271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993809086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.993809086 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.968499395 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 43256036 ps |
| CPU time | 6.74 seconds |
| Started | Jun 30 08:10:59 PM PDT 24 |
| Finished | Jun 30 08:11:06 PM PDT 24 |
| Peak memory | 565920 kb |
| Host | smart-544a2d0e-caaa-4f4d-9783-de954499148e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968499395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays. 968499395 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.2987367997 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 13348732933 ps |
| CPU time | 535.94 seconds |
| Started | Jun 30 08:11:13 PM PDT 24 |
| Finished | Jun 30 08:20:10 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-4bcca27b-48bb-4184-8412-a76aefb26f3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987367997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2987367997 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.1257839790 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 19247350670 ps |
| CPU time | 726.29 seconds |
| Started | Jun 30 08:11:24 PM PDT 24 |
| Finished | Jun 30 08:23:30 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-90d28f9a-81f7-4ba7-991e-15fb2af322f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257839790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1257839790 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.1202833244 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 345386865 ps |
| CPU time | 117.23 seconds |
| Started | Jun 30 08:11:21 PM PDT 24 |
| Finished | Jun 30 08:13:18 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-c49f5988-3068-469c-a770-5b438a9331fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202833244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.1202833244 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.689624595 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 724126815 ps |
| CPU time | 206.56 seconds |
| Started | Jun 30 08:11:22 PM PDT 24 |
| Finished | Jun 30 08:14:49 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-668ba4af-33e4-48a9-99f7-a59f2225db6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689624595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_reset_error.689624595 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.2437282591 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 1137095662 ps |
| CPU time | 54.2 seconds |
| Started | Jun 30 08:11:14 PM PDT 24 |
| Finished | Jun 30 08:12:09 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-f4073845-02ce-4f2c-8f15-76e3ed5e2337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437282591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2437282591 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.2274984034 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1088014420 ps |
| CPU time | 93.13 seconds |
| Started | Jun 30 08:28:37 PM PDT 24 |
| Finished | Jun 30 08:30:10 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-cc6ecc92-dc55-4660-84b0-91a7776108c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274984034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .2274984034 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.1586667006 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 757173323 ps |
| CPU time | 33 seconds |
| Started | Jun 30 08:28:40 PM PDT 24 |
| Finished | Jun 30 08:29:14 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-aec1e27a-d41b-41b1-81c9-9d6a90ffacaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586667006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.1586667006 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.2696855563 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 1494967097 ps |
| CPU time | 56.26 seconds |
| Started | Jun 30 08:28:38 PM PDT 24 |
| Finished | Jun 30 08:29:35 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-751cf8dd-210f-4951-afff-abceb5b9e7cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696855563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.2696855563 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.2449733293 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 985553080 ps |
| CPU time | 39.76 seconds |
| Started | Jun 30 08:28:30 PM PDT 24 |
| Finished | Jun 30 08:29:10 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-6e57e1a3-0243-42d0-b4c7-03613d01c7e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449733293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.2449733293 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.1366466199 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 9213036066 ps |
| CPU time | 98.01 seconds |
| Started | Jun 30 08:28:33 PM PDT 24 |
| Finished | Jun 30 08:30:12 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-2c238834-1274-4089-a4d6-647de939c484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366466199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.1366466199 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.669943383 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 49492733045 ps |
| CPU time | 839.85 seconds |
| Started | Jun 30 08:28:32 PM PDT 24 |
| Finished | Jun 30 08:42:32 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-704feccc-d1b5-4159-92a8-ddf91a717084 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669943383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.669943383 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.2800844482 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 292130872 ps |
| CPU time | 28.31 seconds |
| Started | Jun 30 08:28:32 PM PDT 24 |
| Finished | Jun 30 08:29:01 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-3173244e-2311-44c4-955b-1845a052a609 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800844482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.2800844482 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.3497065816 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 1369877812 ps |
| CPU time | 45.86 seconds |
| Started | Jun 30 08:28:40 PM PDT 24 |
| Finished | Jun 30 08:29:27 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-ef06da4c-1e02-4ad4-acf6-1b9e39129b2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497065816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.3497065816 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.133346502 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 48108299 ps |
| CPU time | 6.23 seconds |
| Started | Jun 30 08:28:28 PM PDT 24 |
| Finished | Jun 30 08:28:35 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-523eb547-aa66-451f-82e9-ccaa0e0c3ec5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133346502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.133346502 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.3081802310 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 10555694777 ps |
| CPU time | 112.46 seconds |
| Started | Jun 30 08:28:32 PM PDT 24 |
| Finished | Jun 30 08:30:25 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-0f06737f-2cbf-40de-b733-eb5854a06f7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081802310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.3081802310 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.2831395181 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 4432785568 ps |
| CPU time | 77.03 seconds |
| Started | Jun 30 08:28:32 PM PDT 24 |
| Finished | Jun 30 08:29:49 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-110c9516-e022-4f88-8831-51c99fc553cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831395181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.2831395181 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2503497679 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 42172833 ps |
| CPU time | 6.62 seconds |
| Started | Jun 30 08:28:32 PM PDT 24 |
| Finished | Jun 30 08:28:39 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-aad7a6cc-0706-4820-8411-fdd44541ef22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503497679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.2503497679 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.146152163 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 18412415511 ps |
| CPU time | 766.21 seconds |
| Started | Jun 30 08:28:39 PM PDT 24 |
| Finished | Jun 30 08:41:27 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-c49bf165-0938-41d6-a43f-44aea227c7d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146152163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.146152163 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.1167502740 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 4059226390 ps |
| CPU time | 368.78 seconds |
| Started | Jun 30 08:28:39 PM PDT 24 |
| Finished | Jun 30 08:34:49 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-99af82a8-b44e-4896-847c-be5dda69ea4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167502740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.1167502740 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.637580232 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 4226473257 ps |
| CPU time | 274.04 seconds |
| Started | Jun 30 08:28:39 PM PDT 24 |
| Finished | Jun 30 08:33:14 PM PDT 24 |
| Peak memory | 576448 kb |
| Host | smart-c051d593-8498-44cf-b0cc-a832bc48c4af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637580232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_ with_rand_reset.637580232 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.2904126076 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 3939330896 ps |
| CPU time | 458.12 seconds |
| Started | Jun 30 08:28:40 PM PDT 24 |
| Finished | Jun 30 08:36:19 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-a86ae9f6-89c1-4a5b-9f10-f964aa65a00c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904126076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.2904126076 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.1177037029 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 379819027 ps |
| CPU time | 19.11 seconds |
| Started | Jun 30 08:28:39 PM PDT 24 |
| Finished | Jun 30 08:28:59 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-57d2d850-a135-47f9-b02d-c8117590f80a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177037029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.1177037029 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.558710036 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 841899993 ps |
| CPU time | 32.22 seconds |
| Started | Jun 30 08:28:44 PM PDT 24 |
| Finished | Jun 30 08:29:16 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-5ae8f1b1-ed32-4305-92e8-57cff2473a84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558710036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device. 558710036 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.3682112379 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 5219182248 ps |
| CPU time | 92.53 seconds |
| Started | Jun 30 08:28:44 PM PDT 24 |
| Finished | Jun 30 08:30:17 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-97678285-f60c-4d20-a4f1-a218e5aa6d68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682112379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.3682112379 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2479571205 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 236471296 ps |
| CPU time | 31.21 seconds |
| Started | Jun 30 08:28:43 PM PDT 24 |
| Finished | Jun 30 08:29:15 PM PDT 24 |
| Peak memory | 573808 kb |
| Host | smart-1e28414d-7a1a-4bfa-96b2-550bec8f7a93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479571205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.2479571205 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.660302192 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 649762050 ps |
| CPU time | 21.73 seconds |
| Started | Jun 30 08:28:46 PM PDT 24 |
| Finished | Jun 30 08:29:08 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-4d717783-d122-4046-ad7c-ac76104a6ba7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660302192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.660302192 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.3435591958 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 156238899 ps |
| CPU time | 18.78 seconds |
| Started | Jun 30 08:28:41 PM PDT 24 |
| Finished | Jun 30 08:29:01 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-b74afe5b-47f7-4d35-a0ab-6cce0cdd241d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435591958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.3435591958 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.2545381230 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 99541458331 ps |
| CPU time | 1064.24 seconds |
| Started | Jun 30 08:28:45 PM PDT 24 |
| Finished | Jun 30 08:46:29 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-6916f04d-ba08-4cce-bcc9-ee3734614a29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545381230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.2545381230 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.2293336654 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 56136486182 ps |
| CPU time | 961.9 seconds |
| Started | Jun 30 08:28:45 PM PDT 24 |
| Finished | Jun 30 08:44:47 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-aafb592f-44a1-4740-a595-42053cbd3df7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293336654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.2293336654 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.3960599133 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 340761819 ps |
| CPU time | 38.66 seconds |
| Started | Jun 30 08:28:43 PM PDT 24 |
| Finished | Jun 30 08:29:21 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-895704a4-2538-42cb-a99a-4a290295a060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960599133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.3960599133 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.3731148659 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 1419420106 ps |
| CPU time | 42.91 seconds |
| Started | Jun 30 08:28:45 PM PDT 24 |
| Finished | Jun 30 08:29:28 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-d8829788-724e-439e-a0a0-3cdd245435a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731148659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.3731148659 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.4293176669 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 174207752 ps |
| CPU time | 8.95 seconds |
| Started | Jun 30 08:28:42 PM PDT 24 |
| Finished | Jun 30 08:28:51 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-798fc7db-c712-4a95-86c9-05153a831634 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293176669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.4293176669 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.2116110066 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 8166619139 ps |
| CPU time | 89.01 seconds |
| Started | Jun 30 08:28:46 PM PDT 24 |
| Finished | Jun 30 08:30:16 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-2930f433-96c9-43b3-be6b-a3656422e7e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116110066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.2116110066 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.1366813003 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 5792938827 ps |
| CPU time | 97.43 seconds |
| Started | Jun 30 08:28:44 PM PDT 24 |
| Finished | Jun 30 08:30:22 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-7874c588-a15e-4e6c-ba8e-6c73aa36f4f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366813003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.1366813003 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2042932811 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 51373115 ps |
| CPU time | 6.89 seconds |
| Started | Jun 30 08:28:46 PM PDT 24 |
| Finished | Jun 30 08:28:54 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-20c6f8f1-68df-40bd-8f01-7833a63f6873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042932811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.2042932811 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.1969103556 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 1593607896 ps |
| CPU time | 70.96 seconds |
| Started | Jun 30 08:28:46 PM PDT 24 |
| Finished | Jun 30 08:29:57 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-b147c87d-02c9-4442-bf75-1b59003a83eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969103556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.1969103556 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.1209046562 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 17952278735 ps |
| CPU time | 669.58 seconds |
| Started | Jun 30 08:28:42 PM PDT 24 |
| Finished | Jun 30 08:39:52 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-420bd9bc-a593-4f45-a44b-2776f3eea52b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209046562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.1209046562 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.4213049755 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 4248401926 ps |
| CPU time | 455.11 seconds |
| Started | Jun 30 08:28:43 PM PDT 24 |
| Finished | Jun 30 08:36:19 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-8b889731-ebe7-4906-9041-9cd3eaa171fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213049755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.4213049755 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.1549324129 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 9751690075 ps |
| CPU time | 480.55 seconds |
| Started | Jun 30 08:28:44 PM PDT 24 |
| Finished | Jun 30 08:36:45 PM PDT 24 |
| Peak memory | 576428 kb |
| Host | smart-96742ad4-f1e2-4277-b9d1-51e13c6c5ffd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549324129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.1549324129 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.3362204478 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 249776638 ps |
| CPU time | 32.15 seconds |
| Started | Jun 30 08:28:47 PM PDT 24 |
| Finished | Jun 30 08:29:19 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-d9480aef-dee9-414d-acbc-1438b34c6ac3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362204478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.3362204478 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.3558253498 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 2382657443 ps |
| CPU time | 107.13 seconds |
| Started | Jun 30 08:28:54 PM PDT 24 |
| Finished | Jun 30 08:30:42 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-9e715c4b-5591-4944-bdde-71663386164e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558253498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .3558253498 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.98702458 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 94951593373 ps |
| CPU time | 1748.29 seconds |
| Started | Jun 30 08:28:54 PM PDT 24 |
| Finished | Jun 30 08:58:04 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-41adf2cc-8125-4f20-9586-a0f5065eaf3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98702458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_de vice_slow_rsp.98702458 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1861416505 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 1313907202 ps |
| CPU time | 52.54 seconds |
| Started | Jun 30 08:29:01 PM PDT 24 |
| Finished | Jun 30 08:29:55 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-f7503e5c-d07f-4647-b935-7e80bd7aed6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861416505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.1861416505 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.209623224 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 606075560 ps |
| CPU time | 23.91 seconds |
| Started | Jun 30 08:28:55 PM PDT 24 |
| Finished | Jun 30 08:29:19 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-a42f482c-8297-40d2-9df1-71a29fa7d9d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209623224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.209623224 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.4094919520 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 304644565 ps |
| CPU time | 16.49 seconds |
| Started | Jun 30 08:28:50 PM PDT 24 |
| Finished | Jun 30 08:29:07 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-351143d3-ca42-42ae-bc69-d1e3fb69476e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094919520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.4094919520 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.1244817350 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 46373360443 ps |
| CPU time | 447.28 seconds |
| Started | Jun 30 08:28:55 PM PDT 24 |
| Finished | Jun 30 08:36:23 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-9f4a158f-18a0-4a4d-9c4d-93df34c0226c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244817350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.1244817350 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.3149334224 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 20546856091 ps |
| CPU time | 345.46 seconds |
| Started | Jun 30 08:28:55 PM PDT 24 |
| Finished | Jun 30 08:34:41 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-8abbc2f0-b7c4-438e-a010-35f636dc4dc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149334224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.3149334224 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.219427077 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 200140000 ps |
| CPU time | 19.5 seconds |
| Started | Jun 30 08:28:48 PM PDT 24 |
| Finished | Jun 30 08:29:08 PM PDT 24 |
| Peak memory | 575192 kb |
| Host | smart-30049ac7-ef07-4d71-a1b2-1ad049c0ea14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219427077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_dela ys.219427077 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.72032379 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 1154956567 ps |
| CPU time | 38.39 seconds |
| Started | Jun 30 08:28:54 PM PDT 24 |
| Finished | Jun 30 08:29:33 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-391735fe-9663-4811-bd89-1c3d3bbc145e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72032379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.72032379 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.76257324 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 178787566 ps |
| CPU time | 8.88 seconds |
| Started | Jun 30 08:28:46 PM PDT 24 |
| Finished | Jun 30 08:28:56 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-eb2d00e4-5f4b-4c04-bb75-9e0eeb13f335 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76257324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.76257324 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.911373066 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 8425177966 ps |
| CPU time | 85.41 seconds |
| Started | Jun 30 08:28:49 PM PDT 24 |
| Finished | Jun 30 08:30:15 PM PDT 24 |
| Peak memory | 566028 kb |
| Host | smart-24136e64-009d-4136-a4c0-91c942007b5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911373066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.911373066 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.1908222113 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 5007313907 ps |
| CPU time | 86.25 seconds |
| Started | Jun 30 08:28:49 PM PDT 24 |
| Finished | Jun 30 08:30:15 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-d53ebbe9-6184-4718-a1b6-2eaf7c9a15cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908222113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.1908222113 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.3282383595 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 44896089 ps |
| CPU time | 6.84 seconds |
| Started | Jun 30 08:28:49 PM PDT 24 |
| Finished | Jun 30 08:28:56 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-582311db-7438-4ee1-9eca-124c4a44806c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282383595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.3282383595 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.2705998455 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 630979028 ps |
| CPU time | 55.24 seconds |
| Started | Jun 30 08:29:00 PM PDT 24 |
| Finished | Jun 30 08:29:56 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-4735fcd8-0a62-49aa-ac7d-20fa7a6ed188 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705998455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.2705998455 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.3842387344 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 13184134395 ps |
| CPU time | 497.96 seconds |
| Started | Jun 30 08:29:06 PM PDT 24 |
| Finished | Jun 30 08:37:25 PM PDT 24 |
| Peak memory | 574828 kb |
| Host | smart-f0a9117a-dd58-41d4-baf9-922e91257751 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842387344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.3842387344 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.151245301 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 377681941 ps |
| CPU time | 110.7 seconds |
| Started | Jun 30 08:29:06 PM PDT 24 |
| Finished | Jun 30 08:30:57 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-d70003c1-8407-4432-a783-7f0507e0e2bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151245301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_ with_rand_reset.151245301 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.2489178436 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 3635347444 ps |
| CPU time | 318.34 seconds |
| Started | Jun 30 08:29:01 PM PDT 24 |
| Finished | Jun 30 08:34:20 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-9fd7a17c-1b30-4788-b920-a89c58312729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489178436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.2489178436 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.2429804407 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 238141635 ps |
| CPU time | 32.53 seconds |
| Started | Jun 30 08:28:56 PM PDT 24 |
| Finished | Jun 30 08:29:29 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-89ec4841-dbce-4be8-9eaa-0a82545057ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429804407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.2429804407 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.1999977002 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 46524125 ps |
| CPU time | 7.7 seconds |
| Started | Jun 30 08:29:07 PM PDT 24 |
| Finished | Jun 30 08:29:15 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-90733050-0be4-4f12-82a1-531c198b4a67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999977002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .1999977002 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.2746056232 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 80211286215 ps |
| CPU time | 1412.36 seconds |
| Started | Jun 30 08:29:06 PM PDT 24 |
| Finished | Jun 30 08:52:39 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-0716455f-eccb-4e42-a70c-b72aceb9f278 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746056232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.2746056232 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.3580072575 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 227711329 ps |
| CPU time | 27.69 seconds |
| Started | Jun 30 08:29:12 PM PDT 24 |
| Finished | Jun 30 08:29:41 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-77136c7c-d1a1-4f6e-a68f-ea6fb3fb5219 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580072575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.3580072575 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.1766888889 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 102033371 ps |
| CPU time | 11.71 seconds |
| Started | Jun 30 08:29:14 PM PDT 24 |
| Finished | Jun 30 08:29:26 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-da655a39-ff3f-4d59-9723-79c7942acb42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766888889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.1766888889 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.2774875471 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 485606180 ps |
| CPU time | 38.86 seconds |
| Started | Jun 30 08:29:07 PM PDT 24 |
| Finished | Jun 30 08:29:46 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-31913a54-2b11-46a1-a54f-1e98e44c42cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774875471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.2774875471 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.869274009 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 11276925932 ps |
| CPU time | 112.99 seconds |
| Started | Jun 30 08:29:07 PM PDT 24 |
| Finished | Jun 30 08:31:00 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-b234fe0a-910f-4e33-bd1e-04ca349239a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869274009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.869274009 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.870018238 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 29687433965 ps |
| CPU time | 531.45 seconds |
| Started | Jun 30 08:29:05 PM PDT 24 |
| Finished | Jun 30 08:37:58 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-f677a6f4-77e7-41db-b0da-6b9e77f3c47c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870018238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.870018238 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.1030259415 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 218262409 ps |
| CPU time | 21.3 seconds |
| Started | Jun 30 08:29:05 PM PDT 24 |
| Finished | Jun 30 08:29:27 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-772b7614-d6b5-464d-9d2c-bb8f110205d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030259415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.1030259415 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.2022067580 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 796057228 ps |
| CPU time | 27.11 seconds |
| Started | Jun 30 08:29:05 PM PDT 24 |
| Finished | Jun 30 08:29:33 PM PDT 24 |
| Peak memory | 575184 kb |
| Host | smart-1b2e33f0-d73e-4a70-abf3-6b567417ca23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022067580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.2022067580 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.631694429 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 43510415 ps |
| CPU time | 7.1 seconds |
| Started | Jun 30 08:29:01 PM PDT 24 |
| Finished | Jun 30 08:29:09 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-2ea6798e-a8a9-44bf-96b1-527645541f6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631694429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.631694429 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.2745797119 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 10048817664 ps |
| CPU time | 109.12 seconds |
| Started | Jun 30 08:29:06 PM PDT 24 |
| Finished | Jun 30 08:30:56 PM PDT 24 |
| Peak memory | 566000 kb |
| Host | smart-f7cd5a02-e1ea-4b4a-b7cf-a96ec7bc5277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745797119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.2745797119 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.1146060287 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 5135052595 ps |
| CPU time | 87.59 seconds |
| Started | Jun 30 08:29:08 PM PDT 24 |
| Finished | Jun 30 08:30:36 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-ad9840f8-22ff-4c35-8946-4349fcfab3c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146060287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.1146060287 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.4091048116 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 42345618 ps |
| CPU time | 6.68 seconds |
| Started | Jun 30 08:29:05 PM PDT 24 |
| Finished | Jun 30 08:29:12 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-636f0252-7d74-4468-aab1-e1025d0749cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091048116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.4091048116 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.68017931 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 3677396590 ps |
| CPU time | 309.8 seconds |
| Started | Jun 30 08:29:13 PM PDT 24 |
| Finished | Jun 30 08:34:23 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-5a4125c4-9888-45ea-aaaf-f09d53647deb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68017931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.68017931 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.4022062986 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 17045803823 ps |
| CPU time | 622.25 seconds |
| Started | Jun 30 08:29:13 PM PDT 24 |
| Finished | Jun 30 08:39:36 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-3b826c54-235d-4c92-b63f-d664ea49cab6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022062986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.4022062986 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1506486703 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 2413348709 ps |
| CPU time | 277.33 seconds |
| Started | Jun 30 08:29:12 PM PDT 24 |
| Finished | Jun 30 08:33:50 PM PDT 24 |
| Peak memory | 576436 kb |
| Host | smart-9320fd5c-1527-42d9-87a9-fd950bff2967 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506486703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.1506486703 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.734477153 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 394792593 ps |
| CPU time | 164.44 seconds |
| Started | Jun 30 08:29:12 PM PDT 24 |
| Finished | Jun 30 08:31:57 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-48468664-8c48-4f82-b772-c9ca8699e3d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734477153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_reset_error.734477153 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.1829944159 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 281865030 ps |
| CPU time | 38.34 seconds |
| Started | Jun 30 08:29:11 PM PDT 24 |
| Finished | Jun 30 08:29:50 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-5e561ab7-cffa-4b01-84f5-978e9b03fd04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829944159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.1829944159 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.4210379477 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 151215769 ps |
| CPU time | 13.25 seconds |
| Started | Jun 30 08:29:27 PM PDT 24 |
| Finished | Jun 30 08:29:41 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-f984f90b-4121-4bac-8113-803106ef8315 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210379477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .4210379477 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.4067298202 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 5612868396 ps |
| CPU time | 104.61 seconds |
| Started | Jun 30 08:29:27 PM PDT 24 |
| Finished | Jun 30 08:31:12 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-ac32c630-dcb3-4d25-8d43-545cedce45e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067298202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.4067298202 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.1664510076 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 106717782 ps |
| CPU time | 14.5 seconds |
| Started | Jun 30 08:29:29 PM PDT 24 |
| Finished | Jun 30 08:29:43 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-50679bf4-73d0-4c1e-8f40-19e5a66e8a44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664510076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.1664510076 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.2884253256 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 123972252 ps |
| CPU time | 8.39 seconds |
| Started | Jun 30 08:29:26 PM PDT 24 |
| Finished | Jun 30 08:29:35 PM PDT 24 |
| Peak memory | 565604 kb |
| Host | smart-1b85fd3c-4670-4779-99a8-944a655d5eea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884253256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.2884253256 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.344181362 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 1985590711 ps |
| CPU time | 77.75 seconds |
| Started | Jun 30 08:29:21 PM PDT 24 |
| Finished | Jun 30 08:30:39 PM PDT 24 |
| Peak memory | 575200 kb |
| Host | smart-705c5684-47d2-4234-9d7f-036d1ca4ef94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344181362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.344181362 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.3525904863 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 49137389111 ps |
| CPU time | 494.99 seconds |
| Started | Jun 30 08:29:17 PM PDT 24 |
| Finished | Jun 30 08:37:33 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-bad719bb-ed22-46dc-9519-56b8a6d43c14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525904863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.3525904863 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.4019274939 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 23670605192 ps |
| CPU time | 405.53 seconds |
| Started | Jun 30 08:29:26 PM PDT 24 |
| Finished | Jun 30 08:36:12 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-e79447a7-273b-44b5-8d1a-18cc95697e21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019274939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.4019274939 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.3697294459 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 421637747 ps |
| CPU time | 41.63 seconds |
| Started | Jun 30 08:29:19 PM PDT 24 |
| Finished | Jun 30 08:30:01 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-6e48d5c8-872c-455c-bc2e-8aa15520cd4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697294459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.3697294459 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.3853186709 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 329583931 ps |
| CPU time | 26.24 seconds |
| Started | Jun 30 08:29:27 PM PDT 24 |
| Finished | Jun 30 08:29:54 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-1004bc70-819d-4ea6-9c5b-3ee852aaff07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853186709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.3853186709 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.3181535033 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 211950435 ps |
| CPU time | 10 seconds |
| Started | Jun 30 08:29:13 PM PDT 24 |
| Finished | Jun 30 08:29:24 PM PDT 24 |
| Peak memory | 565892 kb |
| Host | smart-700ef4da-a1a2-4a2f-a35a-be734922c26f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181535033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.3181535033 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.1578557104 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 7026331444 ps |
| CPU time | 74.25 seconds |
| Started | Jun 30 08:29:19 PM PDT 24 |
| Finished | Jun 30 08:30:33 PM PDT 24 |
| Peak memory | 566036 kb |
| Host | smart-6cdb5fc5-0e4a-4984-81a6-f0668b633733 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578557104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.1578557104 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.1345028974 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 4065273635 ps |
| CPU time | 72.12 seconds |
| Started | Jun 30 08:29:18 PM PDT 24 |
| Finished | Jun 30 08:30:31 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-19ce61de-334c-44e8-9ef6-a8b5bc84f168 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345028974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.1345028974 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.2304120767 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 47337101 ps |
| CPU time | 6.86 seconds |
| Started | Jun 30 08:29:21 PM PDT 24 |
| Finished | Jun 30 08:29:28 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-d02576c5-6f3b-40ac-92f0-45237475900e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304120767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.2304120767 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.1020280174 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 2315139256 ps |
| CPU time | 178.03 seconds |
| Started | Jun 30 08:29:27 PM PDT 24 |
| Finished | Jun 30 08:32:26 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-34308a0c-2e94-43b8-a693-d313498887b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020280174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.1020280174 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.3632481737 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 7806343973 ps |
| CPU time | 247.68 seconds |
| Started | Jun 30 08:29:25 PM PDT 24 |
| Finished | Jun 30 08:33:33 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-6e3fd1da-cc31-4fa6-a231-9b11a1280518 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632481737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.3632481737 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.1229506441 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 642289406 ps |
| CPU time | 258.63 seconds |
| Started | Jun 30 08:29:29 PM PDT 24 |
| Finished | Jun 30 08:33:48 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-83992744-3c2a-49f7-bc82-450f1d7808ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229506441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.1229506441 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.20066058 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 270869508 ps |
| CPU time | 47.13 seconds |
| Started | Jun 30 08:29:27 PM PDT 24 |
| Finished | Jun 30 08:30:14 PM PDT 24 |
| Peak memory | 576432 kb |
| Host | smart-60a26981-b939-4f44-a8be-5a6c57a540a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20066058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_ with_reset_error.20066058 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.935343113 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 1085762545 ps |
| CPU time | 44.59 seconds |
| Started | Jun 30 08:29:24 PM PDT 24 |
| Finished | Jun 30 08:30:09 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-68b01131-67aa-47c9-b0a1-eee85d8c222a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935343113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.935343113 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.1233267224 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 2969114728 ps |
| CPU time | 122.31 seconds |
| Started | Jun 30 08:29:32 PM PDT 24 |
| Finished | Jun 30 08:31:36 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-49cf4ad2-e12d-4b6e-a74c-e2f5cd35872f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233267224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .1233267224 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.3157605262 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 2917398561 ps |
| CPU time | 52.12 seconds |
| Started | Jun 30 08:29:33 PM PDT 24 |
| Finished | Jun 30 08:30:26 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-5f0eb89a-0f5c-4a41-985d-e40118f3f9fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157605262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.3157605262 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.1135096859 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 161403418 ps |
| CPU time | 8.81 seconds |
| Started | Jun 30 08:29:35 PM PDT 24 |
| Finished | Jun 30 08:29:44 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-3577be7b-af75-47fd-8c3a-2acdd47cd964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135096859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.1135096859 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.3641714715 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 1413939328 ps |
| CPU time | 49.72 seconds |
| Started | Jun 30 08:29:32 PM PDT 24 |
| Finished | Jun 30 08:30:22 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-919ab3df-34e3-4eba-aedd-24ca94b32e7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641714715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.3641714715 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.2631344986 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 917130322 ps |
| CPU time | 33.76 seconds |
| Started | Jun 30 08:29:31 PM PDT 24 |
| Finished | Jun 30 08:30:05 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-2e3f2631-a5ae-4d9a-ab1b-811d111b4c0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631344986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.2631344986 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.3579634 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 4232777504 ps |
| CPU time | 47.41 seconds |
| Started | Jun 30 08:29:35 PM PDT 24 |
| Finished | Jun 30 08:30:23 PM PDT 24 |
| Peak memory | 566052 kb |
| Host | smart-43919437-f111-410c-bb9f-8e68085e89fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.3579634 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.3931937163 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 44889496050 ps |
| CPU time | 777.23 seconds |
| Started | Jun 30 08:29:32 PM PDT 24 |
| Finished | Jun 30 08:42:30 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-42ee8f07-1410-46db-99b1-5c8ad4b59322 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931937163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.3931937163 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.836138505 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 316115822 ps |
| CPU time | 30.59 seconds |
| Started | Jun 30 08:29:31 PM PDT 24 |
| Finished | Jun 30 08:30:02 PM PDT 24 |
| Peak memory | 575192 kb |
| Host | smart-81caabc1-2e27-4fbc-8d13-1c32b900dc36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836138505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_dela ys.836138505 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.3223065591 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 442942928 ps |
| CPU time | 15.74 seconds |
| Started | Jun 30 08:29:30 PM PDT 24 |
| Finished | Jun 30 08:29:46 PM PDT 24 |
| Peak memory | 575172 kb |
| Host | smart-b1dd078d-f8be-4883-8989-27eb7f258515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223065591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.3223065591 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.2431218048 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 59288176 ps |
| CPU time | 7.21 seconds |
| Started | Jun 30 08:29:25 PM PDT 24 |
| Finished | Jun 30 08:29:32 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-5e60f0de-3f36-4707-a718-3b92590008ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431218048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.2431218048 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.526738469 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 8281695871 ps |
| CPU time | 93.58 seconds |
| Started | Jun 30 08:29:31 PM PDT 24 |
| Finished | Jun 30 08:31:05 PM PDT 24 |
| Peak memory | 565996 kb |
| Host | smart-e8570e78-6363-4315-ae49-ffdce61e03d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526738469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.526738469 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.3477590461 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 6727256253 ps |
| CPU time | 110.11 seconds |
| Started | Jun 30 08:29:35 PM PDT 24 |
| Finished | Jun 30 08:31:26 PM PDT 24 |
| Peak memory | 566020 kb |
| Host | smart-69ad4177-e018-4ee4-8f20-32c83a7aeaf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477590461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.3477590461 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.210967543 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 40018225 ps |
| CPU time | 6.15 seconds |
| Started | Jun 30 08:29:30 PM PDT 24 |
| Finished | Jun 30 08:29:37 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-8ea51c8b-ce87-4236-a5ab-7b1032b65e06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210967543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delays .210967543 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.3603063575 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 4620215788 ps |
| CPU time | 406.36 seconds |
| Started | Jun 30 08:29:33 PM PDT 24 |
| Finished | Jun 30 08:36:20 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-fa3e0a70-ce68-4840-b7b4-0ba948b8a8d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603063575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.3603063575 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.2425621710 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 3792757936 ps |
| CPU time | 127.91 seconds |
| Started | Jun 30 08:29:31 PM PDT 24 |
| Finished | Jun 30 08:31:40 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-4343e8e4-29bd-4eb9-8853-4c03469ee395 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425621710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.2425621710 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.3189672928 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 1747460769 ps |
| CPU time | 308.21 seconds |
| Started | Jun 30 08:29:31 PM PDT 24 |
| Finished | Jun 30 08:34:40 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-2713bca2-94f0-4957-99a4-f7a164508233 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189672928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.3189672928 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.1566877323 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 11500740 ps |
| CPU time | 28.19 seconds |
| Started | Jun 30 08:29:32 PM PDT 24 |
| Finished | Jun 30 08:30:00 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-07ca993d-ed7a-4ae1-97be-28dd40bc324b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566877323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.1566877323 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.4200784267 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 131401775 ps |
| CPU time | 17.21 seconds |
| Started | Jun 30 08:29:32 PM PDT 24 |
| Finished | Jun 30 08:29:50 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-2f1eb127-df01-4ccf-b2e0-f3346533a029 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200784267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.4200784267 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.2472565943 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 2085128657 ps |
| CPU time | 87.7 seconds |
| Started | Jun 30 08:29:38 PM PDT 24 |
| Finished | Jun 30 08:31:06 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-704fe0a3-d50f-465d-8951-e06a8f6a3b8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472565943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .2472565943 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2454559365 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 29312566109 ps |
| CPU time | 523.92 seconds |
| Started | Jun 30 08:29:37 PM PDT 24 |
| Finished | Jun 30 08:38:22 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-697bbad1-de6d-470c-9090-4f66b89b470f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454559365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.2454559365 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.3652817399 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 784884085 ps |
| CPU time | 33.3 seconds |
| Started | Jun 30 08:29:40 PM PDT 24 |
| Finished | Jun 30 08:30:14 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-8affac7d-31d3-46f6-b31f-7343492b30be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652817399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.3652817399 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.4100376338 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 534145723 ps |
| CPU time | 20.08 seconds |
| Started | Jun 30 08:29:38 PM PDT 24 |
| Finished | Jun 30 08:29:59 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-edecc7ad-0ad2-4263-9248-c55d5b6efc26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100376338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.4100376338 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.3843615032 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 159259691 ps |
| CPU time | 8.98 seconds |
| Started | Jun 30 08:29:36 PM PDT 24 |
| Finished | Jun 30 08:29:46 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-8353885b-f672-4659-a92e-756df4bae2be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843615032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.3843615032 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.3873580258 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 66559966223 ps |
| CPU time | 676.8 seconds |
| Started | Jun 30 08:29:36 PM PDT 24 |
| Finished | Jun 30 08:40:53 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-e9025a75-ffc1-4752-8575-ee9b631b8db8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873580258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.3873580258 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.1180517739 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 54070296337 ps |
| CPU time | 879.98 seconds |
| Started | Jun 30 08:29:40 PM PDT 24 |
| Finished | Jun 30 08:44:21 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-6f578f4c-8c24-4221-8131-faa7ada52928 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180517739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.1180517739 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.966856524 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 83015552 ps |
| CPU time | 9.23 seconds |
| Started | Jun 30 08:29:37 PM PDT 24 |
| Finished | Jun 30 08:29:46 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-a385b7eb-c252-4e0e-9dc8-bb121707056b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966856524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_dela ys.966856524 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.2348114921 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 945134209 ps |
| CPU time | 31.44 seconds |
| Started | Jun 30 08:29:36 PM PDT 24 |
| Finished | Jun 30 08:30:08 PM PDT 24 |
| Peak memory | 575148 kb |
| Host | smart-b48d00d5-683c-4f4e-95cb-10bebfb5ee06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348114921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.2348114921 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.1238895924 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 199408709 ps |
| CPU time | 8.65 seconds |
| Started | Jun 30 08:29:29 PM PDT 24 |
| Finished | Jun 30 08:29:38 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-c7263e17-5a79-49e8-8374-b21065ec00cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238895924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.1238895924 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.2208005381 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 6007595798 ps |
| CPU time | 64.66 seconds |
| Started | Jun 30 08:29:39 PM PDT 24 |
| Finished | Jun 30 08:30:44 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-05139398-6e67-435e-afd7-adb9aa586620 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208005381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.2208005381 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.4237739794 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 4450272973 ps |
| CPU time | 79.59 seconds |
| Started | Jun 30 08:29:39 PM PDT 24 |
| Finished | Jun 30 08:30:59 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-b4c26d82-a2a1-4d9d-9785-d9f654e9863e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237739794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.4237739794 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.1989137498 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 47643277 ps |
| CPU time | 6.43 seconds |
| Started | Jun 30 08:29:38 PM PDT 24 |
| Finished | Jun 30 08:29:45 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-348de8d2-4caf-49e0-9b47-0a00493d7f91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989137498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.1989137498 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.708320357 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 3873991390 ps |
| CPU time | 301.77 seconds |
| Started | Jun 30 08:29:38 PM PDT 24 |
| Finished | Jun 30 08:34:40 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-deb38487-4a71-4346-80e8-9a0e76f0010c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708320357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.708320357 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.97774188 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 9516018064 ps |
| CPU time | 366.87 seconds |
| Started | Jun 30 08:29:39 PM PDT 24 |
| Finished | Jun 30 08:35:46 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-5d7145b8-fee4-42db-bcb0-0b504e5baf71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97774188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.97774188 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.2890322922 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 20971758772 ps |
| CPU time | 1281.33 seconds |
| Started | Jun 30 08:29:39 PM PDT 24 |
| Finished | Jun 30 08:51:01 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-985407a0-9f30-4f79-b7a0-27686d6591b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890322922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.2890322922 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.261506679 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 846755668 ps |
| CPU time | 226.6 seconds |
| Started | Jun 30 08:29:45 PM PDT 24 |
| Finished | Jun 30 08:33:32 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-7fd2b77f-5eee-4e3d-b928-7bbf571583d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261506679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_reset_error.261506679 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.367797513 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1373524164 ps |
| CPU time | 60.43 seconds |
| Started | Jun 30 08:29:36 PM PDT 24 |
| Finished | Jun 30 08:30:37 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-2a9bc475-939b-4b47-bc87-87ec5aa8dfe3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367797513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.367797513 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.484954257 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 3261937263 ps |
| CPU time | 146.73 seconds |
| Started | Jun 30 08:29:49 PM PDT 24 |
| Finished | Jun 30 08:32:17 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-728c2e8a-c254-49aa-b35a-249828989317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484954257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device. 484954257 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.2038649676 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 126568378674 ps |
| CPU time | 2284.37 seconds |
| Started | Jun 30 08:29:49 PM PDT 24 |
| Finished | Jun 30 09:07:54 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-704fa70d-148a-4dad-afa1-d1749f61088d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038649676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.2038649676 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.76709957 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 22882395 ps |
| CPU time | 6.08 seconds |
| Started | Jun 30 08:29:50 PM PDT 24 |
| Finished | Jun 30 08:29:57 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-95e59348-89ca-4a3f-82b7-bc2d66dd24d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76709957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_addr.76709957 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.3491992325 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 241872224 ps |
| CPU time | 22.13 seconds |
| Started | Jun 30 08:29:50 PM PDT 24 |
| Finished | Jun 30 08:30:13 PM PDT 24 |
| Peak memory | 573820 kb |
| Host | smart-412d6670-fee5-41bd-83f2-951f22284dc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491992325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.3491992325 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.2958955746 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 328647061 ps |
| CPU time | 32.75 seconds |
| Started | Jun 30 08:29:42 PM PDT 24 |
| Finished | Jun 30 08:30:15 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-788343fe-db68-4df6-b9d0-e39552fc647d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958955746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.2958955746 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.3372112072 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 25038776595 ps |
| CPU time | 280.59 seconds |
| Started | Jun 30 08:29:46 PM PDT 24 |
| Finished | Jun 30 08:34:27 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-711f2a33-0875-41ef-a575-68c8ecf747a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372112072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.3372112072 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.1683862281 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 39694047646 ps |
| CPU time | 705.95 seconds |
| Started | Jun 30 08:29:43 PM PDT 24 |
| Finished | Jun 30 08:41:29 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-411ae79b-1e63-469a-a878-4c3c4c0fc0c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683862281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.1683862281 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.3211770606 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 483355350 ps |
| CPU time | 40.54 seconds |
| Started | Jun 30 08:29:46 PM PDT 24 |
| Finished | Jun 30 08:30:26 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-4e4acead-abe6-473a-8532-0f7476c1f2fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211770606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.3211770606 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.4257356496 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 1171551667 ps |
| CPU time | 40.15 seconds |
| Started | Jun 30 08:29:50 PM PDT 24 |
| Finished | Jun 30 08:30:31 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-2d0aa760-a4b2-4b17-8722-4d21f5e4d157 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257356496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.4257356496 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.1207324737 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 54185481 ps |
| CPU time | 7.14 seconds |
| Started | Jun 30 08:29:43 PM PDT 24 |
| Finished | Jun 30 08:29:51 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-7cd4a83d-8115-46fa-ba18-79ff804bac2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207324737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.1207324737 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.1816497242 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 7554214267 ps |
| CPU time | 85.44 seconds |
| Started | Jun 30 08:29:45 PM PDT 24 |
| Finished | Jun 30 08:31:11 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-07bbb2c2-c70d-440f-a16e-20a241359659 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816497242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.1816497242 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.221432909 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 4111638300 ps |
| CPU time | 70.31 seconds |
| Started | Jun 30 08:29:44 PM PDT 24 |
| Finished | Jun 30 08:30:55 PM PDT 24 |
| Peak memory | 565912 kb |
| Host | smart-c43a2eea-7f7e-4df9-8d2e-d2c0dc7bd93d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221432909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.221432909 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.3167562185 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 43861341 ps |
| CPU time | 6.59 seconds |
| Started | Jun 30 08:29:44 PM PDT 24 |
| Finished | Jun 30 08:29:51 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-174cc172-644f-4214-8fef-b96c39e93353 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167562185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.3167562185 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.2795931915 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 5728225298 ps |
| CPU time | 236.58 seconds |
| Started | Jun 30 08:29:50 PM PDT 24 |
| Finished | Jun 30 08:33:48 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-608de3f4-a878-4999-b6b6-dd41c6392086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795931915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.2795931915 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.2810176747 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 19061388305 ps |
| CPU time | 788.93 seconds |
| Started | Jun 30 08:29:59 PM PDT 24 |
| Finished | Jun 30 08:43:08 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-c950c0f1-199a-448c-93cf-e1047509baed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810176747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.2810176747 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.2787463951 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 8197567363 ps |
| CPU time | 332.27 seconds |
| Started | Jun 30 08:29:49 PM PDT 24 |
| Finished | Jun 30 08:35:21 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-cb4bd4d5-2f50-4998-8f1d-2157b6d24a24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787463951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.2787463951 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.2150729766 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 5185547005 ps |
| CPU time | 296.18 seconds |
| Started | Jun 30 08:29:54 PM PDT 24 |
| Finished | Jun 30 08:34:51 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-ddc30f6f-e6c9-4a9d-8e56-e0d8b31d6685 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150729766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.2150729766 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.362429823 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 1214957030 ps |
| CPU time | 52.24 seconds |
| Started | Jun 30 08:29:49 PM PDT 24 |
| Finished | Jun 30 08:30:43 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-52a17cb0-deea-4b27-b86c-67fc79316612 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362429823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.362429823 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.1723630613 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 1242601361 ps |
| CPU time | 59.38 seconds |
| Started | Jun 30 08:29:56 PM PDT 24 |
| Finished | Jun 30 08:30:55 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-b1857dd9-d8d3-49e3-a35c-7b00b4781b06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723630613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .1723630613 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.1407732137 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 142218129559 ps |
| CPU time | 2348.21 seconds |
| Started | Jun 30 08:29:54 PM PDT 24 |
| Finished | Jun 30 09:09:02 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-d6c4d5fc-adb6-4af5-9b16-1a2c26a96c07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407732137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.1407732137 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.1128294560 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 71681186 ps |
| CPU time | 10.45 seconds |
| Started | Jun 30 08:30:00 PM PDT 24 |
| Finished | Jun 30 08:30:11 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-56b8e210-806f-459b-befa-bc70830101c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128294560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.1128294560 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.2394358642 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 176080827 ps |
| CPU time | 19.55 seconds |
| Started | Jun 30 08:29:56 PM PDT 24 |
| Finished | Jun 30 08:30:16 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-e6a61e1b-158d-4288-a461-abba3d4c5abd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394358642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.2394358642 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.3819055520 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 102232327050 ps |
| CPU time | 1024.93 seconds |
| Started | Jun 30 08:29:59 PM PDT 24 |
| Finished | Jun 30 08:47:04 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-d177b7af-5d21-407f-a348-b764c26e085f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819055520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.3819055520 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.821426562 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 65155333111 ps |
| CPU time | 1117.46 seconds |
| Started | Jun 30 08:29:57 PM PDT 24 |
| Finished | Jun 30 08:48:35 PM PDT 24 |
| Peak memory | 575108 kb |
| Host | smart-1abc99b4-4862-4256-a634-fdf62bdd9b29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821426562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.821426562 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.4235450509 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 261885510 ps |
| CPU time | 26.83 seconds |
| Started | Jun 30 08:29:56 PM PDT 24 |
| Finished | Jun 30 08:30:23 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-8e625705-49fb-4c4a-a236-fca75d3423db |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235450509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.4235450509 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.937557515 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 2721572883 ps |
| CPU time | 88.04 seconds |
| Started | Jun 30 08:29:56 PM PDT 24 |
| Finished | Jun 30 08:31:24 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-9ad8b4b2-4900-47ab-b4cd-e0be810c6972 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937557515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.937557515 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.632515388 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 36359938 ps |
| CPU time | 6.06 seconds |
| Started | Jun 30 08:29:55 PM PDT 24 |
| Finished | Jun 30 08:30:02 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-fe16e40c-957a-4538-a1f2-aef0b9aff76f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632515388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.632515388 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.1040992934 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 6530059716 ps |
| CPU time | 68.61 seconds |
| Started | Jun 30 08:29:59 PM PDT 24 |
| Finished | Jun 30 08:31:08 PM PDT 24 |
| Peak memory | 565992 kb |
| Host | smart-ea6570ea-746e-4b75-989b-2a210495672d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040992934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.1040992934 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.3364287305 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 4992381953 ps |
| CPU time | 87.66 seconds |
| Started | Jun 30 08:30:00 PM PDT 24 |
| Finished | Jun 30 08:31:28 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-e75e8ad9-8fdc-4fb7-9746-d141f041c631 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364287305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.3364287305 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2705688294 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 53867612 ps |
| CPU time | 7.25 seconds |
| Started | Jun 30 08:29:54 PM PDT 24 |
| Finished | Jun 30 08:30:02 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-7c6c32f2-8dd0-4a97-9faf-4fede0fed594 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705688294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.2705688294 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.3456996393 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 13918297714 ps |
| CPU time | 506.12 seconds |
| Started | Jun 30 08:30:04 PM PDT 24 |
| Finished | Jun 30 08:38:30 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-f6085482-072f-487c-80a6-cc745bb85e68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456996393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.3456996393 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.3614999892 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1094623235 ps |
| CPU time | 99.52 seconds |
| Started | Jun 30 08:30:04 PM PDT 24 |
| Finished | Jun 30 08:31:44 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-8da6dbda-c7f9-48a4-981a-e345e69e1bd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614999892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.3614999892 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.4163772643 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 48310015 ps |
| CPU time | 17.65 seconds |
| Started | Jun 30 08:30:01 PM PDT 24 |
| Finished | Jun 30 08:30:19 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-23639547-4ac5-4b87-b688-bd336388fdcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163772643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.4163772643 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.1015659948 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 1264467907 ps |
| CPU time | 57.73 seconds |
| Started | Jun 30 08:29:58 PM PDT 24 |
| Finished | Jun 30 08:30:56 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-13efcaba-5312-4d66-8b75-71a2507a0d4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015659948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.1015659948 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.297568279 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 1540488937 ps |
| CPU time | 58.6 seconds |
| Started | Jun 30 08:30:04 PM PDT 24 |
| Finished | Jun 30 08:31:03 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-752ac71f-ae57-4955-97b2-393b2dca542f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297568279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device. 297568279 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.525101093 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 56683515827 ps |
| CPU time | 997.15 seconds |
| Started | Jun 30 08:30:06 PM PDT 24 |
| Finished | Jun 30 08:46:44 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-714aa9a6-436d-4160-82db-73f2af6cfc2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525101093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_d evice_slow_rsp.525101093 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.3804406630 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 345097189 ps |
| CPU time | 31.8 seconds |
| Started | Jun 30 08:30:07 PM PDT 24 |
| Finished | Jun 30 08:30:39 PM PDT 24 |
| Peak memory | 573808 kb |
| Host | smart-5d3bb4cd-76ff-4efc-ae8f-5f7573befeab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804406630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.3804406630 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.1207308345 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 1683249642 ps |
| CPU time | 67.54 seconds |
| Started | Jun 30 08:30:06 PM PDT 24 |
| Finished | Jun 30 08:31:14 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-c5a76d23-4394-45a2-863a-d4f2124748cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207308345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.1207308345 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.2394091233 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 1846435449 ps |
| CPU time | 73.18 seconds |
| Started | Jun 30 08:30:01 PM PDT 24 |
| Finished | Jun 30 08:31:15 PM PDT 24 |
| Peak memory | 575172 kb |
| Host | smart-f8380a1e-60db-4788-9b17-b9b756c7f014 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394091233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.2394091233 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.464921397 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 25193039919 ps |
| CPU time | 262.17 seconds |
| Started | Jun 30 08:30:06 PM PDT 24 |
| Finished | Jun 30 08:34:28 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-6daf8392-376b-4dc3-b2af-37b83c31c5c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464921397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.464921397 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.780026342 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 46070220650 ps |
| CPU time | 775.84 seconds |
| Started | Jun 30 08:30:06 PM PDT 24 |
| Finished | Jun 30 08:43:03 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-1a5b51cf-6095-41b5-a13d-3ead3a899699 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780026342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.780026342 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.1727876870 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 84089705 ps |
| CPU time | 9.17 seconds |
| Started | Jun 30 08:30:06 PM PDT 24 |
| Finished | Jun 30 08:30:16 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-7daf1bca-ea18-4b9f-93df-b6fe3514ab24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727876870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.1727876870 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.2218869477 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 1294956068 ps |
| CPU time | 39.56 seconds |
| Started | Jun 30 08:30:06 PM PDT 24 |
| Finished | Jun 30 08:30:45 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-324da193-4ff4-4098-b7df-45f5efeed8ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218869477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.2218869477 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.3776858840 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 214735977 ps |
| CPU time | 9.81 seconds |
| Started | Jun 30 08:30:03 PM PDT 24 |
| Finished | Jun 30 08:30:13 PM PDT 24 |
| Peak memory | 565968 kb |
| Host | smart-f24adcc9-f97b-4201-9afd-2a4b58b6e0f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776858840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.3776858840 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.351557460 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 11027745941 ps |
| CPU time | 118.71 seconds |
| Started | Jun 30 08:30:04 PM PDT 24 |
| Finished | Jun 30 08:32:03 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-f3a2a38c-c61d-40e8-8524-df36ef6cd6d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351557460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.351557460 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.2327982887 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 4380316137 ps |
| CPU time | 69.59 seconds |
| Started | Jun 30 08:30:02 PM PDT 24 |
| Finished | Jun 30 08:31:12 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-0f1a2b72-2ff4-414b-9fc1-ac53aa086822 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327982887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.2327982887 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.3948963346 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 43304517 ps |
| CPU time | 6.61 seconds |
| Started | Jun 30 08:30:01 PM PDT 24 |
| Finished | Jun 30 08:30:09 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-1becb94f-5131-40d2-af48-7d9b5e77a3e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948963346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.3948963346 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.4011586642 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 5071638058 ps |
| CPU time | 157.89 seconds |
| Started | Jun 30 08:30:11 PM PDT 24 |
| Finished | Jun 30 08:32:49 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-cb31f572-680c-4dc2-b9ba-ee2f817489e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011586642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.4011586642 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.2170797263 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 16659836902 ps |
| CPU time | 536.24 seconds |
| Started | Jun 30 08:30:13 PM PDT 24 |
| Finished | Jun 30 08:39:10 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-cae38e1e-62c5-4011-ad64-cf4a435969b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170797263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.2170797263 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.693583720 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 2653254885 ps |
| CPU time | 260.62 seconds |
| Started | Jun 30 08:30:13 PM PDT 24 |
| Finished | Jun 30 08:34:34 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-425b1c81-8347-455b-9c95-3689a2abe33a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693583720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_ with_rand_reset.693583720 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.2046171505 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 326825751 ps |
| CPU time | 125.12 seconds |
| Started | Jun 30 08:30:15 PM PDT 24 |
| Finished | Jun 30 08:32:20 PM PDT 24 |
| Peak memory | 577400 kb |
| Host | smart-72760b30-0101-40f8-94a9-9caaacb069d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046171505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al l_with_reset_error.2046171505 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.2731616479 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 1024440838 ps |
| CPU time | 46.26 seconds |
| Started | Jun 30 08:30:06 PM PDT 24 |
| Finished | Jun 30 08:30:53 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-c30f33b9-6d2a-4f14-8153-d839e1c15a03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731616479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.2731616479 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.1293008461 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 13267277504 ps |
| CPU time | 1654.01 seconds |
| Started | Jun 30 07:25:58 PM PDT 24 |
| Finished | Jun 30 07:53:33 PM PDT 24 |
| Peak memory | 607240 kb |
| Host | smart-9d56f453-ad83-458e-a182-5ba738cb5c1f |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293008461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.1 293008461 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.949879133 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 3251352740 ps |
| CPU time | 291.64 seconds |
| Started | Jun 30 07:28:31 PM PDT 24 |
| Finished | Jun 30 07:33:23 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-70984be4-df65-4cec-99e1-34fae555dca8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=949879133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.949879133 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.1711749830 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 3314329916 ps |
| CPU time | 255.49 seconds |
| Started | Jun 30 07:28:36 PM PDT 24 |
| Finished | Jun 30 07:32:52 PM PDT 24 |
| Peak memory | 607624 kb |
| Host | smart-a1705451-70ac-455f-b861-38e679f1a0bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711749830 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.1711749830 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1825734177 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 2672253581 ps |
| CPU time | 213.78 seconds |
| Started | Jun 30 07:29:34 PM PDT 24 |
| Finished | Jun 30 07:33:08 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-6e739e01-d060-454f-b444-b52ef2020b7b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825 734177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.1825734177 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3213729369 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2987299374 ps |
| CPU time | 255.6 seconds |
| Started | Jun 30 07:35:27 PM PDT 24 |
| Finished | Jun 30 07:39:43 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-8ca8fa5a-e322-45ea-a15f-5fb1b71f2f9d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213729369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.3213729369 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.328924286 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 2710107844 ps |
| CPU time | 284.02 seconds |
| Started | Jun 30 07:31:24 PM PDT 24 |
| Finished | Jun 30 07:36:08 PM PDT 24 |
| Peak memory | 609116 kb |
| Host | smart-e11df8dc-2b0e-406d-816c-78266d121874 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328924286 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.328924286 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.593466498 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 2666579524 ps |
| CPU time | 289.48 seconds |
| Started | Jun 30 07:28:23 PM PDT 24 |
| Finished | Jun 30 07:33:12 PM PDT 24 |
| Peak memory | 607084 kb |
| Host | smart-bb2a68de-4bef-4048-a354-55a55dfd18a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593466498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.593466498 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.726412631 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 3786181102 ps |
| CPU time | 402.17 seconds |
| Started | Jun 30 07:28:33 PM PDT 24 |
| Finished | Jun 30 07:35:16 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-6bbf8fb4-d02c-42ae-bbaa-fe7c383fe2a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726412631 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.726412631 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.3056849838 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 2638605118 ps |
| CPU time | 218.31 seconds |
| Started | Jun 30 07:40:35 PM PDT 24 |
| Finished | Jun 30 07:44:14 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-ba36f85f-2ac5-4317-be91-9299c35b331d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056849838 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.3056849838 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3817367363 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 3652479888 ps |
| CPU time | 383.6 seconds |
| Started | Jun 30 07:28:41 PM PDT 24 |
| Finished | Jun 30 07:35:05 PM PDT 24 |
| Peak memory | 607464 kb |
| Host | smart-4eaa8bbf-5b6f-40f1-9985-c488a091f9bb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3817367363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.3817367363 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3569967954 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 5370339894 ps |
| CPU time | 605.51 seconds |
| Started | Jun 30 07:29:02 PM PDT 24 |
| Finished | Jun 30 07:39:08 PM PDT 24 |
| Peak memory | 617288 kb |
| Host | smart-052e23ea-3068-48b7-92c6-27abdd293938 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3569967954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.3569967954 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1553284912 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 6499846448 ps |
| CPU time | 1470.29 seconds |
| Started | Jun 30 07:29:04 PM PDT 24 |
| Finished | Jun 30 07:53:35 PM PDT 24 |
| Peak memory | 607880 kb |
| Host | smart-669b7bb3-376b-4acc-bda7-77bcb7e1aab0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1553284912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.1553284912 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1548082397 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 7865316216 ps |
| CPU time | 1796.22 seconds |
| Started | Jun 30 07:28:58 PM PDT 24 |
| Finished | Jun 30 07:58:55 PM PDT 24 |
| Peak memory | 608168 kb |
| Host | smart-4f0a4702-f8fd-4382-8265-c60b3dc2dbf5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548082397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.1548082397 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.183929931 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 13039263852 ps |
| CPU time | 1249.67 seconds |
| Started | Jun 30 07:28:50 PM PDT 24 |
| Finished | Jun 30 07:49:40 PM PDT 24 |
| Peak memory | 609108 kb |
| Host | smart-53d46e3f-77c9-4b0b-acfd-966d1538135f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183929931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.183929931 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3216980258 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 8650775820 ps |
| CPU time | 1624.99 seconds |
| Started | Jun 30 07:30:36 PM PDT 24 |
| Finished | Jun 30 07:57:42 PM PDT 24 |
| Peak memory | 608172 kb |
| Host | smart-8255c954-c239-4bb2-8dee-dd2e5f50e703 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3216980258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.3216980258 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1087403770 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 5695791192 ps |
| CPU time | 600.52 seconds |
| Started | Jun 30 07:28:52 PM PDT 24 |
| Finished | Jun 30 07:38:54 PM PDT 24 |
| Peak memory | 606892 kb |
| Host | smart-3c950f0f-a8c5-4505-a826-77c7f59bc4e9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1087403770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.1087403770 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.3476708315 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3141214174 ps |
| CPU time | 353.08 seconds |
| Started | Jun 30 07:29:55 PM PDT 24 |
| Finished | Jun 30 07:35:48 PM PDT 24 |
| Peak memory | 607140 kb |
| Host | smart-4a0e203c-1385-4ee1-953d-f1e9a471be71 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476708315 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.3476708315 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2388966665 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 6683341580 ps |
| CPU time | 301.16 seconds |
| Started | Jun 30 07:28:28 PM PDT 24 |
| Finished | Jun 30 07:33:29 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-3c6b5c25-e006-41df-b237-804cb34bf2ac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2388966665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2388966665 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2846050673 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 3496177016 ps |
| CPU time | 312.95 seconds |
| Started | Jun 30 07:39:55 PM PDT 24 |
| Finished | Jun 30 07:45:08 PM PDT 24 |
| Peak memory | 607416 kb |
| Host | smart-9007768a-a4ad-4ce1-a387-4c481239a8c5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846050673 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.2846050673 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3031811441 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 9772698840 ps |
| CPU time | 839.76 seconds |
| Started | Jun 30 07:28:32 PM PDT 24 |
| Finished | Jun 30 07:42:32 PM PDT 24 |
| Peak memory | 609236 kb |
| Host | smart-35f17536-ff64-4625-9644-9ddae5c06b97 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3031811441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.3031811441 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.621477205 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 5095466728 ps |
| CPU time | 640.49 seconds |
| Started | Jun 30 07:28:32 PM PDT 24 |
| Finished | Jun 30 07:39:13 PM PDT 24 |
| Peak memory | 608316 kb |
| Host | smart-df5f1e2b-4804-4e97-a48d-cdc77b92e705 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =621477205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.621477205 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.1202147958 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 7535787362 ps |
| CPU time | 1165.54 seconds |
| Started | Jun 30 07:33:27 PM PDT 24 |
| Finished | Jun 30 07:52:53 PM PDT 24 |
| Peak memory | 613760 kb |
| Host | smart-5aa92790-0939-4048-a31e-12d57b8b0049 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202147958 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.1202147958 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2101967343 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 4086491672 ps |
| CPU time | 637.31 seconds |
| Started | Jun 30 07:32:58 PM PDT 24 |
| Finished | Jun 30 07:43:36 PM PDT 24 |
| Peak memory | 609636 kb |
| Host | smart-1a5e6881-2571-4ef9-a13c-15976616b595 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101967343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2101967343 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.306312753 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 4280960972 ps |
| CPU time | 671.15 seconds |
| Started | Jun 30 07:32:59 PM PDT 24 |
| Finished | Jun 30 07:44:11 PM PDT 24 |
| Peak memory | 608608 kb |
| Host | smart-a813f88c-fc77-4d4b-8629-0d60d0e59eb2 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306312753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.306312753 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2852320384 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 3957686680 ps |
| CPU time | 600.05 seconds |
| Started | Jun 30 07:32:21 PM PDT 24 |
| Finished | Jun 30 07:42:21 PM PDT 24 |
| Peak memory | 611920 kb |
| Host | smart-6bd79f8c-7fd3-4ce9-8a9f-ff84c62a2e1c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852320384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2852320384 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1669594782 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 5317319374 ps |
| CPU time | 615.3 seconds |
| Started | Jun 30 07:32:14 PM PDT 24 |
| Finished | Jun 30 07:42:29 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-4134e12f-c2cb-4cbf-9a6e-3487081a0010 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669594782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1669594782 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.458922425 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 4392597932 ps |
| CPU time | 636.42 seconds |
| Started | Jun 30 07:32:03 PM PDT 24 |
| Finished | Jun 30 07:42:40 PM PDT 24 |
| Peak memory | 611892 kb |
| Host | smart-407c54be-f3f6-49d3-b0f6-ebfff175ba9e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458922425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.458922425 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.2075410782 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 2932584748 ps |
| CPU time | 274.13 seconds |
| Started | Jun 30 07:33:25 PM PDT 24 |
| Finished | Jun 30 07:38:00 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-09dbc568-a8f9-443f-b6bd-62280db23d0c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075410782 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.2075410782 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.533466557 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 4046341368 ps |
| CPU time | 385.5 seconds |
| Started | Jun 30 07:31:54 PM PDT 24 |
| Finished | Jun 30 07:38:20 PM PDT 24 |
| Peak memory | 607024 kb |
| Host | smart-46e5269a-6ca4-4f68-9b40-ae9c502b7893 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533466557 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.533466557 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3251326791 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 2719920350 ps |
| CPU time | 136.01 seconds |
| Started | Jun 30 07:37:15 PM PDT 24 |
| Finished | Jun 30 07:39:32 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-5793f92d-df0d-4c5b-9620-e2cd89a9f428 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251326791 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.3251326791 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3792970174 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 4266518616 ps |
| CPU time | 483.7 seconds |
| Started | Jun 30 07:35:10 PM PDT 24 |
| Finished | Jun 30 07:43:14 PM PDT 24 |
| Peak memory | 607684 kb |
| Host | smart-2a02af90-37bd-42f4-bcb6-00d544d0ae8e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792970174 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.3792970174 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2860150753 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 5205730414 ps |
| CPU time | 625.01 seconds |
| Started | Jun 30 07:32:26 PM PDT 24 |
| Finished | Jun 30 07:42:51 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-48ef60f6-4c0a-4844-a065-691e83a4d252 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860150753 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.2860150753 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1000257386 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 5149387656 ps |
| CPU time | 438.22 seconds |
| Started | Jun 30 07:33:12 PM PDT 24 |
| Finished | Jun 30 07:40:30 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-f2f58cd1-1193-4056-91e8-121727a6f421 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000257386 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.1000257386 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1880671695 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 4685298864 ps |
| CPU time | 483.46 seconds |
| Started | Jun 30 07:35:25 PM PDT 24 |
| Finished | Jun 30 07:43:29 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-9f533f10-fb4c-4cc0-9b5e-0bac12a90e2f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880671695 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.1880671695 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3129677663 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 11072697340 ps |
| CPU time | 1433.1 seconds |
| Started | Jun 30 07:31:30 PM PDT 24 |
| Finished | Jun 30 07:55:24 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-3cf18ccc-a38a-4e6d-a206-0cffbd3efc0e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129677663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.3129677663 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3024212778 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 4071564376 ps |
| CPU time | 421.18 seconds |
| Started | Jun 30 07:32:03 PM PDT 24 |
| Finished | Jun 30 07:39:05 PM PDT 24 |
| Peak memory | 607084 kb |
| Host | smart-792442db-a537-4142-8381-dbc3206d7e55 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024212778 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.3024212778 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1343903779 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 4783794502 ps |
| CPU time | 451.32 seconds |
| Started | Jun 30 07:32:25 PM PDT 24 |
| Finished | Jun 30 07:39:56 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-cb7e6735-388d-49d6-8f99-234ba80fdc7a |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343903779 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.1343903779 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.4034831510 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 2194542632 ps |
| CPU time | 197.73 seconds |
| Started | Jun 30 07:39:11 PM PDT 24 |
| Finished | Jun 30 07:42:30 PM PDT 24 |
| Peak memory | 607256 kb |
| Host | smart-b9459b93-c836-49d1-94ed-3957c26e47a1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034831510 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.4034831510 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2500884274 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 20622423998 ps |
| CPU time | 5388.55 seconds |
| Started | Jun 30 07:28:50 PM PDT 24 |
| Finished | Jun 30 08:58:39 PM PDT 24 |
| Peak memory | 608424 kb |
| Host | smart-15972fa7-be8a-4d3d-b194-00490c7b2abe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500884274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.2500884274 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1030941099 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 5088941270 ps |
| CPU time | 509.53 seconds |
| Started | Jun 30 07:31:21 PM PDT 24 |
| Finished | Jun 30 07:39:51 PM PDT 24 |
| Peak memory | 609124 kb |
| Host | smart-ad3434d9-45c3-424d-a2f8-fd206e648433 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10309 41099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.1030941099 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.4289935377 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 3269768088 ps |
| CPU time | 297.4 seconds |
| Started | Jun 30 07:28:25 PM PDT 24 |
| Finished | Jun 30 07:33:22 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-b64250b2-d94d-4246-bf3e-0ae50f5189de |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289935377 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.4289935377 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2153394908 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 5563409384 ps |
| CPU time | 624.08 seconds |
| Started | Jun 30 07:30:37 PM PDT 24 |
| Finished | Jun 30 07:41:02 PM PDT 24 |
| Peak memory | 609424 kb |
| Host | smart-f7fd2e97-ec3f-4054-b455-bf9e7ad38705 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153394908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.2153394908 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.2432074172 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 2736805434 ps |
| CPU time | 202.48 seconds |
| Started | Jun 30 07:39:05 PM PDT 24 |
| Finished | Jun 30 07:42:28 PM PDT 24 |
| Peak memory | 607064 kb |
| Host | smart-3c15cf55-e0ba-4378-bb8a-5541f2f84bb0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432074172 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.2432074172 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.39716587 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 5744108250 ps |
| CPU time | 675.05 seconds |
| Started | Jun 30 07:28:27 PM PDT 24 |
| Finished | Jun 30 07:39:44 PM PDT 24 |
| Peak memory | 608500 kb |
| Host | smart-7881ed61-b382-4308-b794-b933596db63d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=39716587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.39716587 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.2266881755 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 4805332570 ps |
| CPU time | 1322.4 seconds |
| Started | Jun 30 07:29:59 PM PDT 24 |
| Finished | Jun 30 07:52:02 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-a099c58d-3da4-44c7-924a-fb3eff193671 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266881755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.2266881755 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2495733107 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 7134905392 ps |
| CPU time | 1311.36 seconds |
| Started | Jun 30 07:30:29 PM PDT 24 |
| Finished | Jun 30 07:52:21 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-daabd223-754e-4eac-ac26-754db90dcbd3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2495733107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.2495733107 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.2647524262 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 3005945990 ps |
| CPU time | 570.7 seconds |
| Started | Jun 30 07:29:13 PM PDT 24 |
| Finished | Jun 30 07:38:44 PM PDT 24 |
| Peak memory | 614508 kb |
| Host | smart-4c4bd021-4307-4805-9a03-e0462c6c9d81 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647524262 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.2647524262 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.3482463779 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 5650679840 ps |
| CPU time | 1219.33 seconds |
| Started | Jun 30 07:29:58 PM PDT 24 |
| Finished | Jun 30 07:50:18 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-f64d7fe7-81bb-499d-ac09-6dfaec8f7e86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482463779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.3482463779 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1045417683 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 3355964988 ps |
| CPU time | 214.64 seconds |
| Started | Jun 30 07:30:20 PM PDT 24 |
| Finished | Jun 30 07:33:55 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-755b8224-7e8e-48fd-977d-7ebc07e036d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10 45417683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.1045417683 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.3947384065 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 6099609688 ps |
| CPU time | 1085.21 seconds |
| Started | Jun 30 07:30:40 PM PDT 24 |
| Finished | Jun 30 07:48:46 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-2f73c11e-97e7-4802-b997-cf28f4adf83b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3947384065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.3947384065 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2534974435 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 2829578044 ps |
| CPU time | 271.38 seconds |
| Started | Jun 30 07:29:18 PM PDT 24 |
| Finished | Jun 30 07:33:50 PM PDT 24 |
| Peak memory | 607104 kb |
| Host | smart-6354e11a-b8a1-4841-ae8e-2eab9a3f4345 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534974435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.2534974435 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2553654955 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 4005921480 ps |
| CPU time | 514.7 seconds |
| Started | Jun 30 07:38:59 PM PDT 24 |
| Finished | Jun 30 07:47:34 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-ddcd743e-6f7d-4b60-8a85-df684bb4a0df |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2553654955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.2553654955 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.2437082064 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 3575158800 ps |
| CPU time | 305.94 seconds |
| Started | Jun 30 07:32:26 PM PDT 24 |
| Finished | Jun 30 07:37:32 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-eb60eee3-cf5f-4026-a275-f9c537e57a7a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437082064 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.2437082064 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.3796969602 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 3162081060 ps |
| CPU time | 295.98 seconds |
| Started | Jun 30 07:28:24 PM PDT 24 |
| Finished | Jun 30 07:33:21 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-bac11894-a7db-4189-a7d6-c56bc7f25b51 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796969602 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.3796969602 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.3510803998 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 2749576992 ps |
| CPU time | 332.03 seconds |
| Started | Jun 30 07:29:29 PM PDT 24 |
| Finished | Jun 30 07:35:02 PM PDT 24 |
| Peak memory | 606292 kb |
| Host | smart-5d40c72a-4bab-4b35-830e-1a572d9df7b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510803998 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.3510803998 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.596235494 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 2384364952 ps |
| CPU time | 127.27 seconds |
| Started | Jun 30 07:26:43 PM PDT 24 |
| Finished | Jun 30 07:28:51 PM PDT 24 |
| Peak memory | 606744 kb |
| Host | smart-f69b7f30-b851-4108-89ce-f964b26aafcd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596235494 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_example_rom.596235494 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.707624550 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 59939717440 ps |
| CPU time | 11617.2 seconds |
| Started | Jun 30 07:32:12 PM PDT 24 |
| Finished | Jun 30 10:45:50 PM PDT 24 |
| Peak memory | 623428 kb |
| Host | smart-932fcab9-1480-40cb-a495-64f6b72b95fe |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=707624550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.707624550 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.14759992 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 5893059048 ps |
| CPU time | 781.73 seconds |
| Started | Jun 30 07:35:20 PM PDT 24 |
| Finished | Jun 30 07:48:23 PM PDT 24 |
| Peak memory | 608520 kb |
| Host | smart-2bc264ea-4efc-427a-9403-41436b1a9b48 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=14759992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.14759992 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1027959185 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 6122142088 ps |
| CPU time | 1242 seconds |
| Started | Jun 30 07:28:03 PM PDT 24 |
| Finished | Jun 30 07:48:46 PM PDT 24 |
| Peak memory | 607104 kb |
| Host | smart-72f8723b-7240-4d3a-a1c2-45065d028464 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027959185 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.1027959185 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.115461192 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 5374567787 ps |
| CPU time | 1167.05 seconds |
| Started | Jun 30 07:28:03 PM PDT 24 |
| Finished | Jun 30 07:47:31 PM PDT 24 |
| Peak memory | 607632 kb |
| Host | smart-1422b404-69d4-432e-a81e-ee0410308e33 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115461192 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.115461192 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.850398398 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 8288767431 ps |
| CPU time | 1152.79 seconds |
| Started | Jun 30 07:34:05 PM PDT 24 |
| Finished | Jun 30 07:53:18 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-dc1b6ee9-b75e-4cb2-928e-37a426bd5e88 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850398398 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.850398398 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3878154480 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 5566170775 ps |
| CPU time | 1126.04 seconds |
| Started | Jun 30 07:28:15 PM PDT 24 |
| Finished | Jun 30 07:47:02 PM PDT 24 |
| Peak memory | 607080 kb |
| Host | smart-f826a8c9-011c-4685-8961-e01744c9fd34 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878154480 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.3878154480 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.210677493 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3632833782 ps |
| CPU time | 329.36 seconds |
| Started | Jun 30 07:29:35 PM PDT 24 |
| Finished | Jun 30 07:35:05 PM PDT 24 |
| Peak memory | 607320 kb |
| Host | smart-5589bba8-5fb8-4a2f-9cbd-115abff61344 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210677493 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.210677493 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.129932288 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 6129609088 ps |
| CPU time | 1092.33 seconds |
| Started | Jun 30 07:35:53 PM PDT 24 |
| Finished | Jun 30 07:54:07 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-63f49550-8bb0-40e2-b252-fa9243ffa813 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129932288 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.129932288 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3664974619 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 3603988080 ps |
| CPU time | 627.88 seconds |
| Started | Jun 30 07:32:31 PM PDT 24 |
| Finished | Jun 30 07:42:59 PM PDT 24 |
| Peak memory | 609144 kb |
| Host | smart-6a13c5ec-3f84-4f53-a743-f1575dbb97f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664974619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.3664974619 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2425516723 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 3487641011 ps |
| CPU time | 640.77 seconds |
| Started | Jun 30 07:28:28 PM PDT 24 |
| Finished | Jun 30 07:39:09 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-e8c26bb9-62ae-4bbb-9938-9709b8090284 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2425516723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2425516723 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1011888218 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 4618170030 ps |
| CPU time | 716.65 seconds |
| Started | Jun 30 07:34:45 PM PDT 24 |
| Finished | Jun 30 07:46:42 PM PDT 24 |
| Peak memory | 607956 kb |
| Host | smart-4339e21e-3cfe-4b64-8a2f-329ac1eb5c18 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1011888218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1011888218 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3307543142 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 2918111224 ps |
| CPU time | 347.98 seconds |
| Started | Jun 30 07:34:43 PM PDT 24 |
| Finished | Jun 30 07:40:31 PM PDT 24 |
| Peak memory | 609116 kb |
| Host | smart-71cdce89-9341-4186-bb4b-56eaf97e9fc7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307543 142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.3307543142 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.1212621715 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 21560305572 ps |
| CPU time | 2141.11 seconds |
| Started | Jun 30 07:29:53 PM PDT 24 |
| Finished | Jun 30 08:05:35 PM PDT 24 |
| Peak memory | 609632 kb |
| Host | smart-d294f807-be31-4dfb-ac10-5aa286e7e466 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212621715 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.1212621715 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2319107569 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 2653518208 ps |
| CPU time | 316.74 seconds |
| Started | Jun 30 07:39:41 PM PDT 24 |
| Finished | Jun 30 07:44:58 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-724f5897-c600-42d5-8d8b-01cdedcbb507 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2319107569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.2319107569 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.3748567113 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 2632293012 ps |
| CPU time | 308.88 seconds |
| Started | Jun 30 07:28:19 PM PDT 24 |
| Finished | Jun 30 07:33:29 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-d84649f4-a386-43f7-a924-ba96b987c5b9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748567113 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.3748567113 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.249500151 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 3205489022 ps |
| CPU time | 242.44 seconds |
| Started | Jun 30 07:28:35 PM PDT 24 |
| Finished | Jun 30 07:32:38 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-300751e8-e42e-48f2-b133-a12b6f4d5b71 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249500151 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_hmac_enc_idle.249500151 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.4285487958 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 3081976448 ps |
| CPU time | 269.76 seconds |
| Started | Jun 30 07:29:53 PM PDT 24 |
| Finished | Jun 30 07:34:23 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-af620ab1-60a5-4cad-b9ee-c4c698fdbdd4 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285487958 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.4285487958 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3975306192 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 3155248192 ps |
| CPU time | 217.82 seconds |
| Started | Jun 30 07:35:19 PM PDT 24 |
| Finished | Jun 30 07:38:57 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-7b6a93a5-b558-48eb-b9ce-65a284ec65f3 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975306192 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.3975306192 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.2990428130 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 8052144692 ps |
| CPU time | 1949.18 seconds |
| Started | Jun 30 07:28:54 PM PDT 24 |
| Finished | Jun 30 08:01:24 PM PDT 24 |
| Peak memory | 609256 kb |
| Host | smart-c5229525-1289-44f3-bbeb-b2cd7b56494a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990428130 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.2990428130 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.2232860538 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 2585573992 ps |
| CPU time | 344.48 seconds |
| Started | Jun 30 07:30:17 PM PDT 24 |
| Finished | Jun 30 07:36:03 PM PDT 24 |
| Peak memory | 607224 kb |
| Host | smart-15046c68-ce9c-404e-9598-c9b0a1c9f2eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232860538 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.2232860538 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.3684280268 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 2735839750 ps |
| CPU time | 344.89 seconds |
| Started | Jun 30 07:39:31 PM PDT 24 |
| Finished | Jun 30 07:45:17 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-ea450662-6c9f-409d-95d2-90b8723d2d66 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684280268 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.3684280268 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2802434735 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4576800434 ps |
| CPU time | 503.2 seconds |
| Started | Jun 30 07:30:09 PM PDT 24 |
| Finished | Jun 30 07:38:33 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-b1b06ba1-4b8b-44d9-ad98-f78879a4d56b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802434735 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.2802434735 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2346610759 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 4173596750 ps |
| CPU time | 782.58 seconds |
| Started | Jun 30 07:33:28 PM PDT 24 |
| Finished | Jun 30 07:46:31 PM PDT 24 |
| Peak memory | 608204 kb |
| Host | smart-4edeaaf0-3ce5-4bbe-be9d-5288f3c2519c |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346610759 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.2346610759 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.794708653 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 65282938374 ps |
| CPU time | 12060 seconds |
| Started | Jun 30 07:33:04 PM PDT 24 |
| Finished | Jun 30 10:54:06 PM PDT 24 |
| Peak memory | 624016 kb |
| Host | smart-bf2223d0-11cd-47ff-baef-7bc4669eaa4d |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=794708653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.794708653 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2531141 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 9197577052 ps |
| CPU time | 1663.92 seconds |
| Started | Jun 30 07:29:02 PM PDT 24 |
| Finished | Jun 30 07:56:47 PM PDT 24 |
| Peak memory | 615652 kb |
| Host | smart-9bb4409c-0906-4f56-b6f9-e909c311d404 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531 141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.2531141 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3533185658 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 11882268323 ps |
| CPU time | 2653.1 seconds |
| Started | Jun 30 07:30:21 PM PDT 24 |
| Finished | Jun 30 08:14:35 PM PDT 24 |
| Peak memory | 615692 kb |
| Host | smart-3c221c1c-672f-42e1-87ff-819d4b346b45 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3533185658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.3533185658 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1661166713 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 9959928423 ps |
| CPU time | 2195.03 seconds |
| Started | Jun 30 07:34:24 PM PDT 24 |
| Finished | Jun 30 08:11:00 PM PDT 24 |
| Peak memory | 615544 kb |
| Host | smart-e363ea83-9fb6-4eab-9ea1-872bd0e31644 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1661166713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1661166713 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.4003557498 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 9992063726 ps |
| CPU time | 1601.14 seconds |
| Started | Jun 30 07:29:39 PM PDT 24 |
| Finished | Jun 30 07:56:21 PM PDT 24 |
| Peak memory | 607556 kb |
| Host | smart-1f75868a-de06-4326-9a86-4aacd8d4577b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40035 57498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.4003557498 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.42451140 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 15839829296 ps |
| CPU time | 3563.52 seconds |
| Started | Jun 30 07:30:20 PM PDT 24 |
| Finished | Jun 30 08:29:44 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-263ce6ef-65da-41ba-a9d2-8c44cb9e5bfc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42451 140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.42451140 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.1309158989 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 2449041560 ps |
| CPU time | 241.25 seconds |
| Started | Jun 30 07:29:48 PM PDT 24 |
| Finished | Jun 30 07:33:50 PM PDT 24 |
| Peak memory | 607296 kb |
| Host | smart-7cd9e5e4-510e-488b-9b9f-038449b41fee |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309158989 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.1309158989 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.812362791 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2871932630 ps |
| CPU time | 262.19 seconds |
| Started | Jun 30 07:27:29 PM PDT 24 |
| Finished | Jun 30 07:31:51 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-f53d436c-5e39-461e-9712-a3e283abc2ba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812362791 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_entropy.812362791 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.4076800314 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 2887417032 ps |
| CPU time | 247.34 seconds |
| Started | Jun 30 07:30:34 PM PDT 24 |
| Finished | Jun 30 07:34:42 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-ef7a3806-f6cc-4613-a9c0-79d93c0d05ab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076800314 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.4076800314 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.4126727847 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 3081752056 ps |
| CPU time | 244.97 seconds |
| Started | Jun 30 07:30:03 PM PDT 24 |
| Finished | Jun 30 07:34:08 PM PDT 24 |
| Peak memory | 607248 kb |
| Host | smart-8c1f0919-dfe1-4839-83a3-eeda0949cf48 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126727847 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.4126727847 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1323817465 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 3293700070 ps |
| CPU time | 305.77 seconds |
| Started | Jun 30 07:31:12 PM PDT 24 |
| Finished | Jun 30 07:36:18 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-a659e6ac-fc93-47de-9022-138100f9f64a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323817465 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.1323817465 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.333773648 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 2848554334 ps |
| CPU time | 280.14 seconds |
| Started | Jun 30 07:29:33 PM PDT 24 |
| Finished | Jun 30 07:34:14 PM PDT 24 |
| Peak memory | 609116 kb |
| Host | smart-d5892167-f821-4413-9128-4ec115e8286b |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333773648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.333773648 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.509690084 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 3719690979 ps |
| CPU time | 305.8 seconds |
| Started | Jun 30 07:35:24 PM PDT 24 |
| Finished | Jun 30 07:40:31 PM PDT 24 |
| Peak memory | 607232 kb |
| Host | smart-efdfa59a-be53-428c-b14c-33a575c7191e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50969008 4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.509690084 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.106401434 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 2996506840 ps |
| CPU time | 285.92 seconds |
| Started | Jun 30 07:38:34 PM PDT 24 |
| Finished | Jun 30 07:43:20 PM PDT 24 |
| Peak memory | 606260 kb |
| Host | smart-d15ab10f-86b4-46c4-80b8-9dbef2cf6b87 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106401434 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_smoketest.106401434 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3352195308 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 2946900066 ps |
| CPU time | 262.08 seconds |
| Started | Jun 30 07:30:16 PM PDT 24 |
| Finished | Jun 30 07:34:39 PM PDT 24 |
| Peak memory | 609112 kb |
| Host | smart-2d1ceeed-7657-41f7-b88a-c6a71db50745 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352195308 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.3352195308 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.174557841 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 2608718186 ps |
| CPU time | 137.84 seconds |
| Started | Jun 30 07:28:21 PM PDT 24 |
| Finished | Jun 30 07:30:40 PM PDT 24 |
| Peak memory | 617680 kb |
| Host | smart-04aee904-102e-410c-8fab-54a4a36a3bbe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17455784 1 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.174557841 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.238445902 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 2868103352 ps |
| CPU time | 110.37 seconds |
| Started | Jun 30 07:31:26 PM PDT 24 |
| Finished | Jun 30 07:33:17 PM PDT 24 |
| Peak memory | 617576 kb |
| Host | smart-cf207265-3859-40c9-978f-7cc145dc992a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238445902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.238445902 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3653870265 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3256596356 ps |
| CPU time | 162.25 seconds |
| Started | Jun 30 07:29:37 PM PDT 24 |
| Finished | Jun 30 07:32:20 PM PDT 24 |
| Peak memory | 617488 kb |
| Host | smart-597a3297-40d1-4b95-ab55-4855ac834e4d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653870265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.3653870265 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2275083035 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 3868917321 ps |
| CPU time | 159.75 seconds |
| Started | Jun 30 07:29:23 PM PDT 24 |
| Finished | Jun 30 07:32:03 PM PDT 24 |
| Peak memory | 617612 kb |
| Host | smart-ffd149db-9ef6-40f1-8c59-d11b4c319e60 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2275083035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.2275083035 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.263479923 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 6895254774 ps |
| CPU time | 496.87 seconds |
| Started | Jun 30 07:29:49 PM PDT 24 |
| Finished | Jun 30 07:38:07 PM PDT 24 |
| Peak memory | 618980 kb |
| Host | smart-13f66b24-868a-43b6-9d5c-d04c2f3c7442 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263479923 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.263479923 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3593577413 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 2482010020 ps |
| CPU time | 99.72 seconds |
| Started | Jun 30 07:28:51 PM PDT 24 |
| Finished | Jun 30 07:30:31 PM PDT 24 |
| Peak memory | 615940 kb |
| Host | smart-ad456f6a-3b85-4e93-84e4-1dfaada5e234 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3593577413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.3593577413 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2771627267 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 2066318592 ps |
| CPU time | 101.84 seconds |
| Started | Jun 30 07:32:23 PM PDT 24 |
| Finished | Jun 30 07:34:05 PM PDT 24 |
| Peak memory | 614344 kb |
| Host | smart-5ce7fbf6-6b34-4777-b0a6-44a95abb86c6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771627267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2771627267 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.449547773 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 49539722508 ps |
| CPU time | 5820.34 seconds |
| Started | Jun 30 07:27:27 PM PDT 24 |
| Finished | Jun 30 09:04:29 PM PDT 24 |
| Peak memory | 615008 kb |
| Host | smart-8e9b5a3a-52e2-47de-8ceb-eb7d20bc6dce |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449547773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_lc_walkthrough_dev.449547773 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1001355110 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 50699936236 ps |
| CPU time | 5988.14 seconds |
| Started | Jun 30 07:28:38 PM PDT 24 |
| Finished | Jun 30 09:08:27 PM PDT 24 |
| Peak memory | 615028 kb |
| Host | smart-19550bb6-5ad5-466d-9ca1-649e189f609a |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001355110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.1001355110 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3897353257 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 8612992378 ps |
| CPU time | 1064.78 seconds |
| Started | Jun 30 07:29:07 PM PDT 24 |
| Finished | Jun 30 07:46:54 PM PDT 24 |
| Peak memory | 623480 kb |
| Host | smart-572ceffb-3da1-47af-a557-38734a332a62 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897353257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.3897353257 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.614211516 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 16814645080 ps |
| CPU time | 4031.2 seconds |
| Started | Jun 30 07:28:28 PM PDT 24 |
| Finished | Jun 30 08:35:40 PM PDT 24 |
| Peak memory | 608104 kb |
| Host | smart-693f8671-6491-4b39-8dfe-debbd3486366 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=614211516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.614211516 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3073581841 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 18524862407 ps |
| CPU time | 4156.86 seconds |
| Started | Jun 30 07:29:04 PM PDT 24 |
| Finished | Jun 30 08:38:22 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-9e3326f0-c8a2-445e-8d68-f7e80d85b692 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3073581841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3073581841 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3266182083 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 25073990887 ps |
| CPU time | 4903.81 seconds |
| Started | Jun 30 07:35:34 PM PDT 24 |
| Finished | Jun 30 08:57:19 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-4ef6a5f7-5bd0-43c7-82f6-099ad4cb8d09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266182083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3266182083 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2762827974 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3895870324 ps |
| CPU time | 474.07 seconds |
| Started | Jun 30 07:29:59 PM PDT 24 |
| Finished | Jun 30 07:37:54 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-6b4b2628-8cf5-44e4-a30d-550cd07ba30a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762827974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.2762827974 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.2468412175 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 5964982280 ps |
| CPU time | 787.91 seconds |
| Started | Jun 30 07:29:26 PM PDT 24 |
| Finished | Jun 30 07:42:34 PM PDT 24 |
| Peak memory | 608220 kb |
| Host | smart-1284483b-df91-4eaa-af93-388532421470 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2468412175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.2468412175 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.4196923460 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 9656879656 ps |
| CPU time | 2049.89 seconds |
| Started | Jun 30 07:40:03 PM PDT 24 |
| Finished | Jun 30 08:14:13 PM PDT 24 |
| Peak memory | 607256 kb |
| Host | smart-d6c68195-086a-4eb1-b029-7e45b266b80a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196923460 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.4196923460 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2216260829 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 28278260744 ps |
| CPU time | 6401.93 seconds |
| Started | Jun 30 07:28:01 PM PDT 24 |
| Finished | Jun 30 09:14:44 PM PDT 24 |
| Peak memory | 608228 kb |
| Host | smart-04bb9ce4-2563-4580-b777-894a356399ac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221626 0829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.2216260829 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2009779350 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 2777082704 ps |
| CPU time | 187.27 seconds |
| Started | Jun 30 07:31:44 PM PDT 24 |
| Finished | Jun 30 07:34:51 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-0b581944-c25a-4d00-a080-c3033b9892f8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009779350 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.2009779350 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1731791912 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 7016206280 ps |
| CPU time | 1318.13 seconds |
| Started | Jun 30 07:29:57 PM PDT 24 |
| Finished | Jun 30 07:51:55 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-8b60fbcb-7722-4945-87d0-1225395296dc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1731791912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.1731791912 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.100687310 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 7213500680 ps |
| CPU time | 1196.08 seconds |
| Started | Jun 30 07:28:47 PM PDT 24 |
| Finished | Jun 30 07:48:44 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-b71a6ffa-77ad-415b-80dc-248d41f24cb5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=100687310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.100687310 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3377563793 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 7745082532 ps |
| CPU time | 1340.59 seconds |
| Started | Jun 30 07:29:06 PM PDT 24 |
| Finished | Jun 30 07:51:27 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-c40a80dc-3b18-4895-9ed3-6b862e04831a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3377563793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.3377563793 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2964424225 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 5021569460 ps |
| CPU time | 628.76 seconds |
| Started | Jun 30 07:29:50 PM PDT 24 |
| Finished | Jun 30 07:40:19 PM PDT 24 |
| Peak memory | 607720 kb |
| Host | smart-2d84aaa1-6379-4401-b280-8fa53860c3f2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2964424225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2964424225 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2153207982 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 3055123680 ps |
| CPU time | 268.77 seconds |
| Started | Jun 30 07:39:36 PM PDT 24 |
| Finished | Jun 30 07:44:05 PM PDT 24 |
| Peak memory | 607192 kb |
| Host | smart-169b5045-da97-442f-9db0-97d2dad34332 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153207982 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.2153207982 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.1210914689 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 3296794400 ps |
| CPU time | 225.36 seconds |
| Started | Jun 30 07:28:43 PM PDT 24 |
| Finished | Jun 30 07:32:29 PM PDT 24 |
| Peak memory | 607620 kb |
| Host | smart-8606454e-0e68-459d-9725-0e5982faebed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210914689 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.1210914689 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.2088311739 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2422650504 ps |
| CPU time | 244.88 seconds |
| Started | Jun 30 07:32:20 PM PDT 24 |
| Finished | Jun 30 07:36:25 PM PDT 24 |
| Peak memory | 606236 kb |
| Host | smart-9cb9e763-856c-4225-ad65-78b0a7142d32 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088311739 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.2088311739 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.147090220 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 10261052696 ps |
| CPU time | 639.2 seconds |
| Started | Jun 30 07:34:41 PM PDT 24 |
| Finished | Jun 30 07:45:20 PM PDT 24 |
| Peak memory | 608812 kb |
| Host | smart-da7d83dd-14e8-4d9e-b37a-000601f1fd1e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147090220 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.147090220 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2472241295 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 10516354516 ps |
| CPU time | 1698.02 seconds |
| Started | Jun 30 07:28:59 PM PDT 24 |
| Finished | Jun 30 07:57:17 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-10ad3c25-9885-47ca-816c-cc74d633d96b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472 241295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.2472241295 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2160648374 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 23865011834 ps |
| CPU time | 2494.39 seconds |
| Started | Jun 30 07:31:50 PM PDT 24 |
| Finished | Jun 30 08:13:25 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-69b69e1d-dfa8-4e50-befa-69cd5510d7b8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216 0648374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.2160648374 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1004453188 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 13368117933 ps |
| CPU time | 1558.99 seconds |
| Started | Jun 30 07:28:23 PM PDT 24 |
| Finished | Jun 30 07:54:22 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-6a3b0572-7ddc-4058-b05b-e14d583090d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1004453188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1004453188 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1236683746 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 25830783208 ps |
| CPU time | 2519.2 seconds |
| Started | Jun 30 07:34:07 PM PDT 24 |
| Finished | Jun 30 08:16:07 PM PDT 24 |
| Peak memory | 608728 kb |
| Host | smart-04a7b5fd-d7c2-4e3a-8a89-5fb5319a0f22 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1236683746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1236683746 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2860633130 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 8804962780 ps |
| CPU time | 506.08 seconds |
| Started | Jun 30 07:31:38 PM PDT 24 |
| Finished | Jun 30 07:40:04 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-b276861a-1b54-43f1-b8c6-b52ab33ca073 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860633130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.2860633130 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1056729687 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 7577286446 ps |
| CPU time | 520.24 seconds |
| Started | Jun 30 07:28:41 PM PDT 24 |
| Finished | Jun 30 07:37:22 PM PDT 24 |
| Peak memory | 614144 kb |
| Host | smart-df499cd5-9b45-4a55-89d7-bb99fe8c4c55 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1056729687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1056729687 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2786625017 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 4587150545 ps |
| CPU time | 458.38 seconds |
| Started | Jun 30 07:29:03 PM PDT 24 |
| Finished | Jun 30 07:36:42 PM PDT 24 |
| Peak memory | 615304 kb |
| Host | smart-0ed87b71-dccc-4b2c-9389-82060436386d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2786625017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.2786625017 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3361091185 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 12278462577 ps |
| CPU time | 1490.97 seconds |
| Started | Jun 30 07:31:19 PM PDT 24 |
| Finished | Jun 30 07:56:11 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-af37b902-b83e-4fd9-b6ed-d22b76d4a5f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361091185 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3361091185 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.206800209 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 7672213800 ps |
| CPU time | 499.06 seconds |
| Started | Jun 30 07:36:13 PM PDT 24 |
| Finished | Jun 30 07:44:33 PM PDT 24 |
| Peak memory | 608232 kb |
| Host | smart-35cbe712-2766-4ba7-9bca-8c2e565fde7f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206800209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.206800209 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.981174941 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 7116461972 ps |
| CPU time | 645.39 seconds |
| Started | Jun 30 07:31:02 PM PDT 24 |
| Finished | Jun 30 07:41:49 PM PDT 24 |
| Peak memory | 608264 kb |
| Host | smart-1d3aa382-0c40-4fed-bb5e-8a77a6eb1033 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981174941 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.981174941 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2191563032 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 19785749560 ps |
| CPU time | 1330.99 seconds |
| Started | Jun 30 07:34:06 PM PDT 24 |
| Finished | Jun 30 07:56:18 PM PDT 24 |
| Peak memory | 608704 kb |
| Host | smart-8f679917-3e1a-4f54-8852-94eda0668931 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2191563032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2191563032 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3755617818 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 2962656536 ps |
| CPU time | 292.43 seconds |
| Started | Jun 30 07:28:41 PM PDT 24 |
| Finished | Jun 30 07:33:34 PM PDT 24 |
| Peak memory | 607212 kb |
| Host | smart-3e5f16ff-9a17-45e1-862c-f3d46914fe2d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755617818 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.3755617818 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2211369057 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 5423966020 ps |
| CPU time | 452.81 seconds |
| Started | Jun 30 07:29:24 PM PDT 24 |
| Finished | Jun 30 07:36:58 PM PDT 24 |
| Peak memory | 615524 kb |
| Host | smart-9a64e3c6-0f15-455e-91f8-b5ec4dad3793 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2211369057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.2211369057 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2135975432 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 5987502862 ps |
| CPU time | 402.07 seconds |
| Started | Jun 30 07:33:29 PM PDT 24 |
| Finished | Jun 30 07:40:12 PM PDT 24 |
| Peak memory | 608444 kb |
| Host | smart-110f184f-9995-4d85-8f72-8f85de7fed18 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2135975432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.2135975432 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.401628262 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 6458313530 ps |
| CPU time | 500.37 seconds |
| Started | Jun 30 07:40:09 PM PDT 24 |
| Finished | Jun 30 07:48:29 PM PDT 24 |
| Peak memory | 607980 kb |
| Host | smart-15378232-d90b-420b-be22-16e66ab05daa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401628262 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.401628262 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2542623454 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 6108743256 ps |
| CPU time | 1121.9 seconds |
| Started | Jun 30 07:29:56 PM PDT 24 |
| Finished | Jun 30 07:48:38 PM PDT 24 |
| Peak memory | 608276 kb |
| Host | smart-06781901-eaae-443b-b0e0-ebc8b4132f4f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542623454 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.2542623454 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.833717426 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 3517336480 ps |
| CPU time | 270.79 seconds |
| Started | Jun 30 07:27:33 PM PDT 24 |
| Finished | Jun 30 07:32:04 PM PDT 24 |
| Peak memory | 609224 kb |
| Host | smart-a0495c09-2f59-4260-9770-bcc9bd15a90d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833717426 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.833717426 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2429818096 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 6335706604 ps |
| CPU time | 550.98 seconds |
| Started | Jun 30 07:38:52 PM PDT 24 |
| Finished | Jun 30 07:48:03 PM PDT 24 |
| Peak memory | 607912 kb |
| Host | smart-1ae8a0d0-cf9b-47dd-b488-f496fb7b36c8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429818096 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.2429818096 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1774633913 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 4860287228 ps |
| CPU time | 445.44 seconds |
| Started | Jun 30 07:28:41 PM PDT 24 |
| Finished | Jun 30 07:36:07 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-45efac6d-8a15-4d67-87ae-f0b7b6e400ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177 4633913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.1774633913 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1254927013 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 7980517171 ps |
| CPU time | 563.18 seconds |
| Started | Jun 30 07:30:49 PM PDT 24 |
| Finished | Jun 30 07:40:13 PM PDT 24 |
| Peak memory | 607932 kb |
| Host | smart-3825cd33-dee4-4f19-a6a9-ec83642471c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254927013 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.1254927013 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.146623464 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 4560493320 ps |
| CPU time | 628.18 seconds |
| Started | Jun 30 07:29:33 PM PDT 24 |
| Finished | Jun 30 07:40:02 PM PDT 24 |
| Peak memory | 609144 kb |
| Host | smart-f016c682-4c09-42dc-b0da-61769ea900c8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146623464 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_rstmgr_cpu_info.146623464 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3905545294 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 5325492224 ps |
| CPU time | 595.93 seconds |
| Started | Jun 30 07:28:15 PM PDT 24 |
| Finished | Jun 30 07:38:12 PM PDT 24 |
| Peak memory | 639296 kb |
| Host | smart-2e8bbc36-bfe0-4ea6-9399-05958e581744 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3905545294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.3905545294 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1478078922 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 2595635320 ps |
| CPU time | 144.92 seconds |
| Started | Jun 30 07:39:23 PM PDT 24 |
| Finished | Jun 30 07:41:48 PM PDT 24 |
| Peak memory | 607508 kb |
| Host | smart-2916805f-6802-4c3e-a2ce-ce23966d5be1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478078922 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.1478078922 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.80290425 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 2746201408 ps |
| CPU time | 306.59 seconds |
| Started | Jun 30 07:28:42 PM PDT 24 |
| Finished | Jun 30 07:33:49 PM PDT 24 |
| Peak memory | 607048 kb |
| Host | smart-421bd7c8-f997-41a5-8020-d46fecc2a061 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80290425 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_sw_req.80290425 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.132604121 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 2733006284 ps |
| CPU time | 237.9 seconds |
| Started | Jun 30 07:31:57 PM PDT 24 |
| Finished | Jun 30 07:35:56 PM PDT 24 |
| Peak memory | 607332 kb |
| Host | smart-64a3d28a-5cc3-4957-8433-6ef592a438e6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132604121 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.132604121 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.4096197148 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3185697905 ps |
| CPU time | 314.72 seconds |
| Started | Jun 30 07:34:04 PM PDT 24 |
| Finished | Jun 30 07:39:19 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-2507110c-f17d-43ff-ba5f-57d1ed2cf2b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096197148 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.4096197148 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.258742029 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 5199001876 ps |
| CPU time | 1044.33 seconds |
| Started | Jun 30 07:29:20 PM PDT 24 |
| Finished | Jun 30 07:46:45 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-b82be313-308c-4929-90b8-23f6ab7b5112 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=258742029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.258742029 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.295007611 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 3628620360 ps |
| CPU time | 286.01 seconds |
| Started | Jun 30 07:41:30 PM PDT 24 |
| Finished | Jun 30 07:46:16 PM PDT 24 |
| Peak memory | 606460 kb |
| Host | smart-3afe6f41-d821-4872-b47a-809550c9cfdf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295007611 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rv_plic_smoketest.295007611 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.4285138837 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 2965627728 ps |
| CPU time | 176.1 seconds |
| Started | Jun 30 07:28:37 PM PDT 24 |
| Finished | Jun 30 07:31:33 PM PDT 24 |
| Peak memory | 606288 kb |
| Host | smart-535438a7-a56b-4a70-822d-ff1018eb3e30 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285138837 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.4285138837 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3236656349 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 3159939864 ps |
| CPU time | 290.74 seconds |
| Started | Jun 30 07:41:26 PM PDT 24 |
| Finished | Jun 30 07:46:18 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-d2f182ee-3031-4c34-9c24-e90fc00a9a33 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236656349 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.3236656349 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1371692101 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 3261607902 ps |
| CPU time | 263.03 seconds |
| Started | Jun 30 07:30:40 PM PDT 24 |
| Finished | Jun 30 07:35:04 PM PDT 24 |
| Peak memory | 608388 kb |
| Host | smart-5d1e4435-8aa5-4dc5-8ba1-b3c36ef6e56f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371692 101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.1371692101 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.526180140 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4411013792 ps |
| CPU time | 366.32 seconds |
| Started | Jun 30 07:28:01 PM PDT 24 |
| Finished | Jun 30 07:34:08 PM PDT 24 |
| Peak memory | 608248 kb |
| Host | smart-4bf2f2f2-76a3-44db-b202-77c255deb634 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526180140 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.526180140 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3440038114 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 9984818430 ps |
| CPU time | 1422.09 seconds |
| Started | Jun 30 07:28:53 PM PDT 24 |
| Finished | Jun 30 07:52:36 PM PDT 24 |
| Peak memory | 608224 kb |
| Host | smart-318460ff-7651-4b31-81d7-c09afa374489 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440038114 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.3440038114 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.203778794 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 7306983824 ps |
| CPU time | 755.88 seconds |
| Started | Jun 30 07:33:43 PM PDT 24 |
| Finished | Jun 30 07:46:20 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-4beda5ca-7a8a-4104-82b9-72793e5630ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203778794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sle ep_sram_ret_contents_no_scramble.203778794 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2489117125 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 7511560428 ps |
| CPU time | 852.14 seconds |
| Started | Jun 30 07:30:49 PM PDT 24 |
| Finished | Jun 30 07:45:02 PM PDT 24 |
| Peak memory | 609256 kb |
| Host | smart-6230e0db-6e96-4b74-8780-7689482fceb1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489117125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.2489117125 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.2161702282 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5939467097 ps |
| CPU time | 688.43 seconds |
| Started | Jun 30 07:28:32 PM PDT 24 |
| Finished | Jun 30 07:40:01 PM PDT 24 |
| Peak memory | 624260 kb |
| Host | smart-cdeba4a6-bbe5-4a00-aa57-ee05e8f8de29 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161702282 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.2161702282 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2563213397 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 4783963058 ps |
| CPU time | 446.25 seconds |
| Started | Jun 30 07:28:02 PM PDT 24 |
| Finished | Jun 30 07:35:29 PM PDT 24 |
| Peak memory | 624256 kb |
| Host | smart-c3c62b15-6614-4422-b5c7-ae2cf150a2ed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563213397 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.2563213397 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.837283218 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3939113378 ps |
| CPU time | 385.94 seconds |
| Started | Jun 30 07:28:41 PM PDT 24 |
| Finished | Jun 30 07:35:08 PM PDT 24 |
| Peak memory | 617496 kb |
| Host | smart-97c1a2fd-dd1a-4584-9878-22735e03956f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837283218 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.837283218 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1885285782 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2980137784 ps |
| CPU time | 318.34 seconds |
| Started | Jun 30 07:27:58 PM PDT 24 |
| Finished | Jun 30 07:33:16 PM PDT 24 |
| Peak memory | 607988 kb |
| Host | smart-aabc0f37-0059-40df-a7b7-608ce021e22d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885285782 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.1885285782 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1062162974 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 8619190144 ps |
| CPU time | 917.58 seconds |
| Started | Jun 30 07:33:36 PM PDT 24 |
| Finished | Jun 30 07:48:55 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-f2fc92df-e240-4218-97ae-1444fdd068c5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062162974 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.1062162974 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2921270356 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 4479628268 ps |
| CPU time | 742.65 seconds |
| Started | Jun 30 07:31:52 PM PDT 24 |
| Finished | Jun 30 07:44:16 PM PDT 24 |
| Peak memory | 607528 kb |
| Host | smart-2fad495c-31a6-4a8f-b8b6-8c4e16d53eec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921270356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.2921270356 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.395819471 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 3705367189 ps |
| CPU time | 634.76 seconds |
| Started | Jun 30 07:33:26 PM PDT 24 |
| Finished | Jun 30 07:44:02 PM PDT 24 |
| Peak memory | 608552 kb |
| Host | smart-dd93b5e7-2d9f-43b6-8711-bed510979fce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395819471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.395819471 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2336542713 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 5059895964 ps |
| CPU time | 680.38 seconds |
| Started | Jun 30 07:35:12 PM PDT 24 |
| Finished | Jun 30 07:46:33 PM PDT 24 |
| Peak memory | 607452 kb |
| Host | smart-7b4efb0b-bda3-4da2-aa52-8ab6d45dcf32 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336542713 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2336542713 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2241965616 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 3278302440 ps |
| CPU time | 217.27 seconds |
| Started | Jun 30 07:39:57 PM PDT 24 |
| Finished | Jun 30 07:43:35 PM PDT 24 |
| Peak memory | 607288 kb |
| Host | smart-1fe0656c-61f8-40b2-aff9-df4ac27e8ad5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241965616 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.2241965616 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3165873062 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 20771680303 ps |
| CPU time | 4000.19 seconds |
| Started | Jun 30 07:28:11 PM PDT 24 |
| Finished | Jun 30 08:34:52 PM PDT 24 |
| Peak memory | 608348 kb |
| Host | smart-5b822888-9a89-4792-acc3-ce038932d917 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165873062 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.3165873062 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3356678000 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 2895125227 ps |
| CPU time | 331.89 seconds |
| Started | Jun 30 07:30:42 PM PDT 24 |
| Finished | Jun 30 07:36:16 PM PDT 24 |
| Peak memory | 611884 kb |
| Host | smart-5e94982d-e857-4c18-89c8-b3335ceb0abf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356678000 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.3356678000 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2456656481 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 3731044476 ps |
| CPU time | 341.74 seconds |
| Started | Jun 30 07:28:46 PM PDT 24 |
| Finished | Jun 30 07:34:29 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-d592fca1-300f-4cb3-bfa4-840a9109e2ba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456656481 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.2456656481 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.32540574 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 25711573736 ps |
| CPU time | 2129.78 seconds |
| Started | Jun 30 07:27:49 PM PDT 24 |
| Finished | Jun 30 08:03:20 PM PDT 24 |
| Peak memory | 612780 kb |
| Host | smart-9bbd0178-72cb-490d-b5af-a760464c5dbc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32540574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.32540574 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1773152650 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 6379418380 ps |
| CPU time | 527.76 seconds |
| Started | Jun 30 07:29:02 PM PDT 24 |
| Finished | Jun 30 07:37:51 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-23edab62-502a-4436-b8ec-fe170ac32b5d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773152650 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1773152650 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2501312928 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 3517784908 ps |
| CPU time | 490.68 seconds |
| Started | Jun 30 07:31:40 PM PDT 24 |
| Finished | Jun 30 07:39:51 PM PDT 24 |
| Peak memory | 618560 kb |
| Host | smart-a8a4d34d-153f-47a2-86df-13e65171b17f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2501312928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.2501312928 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.2146302170 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 2875735270 ps |
| CPU time | 266.1 seconds |
| Started | Jun 30 07:40:33 PM PDT 24 |
| Finished | Jun 30 07:44:59 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-1c91937f-d3d9-4f11-80c8-8c89e9d0e691 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146302170 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.2146302170 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.1901931895 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 4681523748 ps |
| CPU time | 602.68 seconds |
| Started | Jun 30 07:27:09 PM PDT 24 |
| Finished | Jun 30 07:37:13 PM PDT 24 |
| Peak memory | 615856 kb |
| Host | smart-0972b70e-6ede-4571-9273-5cd8b0520acb |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901931895 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.1901931895 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.487846718 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 8757850473 ps |
| CPU time | 1425.02 seconds |
| Started | Jun 30 07:32:04 PM PDT 24 |
| Finished | Jun 30 07:55:50 PM PDT 24 |
| Peak memory | 617572 kb |
| Host | smart-ba82ca75-b9d8-47f0-9f9e-7f5419383345 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487846718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.487846718 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.450670506 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 78821420606 ps |
| CPU time | 13733.4 seconds |
| Started | Jun 30 07:28:14 PM PDT 24 |
| Finished | Jun 30 11:17:10 PM PDT 24 |
| Peak memory | 632388 kb |
| Host | smart-392a99ba-c249-43ad-89cc-39462dc57241 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=450670506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.450670506 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.42552418 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 4173768704 ps |
| CPU time | 584.82 seconds |
| Started | Jun 30 07:28:21 PM PDT 24 |
| Finished | Jun 30 07:38:06 PM PDT 24 |
| Peak memory | 615868 kb |
| Host | smart-a1e05240-ce9a-4ad2-9ef6-d07497a4378a |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42552418 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.42552418 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1193664726 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 5113473048 ps |
| CPU time | 733.17 seconds |
| Started | Jun 30 07:28:11 PM PDT 24 |
| Finished | Jun 30 07:40:25 PM PDT 24 |
| Peak memory | 624184 kb |
| Host | smart-13ef601c-f4af-48db-b6a4-cc1641efc362 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193664726 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.1193664726 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1518877601 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 3725829280 ps |
| CPU time | 562.63 seconds |
| Started | Jun 30 07:31:21 PM PDT 24 |
| Finished | Jun 30 07:40:45 PM PDT 24 |
| Peak memory | 615872 kb |
| Host | smart-1a17e5e8-873b-4f38-a0c2-9c219d996f2b |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518877601 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.1518877601 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3311745317 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2948746432 ps |
| CPU time | 408.41 seconds |
| Started | Jun 30 07:36:33 PM PDT 24 |
| Finished | Jun 30 07:43:22 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-0040328e-d585-45a8-b983-0051aa9f86b2 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311745317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.3311745317 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.3003293382 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8535003400 ps |
| CPU time | 2342.04 seconds |
| Started | Jun 30 07:27:56 PM PDT 24 |
| Finished | Jun 30 08:06:58 PM PDT 24 |
| Peak memory | 607732 kb |
| Host | smart-d239807a-6c33-42af-ae03-06c529ea0c44 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30032 93382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.3003293382 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.4010563014 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 12017384120 ps |
| CPU time | 3462.61 seconds |
| Started | Jun 30 07:27:21 PM PDT 24 |
| Finished | Jun 30 08:25:04 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-9368a9a5-d94b-43a8-88ac-d18115162bd3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4010563014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.4010563014 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.2029831261 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 3358268680 ps |
| CPU time | 251.71 seconds |
| Started | Jun 30 07:28:46 PM PDT 24 |
| Finished | Jun 30 07:32:58 PM PDT 24 |
| Peak memory | 609144 kb |
| Host | smart-3adea8fe-dd39-4f5b-9e7b-ea0348bddde1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029831261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.2029831261 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2067245461 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 4167623402 ps |
| CPU time | 586.81 seconds |
| Started | Jun 30 07:27:46 PM PDT 24 |
| Finished | Jun 30 07:37:33 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-9a355a6b-337b-4a05-b7c3-3db474e14448 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206724546 1 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.2067245461 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.1482429456 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 19365862842 ps |
| CPU time | 4964.33 seconds |
| Started | Jun 30 07:29:25 PM PDT 24 |
| Finished | Jun 30 08:52:10 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-d2d541ec-f07f-4394-96fc-3739626a9eae |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1482429456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.1482429456 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.1114925458 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 3344599140 ps |
| CPU time | 276.01 seconds |
| Started | Jun 30 07:29:14 PM PDT 24 |
| Finished | Jun 30 07:33:51 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-5aef0f07-6b51-4f06-babc-538294e4e5f0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114925458 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.1114925458 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.996220245 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 3997129277 ps |
| CPU time | 320.34 seconds |
| Started | Jun 30 07:33:24 PM PDT 24 |
| Finished | Jun 30 07:38:45 PM PDT 24 |
| Peak memory | 618972 kb |
| Host | smart-4170af21-04be-433b-862a-926eb5e33990 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=996220245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.996220245 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.1727476690 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 6088107284 ps |
| CPU time | 503.85 seconds |
| Started | Jun 30 07:33:58 PM PDT 24 |
| Finished | Jun 30 07:42:23 PM PDT 24 |
| Peak memory | 617840 kb |
| Host | smart-3a9a57e9-76af-4c72-be07-bafc9ab9db84 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727476690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.1727476690 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.1442867398 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 15017798744 ps |
| CPU time | 4197.11 seconds |
| Started | Jun 30 07:42:20 PM PDT 24 |
| Finished | Jun 30 08:52:18 PM PDT 24 |
| Peak memory | 607200 kb |
| Host | smart-96cd65e0-e353-49ef-86f7-5ff4da78b95b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442867398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.1442867398 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.2267447155 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 15478026926 ps |
| CPU time | 4505.38 seconds |
| Started | Jun 30 07:42:43 PM PDT 24 |
| Finished | Jun 30 08:57:49 PM PDT 24 |
| Peak memory | 607908 kb |
| Host | smart-9d3b791b-c00e-48c0-a31c-6663160e84de |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267447155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.2267447155 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.4171644235 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 16055207583 ps |
| CPU time | 4680.62 seconds |
| Started | Jun 30 07:42:51 PM PDT 24 |
| Finished | Jun 30 09:00:53 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-1e350ce7-4791-4507-9fed-54057d2e2615 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171644235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.4171644235 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.1927607299 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 15448119952 ps |
| CPU time | 4055.61 seconds |
| Started | Jun 30 07:42:40 PM PDT 24 |
| Finished | Jun 30 08:50:17 PM PDT 24 |
| Peak memory | 607436 kb |
| Host | smart-4062579a-942f-4e34-947d-2351f057f814 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927607299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.1927607299 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3859307904 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 11658588296 ps |
| CPU time | 3852.61 seconds |
| Started | Jun 30 07:43:01 PM PDT 24 |
| Finished | Jun 30 08:47:15 PM PDT 24 |
| Peak memory | 607516 kb |
| Host | smart-5d426597-99dd-45c1-b740-fcb706b7576f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859307904 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.3859307904 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.31492343 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 23779047560 ps |
| CPU time | 6554.79 seconds |
| Started | Jun 30 07:40:20 PM PDT 24 |
| Finished | Jun 30 09:29:35 PM PDT 24 |
| Peak memory | 607312 kb |
| Host | smart-246ce520-cec2-41d3-a43c-dcd5e2204495 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=31492343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.31492343 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1765003948 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 24401216078 ps |
| CPU time | 6013.55 seconds |
| Started | Jun 30 07:42:38 PM PDT 24 |
| Finished | Jun 30 09:22:53 PM PDT 24 |
| Peak memory | 608188 kb |
| Host | smart-599b9eed-b906-4913-8f3f-4d1ba65bc461 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1765003948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1765003948 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3341796948 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 23252042900 ps |
| CPU time | 6025.99 seconds |
| Started | Jun 30 07:42:09 PM PDT 24 |
| Finished | Jun 30 09:22:35 PM PDT 24 |
| Peak memory | 608328 kb |
| Host | smart-ae7afc5c-6c0e-4bf2-8b1d-d95242d45b99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3341796948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3341796948 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1896076662 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 18196900312 ps |
| CPU time | 5198.53 seconds |
| Started | Jun 30 07:41:06 PM PDT 24 |
| Finished | Jun 30 09:07:45 PM PDT 24 |
| Peak memory | 608272 kb |
| Host | smart-1e12a3c9-7a1b-416a-be86-c23105da6a22 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896076662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1896076662 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2964826532 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 15767728792 ps |
| CPU time | 4410.34 seconds |
| Started | Jun 30 07:41:42 PM PDT 24 |
| Finished | Jun 30 08:55:13 PM PDT 24 |
| Peak memory | 608124 kb |
| Host | smart-b8dda9fb-d328-4f83-999e-bffaead29dd2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2964826532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2964826532 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3270510185 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 15335120872 ps |
| CPU time | 4569.14 seconds |
| Started | Jun 30 07:40:37 PM PDT 24 |
| Finished | Jun 30 08:56:47 PM PDT 24 |
| Peak memory | 608140 kb |
| Host | smart-bc93dd4b-82b6-4695-b042-189843e45c93 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3270510185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3270510185 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2497796793 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 15431204920 ps |
| CPU time | 4587.59 seconds |
| Started | Jun 30 07:40:25 PM PDT 24 |
| Finished | Jun 30 08:56:54 PM PDT 24 |
| Peak memory | 608344 kb |
| Host | smart-e47971d8-2329-4ffd-96cb-972845bd3a1d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2497796793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2497796793 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.4050580415 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 15432109086 ps |
| CPU time | 3854.89 seconds |
| Started | Jun 30 07:40:19 PM PDT 24 |
| Finished | Jun 30 08:44:35 PM PDT 24 |
| Peak memory | 608356 kb |
| Host | smart-4bd831dd-5510-43d7-8942-8be2de16bab2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4050580415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.4050580415 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1243630889 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 11688530192 ps |
| CPU time | 3506.88 seconds |
| Started | Jun 30 07:41:11 PM PDT 24 |
| Finished | Jun 30 08:39:39 PM PDT 24 |
| Peak memory | 607288 kb |
| Host | smart-59c80203-6516-4f79-b458-139f855ef70f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243630889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1243630889 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3893934945 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 15697970634 ps |
| CPU time | 4840.76 seconds |
| Started | Jun 30 07:41:01 PM PDT 24 |
| Finished | Jun 30 09:01:43 PM PDT 24 |
| Peak memory | 608284 kb |
| Host | smart-55ac44be-7426-4bde-958e-0839d2169bf7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893934945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3893934945 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1979893768 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 15126425100 ps |
| CPU time | 4578.54 seconds |
| Started | Jun 30 07:39:29 PM PDT 24 |
| Finished | Jun 30 08:55:49 PM PDT 24 |
| Peak memory | 608288 kb |
| Host | smart-3e4a4b67-e0f9-4925-a16c-32f7e79702a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197989 3768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1979893768 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.457292331 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 15059737338 ps |
| CPU time | 4485.03 seconds |
| Started | Jun 30 07:41:37 PM PDT 24 |
| Finished | Jun 30 08:56:23 PM PDT 24 |
| Peak memory | 608292 kb |
| Host | smart-f5b36f37-312c-4e91-9aee-f837df54e121 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457292331 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.457292331 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.41652149 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 11571732904 ps |
| CPU time | 2888.36 seconds |
| Started | Jun 30 07:41:10 PM PDT 24 |
| Finished | Jun 30 08:29:19 PM PDT 24 |
| Peak memory | 608124 kb |
| Host | smart-66df5fd5-1706-4fc9-904f-25021f2d1d17 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 41652149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.41652149 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2255263068 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 21987299679 ps |
| CPU time | 3336.46 seconds |
| Started | Jun 30 07:39:11 PM PDT 24 |
| Finished | Jun 30 08:34:49 PM PDT 24 |
| Peak memory | 617544 kb |
| Host | smart-29c2a1fa-2a8b-45e5-add8-379ad3bf507a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2255263068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.2255263068 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.15402530 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 27190914427 ps |
| CPU time | 2921.22 seconds |
| Started | Jun 30 07:38:44 PM PDT 24 |
| Finished | Jun 30 08:27:26 PM PDT 24 |
| Peak memory | 618368 kb |
| Host | smart-ffaac871-ff62-4610-b3e5-88a18682b624 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=15402530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.15402530 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1915262325 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 34160056850 ps |
| CPU time | 3213.91 seconds |
| Started | Jun 30 07:40:00 PM PDT 24 |
| Finished | Jun 30 08:33:35 PM PDT 24 |
| Peak memory | 618568 kb |
| Host | smart-46505f20-7e9e-4828-bd83-46d583b82268 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915262325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.1915262325 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3629740727 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 14798558186 ps |
| CPU time | 4005.1 seconds |
| Started | Jun 30 07:43:05 PM PDT 24 |
| Finished | Jun 30 08:49:51 PM PDT 24 |
| Peak memory | 608444 kb |
| Host | smart-bf632659-fdb3-4e7f-82bb-587656e248ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629740727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3629740727 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.326783812 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 14798304976 ps |
| CPU time | 4245.64 seconds |
| Started | Jun 30 07:43:05 PM PDT 24 |
| Finished | Jun 30 08:53:52 PM PDT 24 |
| Peak memory | 607412 kb |
| Host | smart-26fde877-c46f-4688-83a1-ee4fab407d68 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326783812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.326783812 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1025511436 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 15566909456 ps |
| CPU time | 4173.37 seconds |
| Started | Jun 30 07:43:11 PM PDT 24 |
| Finished | Jun 30 08:52:45 PM PDT 24 |
| Peak memory | 607156 kb |
| Host | smart-713cd6d0-2eaa-4a73-bc6f-ba6cf59761ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025511436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.1025511436 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.2359381408 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 23291793395 ps |
| CPU time | 4562.57 seconds |
| Started | Jun 30 07:40:24 PM PDT 24 |
| Finished | Jun 30 08:56:28 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-c220fa02-2a0a-4e13-9483-6768453ba8e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359381408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.2359381408 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.1536205240 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 15253740800 ps |
| CPU time | 4047.34 seconds |
| Started | Jun 30 07:41:04 PM PDT 24 |
| Finished | Jun 30 08:48:32 PM PDT 24 |
| Peak memory | 607260 kb |
| Host | smart-196c501f-bb68-47a3-86b8-c4e70e06fae1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1536205240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.1536205240 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.2341162255 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 16929082788 ps |
| CPU time | 4713.15 seconds |
| Started | Jun 30 07:43:42 PM PDT 24 |
| Finished | Jun 30 09:02:15 PM PDT 24 |
| Peak memory | 607380 kb |
| Host | smart-bca2d332-e373-4055-9cb6-34766b119b7d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341162255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.2341162255 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.145246990 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 4816265536 ps |
| CPU time | 701.01 seconds |
| Started | Jun 30 07:38:47 PM PDT 24 |
| Finished | Jun 30 07:50:29 PM PDT 24 |
| Peak memory | 608020 kb |
| Host | smart-bf468bfb-7cab-41cb-b321-53dbfb89c30c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145246990 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.145246990 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.1928726678 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2181128629 ps |
| CPU time | 113.02 seconds |
| Started | Jun 30 07:39:11 PM PDT 24 |
| Finished | Jun 30 07:41:04 PM PDT 24 |
| Peak memory | 614372 kb |
| Host | smart-14dc9d63-49e1-433c-8841-616dc7106f0c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928726678 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.1928726678 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.106717189 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 14027917970 ps |
| CPU time | 1859.11 seconds |
| Started | Jun 30 07:39:59 PM PDT 24 |
| Finished | Jun 30 08:10:59 PM PDT 24 |
| Peak memory | 607288 kb |
| Host | smart-0a15d232-5e73-408c-9334-43f6f09857f9 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106717189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.106717189 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.318619379 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5046621300 ps |
| CPU time | 410.11 seconds |
| Started | Jun 30 07:48:28 PM PDT 24 |
| Finished | Jun 30 07:55:19 PM PDT 24 |
| Peak memory | 617716 kb |
| Host | smart-5b041928-0e87-4d9a-b205-f8090e7ce954 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 18619379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.318619379 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.836820203 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2957855250 ps |
| CPU time | 278.56 seconds |
| Started | Jun 30 07:40:57 PM PDT 24 |
| Finished | Jun 30 07:45:36 PM PDT 24 |
| Peak memory | 607084 kb |
| Host | smart-e14ab319-8c4f-416e-a173-f78c3f2d1c2c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=836820203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.836820203 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.641643892 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 18169015000 ps |
| CPU time | 515.14 seconds |
| Started | Jun 30 07:44:27 PM PDT 24 |
| Finished | Jun 30 07:53:04 PM PDT 24 |
| Peak memory | 617460 kb |
| Host | smart-7762b47c-0987-4964-941d-b6af86d4ccfe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=641643892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.641643892 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.1589725032 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 3405678868 ps |
| CPU time | 303.97 seconds |
| Started | Jun 30 07:44:05 PM PDT 24 |
| Finished | Jun 30 07:49:10 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-0c592bf7-fd9e-4736-aa5a-58b72fa56fd8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589725032 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.1589725032 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1486571195 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 2667437319 ps |
| CPU time | 352.9 seconds |
| Started | Jun 30 07:45:07 PM PDT 24 |
| Finished | Jun 30 07:51:00 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-de28b309-db6b-46bc-9f44-38a42a211aa1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486 571195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.1486571195 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2834284822 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3063689149 ps |
| CPU time | 273.69 seconds |
| Started | Jun 30 07:47:57 PM PDT 24 |
| Finished | Jun 30 07:52:31 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-181e663e-be17-46e4-ada8-3ad7952ba42f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834284822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.2834284822 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.1050230520 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 3224194648 ps |
| CPU time | 324.85 seconds |
| Started | Jun 30 07:44:30 PM PDT 24 |
| Finished | Jun 30 07:49:56 PM PDT 24 |
| Peak memory | 609136 kb |
| Host | smart-a0b2efe2-6959-467a-a35a-c3a797bb4540 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050230520 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.1050230520 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.1257860681 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 2233521000 ps |
| CPU time | 234.23 seconds |
| Started | Jun 30 07:45:45 PM PDT 24 |
| Finished | Jun 30 07:49:40 PM PDT 24 |
| Peak memory | 607644 kb |
| Host | smart-6ee69a9a-1292-4d64-a54d-079ed6f6dcb4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257860681 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.1257860681 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.555866617 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 2890559727 ps |
| CPU time | 256.47 seconds |
| Started | Jun 30 07:44:28 PM PDT 24 |
| Finished | Jun 30 07:48:45 PM PDT 24 |
| Peak memory | 609148 kb |
| Host | smart-ee25acaa-4323-4d44-8fcb-0eace2d4c3e2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555866617 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.555866617 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.445737522 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 3228367628 ps |
| CPU time | 319.38 seconds |
| Started | Jun 30 07:48:32 PM PDT 24 |
| Finished | Jun 30 07:53:52 PM PDT 24 |
| Peak memory | 607064 kb |
| Host | smart-00efe4c7-fb21-43f4-babd-1dc2536b94d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445737522 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.445737522 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2552886306 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 2973131615 ps |
| CPU time | 389.06 seconds |
| Started | Jun 30 07:44:30 PM PDT 24 |
| Finished | Jun 30 07:50:59 PM PDT 24 |
| Peak memory | 607464 kb |
| Host | smart-8e9c98ef-9f3e-4ae1-858a-2cddfde73cf2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2552886306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.2552886306 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1780348727 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 5893362494 ps |
| CPU time | 515.45 seconds |
| Started | Jun 30 07:44:03 PM PDT 24 |
| Finished | Jun 30 07:52:39 PM PDT 24 |
| Peak memory | 613748 kb |
| Host | smart-aa32ee04-5710-4b34-b095-b9f39abb3cd8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1780348727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.1780348727 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3672384928 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 8474942104 ps |
| CPU time | 2361.98 seconds |
| Started | Jun 30 07:45:21 PM PDT 24 |
| Finished | Jun 30 08:24:44 PM PDT 24 |
| Peak memory | 607912 kb |
| Host | smart-f07b8662-2758-4344-a507-8382051889b4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3672384928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.3672384928 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1144809942 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 7215925912 ps |
| CPU time | 1697.27 seconds |
| Started | Jun 30 07:45:01 PM PDT 24 |
| Finished | Jun 30 08:13:19 PM PDT 24 |
| Peak memory | 606944 kb |
| Host | smart-88fc1cf2-f9a2-4d3a-b9c8-1256901d6135 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144809942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.1144809942 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3944105382 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 8133920158 ps |
| CPU time | 1493.48 seconds |
| Started | Jun 30 07:45:25 PM PDT 24 |
| Finished | Jun 30 08:10:19 PM PDT 24 |
| Peak memory | 606856 kb |
| Host | smart-b7e0aee1-249b-484f-8531-4d00c4b70c00 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3944105382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.3944105382 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1837001216 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 4009631544 ps |
| CPU time | 403.03 seconds |
| Started | Jun 30 07:44:54 PM PDT 24 |
| Finished | Jun 30 07:51:37 PM PDT 24 |
| Peak memory | 608016 kb |
| Host | smart-742749a3-9687-4b55-9f10-6c5204bc8adb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1837001216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.1837001216 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1726188986 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 254647415436 ps |
| CPU time | 12932.8 seconds |
| Started | Jun 30 07:44:12 PM PDT 24 |
| Finished | Jun 30 11:19:46 PM PDT 24 |
| Peak memory | 608692 kb |
| Host | smart-b46a4a07-769d-4f6b-a053-14f409b3427b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1726188986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1726188986 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.1976237774 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 3361922588 ps |
| CPU time | 330.67 seconds |
| Started | Jun 30 07:45:59 PM PDT 24 |
| Finished | Jun 30 07:51:31 PM PDT 24 |
| Peak memory | 607140 kb |
| Host | smart-10a3e014-84c1-4263-be72-c33007a6dc56 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976237774 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.1976237774 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.2821313220 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 3290879000 ps |
| CPU time | 385.52 seconds |
| Started | Jun 30 07:44:26 PM PDT 24 |
| Finished | Jun 30 07:50:52 PM PDT 24 |
| Peak memory | 609148 kb |
| Host | smart-75d94286-b884-4cf8-91f2-7914a4d791c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821313220 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.2821313220 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1157391922 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 6938714344 ps |
| CPU time | 557.97 seconds |
| Started | Jun 30 07:43:57 PM PDT 24 |
| Finished | Jun 30 07:53:16 PM PDT 24 |
| Peak memory | 607308 kb |
| Host | smart-e339d412-ee0e-4784-9665-21e1ff9d2aee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1157391922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1157391922 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1624741138 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 2884827960 ps |
| CPU time | 285.91 seconds |
| Started | Jun 30 07:49:14 PM PDT 24 |
| Finished | Jun 30 07:54:00 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-b4b8900e-ec0b-4157-b996-7a9652875f7d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624741138 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.1624741138 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1630552700 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 7297954736 ps |
| CPU time | 680.06 seconds |
| Started | Jun 30 07:43:48 PM PDT 24 |
| Finished | Jun 30 07:55:09 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-a720aca7-c9d7-4767-bbb0-dac21bf22b53 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1630552700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.1630552700 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1432871079 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 4873900336 ps |
| CPU time | 580.67 seconds |
| Started | Jun 30 07:42:36 PM PDT 24 |
| Finished | Jun 30 07:52:17 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-ee0c6a2f-0e7a-4125-881b-bfd3c7954fa5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1432871079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.1432871079 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.674848721 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 7077278480 ps |
| CPU time | 949.55 seconds |
| Started | Jun 30 07:47:49 PM PDT 24 |
| Finished | Jun 30 08:03:39 PM PDT 24 |
| Peak memory | 614764 kb |
| Host | smart-3af5da47-7e30-48eb-ab0c-9972d217c745 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674848721 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.674848721 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1313656356 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 7503963701 ps |
| CPU time | 562.88 seconds |
| Started | Jun 30 07:47:03 PM PDT 24 |
| Finished | Jun 30 07:56:26 PM PDT 24 |
| Peak memory | 619172 kb |
| Host | smart-37e32b70-33cf-48f5-82bb-681fc1a1a2d8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1313656356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.1313656356 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3207863185 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 4330959920 ps |
| CPU time | 695.65 seconds |
| Started | Jun 30 07:47:25 PM PDT 24 |
| Finished | Jun 30 07:59:02 PM PDT 24 |
| Peak memory | 610884 kb |
| Host | smart-e84b8e3d-b82b-460e-9ab4-91a17798664d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207863185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3207863185 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3793761582 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 4617313960 ps |
| CPU time | 627.85 seconds |
| Started | Jun 30 07:46:33 PM PDT 24 |
| Finished | Jun 30 07:57:01 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-86e55075-0117-4330-b543-e040ecec4ea4 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793761582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3793761582 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.467855154 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 4689374744 ps |
| CPU time | 622.82 seconds |
| Started | Jun 30 07:45:09 PM PDT 24 |
| Finished | Jun 30 07:55:32 PM PDT 24 |
| Peak memory | 611916 kb |
| Host | smart-c6105326-5c7d-44e5-8a68-c537fc35bd53 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467855154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.467855154 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2832403784 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 5536311368 ps |
| CPU time | 714.31 seconds |
| Started | Jun 30 07:46:46 PM PDT 24 |
| Finished | Jun 30 07:58:41 PM PDT 24 |
| Peak memory | 610816 kb |
| Host | smart-3895c11e-e81c-47f3-9b31-3d5584af5f40 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832403784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2832403784 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.985943439 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 4604913024 ps |
| CPU time | 837.81 seconds |
| Started | Jun 30 07:47:59 PM PDT 24 |
| Finished | Jun 30 08:01:57 PM PDT 24 |
| Peak memory | 610832 kb |
| Host | smart-a1e53e22-5782-44f0-8e23-5df13faa88f7 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985943439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.985943439 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4027659401 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 5075029182 ps |
| CPU time | 755.77 seconds |
| Started | Jun 30 07:46:56 PM PDT 24 |
| Finished | Jun 30 07:59:32 PM PDT 24 |
| Peak memory | 611928 kb |
| Host | smart-2f5c8698-c307-464a-915c-f6ace523aabb |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027659401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4027659401 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.1843826231 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 3506434603 ps |
| CPU time | 250.45 seconds |
| Started | Jun 30 07:47:28 PM PDT 24 |
| Finished | Jun 30 07:51:39 PM PDT 24 |
| Peak memory | 607104 kb |
| Host | smart-fa0c3a70-829c-478f-b569-fe353bd55d81 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843826231 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.1843826231 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2153603210 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 3114201798 ps |
| CPU time | 511.87 seconds |
| Started | Jun 30 07:47:29 PM PDT 24 |
| Finished | Jun 30 07:56:02 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-a840e5c7-876f-4331-859b-7a630027fe1c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153603210 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.2153603210 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1353653721 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 3355082376 ps |
| CPU time | 216.74 seconds |
| Started | Jun 30 07:48:30 PM PDT 24 |
| Finished | Jun 30 07:52:07 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-1e34da55-ca3b-4d65-8803-ac0d82f77e50 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353653721 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.1353653721 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3662923798 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 5127340712 ps |
| CPU time | 621.42 seconds |
| Started | Jun 30 07:47:50 PM PDT 24 |
| Finished | Jun 30 07:58:12 PM PDT 24 |
| Peak memory | 609104 kb |
| Host | smart-a77e532b-b4ec-43f4-b546-cf1be285fb26 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662923798 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.3662923798 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3199451850 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 3835140142 ps |
| CPU time | 359.31 seconds |
| Started | Jun 30 07:46:32 PM PDT 24 |
| Finished | Jun 30 07:52:32 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-c759c052-36fd-49a0-b9b8-9573c6e0e971 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199451850 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.3199451850 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.295222132 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 5516460398 ps |
| CPU time | 509.46 seconds |
| Started | Jun 30 07:45:45 PM PDT 24 |
| Finished | Jun 30 07:54:15 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-568709f8-f84b-4649-b217-b9ec920010bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295222132 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.295222132 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2135593476 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 3997579294 ps |
| CPU time | 442.43 seconds |
| Started | Jun 30 07:46:26 PM PDT 24 |
| Finished | Jun 30 07:53:49 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-46f0c9d4-2546-4dac-ad09-548f43a9b55f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135593476 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.2135593476 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.306978100 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 11337646056 ps |
| CPU time | 1315.22 seconds |
| Started | Jun 30 07:47:11 PM PDT 24 |
| Finished | Jun 30 08:09:07 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-703002a7-99f3-400d-b83c-ee3cec89c567 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306978100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.306978100 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2634750534 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 3861084732 ps |
| CPU time | 538.59 seconds |
| Started | Jun 30 07:48:46 PM PDT 24 |
| Finished | Jun 30 07:57:45 PM PDT 24 |
| Peak memory | 607492 kb |
| Host | smart-14c2c219-28bf-4ac8-a5a8-442ea7910c90 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634750534 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.2634750534 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.902703993 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 4250636656 ps |
| CPU time | 604.64 seconds |
| Started | Jun 30 07:48:09 PM PDT 24 |
| Finished | Jun 30 07:58:15 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-154d8d8e-a7e9-4e85-80fb-5e7ba530f37d |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902703993 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.902703993 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2806870578 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 2899244392 ps |
| CPU time | 202.63 seconds |
| Started | Jun 30 07:49:18 PM PDT 24 |
| Finished | Jun 30 07:52:41 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-feac9328-817b-4422-84ea-c1aae6aef4a2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806870578 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.2806870578 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1462304113 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 26663678536 ps |
| CPU time | 6180.3 seconds |
| Started | Jun 30 07:45:35 PM PDT 24 |
| Finished | Jun 30 09:28:37 PM PDT 24 |
| Peak memory | 608184 kb |
| Host | smart-b41b6a3e-3348-45cc-b81f-eca6d22001f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462304113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.1462304113 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.4087774423 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 4537154324 ps |
| CPU time | 633.95 seconds |
| Started | Jun 30 07:45:16 PM PDT 24 |
| Finished | Jun 30 07:55:50 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-6bc95b92-0e66-4fa9-9edf-2ad96deebb3c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40877 74423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.4087774423 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.2409245051 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 2862444042 ps |
| CPU time | 254.49 seconds |
| Started | Jun 30 07:45:17 PM PDT 24 |
| Finished | Jun 30 07:49:32 PM PDT 24 |
| Peak memory | 607488 kb |
| Host | smart-19a8221b-03e9-47d6-a81d-e935bf6f0179 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409245051 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.2409245051 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1387361528 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 5466899564 ps |
| CPU time | 636.69 seconds |
| Started | Jun 30 07:46:54 PM PDT 24 |
| Finished | Jun 30 07:57:31 PM PDT 24 |
| Peak memory | 609224 kb |
| Host | smart-e0bd762d-ef46-427b-a77a-b01bd87d79d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387361528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.1387361528 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.1745943890 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 3138111800 ps |
| CPU time | 205.88 seconds |
| Started | Jun 30 07:48:09 PM PDT 24 |
| Finished | Jun 30 07:51:36 PM PDT 24 |
| Peak memory | 607292 kb |
| Host | smart-d6b388d6-887e-4498-af3d-d122819181dc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745943890 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.1745943890 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3484649392 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 5637186400 ps |
| CPU time | 543.5 seconds |
| Started | Jun 30 07:41:46 PM PDT 24 |
| Finished | Jun 30 07:50:50 PM PDT 24 |
| Peak memory | 609256 kb |
| Host | smart-aa588fe3-ea17-47e7-bd28-ace985bdee11 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3484649392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.3484649392 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.2488789009 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 3504980880 ps |
| CPU time | 591.49 seconds |
| Started | Jun 30 07:45:08 PM PDT 24 |
| Finished | Jun 30 07:55:00 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-ce6fa473-0672-4c2f-9ede-63c73e61df43 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488789009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.2488789009 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1523656537 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 6210740040 ps |
| CPU time | 1394.81 seconds |
| Started | Jun 30 07:44:55 PM PDT 24 |
| Finished | Jun 30 08:08:11 PM PDT 24 |
| Peak memory | 608676 kb |
| Host | smart-5bb5f6ca-63f6-46e0-840e-04e3d20790d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1523656537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.1523656537 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2669124588 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 7029828006 ps |
| CPU time | 1485.92 seconds |
| Started | Jun 30 07:45:25 PM PDT 24 |
| Finished | Jun 30 08:10:12 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-58d3ad6d-65b4-493f-9b42-644eb7e00d9c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669124588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.2669124588 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.1872843055 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 3214016286 ps |
| CPU time | 809.88 seconds |
| Started | Jun 30 07:45:41 PM PDT 24 |
| Finished | Jun 30 07:59:11 PM PDT 24 |
| Peak memory | 614264 kb |
| Host | smart-02a223c3-36b8-4123-b57f-826eaf148043 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872843055 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.1872843055 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.2537719419 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 10307826292 ps |
| CPU time | 2565.61 seconds |
| Started | Jun 30 07:45:45 PM PDT 24 |
| Finished | Jun 30 08:28:32 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-f33021ac-800a-48df-8e6d-3eee9f2ddca0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537719419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.2537719419 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2055858690 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 2785666082 ps |
| CPU time | 211.75 seconds |
| Started | Jun 30 07:44:49 PM PDT 24 |
| Finished | Jun 30 07:48:21 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-a0f96a9d-a388-4392-95bd-70cd43d2ab7f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20 55858690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.2055858690 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1168798238 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2396620778 ps |
| CPU time | 214.86 seconds |
| Started | Jun 30 07:45:28 PM PDT 24 |
| Finished | Jun 30 07:49:03 PM PDT 24 |
| Peak memory | 607548 kb |
| Host | smart-027c82f8-70ab-4103-b915-31e8805d8a3e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168798238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.1168798238 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.663894531 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 3441130436 ps |
| CPU time | 655.42 seconds |
| Started | Jun 30 07:49:52 PM PDT 24 |
| Finished | Jun 30 08:00:48 PM PDT 24 |
| Peak memory | 609100 kb |
| Host | smart-929e0119-b389-4716-8ebd-7dbc783efb38 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=663894531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.663894531 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.2384649167 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2754080620 ps |
| CPU time | 230.77 seconds |
| Started | Jun 30 07:40:00 PM PDT 24 |
| Finished | Jun 30 07:43:51 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-efd8ddba-1666-40a4-a51a-4807186b3866 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384649167 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.2384649167 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.313653092 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 2180626720 ps |
| CPU time | 230.57 seconds |
| Started | Jun 30 07:41:31 PM PDT 24 |
| Finished | Jun 30 07:45:22 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-3b14f706-e56e-4d20-b108-c3bdc4b40737 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313653092 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.313653092 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.21011053 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 2867760208 ps |
| CPU time | 286.57 seconds |
| Started | Jun 30 07:40:46 PM PDT 24 |
| Finished | Jun 30 07:45:34 PM PDT 24 |
| Peak memory | 607060 kb |
| Host | smart-0119925e-52a3-4789-b25d-b7fad1e388c9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21011053 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_example_manufacturer.21011053 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.116929169 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 2644310022 ps |
| CPU time | 127.54 seconds |
| Started | Jun 30 07:39:56 PM PDT 24 |
| Finished | Jun 30 07:42:04 PM PDT 24 |
| Peak memory | 607256 kb |
| Host | smart-4e0cb395-75bb-48bc-8dfb-50ca2dc2266c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116929169 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_example_rom.116929169 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.1745518387 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 5680554932 ps |
| CPU time | 615.7 seconds |
| Started | Jun 30 07:49:13 PM PDT 24 |
| Finished | Jun 30 07:59:29 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-3f37407a-70a9-45d2-b6de-cbefbee563bd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1745518387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.1745518387 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.1182217111 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 5750652812 ps |
| CPU time | 1318.78 seconds |
| Started | Jun 30 07:42:07 PM PDT 24 |
| Finished | Jun 30 08:04:06 PM PDT 24 |
| Peak memory | 606560 kb |
| Host | smart-0fe44941-ead2-44bd-b34e-5de86ccbf44d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182217111 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.1182217111 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2100054685 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5464339164 ps |
| CPU time | 1114.85 seconds |
| Started | Jun 30 07:41:11 PM PDT 24 |
| Finished | Jun 30 07:59:47 PM PDT 24 |
| Peak memory | 609144 kb |
| Host | smart-b54dbae2-9a0e-4e6d-a6d3-cacbf66e77c9 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100054685 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.2100054685 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.97475520 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 7428022539 ps |
| CPU time | 1256.56 seconds |
| Started | Jun 30 07:47:49 PM PDT 24 |
| Finished | Jun 30 08:08:46 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-a6e4d7d4-1939-4735-b0af-8c888e1b673e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97475520 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.97475520 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2919735580 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 5931898704 ps |
| CPU time | 976.3 seconds |
| Started | Jun 30 07:40:26 PM PDT 24 |
| Finished | Jun 30 07:56:43 PM PDT 24 |
| Peak memory | 607532 kb |
| Host | smart-75caf00c-0134-4973-9b36-799248f74e93 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919735580 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.2919735580 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2328702424 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 3639971420 ps |
| CPU time | 346.51 seconds |
| Started | Jun 30 07:43:32 PM PDT 24 |
| Finished | Jun 30 07:49:19 PM PDT 24 |
| Peak memory | 609216 kb |
| Host | smart-69455080-665c-4e29-909a-7b9c582d36d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328702424 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.2328702424 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3099298305 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 4375020442 ps |
| CPU time | 419.8 seconds |
| Started | Jun 30 07:41:40 PM PDT 24 |
| Finished | Jun 30 07:48:41 PM PDT 24 |
| Peak memory | 607228 kb |
| Host | smart-9586a21f-0f16-4bcf-b35f-c7006b25166d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30 99298305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.3099298305 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1155639876 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 5722562832 ps |
| CPU time | 1165.44 seconds |
| Started | Jun 30 07:48:19 PM PDT 24 |
| Finished | Jun 30 08:07:45 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-a3a90d89-a7df-4807-98d6-8b5bc156fa1a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155639876 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.1155639876 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2013167237 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 3556286524 ps |
| CPU time | 604.88 seconds |
| Started | Jun 30 07:42:29 PM PDT 24 |
| Finished | Jun 30 07:52:34 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-6d5088d0-318c-4a8b-970e-4f4bf87a18cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013167237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.2013167237 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2107915070 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 4684803258 ps |
| CPU time | 643.79 seconds |
| Started | Jun 30 07:48:41 PM PDT 24 |
| Finished | Jun 30 07:59:25 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-172b1467-5722-4e47-9069-07e0e259ca2d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2107915070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2107915070 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.933341638 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 3822614800 ps |
| CPU time | 501.39 seconds |
| Started | Jun 30 07:47:09 PM PDT 24 |
| Finished | Jun 30 07:55:32 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-9825b249-04cf-4f22-9a5f-42333db1dc2d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9333416 38 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.933341638 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.1993189437 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 24915800865 ps |
| CPU time | 2025.65 seconds |
| Started | Jun 30 07:40:51 PM PDT 24 |
| Finished | Jun 30 08:14:37 PM PDT 24 |
| Peak memory | 610700 kb |
| Host | smart-f7271c7c-ed79-4f50-b030-b46c5adb6f1b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993189437 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.1993189437 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.4220863924 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 24994747721 ps |
| CPU time | 2635.45 seconds |
| Started | Jun 30 07:46:57 PM PDT 24 |
| Finished | Jun 30 08:30:54 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-69758733-da02-4e4a-baf5-f6a8ab580bbc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4220863924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.4220863924 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3605128070 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 2030878064 ps |
| CPU time | 178.03 seconds |
| Started | Jun 30 07:51:35 PM PDT 24 |
| Finished | Jun 30 07:54:33 PM PDT 24 |
| Peak memory | 606508 kb |
| Host | smart-c26b9266-3253-475e-8eac-b1e11a646c48 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3605128070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.3605128070 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.2510358176 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 3450295289 ps |
| CPU time | 356.76 seconds |
| Started | Jun 30 07:48:54 PM PDT 24 |
| Finished | Jun 30 07:54:51 PM PDT 24 |
| Peak memory | 607112 kb |
| Host | smart-fcb1234f-e19a-49f2-b7d0-6b444456f4f4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510358176 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.2510358176 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.1213711127 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 2693381044 ps |
| CPU time | 330.14 seconds |
| Started | Jun 30 07:46:06 PM PDT 24 |
| Finished | Jun 30 07:51:37 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-abec75aa-44ca-419f-a3eb-03086a037c95 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213711127 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.1213711127 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1804122333 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2326003265 ps |
| CPU time | 211.07 seconds |
| Started | Jun 30 07:45:11 PM PDT 24 |
| Finished | Jun 30 07:48:43 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-639bec50-e5cc-4fd8-8e85-80953df9be82 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804122333 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.1804122333 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.713570073 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 3282124094 ps |
| CPU time | 263.1 seconds |
| Started | Jun 30 07:49:23 PM PDT 24 |
| Finished | Jun 30 07:53:46 PM PDT 24 |
| Peak memory | 607332 kb |
| Host | smart-8ed81eb2-b79d-4553-92e7-e6a0c8660c15 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713570073 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.713570073 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.2031417328 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 7753890368 ps |
| CPU time | 1979.47 seconds |
| Started | Jun 30 07:45:19 PM PDT 24 |
| Finished | Jun 30 08:18:20 PM PDT 24 |
| Peak memory | 607780 kb |
| Host | smart-1815c308-e67b-409b-85d5-5807a9bcbb4e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031417328 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_multistream.2031417328 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.10140161 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 3035042962 ps |
| CPU time | 462.78 seconds |
| Started | Jun 30 07:45:40 PM PDT 24 |
| Finished | Jun 30 07:53:24 PM PDT 24 |
| Peak memory | 607088 kb |
| Host | smart-f0167adf-d02b-4db1-a54e-4c9ba601075e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10140161 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_hmac_oneshot.10140161 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.2222086888 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 3064921888 ps |
| CPU time | 400.85 seconds |
| Started | Jun 30 07:48:29 PM PDT 24 |
| Finished | Jun 30 07:55:11 PM PDT 24 |
| Peak memory | 607108 kb |
| Host | smart-e8a72b25-8fdc-4c26-800e-c643fbc4e925 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222086888 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.2222086888 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1493388582 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 3907401480 ps |
| CPU time | 560.49 seconds |
| Started | Jun 30 07:40:39 PM PDT 24 |
| Finished | Jun 30 07:50:00 PM PDT 24 |
| Peak memory | 609420 kb |
| Host | smart-91f979f4-df45-4cba-9106-ad33aa3a9402 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493388582 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.1493388582 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3363059991 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 5418460580 ps |
| CPU time | 964.19 seconds |
| Started | Jun 30 07:41:29 PM PDT 24 |
| Finished | Jun 30 07:57:34 PM PDT 24 |
| Peak memory | 608240 kb |
| Host | smart-4996ec1e-43b4-4481-a931-c078938dbdcf |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363059991 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.3363059991 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2829459026 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 5397919144 ps |
| CPU time | 699.97 seconds |
| Started | Jun 30 07:41:06 PM PDT 24 |
| Finished | Jun 30 07:52:47 PM PDT 24 |
| Peak memory | 608200 kb |
| Host | smart-0e289069-6619-4e23-94ac-c45cfe176598 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829459026 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.2829459026 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3974886647 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 4923581532 ps |
| CPU time | 648.12 seconds |
| Started | Jun 30 07:40:52 PM PDT 24 |
| Finished | Jun 30 07:51:41 PM PDT 24 |
| Peak memory | 607436 kb |
| Host | smart-1f34b68c-52c5-4491-8630-5c27335fd15f |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974886647 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.3974886647 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.4043588702 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 65306954406 ps |
| CPU time | 11478.6 seconds |
| Started | Jun 30 07:42:14 PM PDT 24 |
| Finished | Jun 30 10:53:34 PM PDT 24 |
| Peak memory | 624136 kb |
| Host | smart-107b73cc-e88a-4d55-bfcc-6ea48d11dea3 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4043588702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.4043588702 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3382960182 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 7203369624 ps |
| CPU time | 1296.5 seconds |
| Started | Jun 30 07:45:09 PM PDT 24 |
| Finished | Jun 30 08:06:47 PM PDT 24 |
| Peak memory | 616040 kb |
| Host | smart-16b7f394-45d2-4b29-b9ff-1be45412427d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382 960182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.3382960182 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3323145727 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 7751620138 ps |
| CPU time | 1209.27 seconds |
| Started | Jun 30 07:44:52 PM PDT 24 |
| Finished | Jun 30 08:05:02 PM PDT 24 |
| Peak memory | 615652 kb |
| Host | smart-f7bfd652-d810-488b-9957-b208e6fa99c2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3323145727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.3323145727 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3349596289 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 10801779616 ps |
| CPU time | 2190.01 seconds |
| Started | Jun 30 07:47:36 PM PDT 24 |
| Finished | Jun 30 08:24:08 PM PDT 24 |
| Peak memory | 615676 kb |
| Host | smart-be7e4426-507b-4cc0-8dbc-0d19e14c8c39 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3349596289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3349596289 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.537026321 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 11088078072 ps |
| CPU time | 2616.18 seconds |
| Started | Jun 30 07:45:15 PM PDT 24 |
| Finished | Jun 30 08:28:52 PM PDT 24 |
| Peak memory | 615420 kb |
| Host | smart-46df7662-734c-44eb-be89-e3395674156f |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=537026321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.537026321 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2465793688 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 7283024800 ps |
| CPU time | 1448.39 seconds |
| Started | Jun 30 07:46:18 PM PDT 24 |
| Finished | Jun 30 08:10:28 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-5425f39f-abc3-4aec-8011-40f9ead46df2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24657 93688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.2465793688 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.2943033008 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 3522159230 ps |
| CPU time | 305.25 seconds |
| Started | Jun 30 07:46:03 PM PDT 24 |
| Finished | Jun 30 07:51:08 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-06a6e716-0fd6-44db-9c12-e77d7cf6ca5c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943033008 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.2943033008 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.1341554310 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 3634476124 ps |
| CPU time | 291.54 seconds |
| Started | Jun 30 07:41:36 PM PDT 24 |
| Finished | Jun 30 07:46:28 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-1e8422fe-172b-4916-939e-cd3bb64cafd6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341554310 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.1341554310 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.1409689343 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2302363340 ps |
| CPU time | 177.09 seconds |
| Started | Jun 30 07:45:59 PM PDT 24 |
| Finished | Jun 30 07:48:56 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-a8512534-3c22-40b0-b029-978d6a6ad114 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409689343 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.1409689343 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.1851852235 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 2721137532 ps |
| CPU time | 355.76 seconds |
| Started | Jun 30 07:46:35 PM PDT 24 |
| Finished | Jun 30 07:52:31 PM PDT 24 |
| Peak memory | 609124 kb |
| Host | smart-18d5b37a-2d69-4dc0-86da-2fd4385b2d21 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851852235 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.1851852235 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2516266262 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 3630725724 ps |
| CPU time | 292.5 seconds |
| Started | Jun 30 07:46:45 PM PDT 24 |
| Finished | Jun 30 07:51:38 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-6806b6da-4aca-4ec5-89d2-076d9307d0aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516266262 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.2516266262 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1259859883 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 2979758045 ps |
| CPU time | 291.13 seconds |
| Started | Jun 30 07:45:55 PM PDT 24 |
| Finished | Jun 30 07:50:46 PM PDT 24 |
| Peak memory | 609140 kb |
| Host | smart-15e36107-006f-45aa-85cc-3f435d9b00f5 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259859883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.1259859883 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2178403249 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 3082299026 ps |
| CPU time | 275.3 seconds |
| Started | Jun 30 07:49:08 PM PDT 24 |
| Finished | Jun 30 07:53:44 PM PDT 24 |
| Peak memory | 607080 kb |
| Host | smart-344d47c0-2e79-478b-bfe8-2a18cbde0ca8 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21784032 49 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2178403249 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.2149689949 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 2490789024 ps |
| CPU time | 289.23 seconds |
| Started | Jun 30 07:48:43 PM PDT 24 |
| Finished | Jun 30 07:53:33 PM PDT 24 |
| Peak memory | 607056 kb |
| Host | smart-1bbe4a69-d831-474a-82f2-fc4df907f3d9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149689949 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.2149689949 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1011278839 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 3279288838 ps |
| CPU time | 306.77 seconds |
| Started | Jun 30 07:42:31 PM PDT 24 |
| Finished | Jun 30 07:47:38 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-bab6d74c-1e89-4d1f-9789-7b90362ede39 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011278839 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.1011278839 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.275727725 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3522432900 ps |
| CPU time | 491.04 seconds |
| Started | Jun 30 07:48:14 PM PDT 24 |
| Finished | Jun 30 07:56:25 PM PDT 24 |
| Peak memory | 608400 kb |
| Host | smart-847a5dcb-98e6-47c5-b4c4-abaf8ef98858 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=275727725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.275727725 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1597309394 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 3390781169 ps |
| CPU time | 149.39 seconds |
| Started | Jun 30 07:42:20 PM PDT 24 |
| Finished | Jun 30 07:44:50 PM PDT 24 |
| Peak memory | 617572 kb |
| Host | smart-ffc41a1b-a104-4715-9a40-ffecb36b9cef |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15973093 94 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.1597309394 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3785441081 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 13411157122 ps |
| CPU time | 1213.91 seconds |
| Started | Jun 30 07:41:42 PM PDT 24 |
| Finished | Jun 30 08:01:56 PM PDT 24 |
| Peak memory | 619160 kb |
| Host | smart-151eb75f-39a9-43b6-8e50-5ed562769f31 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785441081 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.3785441081 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1267409070 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 2380260309 ps |
| CPU time | 119.12 seconds |
| Started | Jun 30 07:43:45 PM PDT 24 |
| Finished | Jun 30 07:45:45 PM PDT 24 |
| Peak memory | 615896 kb |
| Host | smart-5fec71b4-7c00-4708-ab9e-ac8187125da6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1267409070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.1267409070 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.788573362 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2432924339 ps |
| CPU time | 105.14 seconds |
| Started | Jun 30 07:41:57 PM PDT 24 |
| Finished | Jun 30 07:43:43 PM PDT 24 |
| Peak memory | 614444 kb |
| Host | smart-a48dcfa0-b9c1-4f78-b9f9-a5c5a25e543e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788573362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.788573362 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.936610443 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 48384336220 ps |
| CPU time | 5574.34 seconds |
| Started | Jun 30 07:42:13 PM PDT 24 |
| Finished | Jun 30 09:15:09 PM PDT 24 |
| Peak memory | 615004 kb |
| Host | smart-25328b29-fa1b-456a-8d63-9bcd71403283 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936610443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_lc_walkthrough_dev.936610443 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1216852609 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 9682403125 ps |
| CPU time | 1098.26 seconds |
| Started | Jun 30 07:42:54 PM PDT 24 |
| Finished | Jun 30 08:01:13 PM PDT 24 |
| Peak memory | 623536 kb |
| Host | smart-c6826b60-7045-4672-a2e9-e8a05e6715b4 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216852609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1216852609 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1528725748 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 24165008920 ps |
| CPU time | 2309.75 seconds |
| Started | Jun 30 07:43:23 PM PDT 24 |
| Finished | Jun 30 08:21:54 PM PDT 24 |
| Peak memory | 614924 kb |
| Host | smart-3ad643d2-5e29-4917-aec1-e76bd8ff4f82 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1528725748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.1528725748 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1230790683 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 16818026640 ps |
| CPU time | 3933.4 seconds |
| Started | Jun 30 07:44:28 PM PDT 24 |
| Finished | Jun 30 08:50:02 PM PDT 24 |
| Peak memory | 609228 kb |
| Host | smart-0f96a0a8-59be-4432-8675-4df39f50797b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1230790683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.1230790683 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1984598566 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 17968092260 ps |
| CPU time | 3815.19 seconds |
| Started | Jun 30 07:43:18 PM PDT 24 |
| Finished | Jun 30 08:46:54 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-c387df55-adcc-466d-b4b6-80bb4bc7c550 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1984598566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1984598566 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2491006987 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 24061516703 ps |
| CPU time | 5153.09 seconds |
| Started | Jun 30 07:47:41 PM PDT 24 |
| Finished | Jun 30 09:13:35 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-035e28ff-f166-4299-a915-a335358d4e8e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491006987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.2491006987 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3556239529 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 3698480788 ps |
| CPU time | 501.9 seconds |
| Started | Jun 30 07:43:58 PM PDT 24 |
| Finished | Jun 30 07:52:20 PM PDT 24 |
| Peak memory | 609060 kb |
| Host | smart-08aed234-e012-4924-9edf-62a40b3da637 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556239529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.3556239529 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.1117776828 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 6112207272 ps |
| CPU time | 985.44 seconds |
| Started | Jun 30 07:44:23 PM PDT 24 |
| Finished | Jun 30 08:00:49 PM PDT 24 |
| Peak memory | 607336 kb |
| Host | smart-67d9bd80-1006-441d-b9e8-cc190f8e0757 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1117776828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.1117776828 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.2146234634 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 8322654098 ps |
| CPU time | 2209.5 seconds |
| Started | Jun 30 07:51:23 PM PDT 24 |
| Finished | Jun 30 08:28:13 PM PDT 24 |
| Peak memory | 607268 kb |
| Host | smart-2511acfe-a982-45b2-8aea-55be7d657b5c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146234634 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.2146234634 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2301050976 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 2938887471 ps |
| CPU time | 274.29 seconds |
| Started | Jun 30 07:41:59 PM PDT 24 |
| Finished | Jun 30 07:46:34 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-b8083974-d169-40ca-a4fd-1d7a8226cbda |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301050976 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.2301050976 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.574605046 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 7697173784 ps |
| CPU time | 1192.97 seconds |
| Started | Jun 30 07:42:26 PM PDT 24 |
| Finished | Jun 30 08:02:19 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-871beff7-43cc-4e84-8007-e9b985a372a1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=574605046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.574605046 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.4069737376 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 6958847260 ps |
| CPU time | 1136.86 seconds |
| Started | Jun 30 07:41:14 PM PDT 24 |
| Finished | Jun 30 08:00:11 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-5107a221-8143-4663-9a93-3751f7bea16a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4069737376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.4069737376 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3019712376 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 8058757400 ps |
| CPU time | 1301.55 seconds |
| Started | Jun 30 07:42:31 PM PDT 24 |
| Finished | Jun 30 08:04:13 PM PDT 24 |
| Peak memory | 609244 kb |
| Host | smart-a0fbb270-e96b-499b-9bae-7e6ea8ef2e0a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3019712376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.3019712376 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3300461017 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 4275451852 ps |
| CPU time | 776.32 seconds |
| Started | Jun 30 07:42:05 PM PDT 24 |
| Finished | Jun 30 07:55:01 PM PDT 24 |
| Peak memory | 609104 kb |
| Host | smart-77d54b1c-6547-472c-baf4-16a1d9f1df17 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3300461017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3300461017 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1422208656 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 3507082256 ps |
| CPU time | 378.71 seconds |
| Started | Jun 30 07:50:10 PM PDT 24 |
| Finished | Jun 30 07:56:29 PM PDT 24 |
| Peak memory | 609124 kb |
| Host | smart-8b90d926-bc6c-46c8-b3dc-35ace8cd77b5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422208656 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.1422208656 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.221819699 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 3387669644 ps |
| CPU time | 264.29 seconds |
| Started | Jun 30 07:40:18 PM PDT 24 |
| Finished | Jun 30 07:44:43 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-9c06694e-655c-43dd-8afc-71b369ad423c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221819699 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.221819699 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.3759950284 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 3025567418 ps |
| CPU time | 239.09 seconds |
| Started | Jun 30 07:47:00 PM PDT 24 |
| Finished | Jun 30 07:51:00 PM PDT 24 |
| Peak memory | 607088 kb |
| Host | smart-99c6bc50-728b-4468-89c4-40650f2c6147 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759950284 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.3759950284 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.3585522698 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 4798191662 ps |
| CPU time | 768.19 seconds |
| Started | Jun 30 07:49:20 PM PDT 24 |
| Finished | Jun 30 08:02:09 PM PDT 24 |
| Peak memory | 608128 kb |
| Host | smart-c3095642-9c71-4f9c-8a4c-78c1d2709ee3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585522698 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.3585522698 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.3793996525 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 9033740224 ps |
| CPU time | 486.42 seconds |
| Started | Jun 30 07:48:20 PM PDT 24 |
| Finished | Jun 30 07:56:27 PM PDT 24 |
| Peak memory | 608808 kb |
| Host | smart-be176558-7bfa-4956-af16-273bd85ae90f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793996525 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.3793996525 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2029548612 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 10429436582 ps |
| CPU time | 1485.79 seconds |
| Started | Jun 30 07:42:22 PM PDT 24 |
| Finished | Jun 30 08:07:09 PM PDT 24 |
| Peak memory | 608892 kb |
| Host | smart-c00c02e9-20a7-4f98-bc3e-aa99cba0a686 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029 548612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.2029548612 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.928172849 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 29286368490 ps |
| CPU time | 3444.39 seconds |
| Started | Jun 30 07:46:49 PM PDT 24 |
| Finished | Jun 30 08:44:14 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-545a4b49-4de1-4350-8f86-e26e4ae9d8cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928 172849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.928172849 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3148776459 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 18843734632 ps |
| CPU time | 1825.65 seconds |
| Started | Jun 30 07:42:52 PM PDT 24 |
| Finished | Jun 30 08:13:18 PM PDT 24 |
| Peak memory | 608984 kb |
| Host | smart-22849b47-9d37-4391-9e76-97a6725e4865 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3148776459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3148776459 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2549249953 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 26836048350 ps |
| CPU time | 2116.98 seconds |
| Started | Jun 30 07:47:58 PM PDT 24 |
| Finished | Jun 30 08:23:15 PM PDT 24 |
| Peak memory | 608680 kb |
| Host | smart-1810da78-b8f7-4116-86d8-7aa2404178aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2549249953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2549249953 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3318061232 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 9145684796 ps |
| CPU time | 564.01 seconds |
| Started | Jun 30 07:42:05 PM PDT 24 |
| Finished | Jun 30 07:51:30 PM PDT 24 |
| Peak memory | 609236 kb |
| Host | smart-f40750c1-c974-4143-aed3-9bfe02387a2a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318061232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.3318061232 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1599568959 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 6759412500 ps |
| CPU time | 587.55 seconds |
| Started | Jun 30 07:42:36 PM PDT 24 |
| Finished | Jun 30 07:52:24 PM PDT 24 |
| Peak memory | 614996 kb |
| Host | smart-9d6caca1-aea6-4d41-b8bc-c1d0cf53c98e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1599568959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1599568959 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2547981829 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 8604419211 ps |
| CPU time | 323.08 seconds |
| Started | Jun 30 07:41:29 PM PDT 24 |
| Finished | Jun 30 07:46:52 PM PDT 24 |
| Peak memory | 609116 kb |
| Host | smart-7dadc7a1-f5df-4b96-8b98-10ee12d19a07 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547981829 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.2547981829 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.756906436 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 3942390728 ps |
| CPU time | 521.45 seconds |
| Started | Jun 30 07:41:29 PM PDT 24 |
| Finished | Jun 30 07:50:11 PM PDT 24 |
| Peak memory | 615044 kb |
| Host | smart-1be0229f-d05b-417b-91ca-74ca801aa9bf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=756906436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.756906436 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1544010336 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 11912525672 ps |
| CPU time | 1272.47 seconds |
| Started | Jun 30 07:44:31 PM PDT 24 |
| Finished | Jun 30 08:05:44 PM PDT 24 |
| Peak memory | 608984 kb |
| Host | smart-f365950d-8c6a-489d-8ebf-f559c6131109 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544010336 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1544010336 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2089507449 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6656927912 ps |
| CPU time | 372.1 seconds |
| Started | Jun 30 07:47:07 PM PDT 24 |
| Finished | Jun 30 07:53:19 PM PDT 24 |
| Peak memory | 608096 kb |
| Host | smart-281dd82a-6215-4287-b0d2-0fed374589d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089507449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2089507449 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1583122567 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 5703807620 ps |
| CPU time | 566.37 seconds |
| Started | Jun 30 07:43:11 PM PDT 24 |
| Finished | Jun 30 07:52:38 PM PDT 24 |
| Peak memory | 609244 kb |
| Host | smart-36f44d6e-e1cc-4215-9a6f-30d99d6bcc5e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583122567 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.1583122567 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3206823014 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 21497547327 ps |
| CPU time | 2429.68 seconds |
| Started | Jun 30 07:42:04 PM PDT 24 |
| Finished | Jun 30 08:22:34 PM PDT 24 |
| Peak memory | 609320 kb |
| Host | smart-ef6fd2f6-8bbd-495a-b985-62813942a525 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3206823014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3206823014 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1266853118 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 21900858704 ps |
| CPU time | 1872.77 seconds |
| Started | Jun 30 07:48:36 PM PDT 24 |
| Finished | Jun 30 08:19:50 PM PDT 24 |
| Peak memory | 608688 kb |
| Host | smart-524b68cc-e788-43e8-bc71-510266137ec3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1266853118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1266853118 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3218129170 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 37165250358 ps |
| CPU time | 3563.71 seconds |
| Started | Jun 30 07:42:44 PM PDT 24 |
| Finished | Jun 30 08:42:08 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-ea81ef5f-005b-493e-8fcd-a5fc379d51c7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218129170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.3218129170 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3117610326 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 5355722360 ps |
| CPU time | 284.37 seconds |
| Started | Jun 30 07:47:28 PM PDT 24 |
| Finished | Jun 30 07:52:13 PM PDT 24 |
| Peak memory | 609344 kb |
| Host | smart-c2c028b0-0920-4108-8d8c-ae9739be5dda |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3117610326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3117610326 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2898288023 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 3035752728 ps |
| CPU time | 281.94 seconds |
| Started | Jun 30 07:42:03 PM PDT 24 |
| Finished | Jun 30 07:46:46 PM PDT 24 |
| Peak memory | 607280 kb |
| Host | smart-fc87bbb3-9303-49b3-a162-776866beab89 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898288023 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.2898288023 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2315591391 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 5881976588 ps |
| CPU time | 464.95 seconds |
| Started | Jun 30 07:43:44 PM PDT 24 |
| Finished | Jun 30 07:51:30 PM PDT 24 |
| Peak memory | 615528 kb |
| Host | smart-6bd5b680-f045-4873-9336-ea76ad7558d0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2315591391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.2315591391 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3436214983 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 5474069644 ps |
| CPU time | 499.85 seconds |
| Started | Jun 30 07:46:42 PM PDT 24 |
| Finished | Jun 30 07:55:02 PM PDT 24 |
| Peak memory | 609236 kb |
| Host | smart-436c491e-6506-4d39-84b6-8a667de280e4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34362149 83 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3436214983 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1739345348 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 6960373312 ps |
| CPU time | 448.81 seconds |
| Started | Jun 30 07:47:15 PM PDT 24 |
| Finished | Jun 30 07:54:44 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-61bc8b9c-7b23-4ef3-ace0-d63ce640bdeb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1739345348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.1739345348 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1084683571 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 5697363398 ps |
| CPU time | 454.29 seconds |
| Started | Jun 30 07:48:51 PM PDT 24 |
| Finished | Jun 30 07:56:26 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-44a6fa6e-1384-4607-a63a-f46b0123f7a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084683571 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.1084683571 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1085614763 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 8881506184 ps |
| CPU time | 1421.08 seconds |
| Started | Jun 30 07:42:45 PM PDT 24 |
| Finished | Jun 30 08:06:27 PM PDT 24 |
| Peak memory | 608732 kb |
| Host | smart-45bf3ec4-9474-4571-80ad-134a806bbe16 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085614763 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.1085614763 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1273584898 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 5299897256 ps |
| CPU time | 572.44 seconds |
| Started | Jun 30 07:43:48 PM PDT 24 |
| Finished | Jun 30 07:53:22 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-a8a1a27a-db95-45d1-8736-1500931be8b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273584898 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1273584898 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.210268750 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 6073873420 ps |
| CPU time | 393.96 seconds |
| Started | Jun 30 07:49:13 PM PDT 24 |
| Finished | Jun 30 07:55:47 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-d3f8918d-902f-432a-8eb3-84dab119384f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210268750 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.210268750 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.3715946790 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 5650167168 ps |
| CPU time | 752.64 seconds |
| Started | Jun 30 07:44:13 PM PDT 24 |
| Finished | Jun 30 07:56:46 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-9ffa5a53-d237-41ab-aa1d-1b5cfb053396 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371 5946790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.3715946790 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1099969570 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 8954690504 ps |
| CPU time | 698.45 seconds |
| Started | Jun 30 07:46:04 PM PDT 24 |
| Finished | Jun 30 07:57:43 PM PDT 24 |
| Peak memory | 607960 kb |
| Host | smart-f5e905a7-047d-42c0-8644-26ebcd1e3116 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099969570 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.1099969570 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1619320106 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 12260630810 ps |
| CPU time | 1451.77 seconds |
| Started | Jun 30 07:43:28 PM PDT 24 |
| Finished | Jun 30 08:07:41 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-11ead566-5fdf-43e3-ab9d-28eabf19579e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1619320106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.1619320106 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2182218257 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 4386979638 ps |
| CPU time | 461.12 seconds |
| Started | Jun 30 07:41:35 PM PDT 24 |
| Finished | Jun 30 07:49:17 PM PDT 24 |
| Peak memory | 607116 kb |
| Host | smart-22f23217-4182-4fea-87fa-3efd45c389fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182218257 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.2182218257 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3973674748 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 5396077876 ps |
| CPU time | 555.02 seconds |
| Started | Jun 30 07:40:43 PM PDT 24 |
| Finished | Jun 30 07:49:59 PM PDT 24 |
| Peak memory | 639608 kb |
| Host | smart-80de7cae-0406-4142-a995-e43e2e8dddde |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3973674748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.3973674748 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1733573364 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 2702438046 ps |
| CPU time | 197.98 seconds |
| Started | Jun 30 07:48:29 PM PDT 24 |
| Finished | Jun 30 07:51:47 PM PDT 24 |
| Peak memory | 607116 kb |
| Host | smart-b6163ffc-0266-4de2-9db4-28641ea29345 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733573364 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.1733573364 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.252932780 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 4385594832 ps |
| CPU time | 462.2 seconds |
| Started | Jun 30 07:43:14 PM PDT 24 |
| Finished | Jun 30 07:50:57 PM PDT 24 |
| Peak memory | 607832 kb |
| Host | smart-3ee2574e-920f-431e-9c61-2578b92a51ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252932780 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rstmgr_sw_req.252932780 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1576619124 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 2909555840 ps |
| CPU time | 156.12 seconds |
| Started | Jun 30 07:40:54 PM PDT 24 |
| Finished | Jun 30 07:43:31 PM PDT 24 |
| Peak memory | 609064 kb |
| Host | smart-1febe902-b718-4e28-bc1f-3f682712f218 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576619124 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.1576619124 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1241966651 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 3258348624 ps |
| CPU time | 405.37 seconds |
| Started | Jun 30 07:49:07 PM PDT 24 |
| Finished | Jun 30 07:55:54 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-235c389f-7938-4cee-9d08-a8dcaa28c89f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1241966651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.1241966651 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.960550750 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 2033716915 ps |
| CPU time | 192.1 seconds |
| Started | Jun 30 07:46:57 PM PDT 24 |
| Finished | Jun 30 07:50:10 PM PDT 24 |
| Peak memory | 607412 kb |
| Host | smart-c4835d4a-16ff-4252-969b-bfba54183b4c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960550750 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.960550750 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1679089866 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 5553557236 ps |
| CPU time | 914.89 seconds |
| Started | Jun 30 07:44:13 PM PDT 24 |
| Finished | Jun 30 07:59:29 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-a811baa2-0f94-4d53-b555-f6c8eac9bcd0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16790 89866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.1679089866 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2734859810 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 5799600542 ps |
| CPU time | 1076.58 seconds |
| Started | Jun 30 07:44:39 PM PDT 24 |
| Finished | Jun 30 08:02:36 PM PDT 24 |
| Peak memory | 609096 kb |
| Host | smart-a0aa98d8-edae-4bc1-9c8f-41aff773a3c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2734859810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.2734859810 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.838184939 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 4637715749 ps |
| CPU time | 417.23 seconds |
| Started | Jun 30 07:47:53 PM PDT 24 |
| Finished | Jun 30 07:54:51 PM PDT 24 |
| Peak memory | 618308 kb |
| Host | smart-fc16067f-8c9e-4097-ab3f-60e8b61c2c2c |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838184939 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.838184939 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.72653795 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 4539034840 ps |
| CPU time | 585.58 seconds |
| Started | Jun 30 07:46:46 PM PDT 24 |
| Finished | Jun 30 07:56:33 PM PDT 24 |
| Peak memory | 617672 kb |
| Host | smart-3226ae51-54cf-4283-a5ce-ec0d31538767 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726537 95 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.72653795 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.591414713 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 2534003808 ps |
| CPU time | 204.15 seconds |
| Started | Jun 30 07:49:32 PM PDT 24 |
| Finished | Jun 30 07:52:57 PM PDT 24 |
| Peak memory | 607008 kb |
| Host | smart-43ae9dc5-dd8e-48e7-9fe6-898056bbd880 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591414713 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rv_plic_smoketest.591414713 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.4216767110 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 3031977350 ps |
| CPU time | 243.3 seconds |
| Started | Jun 30 07:43:18 PM PDT 24 |
| Finished | Jun 30 07:47:21 PM PDT 24 |
| Peak memory | 606280 kb |
| Host | smart-0cde2244-37bd-4739-8662-2b90b883e6ae |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216767110 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.4216767110 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.768447714 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 3097874080 ps |
| CPU time | 259.94 seconds |
| Started | Jun 30 07:49:02 PM PDT 24 |
| Finished | Jun 30 07:53:22 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-fb69b23c-5c6a-4b46-b4da-67666377cedd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768447714 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_timer_smoketest.768447714 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3915970134 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 8835670034 ps |
| CPU time | 905.75 seconds |
| Started | Jun 30 07:48:11 PM PDT 24 |
| Finished | Jun 30 08:03:17 PM PDT 24 |
| Peak memory | 607604 kb |
| Host | smart-c223cdc5-c1e7-47b1-94c7-d75949e734ae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39159701 34 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.3915970134 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3011904669 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 3082284446 ps |
| CPU time | 239.4 seconds |
| Started | Jun 30 07:48:56 PM PDT 24 |
| Finished | Jun 30 07:52:56 PM PDT 24 |
| Peak memory | 608608 kb |
| Host | smart-f11e0d85-f149-49f0-ad91-3fc9d59c76d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011904 669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.3011904669 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1147801520 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3353889384 ps |
| CPU time | 275.77 seconds |
| Started | Jun 30 07:41:17 PM PDT 24 |
| Finished | Jun 30 07:45:54 PM PDT 24 |
| Peak memory | 607984 kb |
| Host | smart-0902b8b6-27f2-47b4-ae25-c108a19c272e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147801520 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.1147801520 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2018794109 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 9837481998 ps |
| CPU time | 1467.55 seconds |
| Started | Jun 30 07:40:56 PM PDT 24 |
| Finished | Jun 30 08:05:25 PM PDT 24 |
| Peak memory | 607356 kb |
| Host | smart-e00767c3-cb48-4849-b484-a26c6237c4a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018794109 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.2018794109 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1860957086 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 9331576100 ps |
| CPU time | 1017.37 seconds |
| Started | Jun 30 07:47:06 PM PDT 24 |
| Finished | Jun 30 08:04:04 PM PDT 24 |
| Peak memory | 608432 kb |
| Host | smart-51630103-4f3b-4a08-b44f-d6ccc6bac9b6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860957086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.1860957086 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3672894458 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 8379430388 ps |
| CPU time | 974.49 seconds |
| Started | Jun 30 07:45:29 PM PDT 24 |
| Finished | Jun 30 08:01:44 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-cd142d87-56d8-4f90-88e2-c701cf52c3e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672894458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.3672894458 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.1755092385 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 7546497121 ps |
| CPU time | 1163.97 seconds |
| Started | Jun 30 07:41:24 PM PDT 24 |
| Finished | Jun 30 08:00:48 PM PDT 24 |
| Peak memory | 624212 kb |
| Host | smart-f08b8c8b-ea73-440e-b6c1-d0d6919861d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755092385 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.1755092385 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.1803168331 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 3458603178 ps |
| CPU time | 311.16 seconds |
| Started | Jun 30 07:41:12 PM PDT 24 |
| Finished | Jun 30 07:46:24 PM PDT 24 |
| Peak memory | 622176 kb |
| Host | smart-32a23c65-aec2-4137-91fd-3154dd53973e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803168331 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.1803168331 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3118544082 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3267584652 ps |
| CPU time | 347.42 seconds |
| Started | Jun 30 07:40:19 PM PDT 24 |
| Finished | Jun 30 07:46:07 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-ba3a15ac-5e44-4565-9cac-2fe0cdc45eed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118544082 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.3118544082 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.4265676610 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 5019706040 ps |
| CPU time | 767.73 seconds |
| Started | Jun 30 07:46:46 PM PDT 24 |
| Finished | Jun 30 07:59:35 PM PDT 24 |
| Peak memory | 607468 kb |
| Host | smart-24730c13-ca76-4759-af7f-364d8040797f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265676610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.4265676610 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1025395298 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 4375295948 ps |
| CPU time | 608.73 seconds |
| Started | Jun 30 07:46:29 PM PDT 24 |
| Finished | Jun 30 07:56:39 PM PDT 24 |
| Peak memory | 608736 kb |
| Host | smart-d5f934fa-7cb0-418f-be23-fb8ce84a0d65 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025395298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1025395298 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2114042244 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 3388085980 ps |
| CPU time | 258.09 seconds |
| Started | Jun 30 07:49:33 PM PDT 24 |
| Finished | Jun 30 07:53:51 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-e92bf812-c426-45f0-9e86-404dbed4ba4c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114042244 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.2114042244 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3930454332 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 20204230951 ps |
| CPU time | 3199.51 seconds |
| Started | Jun 30 07:44:33 PM PDT 24 |
| Finished | Jun 30 08:37:54 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-59c848a0-9552-4065-8445-ed775d234e66 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930454332 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.3930454332 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2715900322 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 5211668357 ps |
| CPU time | 781.78 seconds |
| Started | Jun 30 07:44:04 PM PDT 24 |
| Finished | Jun 30 07:57:08 PM PDT 24 |
| Peak memory | 611196 kb |
| Host | smart-323c6ec5-71a7-4f3a-af40-39c3d9e2efc4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715900322 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.2715900322 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3670486874 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 2736574017 ps |
| CPU time | 316.04 seconds |
| Started | Jun 30 07:44:34 PM PDT 24 |
| Finished | Jun 30 07:49:51 PM PDT 24 |
| Peak memory | 611936 kb |
| Host | smart-653be47e-86cf-4e95-a00a-b002b4ff851f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670486874 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.3670486874 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2575824713 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4442919327 ps |
| CPU time | 471.02 seconds |
| Started | Jun 30 07:43:50 PM PDT 24 |
| Finished | Jun 30 07:51:42 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-9b1411af-8cae-4950-b491-4af4005e09a6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575824713 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.2575824713 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3259485480 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 25010473650 ps |
| CPU time | 1946.9 seconds |
| Started | Jun 30 07:43:05 PM PDT 24 |
| Finished | Jun 30 08:15:32 PM PDT 24 |
| Peak memory | 612836 kb |
| Host | smart-9e1be0d7-c2fa-492a-86f6-c7a92b2663ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32594854 80 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.3259485480 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2673802806 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5875612616 ps |
| CPU time | 743.68 seconds |
| Started | Jun 30 07:43:08 PM PDT 24 |
| Finished | Jun 30 07:55:32 PM PDT 24 |
| Peak memory | 608380 kb |
| Host | smart-b5d9369b-cf49-4239-ae4d-4a09ad6ddebd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673802806 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2673802806 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.4233527861 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 4397876576 ps |
| CPU time | 534.26 seconds |
| Started | Jun 30 07:42:35 PM PDT 24 |
| Finished | Jun 30 07:51:30 PM PDT 24 |
| Peak memory | 618568 kb |
| Host | smart-f9f75892-81d3-4c2c-9979-91e03109a439 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4233527861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.4233527861 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.2246351355 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 3265027664 ps |
| CPU time | 264.95 seconds |
| Started | Jun 30 07:50:16 PM PDT 24 |
| Finished | Jun 30 07:54:42 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-05f686b3-d52c-486d-8a9d-7ad6d5e421b0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246351355 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.2246351355 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2453521565 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 8527534337 ps |
| CPU time | 1726.44 seconds |
| Started | Jun 30 07:41:23 PM PDT 24 |
| Finished | Jun 30 08:10:11 PM PDT 24 |
| Peak memory | 620376 kb |
| Host | smart-7501c8a4-aa9a-4e3c-b97d-b4dfc86398e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453521565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.2453521565 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1234807741 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 8402666222 ps |
| CPU time | 1062.34 seconds |
| Started | Jun 30 07:42:42 PM PDT 24 |
| Finished | Jun 30 08:00:25 PM PDT 24 |
| Peak memory | 620428 kb |
| Host | smart-342cc355-508a-4d63-9e02-47fe34195af5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234807741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1234807741 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.337636145 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 79160969394 ps |
| CPU time | 13311.5 seconds |
| Started | Jun 30 07:42:39 PM PDT 24 |
| Finished | Jun 30 11:24:32 PM PDT 24 |
| Peak memory | 632308 kb |
| Host | smart-11966900-1e0b-4a07-80f8-40b6214f97d0 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=337636145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.337636145 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3291284589 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 4570667894 ps |
| CPU time | 477.12 seconds |
| Started | Jun 30 07:40:13 PM PDT 24 |
| Finished | Jun 30 07:48:10 PM PDT 24 |
| Peak memory | 616068 kb |
| Host | smart-1384a042-ae2c-4c1f-b3cc-e93d97af1962 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291284589 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.3291284589 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3407826939 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 4619455300 ps |
| CPU time | 775.23 seconds |
| Started | Jun 30 07:40:43 PM PDT 24 |
| Finished | Jun 30 07:53:39 PM PDT 24 |
| Peak memory | 615872 kb |
| Host | smart-84fde223-c480-4d88-b17a-fc2895c5d8e1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407826939 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.3407826939 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1755993566 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 4494836482 ps |
| CPU time | 589.92 seconds |
| Started | Jun 30 07:40:45 PM PDT 24 |
| Finished | Jun 30 07:50:37 PM PDT 24 |
| Peak memory | 624036 kb |
| Host | smart-6c6da4a5-62a0-4c40-bafd-edd06efdcdba |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755993566 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.1755993566 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.3099355982 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2211466932 ps |
| CPU time | 199.17 seconds |
| Started | Jun 30 07:46:46 PM PDT 24 |
| Finished | Jun 30 07:50:06 PM PDT 24 |
| Peak memory | 618036 kb |
| Host | smart-a58ba0f9-f8ed-49b8-80b0-fa05bb1adac6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3099355982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.3099355982 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.2180781926 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 12980312885 ps |
| CPU time | 1727.46 seconds |
| Started | Jun 30 07:48:28 PM PDT 24 |
| Finished | Jun 30 08:17:17 PM PDT 24 |
| Peak memory | 620412 kb |
| Host | smart-73b8d92d-8290-40fc-af6e-9a293d42befc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180781926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.2180781926 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.3361131359 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 3838074325 ps |
| CPU time | 301.27 seconds |
| Started | Jun 30 07:47:59 PM PDT 24 |
| Finished | Jun 30 07:53:01 PM PDT 24 |
| Peak memory | 619460 kb |
| Host | smart-0feaf869-823c-4924-93ae-696c1b0f9e76 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3361131359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.3361131359 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.2953313825 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 15007058274 ps |
| CPU time | 4072.16 seconds |
| Started | Jun 30 07:54:45 PM PDT 24 |
| Finished | Jun 30 09:02:38 PM PDT 24 |
| Peak memory | 607152 kb |
| Host | smart-c96aa467-01e1-4158-94f4-0647af0b4dc2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953313825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.2953313825 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.1548792277 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 15949436954 ps |
| CPU time | 4049.13 seconds |
| Started | Jun 30 07:52:42 PM PDT 24 |
| Finished | Jun 30 09:00:13 PM PDT 24 |
| Peak memory | 608212 kb |
| Host | smart-89cf5f2a-dde5-4610-a486-aaafd3a8c7cf |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548792277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.1548792277 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1339384409 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 16021142760 ps |
| CPU time | 3996.78 seconds |
| Started | Jun 30 07:53:30 PM PDT 24 |
| Finished | Jun 30 09:00:08 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-8563dc66-fbe3-4ca3-a955-7c64441d5520 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339384409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.1339384409 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.1260535567 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 15176824523 ps |
| CPU time | 3858.58 seconds |
| Started | Jun 30 07:53:12 PM PDT 24 |
| Finished | Jun 30 08:57:32 PM PDT 24 |
| Peak memory | 607872 kb |
| Host | smart-27e25290-a17f-412a-9b67-a08660deffed |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260535567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.1260535567 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3862783865 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 11393401639 ps |
| CPU time | 3343.71 seconds |
| Started | Jun 30 07:52:50 PM PDT 24 |
| Finished | Jun 30 08:48:35 PM PDT 24 |
| Peak memory | 608196 kb |
| Host | smart-fed5dcbd-55fe-4f5d-b4a9-e18e34947ad0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862783865 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.3862783865 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2539826824 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 14681311880 ps |
| CPU time | 4210.95 seconds |
| Started | Jun 30 07:52:30 PM PDT 24 |
| Finished | Jun 30 09:02:42 PM PDT 24 |
| Peak memory | 607320 kb |
| Host | smart-62420158-d9d0-45da-b9e6-6da9c8a347bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539826824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.2539826824 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2790836908 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 14600678696 ps |
| CPU time | 4037.87 seconds |
| Started | Jun 30 07:52:59 PM PDT 24 |
| Finished | Jun 30 09:00:18 PM PDT 24 |
| Peak memory | 607276 kb |
| Host | smart-3b54805c-6205-4764-a176-4842e41bdf99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790836908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.2790836908 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1867241126 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 14636463224 ps |
| CPU time | 5242.46 seconds |
| Started | Jun 30 07:52:21 PM PDT 24 |
| Finished | Jun 30 09:19:44 PM PDT 24 |
| Peak memory | 607248 kb |
| Host | smart-a823111c-455c-444a-b402-13ede9ee1b38 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867241126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.1867241126 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2630339131 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 14010912141 ps |
| CPU time | 4009.22 seconds |
| Started | Jun 30 07:52:54 PM PDT 24 |
| Finished | Jun 30 08:59:43 PM PDT 24 |
| Peak memory | 607384 kb |
| Host | smart-53be8c01-de50-4834-823d-ec3d83255c78 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630339131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.2630339131 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.1207787635 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 29624084091 ps |
| CPU time | 4612.09 seconds |
| Started | Jun 30 07:53:45 PM PDT 24 |
| Finished | Jun 30 09:10:38 PM PDT 24 |
| Peak memory | 608476 kb |
| Host | smart-f2ab5306-42f6-4dd7-ac84-93a1a737660a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207787635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.1207787635 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.3484385887 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 15664814668 ps |
| CPU time | 4328.89 seconds |
| Started | Jun 30 07:52:05 PM PDT 24 |
| Finished | Jun 30 09:04:15 PM PDT 24 |
| Peak memory | 607900 kb |
| Host | smart-b2caf78b-51d3-4d2c-ad97-760e7c373093 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=3484385887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.3484385887 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.3276583699 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 17361699046 ps |
| CPU time | 4924.64 seconds |
| Started | Jun 30 07:52:24 PM PDT 24 |
| Finished | Jun 30 09:14:29 PM PDT 24 |
| Peak memory | 608152 kb |
| Host | smart-a78c3c1c-72b3-4897-a14e-13d1b5b033be |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276583699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.3276583699 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.2497410771 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 5798075620 ps |
| CPU time | 731.81 seconds |
| Started | Jun 30 07:50:12 PM PDT 24 |
| Finished | Jun 30 08:02:24 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-8e1b3397-41df-4ff5-a085-2293b8d3d169 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497410771 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.2497410771 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.2716357923 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 2582605337 ps |
| CPU time | 110.3 seconds |
| Started | Jun 30 07:49:06 PM PDT 24 |
| Finished | Jun 30 07:50:57 PM PDT 24 |
| Peak memory | 614416 kb |
| Host | smart-65a80009-001f-46f4-af91-46a1edf60a50 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716357923 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.2716357923 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.1372723624 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 5491276008 ps |
| CPU time | 730.77 seconds |
| Started | Jun 30 08:02:47 PM PDT 24 |
| Finished | Jun 30 08:14:58 PM PDT 24 |
| Peak memory | 617172 kb |
| Host | smart-8f7f742b-c2e0-4bdd-a644-b7b9ec83a33d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1372723624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.1372723624 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1549046789 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 10239106828 ps |
| CPU time | 1108.84 seconds |
| Started | Jun 30 08:03:25 PM PDT 24 |
| Finished | Jun 30 08:21:55 PM PDT 24 |
| Peak memory | 620756 kb |
| Host | smart-8b2b4898-f21c-4ebe-a15f-541cb24ac42a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549046789 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.1549046789 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2459624075 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 8419363188 ps |
| CPU time | 1999.22 seconds |
| Started | Jun 30 08:03:04 PM PDT 24 |
| Finished | Jun 30 08:36:24 PM PDT 24 |
| Peak memory | 618552 kb |
| Host | smart-9d627ffc-b8be-4edb-82cc-601fff35f025 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2459624075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.2459624075 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3198760259 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 4016814340 ps |
| CPU time | 471.81 seconds |
| Started | Jun 30 08:01:42 PM PDT 24 |
| Finished | Jun 30 08:09:35 PM PDT 24 |
| Peak memory | 642764 kb |
| Host | smart-37d612d0-27fb-4d59-b72d-c9bc76f55c42 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198760259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3198760259 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2919966914 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 8971871948 ps |
| CPU time | 753.4 seconds |
| Started | Jun 30 08:02:54 PM PDT 24 |
| Finished | Jun 30 08:15:28 PM PDT 24 |
| Peak memory | 620924 kb |
| Host | smart-524cae0a-070b-403c-8681-76b4fa16d4c5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919966914 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.2919966914 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1191413129 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 7270793404 ps |
| CPU time | 1575.56 seconds |
| Started | Jun 30 08:03:27 PM PDT 24 |
| Finished | Jun 30 08:29:43 PM PDT 24 |
| Peak memory | 618520 kb |
| Host | smart-36497ad7-408f-4094-b04a-f020e711dbde |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1191413129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1191413129 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.909611484 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 7585644670 ps |
| CPU time | 532.73 seconds |
| Started | Jun 30 08:02:26 PM PDT 24 |
| Finished | Jun 30 08:11:19 PM PDT 24 |
| Peak memory | 618984 kb |
| Host | smart-b65f0643-a887-4790-ba0e-058be50353e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909611484 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.909611484 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3899870634 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 8369699796 ps |
| CPU time | 1634.11 seconds |
| Started | Jun 30 08:02:02 PM PDT 24 |
| Finished | Jun 30 08:29:17 PM PDT 24 |
| Peak memory | 618864 kb |
| Host | smart-0612b3b7-cf2b-485e-bc71-68a46f35ec4f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3899870634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.3899870634 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.257541662 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 12655592520 ps |
| CPU time | 959.38 seconds |
| Started | Jun 30 08:01:34 PM PDT 24 |
| Finished | Jun 30 08:17:34 PM PDT 24 |
| Peak memory | 621024 kb |
| Host | smart-72739028-a3e4-4b60-a3e8-648092caa956 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257541662 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.257541662 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.4139935856 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 9035563464 ps |
| CPU time | 1843.87 seconds |
| Started | Jun 30 08:02:19 PM PDT 24 |
| Finished | Jun 30 08:33:04 PM PDT 24 |
| Peak memory | 618512 kb |
| Host | smart-c473a586-0c45-4f9a-b5d0-1e338326a84a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4139935856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.4139935856 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1789647241 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 11113393206 ps |
| CPU time | 864.73 seconds |
| Started | Jun 30 08:04:14 PM PDT 24 |
| Finished | Jun 30 08:18:40 PM PDT 24 |
| Peak memory | 619116 kb |
| Host | smart-8ec8ef8e-1746-405b-9cae-420a22cd01d6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789647241 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.1789647241 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3017593870 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 4389702610 ps |
| CPU time | 864.77 seconds |
| Started | Jun 30 08:02:44 PM PDT 24 |
| Finished | Jun 30 08:17:09 PM PDT 24 |
| Peak memory | 618588 kb |
| Host | smart-d21ef38b-c847-41a7-b9f9-99546bcf6147 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3017593870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.3017593870 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1437388547 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 8919602520 ps |
| CPU time | 1794.17 seconds |
| Started | Jun 30 08:02:02 PM PDT 24 |
| Finished | Jun 30 08:31:57 PM PDT 24 |
| Peak memory | 618576 kb |
| Host | smart-37e46c18-075d-41df-8912-582cc4810790 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1437388547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.1437388547 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2718841137 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 12524194300 ps |
| CPU time | 2501.34 seconds |
| Started | Jun 30 08:02:33 PM PDT 24 |
| Finished | Jun 30 08:44:15 PM PDT 24 |
| Peak memory | 618336 kb |
| Host | smart-f0fe31cd-648f-48e5-9f5c-141a624265a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2718841137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.2718841137 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1760266799 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 3568449568 ps |
| CPU time | 545.75 seconds |
| Started | Jun 30 08:03:52 PM PDT 24 |
| Finished | Jun 30 08:12:59 PM PDT 24 |
| Peak memory | 618292 kb |
| Host | smart-8a0a0b50-669d-470c-a669-24621f7508e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1760266799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.1760266799 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3715289924 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 3425785308 ps |
| CPU time | 427.47 seconds |
| Started | Jun 30 08:03:38 PM PDT 24 |
| Finished | Jun 30 08:10:46 PM PDT 24 |
| Peak memory | 647016 kb |
| Host | smart-cef477f0-af49-417e-bd93-7803f6bb2641 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715289924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3715289924 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.1894290453 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 4958139760 ps |
| CPU time | 473.29 seconds |
| Started | Jun 30 08:06:25 PM PDT 24 |
| Finished | Jun 30 08:14:19 PM PDT 24 |
| Peak memory | 615136 kb |
| Host | smart-821b51e4-f782-4566-b349-3fd81e0277cd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1894290453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.1894290453 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.518246602 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 13088460384 ps |
| CPU time | 2803.57 seconds |
| Started | Jun 30 08:02:47 PM PDT 24 |
| Finished | Jun 30 08:49:31 PM PDT 24 |
| Peak memory | 618496 kb |
| Host | smart-e90feb86-a296-4f89-8095-5042072e5218 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=518246602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.518246602 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3218387520 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 4084973350 ps |
| CPU time | 461.36 seconds |
| Started | Jun 30 08:06:40 PM PDT 24 |
| Finished | Jun 30 08:14:23 PM PDT 24 |
| Peak memory | 618892 kb |
| Host | smart-3712b18a-7006-49ea-adfa-9dcab269dcc5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3218387520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.3218387520 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.3058290425 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 13506022938 ps |
| CPU time | 1476.57 seconds |
| Started | Jun 30 07:50:12 PM PDT 24 |
| Finished | Jun 30 08:14:49 PM PDT 24 |
| Peak memory | 606852 kb |
| Host | smart-6ab90617-ee65-4400-899e-cb3584849859 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058290425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.3 058290425 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3472912974 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4725135474 ps |
| CPU time | 574.92 seconds |
| Started | Jun 30 07:58:12 PM PDT 24 |
| Finished | Jun 30 08:07:48 PM PDT 24 |
| Peak memory | 617460 kb |
| Host | smart-8a3811a1-6fe3-4fd2-a8a8-55b8e8d386e6 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 472912974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.3472912974 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.2024488965 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 3360205306 ps |
| CPU time | 388.63 seconds |
| Started | Jun 30 07:50:06 PM PDT 24 |
| Finished | Jun 30 07:56:35 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-5da183ed-9ce3-4ffd-a5de-ce2e3fcf45e2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2024488965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.2024488965 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1290963762 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 18741235412 ps |
| CPU time | 534.31 seconds |
| Started | Jun 30 07:53:51 PM PDT 24 |
| Finished | Jun 30 08:02:47 PM PDT 24 |
| Peak memory | 617444 kb |
| Host | smart-e62a1ae6-e30f-4288-8a79-272d3f698f69 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1290963762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1290963762 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.839082966 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 2673479590 ps |
| CPU time | 289.4 seconds |
| Started | Jun 30 07:53:09 PM PDT 24 |
| Finished | Jun 30 07:57:59 PM PDT 24 |
| Peak memory | 607116 kb |
| Host | smart-9d53f96e-14ac-4c71-96ba-edd75ecdfaee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839082966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.839082966 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1143690871 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 2670729161 ps |
| CPU time | 302.42 seconds |
| Started | Jun 30 07:53:31 PM PDT 24 |
| Finished | Jun 30 07:58:34 PM PDT 24 |
| Peak memory | 609200 kb |
| Host | smart-352cc889-0820-41eb-b00f-19e306f3d8a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143 690871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.1143690871 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3109606012 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2933974494 ps |
| CPU time | 307.33 seconds |
| Started | Jun 30 07:58:42 PM PDT 24 |
| Finished | Jun 30 08:03:50 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-77010b63-54bc-4f41-986d-00ff3a6ec128 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109606012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.3109606012 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.3577763653 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 3224225496 ps |
| CPU time | 305.28 seconds |
| Started | Jun 30 07:59:00 PM PDT 24 |
| Finished | Jun 30 08:04:06 PM PDT 24 |
| Peak memory | 607496 kb |
| Host | smart-6d640ec5-ef74-4ca5-9d3b-436a86e16f28 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577763653 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.3577763653 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.3213175343 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2596838240 ps |
| CPU time | 293.62 seconds |
| Started | Jun 30 07:54:47 PM PDT 24 |
| Finished | Jun 30 07:59:41 PM PDT 24 |
| Peak memory | 607664 kb |
| Host | smart-00344735-6ecc-48e8-bbd8-fb8353fee996 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213175343 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.3213175343 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.2201787937 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 3783741429 ps |
| CPU time | 383.38 seconds |
| Started | Jun 30 07:53:27 PM PDT 24 |
| Finished | Jun 30 07:59:51 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-5a23ece3-e4de-443b-92f2-65f314b838a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201787937 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.2201787937 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.1517001892 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 2981318468 ps |
| CPU time | 296.36 seconds |
| Started | Jun 30 07:59:13 PM PDT 24 |
| Finished | Jun 30 08:04:10 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-66dbcf11-932d-4853-9435-aecc1693f5dd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517001892 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.1517001892 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.2330592365 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 3021488359 ps |
| CPU time | 285.97 seconds |
| Started | Jun 30 07:54:29 PM PDT 24 |
| Finished | Jun 30 07:59:15 PM PDT 24 |
| Peak memory | 607784 kb |
| Host | smart-1dcc15e2-a7aa-4b95-9a71-affae8ada250 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2330592365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.2330592365 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2521803216 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 4704476778 ps |
| CPU time | 520.72 seconds |
| Started | Jun 30 07:53:49 PM PDT 24 |
| Finished | Jun 30 08:02:31 PM PDT 24 |
| Peak memory | 613676 kb |
| Host | smart-ef6886e5-2d9a-49b1-9bd7-3758cd0ae124 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2521803216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.2521803216 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2932792669 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 7288367668 ps |
| CPU time | 1525.89 seconds |
| Started | Jun 30 07:54:08 PM PDT 24 |
| Finished | Jun 30 08:19:35 PM PDT 24 |
| Peak memory | 608224 kb |
| Host | smart-e8bee260-8b81-49e9-96fa-bdf6466a02df |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2932792669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.2932792669 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4007571287 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 7627476216 ps |
| CPU time | 2050.26 seconds |
| Started | Jun 30 07:55:39 PM PDT 24 |
| Finished | Jun 30 08:29:50 PM PDT 24 |
| Peak memory | 606924 kb |
| Host | smart-42d0de2e-9817-47d3-a783-f799884d5c86 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007571287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.4007571287 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2691664524 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3672852360 ps |
| CPU time | 453.75 seconds |
| Started | Jun 30 07:54:49 PM PDT 24 |
| Finished | Jun 30 08:02:24 PM PDT 24 |
| Peak memory | 646960 kb |
| Host | smart-5ef1c51f-6844-4fce-9471-5bb4c1881e8f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691664524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.2691664524 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2400479505 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 13243297360 ps |
| CPU time | 1946.48 seconds |
| Started | Jun 30 07:54:21 PM PDT 24 |
| Finished | Jun 30 08:26:48 PM PDT 24 |
| Peak memory | 608876 kb |
| Host | smart-0173b572-8f26-4138-9f99-20f225962379 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400479505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.2400479505 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.78208899 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 7675878882 ps |
| CPU time | 1310.32 seconds |
| Started | Jun 30 07:54:38 PM PDT 24 |
| Finished | Jun 30 08:16:29 PM PDT 24 |
| Peak memory | 606892 kb |
| Host | smart-39176bb5-a21b-4290-af5d-70d6279a5563 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=78208899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.78208899 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.988607250 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 3803876436 ps |
| CPU time | 411.83 seconds |
| Started | Jun 30 07:54:12 PM PDT 24 |
| Finished | Jun 30 08:01:04 PM PDT 24 |
| Peak memory | 608100 kb |
| Host | smart-1d56bb1d-a334-4e2f-b586-07018627bf22 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=988607250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.988607250 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.757570221 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 255232801976 ps |
| CPU time | 12998.2 seconds |
| Started | Jun 30 07:55:28 PM PDT 24 |
| Finished | Jun 30 11:32:08 PM PDT 24 |
| Peak memory | 607364 kb |
| Host | smart-cb81f2ea-1bbd-4bdd-9887-37f6674f7a0b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=757570221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.757570221 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.1879934870 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 3879838870 ps |
| CPU time | 421.31 seconds |
| Started | Jun 30 07:56:14 PM PDT 24 |
| Finished | Jun 30 08:03:16 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-52e941bf-5287-432c-b5b7-0e7d9504eba1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879934870 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.1879934870 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2565089081 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 7754353680 ps |
| CPU time | 465.83 seconds |
| Started | Jun 30 07:53:19 PM PDT 24 |
| Finished | Jun 30 08:01:05 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-3e2302b8-3699-405f-b389-f2fccd70419f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2565089081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2565089081 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3460481145 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 3330695332 ps |
| CPU time | 400.12 seconds |
| Started | Jun 30 08:00:13 PM PDT 24 |
| Finished | Jun 30 08:06:53 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-550cdf37-c11a-4ee2-a43c-8a381aa0d1ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460481145 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.3460481145 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3801315552 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 8307680984 ps |
| CPU time | 777.12 seconds |
| Started | Jun 30 07:54:00 PM PDT 24 |
| Finished | Jun 30 08:06:58 PM PDT 24 |
| Peak memory | 607316 kb |
| Host | smart-b35f0e82-9b9a-416e-af6d-f70287761565 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3801315552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.3801315552 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1508791566 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 5677428288 ps |
| CPU time | 638.46 seconds |
| Started | Jun 30 07:53:43 PM PDT 24 |
| Finished | Jun 30 08:04:22 PM PDT 24 |
| Peak memory | 608364 kb |
| Host | smart-e78967e2-5c77-473f-8b19-d5f3a85406a9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1508791566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.1508791566 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.177917577 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 6537899096 ps |
| CPU time | 963.44 seconds |
| Started | Jun 30 07:57:40 PM PDT 24 |
| Finished | Jun 30 08:13:44 PM PDT 24 |
| Peak memory | 615052 kb |
| Host | smart-31dc4f0b-6546-46a4-8f4c-96ca9ee74545 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177917577 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.177917577 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2638013761 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 6372828332 ps |
| CPU time | 671.96 seconds |
| Started | Jun 30 07:57:09 PM PDT 24 |
| Finished | Jun 30 08:08:22 PM PDT 24 |
| Peak memory | 619172 kb |
| Host | smart-b311dbae-4060-4d74-a3bd-90d98bc280ff |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2638013761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.2638013761 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1521109792 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 4562164784 ps |
| CPU time | 670.19 seconds |
| Started | Jun 30 07:57:01 PM PDT 24 |
| Finished | Jun 30 08:08:11 PM PDT 24 |
| Peak memory | 611896 kb |
| Host | smart-8827a9de-9e56-4f26-96d0-865af26ff760 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521109792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1521109792 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3811046320 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 3988093572 ps |
| CPU time | 565.11 seconds |
| Started | Jun 30 07:56:44 PM PDT 24 |
| Finished | Jun 30 08:06:09 PM PDT 24 |
| Peak memory | 610892 kb |
| Host | smart-b21f7771-4be1-41d0-9806-343c422183b2 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811046320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3811046320 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.570655545 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 3901693562 ps |
| CPU time | 839.95 seconds |
| Started | Jun 30 07:56:17 PM PDT 24 |
| Finished | Jun 30 08:10:18 PM PDT 24 |
| Peak memory | 610832 kb |
| Host | smart-4740508f-2814-40c6-af98-aa7cda658dde |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570655545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.570655545 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1811115149 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 4093337318 ps |
| CPU time | 676.4 seconds |
| Started | Jun 30 07:58:07 PM PDT 24 |
| Finished | Jun 30 08:09:24 PM PDT 24 |
| Peak memory | 610884 kb |
| Host | smart-30724700-83f7-463a-ba37-c51b9cb757b6 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811115149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1811115149 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1715577926 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 4918987440 ps |
| CPU time | 710.14 seconds |
| Started | Jun 30 07:58:06 PM PDT 24 |
| Finished | Jun 30 08:09:57 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-bff160bf-b2b3-4cad-98d6-2df4d93a0b35 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715577926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1715577926 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3169877271 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 4899860308 ps |
| CPU time | 684.79 seconds |
| Started | Jun 30 07:56:13 PM PDT 24 |
| Finished | Jun 30 08:07:38 PM PDT 24 |
| Peak memory | 611936 kb |
| Host | smart-c2b6440e-3224-49b1-9352-10b619e9cdae |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169877271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3169877271 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.428366186 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 2643205582 ps |
| CPU time | 271.03 seconds |
| Started | Jun 30 07:58:05 PM PDT 24 |
| Finished | Jun 30 08:02:37 PM PDT 24 |
| Peak memory | 607308 kb |
| Host | smart-0272291f-f1c8-47b4-969b-8631ed520737 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428366186 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_clkmgr_jitter.428366186 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1098655295 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 3440105632 ps |
| CPU time | 431.31 seconds |
| Started | Jun 30 07:58:09 PM PDT 24 |
| Finished | Jun 30 08:05:20 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-007cf3a6-2e48-4bb0-89d9-196607a478a2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098655295 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.1098655295 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3465906215 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 2069113609 ps |
| CPU time | 203.3 seconds |
| Started | Jun 30 07:59:03 PM PDT 24 |
| Finished | Jun 30 08:02:26 PM PDT 24 |
| Peak memory | 609100 kb |
| Host | smart-0dc8132e-1d41-4150-a0b2-1e4caee16733 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465906215 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.3465906215 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2879640346 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 4529479176 ps |
| CPU time | 407.66 seconds |
| Started | Jun 30 07:56:13 PM PDT 24 |
| Finished | Jun 30 08:03:01 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-d2ed958b-ff57-47a0-a388-5919060eb48e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879640346 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.2879640346 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3213579532 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 5045431650 ps |
| CPU time | 730.13 seconds |
| Started | Jun 30 07:57:16 PM PDT 24 |
| Finished | Jun 30 08:09:26 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-bed17f62-a5d7-4859-aa9f-9f18df3552ee |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213579532 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.3213579532 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3039880581 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 5075931280 ps |
| CPU time | 513.15 seconds |
| Started | Jun 30 07:57:33 PM PDT 24 |
| Finished | Jun 30 08:06:06 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-dcaaf486-6929-45cd-a927-90777620d3b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039880581 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.3039880581 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1423468724 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 3800560696 ps |
| CPU time | 379.16 seconds |
| Started | Jun 30 07:56:29 PM PDT 24 |
| Finished | Jun 30 08:02:49 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-14f770c2-b799-4e0c-9295-29316d0a7e34 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423468724 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.1423468724 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.754975568 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 11750938268 ps |
| CPU time | 1192.48 seconds |
| Started | Jun 30 07:56:20 PM PDT 24 |
| Finished | Jun 30 08:16:13 PM PDT 24 |
| Peak memory | 608336 kb |
| Host | smart-4cb68dc5-00a9-47b5-a6c8-ff079638fa7c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754975568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.754975568 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2664837526 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 3345900296 ps |
| CPU time | 474.57 seconds |
| Started | Jun 30 07:56:33 PM PDT 24 |
| Finished | Jun 30 08:04:28 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-afe6aef2-2e0b-4379-a863-f9d7e292abb1 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664837526 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.2664837526 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1266452083 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 4795376584 ps |
| CPU time | 731.84 seconds |
| Started | Jun 30 07:56:56 PM PDT 24 |
| Finished | Jun 30 08:09:09 PM PDT 24 |
| Peak memory | 607792 kb |
| Host | smart-6e2839cd-4353-4b2e-9b06-524566c98f6f |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266452083 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.1266452083 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3652738440 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 3344914780 ps |
| CPU time | 193.52 seconds |
| Started | Jun 30 08:00:08 PM PDT 24 |
| Finished | Jun 30 08:03:22 PM PDT 24 |
| Peak memory | 607104 kb |
| Host | smart-966889c2-3fbf-4e75-915f-15e7ae647977 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652738440 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.3652738440 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.793925302 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 23711279902 ps |
| CPU time | 6664.87 seconds |
| Started | Jun 30 07:55:05 PM PDT 24 |
| Finished | Jun 30 09:46:11 PM PDT 24 |
| Peak memory | 608432 kb |
| Host | smart-d968ebd2-c4d3-4621-8622-40ad829482e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793925302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.793925302 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1869751255 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 24743472310 ps |
| CPU time | 3689.98 seconds |
| Started | Jun 30 07:58:49 PM PDT 24 |
| Finished | Jun 30 09:00:21 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-7d658f0c-a4fc-4680-aa88-4336955385de |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1869751255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.1869751255 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3245815946 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 4594097046 ps |
| CPU time | 385.9 seconds |
| Started | Jun 30 07:55:23 PM PDT 24 |
| Finished | Jun 30 08:01:49 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-865bad3e-c9a7-47e0-acf5-fe81268e9cba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32458 15946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.3245815946 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.4191214981 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 2826618704 ps |
| CPU time | 271.56 seconds |
| Started | Jun 30 07:54:35 PM PDT 24 |
| Finished | Jun 30 07:59:07 PM PDT 24 |
| Peak memory | 609088 kb |
| Host | smart-b3a530fb-8ab6-43ba-9141-19853217cfb0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191214981 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.4191214981 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1723262565 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 6453265000 ps |
| CPU time | 748.73 seconds |
| Started | Jun 30 07:56:38 PM PDT 24 |
| Finished | Jun 30 08:09:07 PM PDT 24 |
| Peak memory | 608904 kb |
| Host | smart-973daf7d-c191-48b3-a5db-22dd858aeae5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723262565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.1723262565 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.2198427878 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 3278746300 ps |
| CPU time | 292.84 seconds |
| Started | Jun 30 08:00:07 PM PDT 24 |
| Finished | Jun 30 08:05:01 PM PDT 24 |
| Peak memory | 607108 kb |
| Host | smart-e5284b6a-7273-4d14-b3d9-c0e714e95ba4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198427878 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.2198427878 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3766563972 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 6363689340 ps |
| CPU time | 915.15 seconds |
| Started | Jun 30 07:49:07 PM PDT 24 |
| Finished | Jun 30 08:04:23 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-6f0ded27-d0d7-4480-b024-1abdcf92f2f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3766563972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.3766563972 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.1674457804 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 3251388984 ps |
| CPU time | 717.44 seconds |
| Started | Jun 30 07:54:36 PM PDT 24 |
| Finished | Jun 30 08:06:34 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-490a08c4-49ea-40ff-9815-049e93f950fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674457804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.1674457804 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.3470422745 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 3491314338 ps |
| CPU time | 596.23 seconds |
| Started | Jun 30 07:54:49 PM PDT 24 |
| Finished | Jun 30 08:04:46 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-b51a30ca-8dfd-479c-87da-75c396c6d101 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470422745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.3470422745 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.909080489 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 5904526770 ps |
| CPU time | 1090.05 seconds |
| Started | Jun 30 07:55:16 PM PDT 24 |
| Finished | Jun 30 08:13:27 PM PDT 24 |
| Peak memory | 609436 kb |
| Host | smart-c500abd1-e798-45e7-94c4-45f8f997002b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=909080489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.909080489 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.3066408048 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 3141043000 ps |
| CPU time | 669.65 seconds |
| Started | Jun 30 07:54:00 PM PDT 24 |
| Finished | Jun 30 08:05:10 PM PDT 24 |
| Peak memory | 614276 kb |
| Host | smart-4bb5ee7a-5ad8-4e59-a93c-fd215cc03b09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066408048 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.3066408048 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.1986586215 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 6454771860 ps |
| CPU time | 1586.58 seconds |
| Started | Jun 30 07:55:07 PM PDT 24 |
| Finished | Jun 30 08:21:34 PM PDT 24 |
| Peak memory | 607824 kb |
| Host | smart-65b7e306-44a8-4940-b230-0ce0d24e57ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986586215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.1986586215 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.540843126 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 2884795090 ps |
| CPU time | 227.41 seconds |
| Started | Jun 30 07:55:28 PM PDT 24 |
| Finished | Jun 30 07:59:16 PM PDT 24 |
| Peak memory | 607552 kb |
| Host | smart-923f4bd5-d3c1-48f1-ac08-28b866642434 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54 0843126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.540843126 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2705647716 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 6911374328 ps |
| CPU time | 1428.63 seconds |
| Started | Jun 30 07:55:10 PM PDT 24 |
| Finished | Jun 30 08:19:00 PM PDT 24 |
| Peak memory | 608040 kb |
| Host | smart-38d3bd4d-8304-45eb-90ec-fb650e37f6b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2705647716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.2705647716 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1910103762 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 3350256280 ps |
| CPU time | 247.97 seconds |
| Started | Jun 30 07:54:48 PM PDT 24 |
| Finished | Jun 30 07:58:57 PM PDT 24 |
| Peak memory | 607720 kb |
| Host | smart-c01c260f-910b-4df6-9ca8-774015969bde |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910103762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.1910103762 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.4174216255 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 3382862890 ps |
| CPU time | 402.64 seconds |
| Started | Jun 30 07:59:06 PM PDT 24 |
| Finished | Jun 30 08:05:49 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-16d77ac2-74b1-49cb-a111-1619406bf302 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4174216255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.4174216255 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.409546998 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 2724893400 ps |
| CPU time | 267.19 seconds |
| Started | Jun 30 07:49:45 PM PDT 24 |
| Finished | Jun 30 07:54:12 PM PDT 24 |
| Peak memory | 607316 kb |
| Host | smart-8cb53c9f-a082-4d0b-9ad7-e744e5003d7a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409546998 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_concurrency.409546998 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.3817883020 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 3078521320 ps |
| CPU time | 221.06 seconds |
| Started | Jun 30 07:49:39 PM PDT 24 |
| Finished | Jun 30 07:53:21 PM PDT 24 |
| Peak memory | 609092 kb |
| Host | smart-dc0f7128-e49f-4256-884b-ee7adb7780b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817883020 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.3817883020 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.2564080179 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 2119430836 ps |
| CPU time | 235.7 seconds |
| Started | Jun 30 07:51:30 PM PDT 24 |
| Finished | Jun 30 07:55:26 PM PDT 24 |
| Peak memory | 607016 kb |
| Host | smart-c04abe24-e912-4dd4-9e2a-38acc3cdfba0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564080179 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.2564080179 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.4078847058 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 2612947340 ps |
| CPU time | 156.67 seconds |
| Started | Jun 30 07:51:03 PM PDT 24 |
| Finished | Jun 30 07:53:41 PM PDT 24 |
| Peak memory | 606832 kb |
| Host | smart-6916a1af-628e-4d3e-aa3f-5124ae483abf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078847058 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.4078847058 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3764817316 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 58242955192 ps |
| CPU time | 10641.7 seconds |
| Started | Jun 30 07:50:15 PM PDT 24 |
| Finished | Jun 30 10:47:38 PM PDT 24 |
| Peak memory | 623432 kb |
| Host | smart-4fff7609-5260-4414-8396-82ecd69e09d4 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3764817316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.3764817316 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.2296298102 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 4402009124 ps |
| CPU time | 705.91 seconds |
| Started | Jun 30 07:58:21 PM PDT 24 |
| Finished | Jun 30 08:10:08 PM PDT 24 |
| Peak memory | 609352 kb |
| Host | smart-4577d013-bb03-4a74-8026-56a6feaedf94 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2296298102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.2296298102 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1454287606 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 5419998248 ps |
| CPU time | 1029.52 seconds |
| Started | Jun 30 07:50:13 PM PDT 24 |
| Finished | Jun 30 08:07:23 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-ec0f8e71-45f1-46d7-87f7-d7308c124b40 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454287606 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.1454287606 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1219534674 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 6230375058 ps |
| CPU time | 1086.56 seconds |
| Started | Jun 30 07:51:37 PM PDT 24 |
| Finished | Jun 30 08:09:44 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-2a759158-3609-4c28-974e-36a86e4b4f8f |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219534674 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.1219534674 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1321400621 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 7550533975 ps |
| CPU time | 1451.11 seconds |
| Started | Jun 30 07:59:49 PM PDT 24 |
| Finished | Jun 30 08:24:00 PM PDT 24 |
| Peak memory | 607584 kb |
| Host | smart-7f76cb48-a246-4c37-b69f-6801c68f0be8 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321400621 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1321400621 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.232073701 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 5592004875 ps |
| CPU time | 1181.21 seconds |
| Started | Jun 30 07:50:56 PM PDT 24 |
| Finished | Jun 30 08:10:38 PM PDT 24 |
| Peak memory | 607080 kb |
| Host | smart-4abac542-22dc-483a-be22-b76e254eb6a4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232073701 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.232073701 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1184718884 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 3489522486 ps |
| CPU time | 425.86 seconds |
| Started | Jun 30 07:52:58 PM PDT 24 |
| Finished | Jun 30 08:00:04 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-160820fe-aa9c-4d62-ad03-b8b3d6c4a54f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184718884 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.1184718884 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1096410911 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 5752492530 ps |
| CPU time | 596.88 seconds |
| Started | Jun 30 07:51:23 PM PDT 24 |
| Finished | Jun 30 08:01:20 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-f7cb9baf-b50a-4663-828b-8bbdc776088d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10 96410911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.1096410911 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2981065096 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 6267994840 ps |
| CPU time | 1673.92 seconds |
| Started | Jun 30 07:59:27 PM PDT 24 |
| Finished | Jun 30 08:27:22 PM PDT 24 |
| Peak memory | 609060 kb |
| Host | smart-803ede5e-ca75-46b1-8e07-6c9d6af9f995 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981065096 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.2981065096 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2236441802 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 3798610566 ps |
| CPU time | 673.34 seconds |
| Started | Jun 30 07:51:42 PM PDT 24 |
| Finished | Jun 30 08:02:56 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-c490ee74-c82d-40c7-b1c4-ad71a7acfba7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236441802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.2236441802 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2078040820 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 4728660574 ps |
| CPU time | 702.69 seconds |
| Started | Jun 30 07:50:18 PM PDT 24 |
| Finished | Jun 30 08:02:02 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-051e887b-f1cc-4c33-8d1e-a305d3e338f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2078040820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.2078040820 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1029123248 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2473041200 ps |
| CPU time | 331.41 seconds |
| Started | Jun 30 07:58:42 PM PDT 24 |
| Finished | Jun 30 08:04:14 PM PDT 24 |
| Peak memory | 607088 kb |
| Host | smart-bf3cc2b8-5ac9-4764-8700-16ccdef3ef6d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029123 248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.1029123248 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.3106558342 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 21818943396 ps |
| CPU time | 2100.97 seconds |
| Started | Jun 30 07:49:38 PM PDT 24 |
| Finished | Jun 30 08:24:40 PM PDT 24 |
| Peak memory | 611360 kb |
| Host | smart-507c6c97-3e54-4bef-893c-e46aa2c1fa60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106558342 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.3106558342 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2534437445 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 20080963853 ps |
| CPU time | 2356.75 seconds |
| Started | Jun 30 07:57:36 PM PDT 24 |
| Finished | Jun 30 08:36:55 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-a10636b4-a101-4915-b59b-b136c8003a31 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2534437445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.2534437445 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2236940910 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 2853473516 ps |
| CPU time | 249.23 seconds |
| Started | Jun 30 08:03:33 PM PDT 24 |
| Finished | Jun 30 08:07:42 PM PDT 24 |
| Peak memory | 607584 kb |
| Host | smart-249ad3aa-1bb2-4a23-809b-751bdfbc67a4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2236940910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.2236940910 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.2464306324 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3327489831 ps |
| CPU time | 392.08 seconds |
| Started | Jun 30 07:58:47 PM PDT 24 |
| Finished | Jun 30 08:05:20 PM PDT 24 |
| Peak memory | 607600 kb |
| Host | smart-dd9f3119-444b-41ab-89d5-402e39c9d227 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464306324 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.2464306324 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.2447039057 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 3141501452 ps |
| CPU time | 345.02 seconds |
| Started | Jun 30 07:55:11 PM PDT 24 |
| Finished | Jun 30 08:00:56 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-1e081383-8ef4-46a8-a86a-c76c4313b40d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447039057 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.2447039057 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.4004103662 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 2825688868 ps |
| CPU time | 324.43 seconds |
| Started | Jun 30 07:54:46 PM PDT 24 |
| Finished | Jun 30 08:00:12 PM PDT 24 |
| Peak memory | 607332 kb |
| Host | smart-961167a3-8917-466d-aae8-f34d2ce3a20a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004103662 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.4004103662 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.4145611847 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 2892063284 ps |
| CPU time | 209.81 seconds |
| Started | Jun 30 07:55:35 PM PDT 24 |
| Finished | Jun 30 07:59:05 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-4c43b5db-646b-45db-860e-49cc83a67ef8 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145611847 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.4145611847 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.4213961050 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 4013539219 ps |
| CPU time | 329.72 seconds |
| Started | Jun 30 07:59:07 PM PDT 24 |
| Finished | Jun 30 08:04:37 PM PDT 24 |
| Peak memory | 607280 kb |
| Host | smart-b201f523-ca1c-47fd-8cdd-393815c8ffee |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213961050 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.4213961050 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.2364172349 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 7222110570 ps |
| CPU time | 1652.74 seconds |
| Started | Jun 30 07:56:45 PM PDT 24 |
| Finished | Jun 30 08:24:18 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-3a3e1a0a-b95f-4c70-a02d-e5fee4bbd6bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364172349 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.2364172349 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.1331080520 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 3049696138 ps |
| CPU time | 427.2 seconds |
| Started | Jun 30 07:57:04 PM PDT 24 |
| Finished | Jun 30 08:04:11 PM PDT 24 |
| Peak memory | 606236 kb |
| Host | smart-ef6afae4-4324-43ef-9f5f-61a0c8e8d177 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331080520 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.1331080520 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.2403543712 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 3194197328 ps |
| CPU time | 292.68 seconds |
| Started | Jun 30 08:00:29 PM PDT 24 |
| Finished | Jun 30 08:05:22 PM PDT 24 |
| Peak memory | 607336 kb |
| Host | smart-5abce710-ee8b-4031-b07b-c15bca9aee92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403543712 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.2403543712 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.335485557 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 3489162344 ps |
| CPU time | 424.44 seconds |
| Started | Jun 30 07:50:43 PM PDT 24 |
| Finished | Jun 30 07:57:49 PM PDT 24 |
| Peak memory | 607476 kb |
| Host | smart-a9df1050-7df9-48eb-9728-363e6d402db9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335485557 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.335485557 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3411575344 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 5070924350 ps |
| CPU time | 734.59 seconds |
| Started | Jun 30 07:52:12 PM PDT 24 |
| Finished | Jun 30 08:04:27 PM PDT 24 |
| Peak memory | 607224 kb |
| Host | smart-0291c905-18ee-486f-b9f2-c9d4495e13fd |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411575344 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.3411575344 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3109667662 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 4399833970 ps |
| CPU time | 656.69 seconds |
| Started | Jun 30 07:50:14 PM PDT 24 |
| Finished | Jun 30 08:01:12 PM PDT 24 |
| Peak memory | 608300 kb |
| Host | smart-b9506969-bdab-4e60-ad2e-e53cb59831a1 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109667662 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.3109667662 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4071774642 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 5543530380 ps |
| CPU time | 1203.82 seconds |
| Started | Jun 30 07:51:23 PM PDT 24 |
| Finished | Jun 30 08:11:28 PM PDT 24 |
| Peak memory | 608268 kb |
| Host | smart-37a0d0a7-74d7-4cb0-87a1-54ee12fedf88 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071774642 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.4071774642 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.3896238391 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 65828919897 ps |
| CPU time | 11563.7 seconds |
| Started | Jun 30 07:50:58 PM PDT 24 |
| Finished | Jun 30 11:03:44 PM PDT 24 |
| Peak memory | 624148 kb |
| Host | smart-5b0e2109-bc51-4d7d-a5c2-32d7efdac10f |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3896238391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.3896238391 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2683237716 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 8240874466 ps |
| CPU time | 2104.8 seconds |
| Started | Jun 30 07:56:56 PM PDT 24 |
| Finished | Jun 30 08:32:01 PM PDT 24 |
| Peak memory | 615724 kb |
| Host | smart-38aba323-b3a4-4bc6-8f2e-ac28ab88092e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683 237716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.2683237716 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.762382329 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 8803616383 ps |
| CPU time | 1740.59 seconds |
| Started | Jun 30 07:55:37 PM PDT 24 |
| Finished | Jun 30 08:24:38 PM PDT 24 |
| Peak memory | 615620 kb |
| Host | smart-b9952b99-9297-42d4-8166-be55f03a41a1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=762382329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.762382329 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3302374806 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 11687448929 ps |
| CPU time | 2068.65 seconds |
| Started | Jun 30 07:59:37 PM PDT 24 |
| Finished | Jun 30 08:34:06 PM PDT 24 |
| Peak memory | 615408 kb |
| Host | smart-8036f721-6b42-4930-abae-492e40b9e1cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3302374806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3302374806 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3962779296 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 10415179098 ps |
| CPU time | 2230.79 seconds |
| Started | Jun 30 07:55:49 PM PDT 24 |
| Finished | Jun 30 08:33:00 PM PDT 24 |
| Peak memory | 615656 kb |
| Host | smart-ed3c7a34-1935-4956-9c04-22fafc74d8b8 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3962779296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.3962779296 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4187929421 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 11134084942 ps |
| CPU time | 2389.87 seconds |
| Started | Jun 30 07:55:49 PM PDT 24 |
| Finished | Jun 30 08:35:41 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-04dcea24-683b-4abd-817e-2c47990d9f87 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418792 9421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.4187929421 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3745576983 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 18703434104 ps |
| CPU time | 4219.51 seconds |
| Started | Jun 30 07:56:03 PM PDT 24 |
| Finished | Jun 30 09:06:23 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-d7fb68e2-0bc0-47bf-82e0-16663e216610 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37455 76983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.3745576983 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.2693923577 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 3250184968 ps |
| CPU time | 277.48 seconds |
| Started | Jun 30 07:56:44 PM PDT 24 |
| Finished | Jun 30 08:01:22 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-5a31b418-f3e3-4ee2-9f24-4d6bfa359d21 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693923577 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.2693923577 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.3972156353 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 2684014266 ps |
| CPU time | 248.15 seconds |
| Started | Jun 30 07:52:10 PM PDT 24 |
| Finished | Jun 30 07:56:18 PM PDT 24 |
| Peak memory | 607104 kb |
| Host | smart-3251663d-7dc3-4b4d-9e1b-d097d54cd445 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972156353 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.3972156353 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.2480668938 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 2310803540 ps |
| CPU time | 234.7 seconds |
| Started | Jun 30 07:56:06 PM PDT 24 |
| Finished | Jun 30 08:00:01 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-18349003-87c8-442d-8cb8-76ce96dddaf4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480668938 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.2480668938 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.4263558247 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 2942376000 ps |
| CPU time | 242.99 seconds |
| Started | Jun 30 07:55:37 PM PDT 24 |
| Finished | Jun 30 07:59:40 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-4fa6521c-4231-4ac5-887b-99bb0c4bbe64 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263558247 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.4263558247 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3892930277 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 2856792048 ps |
| CPU time | 311.06 seconds |
| Started | Jun 30 07:57:18 PM PDT 24 |
| Finished | Jun 30 08:02:30 PM PDT 24 |
| Peak memory | 609088 kb |
| Host | smart-f4f05927-9f14-45ca-ab62-7d4675a091f4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892930277 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.3892930277 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3729026307 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 3537195911 ps |
| CPU time | 288.91 seconds |
| Started | Jun 30 07:55:28 PM PDT 24 |
| Finished | Jun 30 08:00:17 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-145f641e-1e26-486a-82d9-c92a331016b7 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729026307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.3729026307 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3616250993 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 2888190250 ps |
| CPU time | 293.5 seconds |
| Started | Jun 30 07:59:06 PM PDT 24 |
| Finished | Jun 30 08:04:00 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-51d48f53-6945-4774-8ca9-f1ff26b0fac3 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36162509 93 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3616250993 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.3509023988 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 3314672660 ps |
| CPU time | 308.24 seconds |
| Started | Jun 30 07:59:05 PM PDT 24 |
| Finished | Jun 30 08:04:13 PM PDT 24 |
| Peak memory | 607108 kb |
| Host | smart-78c0d74a-217b-4f14-b426-6f3dab389ec9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509023988 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.3509023988 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3336369447 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 3180262200 ps |
| CPU time | 322.57 seconds |
| Started | Jun 30 07:53:49 PM PDT 24 |
| Finished | Jun 30 07:59:12 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-cdc78cbc-41a7-4298-888b-1ac015b65a69 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336369447 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.3336369447 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.3609182613 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 5549918432 ps |
| CPU time | 588.68 seconds |
| Started | Jun 30 07:57:47 PM PDT 24 |
| Finished | Jun 30 08:07:36 PM PDT 24 |
| Peak memory | 608660 kb |
| Host | smart-e629591d-0bd0-43e2-937b-88b3b18c9356 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3609182613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.3609182613 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1106416166 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 9697454004 ps |
| CPU time | 1110.95 seconds |
| Started | Jun 30 07:52:10 PM PDT 24 |
| Finished | Jun 30 08:10:42 PM PDT 24 |
| Peak memory | 620996 kb |
| Host | smart-5220deea-8b0e-4684-9fb1-26aed70f1d95 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106416166 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.1106416166 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.16765716 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 2345678513 ps |
| CPU time | 106.91 seconds |
| Started | Jun 30 07:51:51 PM PDT 24 |
| Finished | Jun 30 07:53:38 PM PDT 24 |
| Peak memory | 614356 kb |
| Host | smart-59aec266-0fa1-4f66-8c82-05d75ddd1e89 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=16765716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.16765716 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3649402406 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2099950097 ps |
| CPU time | 123.63 seconds |
| Started | Jun 30 07:53:14 PM PDT 24 |
| Finished | Jun 30 07:55:18 PM PDT 24 |
| Peak memory | 614276 kb |
| Host | smart-4f5d2c52-c947-44cc-bf3b-9290dcd06fb2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649402406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3649402406 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2572693524 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 49695455962 ps |
| CPU time | 5781.2 seconds |
| Started | Jun 30 07:52:30 PM PDT 24 |
| Finished | Jun 30 09:28:52 PM PDT 24 |
| Peak memory | 613984 kb |
| Host | smart-44ff5534-cdcc-4f4e-b8ac-9c4ecdf82eb4 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572693524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.2572693524 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1025827392 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 10571579433 ps |
| CPU time | 1239.81 seconds |
| Started | Jun 30 07:51:34 PM PDT 24 |
| Finished | Jun 30 08:12:15 PM PDT 24 |
| Peak memory | 616680 kb |
| Host | smart-649c74c0-58fd-4846-92b5-7263a171635b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025827392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.1025827392 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1320200865 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 47215071650 ps |
| CPU time | 5458.04 seconds |
| Started | Jun 30 07:53:10 PM PDT 24 |
| Finished | Jun 30 09:24:09 PM PDT 24 |
| Peak memory | 617028 kb |
| Host | smart-6c50dae6-e9aa-45d1-a3de-ef17683e9908 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320200865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.1320200865 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1208845619 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 32233276074 ps |
| CPU time | 2637.06 seconds |
| Started | Jun 30 07:52:29 PM PDT 24 |
| Finished | Jun 30 08:36:27 PM PDT 24 |
| Peak memory | 613880 kb |
| Host | smart-cccaaf52-33eb-453e-8533-c63bf960aa45 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1208845619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.1208845619 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3475476276 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 17634618080 ps |
| CPU time | 3492.34 seconds |
| Started | Jun 30 07:57:30 PM PDT 24 |
| Finished | Jun 30 08:55:43 PM PDT 24 |
| Peak memory | 607228 kb |
| Host | smart-bcda8fc0-1001-45c8-b779-8f70a79e91da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3475476276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.3475476276 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1436646961 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 18476972484 ps |
| CPU time | 3491.47 seconds |
| Started | Jun 30 07:57:22 PM PDT 24 |
| Finished | Jun 30 08:55:34 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-ce75d243-dcb4-48a7-86ee-1f98e0e4a424 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1436646961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1436646961 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3091550463 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 24521884016 ps |
| CPU time | 3908.28 seconds |
| Started | Jun 30 07:58:24 PM PDT 24 |
| Finished | Jun 30 09:03:33 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-8e86c6ae-9054-4e7d-aae4-93b188f73d13 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091550463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3091550463 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2217067062 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 3592462662 ps |
| CPU time | 584.02 seconds |
| Started | Jun 30 07:53:09 PM PDT 24 |
| Finished | Jun 30 08:02:54 PM PDT 24 |
| Peak memory | 607108 kb |
| Host | smart-4a744ca8-dc15-49ea-bd2b-0e7ef3e233c0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217067062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.2217067062 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.2234343636 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 5723959824 ps |
| CPU time | 969.78 seconds |
| Started | Jun 30 07:57:26 PM PDT 24 |
| Finished | Jun 30 08:13:36 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-1d445ea6-e631-43b4-a864-37b1197f89ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2234343636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.2234343636 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.969142850 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 6683255256 ps |
| CPU time | 1642.77 seconds |
| Started | Jun 30 07:59:44 PM PDT 24 |
| Finished | Jun 30 08:27:07 PM PDT 24 |
| Peak memory | 607264 kb |
| Host | smart-35090167-a7d8-4daf-82af-7334228d8361 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969142850 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_smoketest.969142850 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.660309484 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 2200904727 ps |
| CPU time | 279.25 seconds |
| Started | Jun 30 07:52:25 PM PDT 24 |
| Finished | Jun 30 07:57:04 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-692ed39f-e338-4707-9757-29cac314220e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660309484 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.660309484 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.653232664 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 8035234312 ps |
| CPU time | 1606.81 seconds |
| Started | Jun 30 07:52:00 PM PDT 24 |
| Finished | Jun 30 08:18:47 PM PDT 24 |
| Peak memory | 608172 kb |
| Host | smart-3048baf8-5b5a-42cc-8ffc-f087b0ab752a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=653232664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.653232664 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1358571108 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 8297185044 ps |
| CPU time | 1593.59 seconds |
| Started | Jun 30 07:52:06 PM PDT 24 |
| Finished | Jun 30 08:18:40 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-b89f5374-be01-4617-8f8b-875c14985e1c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1358571108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.1358571108 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3288305826 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 8098779848 ps |
| CPU time | 1238.34 seconds |
| Started | Jun 30 07:51:24 PM PDT 24 |
| Finished | Jun 30 08:12:03 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-bd03abc6-cbfc-4034-9a5c-7b100848f960 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3288305826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.3288305826 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3409979752 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 5082481420 ps |
| CPU time | 753.52 seconds |
| Started | Jun 30 07:51:57 PM PDT 24 |
| Finished | Jun 30 08:04:31 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-36ef92d1-bf24-4fb4-b0f5-72affe257a80 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3409979752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3409979752 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1442619842 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 3473516840 ps |
| CPU time | 315.16 seconds |
| Started | Jun 30 08:00:43 PM PDT 24 |
| Finished | Jun 30 08:05:59 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-a7bfa77e-62ac-4a87-8986-4965ea353652 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442619842 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.1442619842 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.3559726034 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2965527162 ps |
| CPU time | 320.91 seconds |
| Started | Jun 30 07:57:53 PM PDT 24 |
| Finished | Jun 30 08:03:15 PM PDT 24 |
| Peak memory | 606328 kb |
| Host | smart-091967bf-1447-487d-8279-310dcbb12360 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559726034 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.3559726034 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.1577992611 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 4028270100 ps |
| CPU time | 746.7 seconds |
| Started | Jun 30 07:58:51 PM PDT 24 |
| Finished | Jun 30 08:11:19 PM PDT 24 |
| Peak memory | 608140 kb |
| Host | smart-6a25c775-c1ab-4c2a-90be-9ac8590a968b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577992611 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.1577992611 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.705634314 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 10687630320 ps |
| CPU time | 832.48 seconds |
| Started | Jun 30 08:00:26 PM PDT 24 |
| Finished | Jun 30 08:14:19 PM PDT 24 |
| Peak memory | 608192 kb |
| Host | smart-eb428246-9925-4c1f-9769-05690aa02bd0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705634314 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.705634314 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1060020943 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 10318394348 ps |
| CPU time | 1576.5 seconds |
| Started | Jun 30 07:52:32 PM PDT 24 |
| Finished | Jun 30 08:18:49 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-e991e689-45d8-4fe5-8606-49efda04e208 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060 020943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.1060020943 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3139641270 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 24895905480 ps |
| CPU time | 2711.95 seconds |
| Started | Jun 30 07:57:58 PM PDT 24 |
| Finished | Jun 30 08:43:11 PM PDT 24 |
| Peak memory | 609212 kb |
| Host | smart-f71560ab-0031-4753-9edb-dce0115d7c86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313 9641270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.3139641270 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.976802058 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 18123603301 ps |
| CPU time | 1803.97 seconds |
| Started | Jun 30 07:53:40 PM PDT 24 |
| Finished | Jun 30 08:23:45 PM PDT 24 |
| Peak memory | 609372 kb |
| Host | smart-c81e73e4-cb57-47fe-8b90-393135cb66d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=976802058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.976802058 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3201366662 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 9404312276 ps |
| CPU time | 1031.44 seconds |
| Started | Jun 30 07:54:17 PM PDT 24 |
| Finished | Jun 30 08:11:29 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-9cb047a6-0d6d-4a96-84be-b9839b6810d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201366662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.3201366662 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2479890288 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 7325113608 ps |
| CPU time | 422.19 seconds |
| Started | Jun 30 07:53:34 PM PDT 24 |
| Finished | Jun 30 08:00:37 PM PDT 24 |
| Peak memory | 615080 kb |
| Host | smart-b0e4faa4-db32-438b-b872-d9a558c11caa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2479890288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2479890288 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.645491303 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 7482619785 ps |
| CPU time | 619.78 seconds |
| Started | Jun 30 07:52:24 PM PDT 24 |
| Finished | Jun 30 08:02:44 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-5f1db9f8-89db-4bfc-b5f0-6cdcb36b2cd7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645491303 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.645491303 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.747234782 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4270259400 ps |
| CPU time | 520.11 seconds |
| Started | Jun 30 07:58:44 PM PDT 24 |
| Finished | Jun 30 08:07:24 PM PDT 24 |
| Peak memory | 607356 kb |
| Host | smart-014d0afc-7ae1-4820-b4c1-93a757801739 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747234782 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.747234782 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3589951664 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 4073532630 ps |
| CPU time | 536.29 seconds |
| Started | Jun 30 07:55:02 PM PDT 24 |
| Finished | Jun 30 08:03:58 PM PDT 24 |
| Peak memory | 614792 kb |
| Host | smart-f0ee4035-8787-4600-8da3-508387a95a47 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3589951664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.3589951664 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.322511676 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 12269501951 ps |
| CPU time | 1077.29 seconds |
| Started | Jun 30 07:52:15 PM PDT 24 |
| Finished | Jun 30 08:10:12 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-e315b9a2-76be-4957-886f-a05dd9478440 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322511676 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.322511676 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1745951317 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 5730468804 ps |
| CPU time | 618 seconds |
| Started | Jun 30 07:52:42 PM PDT 24 |
| Finished | Jun 30 08:03:01 PM PDT 24 |
| Peak memory | 608316 kb |
| Host | smart-ed4a7bb6-50c5-4491-b49d-2decd2110d0a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745951317 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.1745951317 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.368500115 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 28089451156 ps |
| CPU time | 2699.96 seconds |
| Started | Jun 30 07:53:45 PM PDT 24 |
| Finished | Jun 30 08:38:46 PM PDT 24 |
| Peak memory | 609004 kb |
| Host | smart-49f4de0b-237d-48bc-9768-4c6af66001a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=368500115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.368500115 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1927733377 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 21868410782 ps |
| CPU time | 1641.55 seconds |
| Started | Jun 30 07:57:36 PM PDT 24 |
| Finished | Jun 30 08:24:59 PM PDT 24 |
| Peak memory | 607488 kb |
| Host | smart-1cafe341-c8ea-4381-b494-f0b9f8d9390a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1927733377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1927733377 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.151178718 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 27781925556 ps |
| CPU time | 2797.1 seconds |
| Started | Jun 30 07:52:30 PM PDT 24 |
| Finished | Jun 30 08:39:08 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-fb627b1a-2d1e-4591-bd36-171aa2b21bee |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151178718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.151178718 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1298514005 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 6373427336 ps |
| CPU time | 534.88 seconds |
| Started | Jun 30 07:58:14 PM PDT 24 |
| Finished | Jun 30 08:07:10 PM PDT 24 |
| Peak memory | 609320 kb |
| Host | smart-3f80328f-242c-4e3b-ba97-621231d3b8b8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1298514005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1298514005 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3162254493 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 3164892516 ps |
| CPU time | 214.56 seconds |
| Started | Jun 30 07:53:59 PM PDT 24 |
| Finished | Jun 30 07:57:34 PM PDT 24 |
| Peak memory | 607116 kb |
| Host | smart-4813f83e-9933-44c6-b720-fc13a1b563c4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162254493 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.3162254493 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1335422564 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 4308192920 ps |
| CPU time | 606.61 seconds |
| Started | Jun 30 07:52:33 PM PDT 24 |
| Finished | Jun 30 08:02:40 PM PDT 24 |
| Peak memory | 615544 kb |
| Host | smart-1a024b7a-b884-4373-814f-ced075079432 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1335422564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.1335422564 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2782521957 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 5822770192 ps |
| CPU time | 491.33 seconds |
| Started | Jun 30 07:57:53 PM PDT 24 |
| Finished | Jun 30 08:06:05 PM PDT 24 |
| Peak memory | 607140 kb |
| Host | smart-e0bd7b9c-3814-4037-bedc-0889a182c7e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27825219 57 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2782521957 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.4085695987 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 6377935474 ps |
| CPU time | 410.42 seconds |
| Started | Jun 30 07:57:41 PM PDT 24 |
| Finished | Jun 30 08:04:33 PM PDT 24 |
| Peak memory | 608424 kb |
| Host | smart-13f09405-3671-4836-a504-a923a798e48f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4085695987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.4085695987 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1145712860 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 5017952326 ps |
| CPU time | 502.45 seconds |
| Started | Jun 30 08:02:12 PM PDT 24 |
| Finished | Jun 30 08:10:35 PM PDT 24 |
| Peak memory | 609428 kb |
| Host | smart-490f9305-943a-4275-8dbe-dbb965f3eab8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145712860 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.1145712860 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2956540210 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 5986552562 ps |
| CPU time | 962.35 seconds |
| Started | Jun 30 07:53:32 PM PDT 24 |
| Finished | Jun 30 08:09:35 PM PDT 24 |
| Peak memory | 607396 kb |
| Host | smart-7d9fb78f-8f9a-42bf-b886-df6a40149a06 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956540210 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.2956540210 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2303373049 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 5127622742 ps |
| CPU time | 595.25 seconds |
| Started | Jun 30 07:52:54 PM PDT 24 |
| Finished | Jun 30 08:02:50 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-908466ed-6592-4523-975b-d68c751d5100 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303373049 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2303373049 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1288249386 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 5709922380 ps |
| CPU time | 561.01 seconds |
| Started | Jun 30 07:59:25 PM PDT 24 |
| Finished | Jun 30 08:08:46 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-54442f60-de63-497c-bc4e-ef8ec95d74b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288249386 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.1288249386 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3395895283 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 4325752220 ps |
| CPU time | 587.22 seconds |
| Started | Jun 30 07:57:07 PM PDT 24 |
| Finished | Jun 30 08:06:56 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-eacacf93-0384-4a75-ae9e-846711ddc272 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339 5895283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.3395895283 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3217396099 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 9305629159 ps |
| CPU time | 695.78 seconds |
| Started | Jun 30 07:56:11 PM PDT 24 |
| Finished | Jun 30 08:07:48 PM PDT 24 |
| Peak memory | 609236 kb |
| Host | smart-9398ab8a-b69a-4ac2-bd99-f71602b3341f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217396099 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.3217396099 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1034922345 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 16612941364 ps |
| CPU time | 2153.46 seconds |
| Started | Jun 30 07:52:31 PM PDT 24 |
| Finished | Jun 30 08:28:25 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-b43af593-f785-449d-9ecc-033ab02f3cd4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1034922345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.1034922345 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.778691314 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 5089689666 ps |
| CPU time | 535.83 seconds |
| Started | Jun 30 07:52:48 PM PDT 24 |
| Finished | Jun 30 08:01:45 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-65739850-912f-43b6-9d53-39eb9f9b15a4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778691314 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_rstmgr_cpu_info.778691314 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3420762568 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 5114913412 ps |
| CPU time | 682.23 seconds |
| Started | Jun 30 07:49:24 PM PDT 24 |
| Finished | Jun 30 08:00:47 PM PDT 24 |
| Peak memory | 639532 kb |
| Host | smart-50c0764c-14c2-420c-a314-e4574ceb254c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3420762568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.3420762568 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3472744243 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 2696685800 ps |
| CPU time | 204.54 seconds |
| Started | Jun 30 08:00:32 PM PDT 24 |
| Finished | Jun 30 08:03:56 PM PDT 24 |
| Peak memory | 607008 kb |
| Host | smart-0c062ae8-aa70-40ae-b2aa-d82f14f688b0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472744243 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.3472744243 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1677978798 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 4725498528 ps |
| CPU time | 426.7 seconds |
| Started | Jun 30 07:52:37 PM PDT 24 |
| Finished | Jun 30 07:59:44 PM PDT 24 |
| Peak memory | 607200 kb |
| Host | smart-0f71739a-a126-4299-9d3a-609936f51bfa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677978798 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.1677978798 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3396285822 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 2576250856 ps |
| CPU time | 220.8 seconds |
| Started | Jun 30 07:53:11 PM PDT 24 |
| Finished | Jun 30 07:56:52 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-5fe5ba8e-bd7e-4835-9aa4-65813d16115c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396285822 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.3396285822 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2112754308 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 3084547400 ps |
| CPU time | 255.81 seconds |
| Started | Jun 30 07:58:18 PM PDT 24 |
| Finished | Jun 30 08:02:35 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-27caa4d2-1963-4898-aced-d355c1a70491 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2112754308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.2112754308 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3621638779 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 3068275593 ps |
| CPU time | 234.3 seconds |
| Started | Jun 30 07:59:53 PM PDT 24 |
| Finished | Jun 30 08:03:49 PM PDT 24 |
| Peak memory | 607944 kb |
| Host | smart-746706b2-ae4d-4f3a-bdf4-db4299517b76 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621638779 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.3621638779 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.906148816 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2412248278 ps |
| CPU time | 181.74 seconds |
| Started | Jun 30 07:58:31 PM PDT 24 |
| Finished | Jun 30 08:01:33 PM PDT 24 |
| Peak memory | 613276 kb |
| Host | smart-98c8babf-b96d-4ab7-b4e3-5afd4cda7713 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906148816 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.906148816 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1694322094 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 4091640440 ps |
| CPU time | 807.49 seconds |
| Started | Jun 30 07:53:10 PM PDT 24 |
| Finished | Jun 30 08:06:38 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-190ac86c-5bc7-4204-b7be-4fadc922ec1a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16943 22094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.1694322094 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3532982524 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 5562350670 ps |
| CPU time | 983.94 seconds |
| Started | Jun 30 07:56:51 PM PDT 24 |
| Finished | Jun 30 08:13:16 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-ff80c80c-2616-4c7c-bb22-357918f48b2e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3532982524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.3532982524 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3408241363 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 5731194271 ps |
| CPU time | 810 seconds |
| Started | Jun 30 07:58:12 PM PDT 24 |
| Finished | Jun 30 08:11:42 PM PDT 24 |
| Peak memory | 617928 kb |
| Host | smart-42f16bc6-3fb9-4986-b5fd-c5a375708104 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408241363 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.3408241363 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1832124343 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 5305056410 ps |
| CPU time | 531.62 seconds |
| Started | Jun 30 07:58:10 PM PDT 24 |
| Finished | Jun 30 08:07:02 PM PDT 24 |
| Peak memory | 617908 kb |
| Host | smart-2df726b3-9868-41c3-8fe6-d603baf185a3 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183212 4343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1832124343 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2773380045 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 2678619236 ps |
| CPU time | 328.14 seconds |
| Started | Jun 30 08:01:29 PM PDT 24 |
| Finished | Jun 30 08:06:58 PM PDT 24 |
| Peak memory | 607260 kb |
| Host | smart-7823990f-6063-4965-a31e-7f2e0bfcb6f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773380045 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.2773380045 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.2917758509 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 3337528090 ps |
| CPU time | 327.15 seconds |
| Started | Jun 30 07:53:11 PM PDT 24 |
| Finished | Jun 30 07:58:40 PM PDT 24 |
| Peak memory | 606328 kb |
| Host | smart-aa8204c7-cd24-4ce0-9c0c-2cd38ba7c9d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917758509 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.2917758509 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2879225118 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 2972238000 ps |
| CPU time | 251 seconds |
| Started | Jun 30 08:00:17 PM PDT 24 |
| Finished | Jun 30 08:04:28 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-e83cab38-7e78-4007-a9f7-a595c623e9f4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879225118 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.2879225118 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2497505176 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 2858550551 ps |
| CPU time | 243.64 seconds |
| Started | Jun 30 07:56:48 PM PDT 24 |
| Finished | Jun 30 08:00:53 PM PDT 24 |
| Peak memory | 608368 kb |
| Host | smart-f5890910-745d-4fd8-a5cc-33c5e129cf7c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497505 176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.2497505176 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.4208508641 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 8249930438 ps |
| CPU time | 1516.15 seconds |
| Started | Jun 30 07:49:33 PM PDT 24 |
| Finished | Jun 30 08:14:50 PM PDT 24 |
| Peak memory | 608224 kb |
| Host | smart-73f8fa5b-5969-44b2-afc7-a4bed896d2e3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208508641 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.4208508641 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.312751298 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 7862934878 ps |
| CPU time | 655.83 seconds |
| Started | Jun 30 07:55:45 PM PDT 24 |
| Finished | Jun 30 08:06:41 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-b5935f79-3aec-4fcf-a88e-71f7e950e5fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312751298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sle ep_sram_ret_contents_no_scramble.312751298 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1559277708 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 7943867082 ps |
| CPU time | 844 seconds |
| Started | Jun 30 07:56:14 PM PDT 24 |
| Finished | Jun 30 08:10:18 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-6290ee79-f269-4260-8b12-9ae4c0df1c42 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559277708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.1559277708 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3350659773 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 6245894095 ps |
| CPU time | 658.79 seconds |
| Started | Jun 30 07:50:26 PM PDT 24 |
| Finished | Jun 30 08:01:25 PM PDT 24 |
| Peak memory | 624156 kb |
| Host | smart-937a6875-8ae9-464e-b9e9-b2e6b6a2c8b4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350659773 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.3350659773 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1937068078 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 4816386509 ps |
| CPU time | 801.08 seconds |
| Started | Jun 30 07:50:30 PM PDT 24 |
| Finished | Jun 30 08:03:51 PM PDT 24 |
| Peak memory | 624276 kb |
| Host | smart-56440df2-7175-4dde-822d-7d9dce8ce83c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937068078 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.1937068078 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.1441847535 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3050074918 ps |
| CPU time | 370.66 seconds |
| Started | Jun 30 07:51:06 PM PDT 24 |
| Finished | Jun 30 07:57:17 PM PDT 24 |
| Peak memory | 617592 kb |
| Host | smart-7f0e3cb4-1e93-4127-8bf5-b00ed6ff222e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441847535 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.1441847535 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3819279971 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2446283580 ps |
| CPU time | 315.68 seconds |
| Started | Jun 30 07:49:59 PM PDT 24 |
| Finished | Jun 30 07:55:16 PM PDT 24 |
| Peak memory | 607960 kb |
| Host | smart-aa7e1809-6e0e-44bb-971f-98027fb56f8a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819279971 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.3819279971 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1978667087 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 6903711027 ps |
| CPU time | 1050.28 seconds |
| Started | Jun 30 07:56:41 PM PDT 24 |
| Finished | Jun 30 08:14:12 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-23094b7b-9945-45bb-a213-61e653a7be11 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978667087 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.1978667087 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.871732293 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 3704538274 ps |
| CPU time | 432.83 seconds |
| Started | Jun 30 07:56:26 PM PDT 24 |
| Finished | Jun 30 08:03:39 PM PDT 24 |
| Peak memory | 608444 kb |
| Host | smart-cbaf13c3-1ab5-499d-a6f0-3ab649e2617f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871732293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ sram_ctrl_scrambled_access.871732293 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2964988277 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 3789288407 ps |
| CPU time | 588.66 seconds |
| Started | Jun 30 07:57:16 PM PDT 24 |
| Finished | Jun 30 08:07:06 PM PDT 24 |
| Peak memory | 608504 kb |
| Host | smart-f9b7d9cc-1eed-455c-bf8a-d9215159caff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964988277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2964988277 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.538594806 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 5382482460 ps |
| CPU time | 542.94 seconds |
| Started | Jun 30 07:59:33 PM PDT 24 |
| Finished | Jun 30 08:08:37 PM PDT 24 |
| Peak memory | 608188 kb |
| Host | smart-072ef626-9941-4bfd-8451-2471fb17d33f |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538594806 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.538594806 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2189265141 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 2266523918 ps |
| CPU time | 180.97 seconds |
| Started | Jun 30 08:01:20 PM PDT 24 |
| Finished | Jun 30 08:04:23 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-c3320667-54ef-413e-9478-0979454f59b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189265141 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.2189265141 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1464101051 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 5101344296 ps |
| CPU time | 721.54 seconds |
| Started | Jun 30 07:54:24 PM PDT 24 |
| Finished | Jun 30 08:06:28 PM PDT 24 |
| Peak memory | 611076 kb |
| Host | smart-85247845-c6b9-4be6-8d46-710cc3dea050 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464101051 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.1464101051 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.5259948 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 2804527221 ps |
| CPU time | 208.43 seconds |
| Started | Jun 30 07:56:08 PM PDT 24 |
| Finished | Jun 30 07:59:37 PM PDT 24 |
| Peak memory | 611956 kb |
| Host | smart-d4ec1a7c-0148-42a2-9544-aea092ed4b71 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5259948 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.5259948 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2685472452 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3614099000 ps |
| CPU time | 485.85 seconds |
| Started | Jun 30 07:55:31 PM PDT 24 |
| Finished | Jun 30 08:03:38 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-5a0ebfce-d7d5-4ab7-b649-9e1981851c39 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685472452 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.2685472452 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.618459688 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 24264663336 ps |
| CPU time | 1742.55 seconds |
| Started | Jun 30 07:53:54 PM PDT 24 |
| Finished | Jun 30 08:22:57 PM PDT 24 |
| Peak memory | 612576 kb |
| Host | smart-0bb1824c-5369-4585-a735-2d82c94cff47 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61845968 8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.618459688 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1721475041 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 5463250052 ps |
| CPU time | 494.38 seconds |
| Started | Jun 30 07:52:56 PM PDT 24 |
| Finished | Jun 30 08:01:11 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-82bfcfd9-5bd8-4c6c-bda8-d4cc7ca4b530 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721475041 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1721475041 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3124433846 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 8965200996 ps |
| CPU time | 1814.05 seconds |
| Started | Jun 30 07:51:28 PM PDT 24 |
| Finished | Jun 30 08:21:42 PM PDT 24 |
| Peak memory | 618856 kb |
| Host | smart-05c4b357-43ec-4447-b212-e95898c38470 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3124433846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.3124433846 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.2378535248 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 3112886340 ps |
| CPU time | 304.57 seconds |
| Started | Jun 30 08:00:18 PM PDT 24 |
| Finished | Jun 30 08:05:22 PM PDT 24 |
| Peak memory | 609568 kb |
| Host | smart-8e2b2840-07c8-44fd-a9a8-f9ed1cbf93df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378535248 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.2378535248 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.3604258553 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 3686404638 ps |
| CPU time | 669.63 seconds |
| Started | Jun 30 07:51:06 PM PDT 24 |
| Finished | Jun 30 08:02:16 PM PDT 24 |
| Peak memory | 615848 kb |
| Host | smart-8ad661ea-e1df-40b0-b84b-e4a4db8c242c |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604258553 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.3604258553 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.4283243825 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 3999420859 ps |
| CPU time | 854.39 seconds |
| Started | Jun 30 07:50:28 PM PDT 24 |
| Finished | Jun 30 08:04:43 PM PDT 24 |
| Peak memory | 617588 kb |
| Host | smart-00a7afdd-3aef-4ad1-943a-42cea1cda4b7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283243825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.4283243825 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2493527299 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 4510764207 ps |
| CPU time | 504.97 seconds |
| Started | Jun 30 07:50:05 PM PDT 24 |
| Finished | Jun 30 07:58:31 PM PDT 24 |
| Peak memory | 620696 kb |
| Host | smart-37c24df1-4a8d-489a-b2ca-79556e5ddd49 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493527299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2493527299 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.297838764 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 3713570640 ps |
| CPU time | 701.09 seconds |
| Started | Jun 30 07:52:40 PM PDT 24 |
| Finished | Jun 30 08:04:22 PM PDT 24 |
| Peak memory | 615892 kb |
| Host | smart-0378f878-27f0-413c-aae7-2ed2f824d7c3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297838764 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.297838764 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2554009031 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 4255931580 ps |
| CPU time | 508.53 seconds |
| Started | Jun 30 07:49:36 PM PDT 24 |
| Finished | Jun 30 07:58:05 PM PDT 24 |
| Peak memory | 615832 kb |
| Host | smart-31d02aba-cc31-4f3f-90dd-06ad30715608 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554009031 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.2554009031 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.9202636 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 4233011496 ps |
| CPU time | 571.88 seconds |
| Started | Jun 30 07:50:37 PM PDT 24 |
| Finished | Jun 30 08:00:09 PM PDT 24 |
| Peak memory | 615836 kb |
| Host | smart-573aa4c3-cf05-4f5e-b9f5-9ef25aa93ff8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9202636 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.9202636 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.1155849983 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 6355174774 ps |
| CPU time | 710.2 seconds |
| Started | Jun 30 07:57:14 PM PDT 24 |
| Finished | Jun 30 08:09:05 PM PDT 24 |
| Peak memory | 618112 kb |
| Host | smart-3aacda0b-e17a-4511-aa5d-d41aa2980686 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1155849983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.1155849983 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.416145496 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 6387410866 ps |
| CPU time | 703.58 seconds |
| Started | Jun 30 07:57:18 PM PDT 24 |
| Finished | Jun 30 08:09:02 PM PDT 24 |
| Peak memory | 620360 kb |
| Host | smart-6beb9c89-87ba-45aa-8d3d-27dbdc66bb4c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416145496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.416145496 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.3243299294 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 3833665962 ps |
| CPU time | 383.67 seconds |
| Started | Jun 30 07:58:22 PM PDT 24 |
| Finished | Jun 30 08:04:46 PM PDT 24 |
| Peak memory | 620352 kb |
| Host | smart-a47eedf4-3f0c-4b61-81e4-4d73155d8f13 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3243299294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.3243299294 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.1485762023 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 15452432691 ps |
| CPU time | 4126.42 seconds |
| Started | Jun 30 08:06:57 PM PDT 24 |
| Finished | Jun 30 09:15:44 PM PDT 24 |
| Peak memory | 608264 kb |
| Host | smart-27012645-7038-4216-89f3-9c5237480365 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485762023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.1485762023 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.3463227984 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 15286912008 ps |
| CPU time | 4406.41 seconds |
| Started | Jun 30 08:05:53 PM PDT 24 |
| Finished | Jun 30 09:19:20 PM PDT 24 |
| Peak memory | 607188 kb |
| Host | smart-1e2ad6b8-02c9-4959-b5a3-f5d3b028d570 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463227984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.3463227984 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2853496293 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 15360153585 ps |
| CPU time | 4224.4 seconds |
| Started | Jun 30 08:06:54 PM PDT 24 |
| Finished | Jun 30 09:17:19 PM PDT 24 |
| Peak memory | 607896 kb |
| Host | smart-e050b3d5-5fa8-40cf-abc5-d6e44a4e58b1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853496293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.2853496293 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.2150019623 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 14566275185 ps |
| CPU time | 3847.21 seconds |
| Started | Jun 30 08:05:17 PM PDT 24 |
| Finished | Jun 30 09:09:25 PM PDT 24 |
| Peak memory | 607884 kb |
| Host | smart-41108d4f-caa1-41dc-980d-4787b6a6712c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150019623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.2150019623 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2603712793 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 11890088260 ps |
| CPU time | 2761.88 seconds |
| Started | Jun 30 08:05:01 PM PDT 24 |
| Finished | Jun 30 08:51:03 PM PDT 24 |
| Peak memory | 607712 kb |
| Host | smart-caf6f4b1-859b-4dda-a57b-3b313388c1fc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603712793 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.2603712793 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1857326614 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 14830442376 ps |
| CPU time | 3218.5 seconds |
| Started | Jun 30 08:03:58 PM PDT 24 |
| Finished | Jun 30 08:57:37 PM PDT 24 |
| Peak memory | 608344 kb |
| Host | smart-7857ed8e-d285-4052-bbc3-eb75779d3d82 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857326614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1857326614 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.899086897 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 14850867564 ps |
| CPU time | 4031.87 seconds |
| Started | Jun 30 08:04:46 PM PDT 24 |
| Finished | Jun 30 09:11:59 PM PDT 24 |
| Peak memory | 608072 kb |
| Host | smart-b114d241-88ff-4dd4-a958-cf89c72b948d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899086897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.899086897 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.353731647 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 15096030986 ps |
| CPU time | 4501.8 seconds |
| Started | Jun 30 08:04:14 PM PDT 24 |
| Finished | Jun 30 09:19:16 PM PDT 24 |
| Peak memory | 607364 kb |
| Host | smart-ec7002c9-c892-4d59-95b7-3599e5386e3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353731647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_ no_meas.353731647 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2363954326 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 14821037002 ps |
| CPU time | 4238.4 seconds |
| Started | Jun 30 08:05:51 PM PDT 24 |
| Finished | Jun 30 09:16:30 PM PDT 24 |
| Peak memory | 608280 kb |
| Host | smart-ab5521ef-ce0a-41bf-9f38-a69d7015ff90 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363954326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.2363954326 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.1844595631 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 28464129875 ps |
| CPU time | 3430.94 seconds |
| Started | Jun 30 08:02:23 PM PDT 24 |
| Finished | Jun 30 08:59:35 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-e6e101ae-8a93-4c50-960b-641ec7633ea4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844595631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.1844595631 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.319635082 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 15068260744 ps |
| CPU time | 3428.43 seconds |
| Started | Jun 30 08:05:42 PM PDT 24 |
| Finished | Jun 30 09:02:51 PM PDT 24 |
| Peak memory | 608272 kb |
| Host | smart-755c5b2d-8bce-46be-b5a2-712de34cbf01 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=319635082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.319635082 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.3364957121 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 17018658800 ps |
| CPU time | 4328.48 seconds |
| Started | Jun 30 08:05:17 PM PDT 24 |
| Finished | Jun 30 09:17:26 PM PDT 24 |
| Peak memory | 607304 kb |
| Host | smart-a21985b1-db99-49de-a476-f0d79fdd0580 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364957121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.3364957121 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.2306891566 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 4038015960 ps |
| CPU time | 574.3 seconds |
| Started | Jun 30 07:58:27 PM PDT 24 |
| Finished | Jun 30 08:08:01 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-7a7af9ee-d0d1-4d65-9b8a-90046cef58ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306891566 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.2306891566 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.903786307 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 3007250323 ps |
| CPU time | 106.72 seconds |
| Started | Jun 30 07:58:55 PM PDT 24 |
| Finished | Jun 30 08:00:42 PM PDT 24 |
| Peak memory | 614424 kb |
| Host | smart-ab2eecf6-c773-4515-886a-4094e2643c7e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903786307 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.903786307 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1966623700 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 4226497450 ps |
| CPU time | 521.59 seconds |
| Started | Jun 30 08:04:03 PM PDT 24 |
| Finished | Jun 30 08:12:45 PM PDT 24 |
| Peak memory | 642188 kb |
| Host | smart-23f7917e-c354-4e48-a3de-bdffab397c5c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966623700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1966623700 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3326715491 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3243292392 ps |
| CPU time | 378.38 seconds |
| Started | Jun 30 08:03:38 PM PDT 24 |
| Finished | Jun 30 08:09:57 PM PDT 24 |
| Peak memory | 646908 kb |
| Host | smart-5e5fef1e-f2c2-4cb9-bba2-70e8069aac90 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326715491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3326715491 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.1210342368 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 4919121800 ps |
| CPU time | 554.29 seconds |
| Started | Jun 30 08:04:36 PM PDT 24 |
| Finished | Jun 30 08:13:51 PM PDT 24 |
| Peak memory | 643348 kb |
| Host | smart-1eb03768-449f-4699-b822-7b7aabb92a7a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1210342368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.1210342368 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2199582937 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 3468474264 ps |
| CPU time | 360.79 seconds |
| Started | Jun 30 08:05:55 PM PDT 24 |
| Finished | Jun 30 08:11:56 PM PDT 24 |
| Peak memory | 647140 kb |
| Host | smart-ffe406ed-5d35-4e32-9f2a-0ff375e7e500 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199582937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2199582937 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.1968056266 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 5706621132 ps |
| CPU time | 552.67 seconds |
| Started | Jun 30 08:06:07 PM PDT 24 |
| Finished | Jun 30 08:15:20 PM PDT 24 |
| Peak memory | 608660 kb |
| Host | smart-7039fad7-4a32-4f01-a64e-0912801c4aad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1968056266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.1968056266 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.792884368 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3825455880 ps |
| CPU time | 369.03 seconds |
| Started | Jun 30 08:06:08 PM PDT 24 |
| Finished | Jun 30 08:12:17 PM PDT 24 |
| Peak memory | 647032 kb |
| Host | smart-7e20d0d5-4289-4421-92d5-99a9ebd2863e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792884368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_s w_alert_handler_lpg_sleep_mode_alerts.792884368 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.1373850617 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 4992974384 ps |
| CPU time | 740.13 seconds |
| Started | Jun 30 08:00:40 PM PDT 24 |
| Finished | Jun 30 08:13:01 PM PDT 24 |
| Peak memory | 615140 kb |
| Host | smart-596791a0-379f-4844-b017-914b19df35d2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1373850617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.1373850617 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3909687222 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 7774103932 ps |
| CPU time | 616.4 seconds |
| Started | Jun 30 08:01:45 PM PDT 24 |
| Finished | Jun 30 08:12:02 PM PDT 24 |
| Peak memory | 609244 kb |
| Host | smart-ac211027-1112-4aac-9283-47d1893deaef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3909687222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3909687222 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3020227241 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 32256551560 ps |
| CPU time | 7839.86 seconds |
| Started | Jun 30 08:00:07 PM PDT 24 |
| Finished | Jun 30 10:10:48 PM PDT 24 |
| Peak memory | 608392 kb |
| Host | smart-bce6f939-8f63-4021-a43a-e238818eb31c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020227241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.3020227241 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1978605930 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 5922727088 ps |
| CPU time | 752.94 seconds |
| Started | Jun 30 08:01:26 PM PDT 24 |
| Finished | Jun 30 08:14:00 PM PDT 24 |
| Peak memory | 608468 kb |
| Host | smart-473dd6f7-6ace-4393-964e-cad90e22e17e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1978605930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.1978605930 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.17847299 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 7438417250 ps |
| CPU time | 1117.81 seconds |
| Started | Jun 30 08:00:15 PM PDT 24 |
| Finished | Jun 30 08:18:53 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-4423f80a-e360-4715-839f-594125aed24d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17847299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.17847299 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3415958781 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 13577091090 ps |
| CPU time | 3198.18 seconds |
| Started | Jun 30 08:01:39 PM PDT 24 |
| Finished | Jun 30 08:54:58 PM PDT 24 |
| Peak memory | 618908 kb |
| Host | smart-8369b4bd-5222-4674-932f-48571679e86e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3415958781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.3415958781 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.2700897803 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 4412985508 ps |
| CPU time | 694.24 seconds |
| Started | Jun 30 07:59:19 PM PDT 24 |
| Finished | Jun 30 08:10:53 PM PDT 24 |
| Peak memory | 615892 kb |
| Host | smart-bce2d879-d008-4eb9-aaa1-353cbec17b2e |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700897803 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.2700897803 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3344988118 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 4484298950 ps |
| CPU time | 476.61 seconds |
| Started | Jun 30 08:00:42 PM PDT 24 |
| Finished | Jun 30 08:08:39 PM PDT 24 |
| Peak memory | 617912 kb |
| Host | smart-fd99d79a-19a4-41f0-9361-096bdf460020 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344988118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3344988118 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2327197607 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 4302474400 ps |
| CPU time | 770.17 seconds |
| Started | Jun 30 08:00:52 PM PDT 24 |
| Finished | Jun 30 08:13:43 PM PDT 24 |
| Peak memory | 615780 kb |
| Host | smart-69300701-ae5b-40cd-9622-4d3323fa5e71 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327197607 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.2327197607 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.157784039 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3947262650 ps |
| CPU time | 638.54 seconds |
| Started | Jun 30 08:00:47 PM PDT 24 |
| Finished | Jun 30 08:11:26 PM PDT 24 |
| Peak memory | 615824 kb |
| Host | smart-e7b1a5ee-768b-49a5-957f-0bb8cd65eb4e |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157784039 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.157784039 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3570436787 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4246368312 ps |
| CPU time | 657.49 seconds |
| Started | Jun 30 08:01:33 PM PDT 24 |
| Finished | Jun 30 08:12:32 PM PDT 24 |
| Peak memory | 615876 kb |
| Host | smart-837b861b-d4f0-4fc7-b4b8-ea61abfdf790 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570436787 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.3570436787 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.1656295126 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 2780983167 ps |
| CPU time | 193.06 seconds |
| Started | Jun 30 07:59:30 PM PDT 24 |
| Finished | Jun 30 08:02:44 PM PDT 24 |
| Peak memory | 618056 kb |
| Host | smart-1104d3b3-ac28-4169-9011-401311040df0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656295126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.1656295126 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.627586040 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 2262120299 ps |
| CPU time | 211.29 seconds |
| Started | Jun 30 08:01:06 PM PDT 24 |
| Finished | Jun 30 08:04:38 PM PDT 24 |
| Peak memory | 617652 kb |
| Host | smart-3598dd73-29a2-46aa-b397-b46cf1246613 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=627586040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.627586040 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.2479044177 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 4814656674 ps |
| CPU time | 726.89 seconds |
| Started | Jun 30 08:04:28 PM PDT 24 |
| Finished | Jun 30 08:16:35 PM PDT 24 |
| Peak memory | 643352 kb |
| Host | smart-5068f89f-decb-403a-81d8-58706d8cc8d7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2479044177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.2479044177 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1938082883 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 3638683552 ps |
| CPU time | 368.63 seconds |
| Started | Jun 30 08:05:28 PM PDT 24 |
| Finished | Jun 30 08:11:37 PM PDT 24 |
| Peak memory | 646952 kb |
| Host | smart-ddba0b3c-dfd6-470e-91ab-569daffaa995 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938082883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1938082883 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.477942676 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 5062421950 ps |
| CPU time | 840.93 seconds |
| Started | Jun 30 08:05:13 PM PDT 24 |
| Finished | Jun 30 08:19:14 PM PDT 24 |
| Peak memory | 643516 kb |
| Host | smart-6ca79cca-5366-481b-9cdf-aa01cb17d2bb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 477942676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.477942676 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.4072711359 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 4323876378 ps |
| CPU time | 436.12 seconds |
| Started | Jun 30 08:04:14 PM PDT 24 |
| Finished | Jun 30 08:11:31 PM PDT 24 |
| Peak memory | 647216 kb |
| Host | smart-72536184-428f-4da4-bf4c-e7156e38cc0c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072711359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4072711359 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.1069113284 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 4599704856 ps |
| CPU time | 765.64 seconds |
| Started | Jun 30 08:06:27 PM PDT 24 |
| Finished | Jun 30 08:19:14 PM PDT 24 |
| Peak memory | 643416 kb |
| Host | smart-b9480d68-b78a-4d93-b731-b8e012746cbb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1069113284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.1069113284 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.993702090 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 4551968600 ps |
| CPU time | 606.63 seconds |
| Started | Jun 30 08:07:59 PM PDT 24 |
| Finished | Jun 30 08:18:08 PM PDT 24 |
| Peak memory | 643504 kb |
| Host | smart-995a2a7b-1762-4146-bd86-5828cc4dcd04 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 993702090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.993702090 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.693244415 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 3766834822 ps |
| CPU time | 391.21 seconds |
| Started | Jun 30 08:07:26 PM PDT 24 |
| Finished | Jun 30 08:13:57 PM PDT 24 |
| Peak memory | 647040 kb |
| Host | smart-6156b432-4543-4514-8ef0-8dc3c78f4df0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693244415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_s w_alert_handler_lpg_sleep_mode_alerts.693244415 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2322792954 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 4048840050 ps |
| CPU time | 385 seconds |
| Started | Jun 30 08:04:16 PM PDT 24 |
| Finished | Jun 30 08:10:41 PM PDT 24 |
| Peak memory | 647064 kb |
| Host | smart-92ca9d7e-7b72-4d49-b841-38c4342fe44d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322792954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2322792954 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2826712235 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 3345916516 ps |
| CPU time | 421.89 seconds |
| Started | Jun 30 08:05:11 PM PDT 24 |
| Finished | Jun 30 08:12:13 PM PDT 24 |
| Peak memory | 642228 kb |
| Host | smart-e19bc678-f729-406d-89a0-2e5d2a7638c6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826712235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2826712235 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1929459142 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 4233521600 ps |
| CPU time | 452.05 seconds |
| Started | Jun 30 08:05:01 PM PDT 24 |
| Finished | Jun 30 08:12:34 PM PDT 24 |
| Peak memory | 647360 kb |
| Host | smart-e59d22cf-1bf5-4859-bcfc-808e993fc60c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929459142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1929459142 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.418685872 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 5309176516 ps |
| CPU time | 589.65 seconds |
| Started | Jun 30 08:05:32 PM PDT 24 |
| Finished | Jun 30 08:15:22 PM PDT 24 |
| Peak memory | 643656 kb |
| Host | smart-a50a0ad5-c8e1-48d7-a064-9e0883c31b71 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 418685872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.418685872 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1977055330 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 3601017266 ps |
| CPU time | 453.74 seconds |
| Started | Jun 30 08:05:30 PM PDT 24 |
| Finished | Jun 30 08:13:04 PM PDT 24 |
| Peak memory | 642084 kb |
| Host | smart-e4d0b11e-c5a3-43dc-a4a4-a0d9953787bf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977055330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1977055330 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.1044367804 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 4779462144 ps |
| CPU time | 660.7 seconds |
| Started | Jun 30 08:07:21 PM PDT 24 |
| Finished | Jun 30 08:18:22 PM PDT 24 |
| Peak memory | 643404 kb |
| Host | smart-00ce3ebc-3ba0-4bf4-92fd-b205e63d7a77 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1044367804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.1044367804 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1740633773 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 4134648630 ps |
| CPU time | 405.99 seconds |
| Started | Jun 30 08:02:26 PM PDT 24 |
| Finished | Jun 30 08:09:12 PM PDT 24 |
| Peak memory | 616648 kb |
| Host | smart-832dd250-5cd8-4c4f-aea7-ec9905f23ebd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740633773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.1740633773 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2740723118 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 7085745344 ps |
| CPU time | 409.65 seconds |
| Started | Jun 30 08:02:17 PM PDT 24 |
| Finished | Jun 30 08:09:07 PM PDT 24 |
| Peak memory | 608296 kb |
| Host | smart-4153f345-dd1c-4e9a-b408-fad2660ca172 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2740723118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2740723118 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.603965837 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 29466969050 ps |
| CPU time | 6566.21 seconds |
| Started | Jun 30 08:01:40 PM PDT 24 |
| Finished | Jun 30 09:51:07 PM PDT 24 |
| Peak memory | 608408 kb |
| Host | smart-218b3a82-94b9-4dbb-afd5-a86356867083 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603965837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.603965837 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2579604007 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 5830627604 ps |
| CPU time | 815.18 seconds |
| Started | Jun 30 07:59:40 PM PDT 24 |
| Finished | Jun 30 08:13:16 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-ecbbbfea-bd56-4dc7-8781-f2739c6196d9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2579604007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.2579604007 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1404773489 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 6973388271 ps |
| CPU time | 509.78 seconds |
| Started | Jun 30 08:00:49 PM PDT 24 |
| Finished | Jun 30 08:09:21 PM PDT 24 |
| Peak memory | 620196 kb |
| Host | smart-a09c905f-f697-49eb-abb3-a7c5e7b7b3aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404773489 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.1404773489 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.192937109 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 8052318552 ps |
| CPU time | 1529.92 seconds |
| Started | Jun 30 08:01:46 PM PDT 24 |
| Finished | Jun 30 08:27:17 PM PDT 24 |
| Peak memory | 618460 kb |
| Host | smart-e6bcb0b1-85d6-4ed9-8c9b-74fdd42b0030 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=192937109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.192937109 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.2917181982 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 3915396476 ps |
| CPU time | 614.51 seconds |
| Started | Jun 30 08:00:09 PM PDT 24 |
| Finished | Jun 30 08:10:24 PM PDT 24 |
| Peak memory | 616020 kb |
| Host | smart-9704de06-240a-46b7-bbfc-2d3862709517 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917181982 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.2917181982 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2015639536 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 7605602085 ps |
| CPU time | 1576.28 seconds |
| Started | Jun 30 08:01:24 PM PDT 24 |
| Finished | Jun 30 08:27:42 PM PDT 24 |
| Peak memory | 617624 kb |
| Host | smart-eef5826f-34c3-46ae-b85a-4956a8a17002 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015639536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.2015639536 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1806967167 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 8577298948 ps |
| CPU time | 1143.02 seconds |
| Started | Jun 30 08:02:58 PM PDT 24 |
| Finished | Jun 30 08:22:02 PM PDT 24 |
| Peak memory | 617912 kb |
| Host | smart-d8b36aaa-9ed8-417d-a5fa-bfee702d2b05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806967167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1806967167 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1211270751 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 3560897860 ps |
| CPU time | 640.12 seconds |
| Started | Jun 30 08:00:09 PM PDT 24 |
| Finished | Jun 30 08:10:50 PM PDT 24 |
| Peak memory | 615880 kb |
| Host | smart-62e4eaaa-a7c0-4beb-9e79-ae5b35333688 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211270751 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.1211270751 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1388103025 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 3917794520 ps |
| CPU time | 643.2 seconds |
| Started | Jun 30 08:02:02 PM PDT 24 |
| Finished | Jun 30 08:12:46 PM PDT 24 |
| Peak memory | 615864 kb |
| Host | smart-45a786c5-ce30-42c6-a4c8-508d8251d8ad |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388103025 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.1388103025 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2758212890 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 4980130430 ps |
| CPU time | 696.18 seconds |
| Started | Jun 30 08:00:57 PM PDT 24 |
| Finished | Jun 30 08:12:34 PM PDT 24 |
| Peak memory | 615860 kb |
| Host | smart-0ff81740-d354-4949-ac3c-1726b62b05d6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758212890 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.2758212890 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.161532755 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 2405800910 ps |
| CPU time | 141.45 seconds |
| Started | Jun 30 08:00:55 PM PDT 24 |
| Finished | Jun 30 08:03:17 PM PDT 24 |
| Peak memory | 618460 kb |
| Host | smart-7441f30b-c119-4af9-a8cd-d984148aa8e3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161532755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.161532755 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.620745348 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2416991479 ps |
| CPU time | 200.55 seconds |
| Started | Jun 30 07:59:41 PM PDT 24 |
| Finished | Jun 30 08:03:02 PM PDT 24 |
| Peak memory | 617608 kb |
| Host | smart-ea747515-970a-4132-9410-e6f8f107e4f5 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620745348 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.620745348 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.1201562996 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 2817727562 ps |
| CPU time | 119.5 seconds |
| Started | Jun 30 08:01:11 PM PDT 24 |
| Finished | Jun 30 08:03:11 PM PDT 24 |
| Peak memory | 620076 kb |
| Host | smart-f71f6b4a-db17-4829-9627-e5973fc0d987 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1201562996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.1201562996 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1310247059 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 3570501296 ps |
| CPU time | 408.43 seconds |
| Started | Jun 30 08:05:47 PM PDT 24 |
| Finished | Jun 30 08:12:36 PM PDT 24 |
| Peak memory | 647044 kb |
| Host | smart-1c0e3bab-a917-4ab5-be42-1cab8d64d32a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310247059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1310247059 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.4053456243 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 5943244460 ps |
| CPU time | 696.44 seconds |
| Started | Jun 30 08:05:50 PM PDT 24 |
| Finished | Jun 30 08:17:27 PM PDT 24 |
| Peak memory | 647876 kb |
| Host | smart-f81045f9-d5f1-4c6a-9277-044e70ea7486 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4053456243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.4053456243 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.1836812310 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 5104922936 ps |
| CPU time | 648.69 seconds |
| Started | Jun 30 08:05:43 PM PDT 24 |
| Finished | Jun 30 08:16:32 PM PDT 24 |
| Peak memory | 648016 kb |
| Host | smart-03eabf0e-5f2a-405c-9e8e-4e7bba22f29f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1836812310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.1836812310 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119592798 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 4588282860 ps |
| CPU time | 462.79 seconds |
| Started | Jun 30 08:08:25 PM PDT 24 |
| Finished | Jun 30 08:16:08 PM PDT 24 |
| Peak memory | 647260 kb |
| Host | smart-1baf6cff-1375-4b80-a8a4-1caa247047db |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119592798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2119592798 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.3123426046 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 4738610890 ps |
| CPU time | 525.66 seconds |
| Started | Jun 30 08:05:14 PM PDT 24 |
| Finished | Jun 30 08:14:00 PM PDT 24 |
| Peak memory | 615108 kb |
| Host | smart-e9ec2f05-9c71-458b-bb49-7c061f6d7625 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3123426046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.3123426046 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.459392976 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 3690959280 ps |
| CPU time | 403.26 seconds |
| Started | Jun 30 08:05:31 PM PDT 24 |
| Finished | Jun 30 08:12:15 PM PDT 24 |
| Peak memory | 647180 kb |
| Host | smart-1cf99a59-47e5-490a-9919-544241f283f5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459392976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_s w_alert_handler_lpg_sleep_mode_alerts.459392976 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.4041947803 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 4661345070 ps |
| CPU time | 522.87 seconds |
| Started | Jun 30 08:06:12 PM PDT 24 |
| Finished | Jun 30 08:14:55 PM PDT 24 |
| Peak memory | 615148 kb |
| Host | smart-6d2f2711-1e7a-4e76-b372-58ca907f2edf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4041947803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.4041947803 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.1127388745 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 6298037500 ps |
| CPU time | 635.35 seconds |
| Started | Jun 30 08:08:29 PM PDT 24 |
| Finished | Jun 30 08:19:05 PM PDT 24 |
| Peak memory | 648048 kb |
| Host | smart-7a4ff0ea-aeab-400e-9328-a8b1c5b9a0aa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1127388745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.1127388745 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.639616173 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 3343487482 ps |
| CPU time | 403.22 seconds |
| Started | Jun 30 08:06:22 PM PDT 24 |
| Finished | Jun 30 08:13:05 PM PDT 24 |
| Peak memory | 647288 kb |
| Host | smart-0f3bb2ef-b663-44c9-8ed8-1c655fe4615c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639616173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_s w_alert_handler_lpg_sleep_mode_alerts.639616173 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3695707650 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 4246803468 ps |
| CPU time | 444.12 seconds |
| Started | Jun 30 08:02:53 PM PDT 24 |
| Finished | Jun 30 08:10:18 PM PDT 24 |
| Peak memory | 646992 kb |
| Host | smart-0ceebc75-c7d4-4d97-bdff-a205d8c7a0f4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695707650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.3695707650 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.2206043000 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 6136556388 ps |
| CPU time | 882.17 seconds |
| Started | Jun 30 08:01:36 PM PDT 24 |
| Finished | Jun 30 08:16:19 PM PDT 24 |
| Peak memory | 647848 kb |
| Host | smart-6bf7bca5-713a-42d5-9d75-0cc43a223c47 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2206043000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.2206043000 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3321174439 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 25937204700 ps |
| CPU time | 6330.08 seconds |
| Started | Jun 30 08:03:14 PM PDT 24 |
| Finished | Jun 30 09:48:45 PM PDT 24 |
| Peak memory | 608444 kb |
| Host | smart-9dfb51ad-589b-43d0-a945-34190e273ede |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321174439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.3321174439 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.548423767 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 9040074240 ps |
| CPU time | 917.89 seconds |
| Started | Jun 30 08:03:12 PM PDT 24 |
| Finished | Jun 30 08:18:30 PM PDT 24 |
| Peak memory | 620900 kb |
| Host | smart-9f3307ea-db83-42bd-b633-aada133af62e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548423767 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.548423767 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.968491016 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 4142115398 ps |
| CPU time | 590.13 seconds |
| Started | Jun 30 08:01:26 PM PDT 24 |
| Finished | Jun 30 08:11:17 PM PDT 24 |
| Peak memory | 618572 kb |
| Host | smart-2778909b-8b8b-40ab-a536-2820d3e211ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=968491016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.968491016 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.255049264 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 5457969614 ps |
| CPU time | 677.25 seconds |
| Started | Jun 30 08:06:42 PM PDT 24 |
| Finished | Jun 30 08:18:00 PM PDT 24 |
| Peak memory | 648032 kb |
| Host | smart-4c69ab87-4c65-43ba-b590-38a46f8383cd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 255049264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.255049264 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1262509774 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 3489955520 ps |
| CPU time | 519.22 seconds |
| Started | Jun 30 08:07:07 PM PDT 24 |
| Finished | Jun 30 08:15:47 PM PDT 24 |
| Peak memory | 647188 kb |
| Host | smart-2a3a5d72-dc02-4e31-b076-e8aed3898ea4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262509774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1262509774 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.1536822133 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 5991728660 ps |
| CPU time | 587 seconds |
| Started | Jun 30 08:06:29 PM PDT 24 |
| Finished | Jun 30 08:16:17 PM PDT 24 |
| Peak memory | 617276 kb |
| Host | smart-d0e2e5b7-9372-4b34-8724-f4cf51084d14 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1536822133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.1536822133 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2087441151 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 3855084006 ps |
| CPU time | 530.16 seconds |
| Started | Jun 30 08:06:28 PM PDT 24 |
| Finished | Jun 30 08:15:18 PM PDT 24 |
| Peak memory | 642216 kb |
| Host | smart-b6739f94-e2ca-422c-bcaf-33427fd18f8f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087441151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2087441151 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.246092758 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 4873789650 ps |
| CPU time | 515.97 seconds |
| Started | Jun 30 08:06:59 PM PDT 24 |
| Finished | Jun 30 08:15:36 PM PDT 24 |
| Peak memory | 643588 kb |
| Host | smart-f991fdde-97b4-41d5-ad59-ab42ce4d85d7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 246092758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.246092758 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3975706535 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 3488884424 ps |
| CPU time | 373.81 seconds |
| Started | Jun 30 08:07:28 PM PDT 24 |
| Finished | Jun 30 08:13:43 PM PDT 24 |
| Peak memory | 615168 kb |
| Host | smart-189f1277-ff82-44a7-80be-90df73281519 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975706535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3975706535 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.1847139374 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 4789875408 ps |
| CPU time | 754.42 seconds |
| Started | Jun 30 08:06:25 PM PDT 24 |
| Finished | Jun 30 08:19:00 PM PDT 24 |
| Peak memory | 648064 kb |
| Host | smart-a9c7817f-296e-4e36-bcf1-37bca34636c0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1847139374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.1847139374 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.571685186 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4332526920 ps |
| CPU time | 508.01 seconds |
| Started | Jun 30 08:06:34 PM PDT 24 |
| Finished | Jun 30 08:15:03 PM PDT 24 |
| Peak memory | 647260 kb |
| Host | smart-13591696-3bfc-4be6-9e93-7b35e43dbcb2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571685186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_s w_alert_handler_lpg_sleep_mode_alerts.571685186 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2734766511 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 3895768880 ps |
| CPU time | 392.44 seconds |
| Started | Jun 30 08:07:26 PM PDT 24 |
| Finished | Jun 30 08:13:59 PM PDT 24 |
| Peak memory | 646964 kb |
| Host | smart-5de11182-5de5-4381-9dd7-19995a96e037 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734766511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2734766511 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.3799658231 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 5637327688 ps |
| CPU time | 623.65 seconds |
| Started | Jun 30 08:07:18 PM PDT 24 |
| Finished | Jun 30 08:17:43 PM PDT 24 |
| Peak memory | 643556 kb |
| Host | smart-9c635207-83d1-46c1-8801-6c60369e741f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3799658231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.3799658231 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1871410141 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 3384240056 ps |
| CPU time | 391.12 seconds |
| Started | Jun 30 08:07:16 PM PDT 24 |
| Finished | Jun 30 08:13:48 PM PDT 24 |
| Peak memory | 646940 kb |
| Host | smart-6911edd6-890d-45e6-afc6-1b61b9a7f1af |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871410141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1871410141 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.1781422350 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 4673485436 ps |
| CPU time | 551.63 seconds |
| Started | Jun 30 08:07:47 PM PDT 24 |
| Finished | Jun 30 08:16:59 PM PDT 24 |
| Peak memory | 643744 kb |
| Host | smart-93f5f76e-d09c-4430-99cf-4397a22e3fa3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1781422350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.1781422350 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1268092005 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4052224392 ps |
| CPU time | 377.73 seconds |
| Started | Jun 30 08:07:18 PM PDT 24 |
| Finished | Jun 30 08:13:36 PM PDT 24 |
| Peak memory | 646944 kb |
| Host | smart-af2fa53e-1a1c-4f06-9c3d-0070a7b0f7fb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268092005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1268092005 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.2958343640 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 6248379558 ps |
| CPU time | 891.18 seconds |
| Started | Jun 30 08:09:18 PM PDT 24 |
| Finished | Jun 30 08:24:10 PM PDT 24 |
| Peak memory | 643572 kb |
| Host | smart-d56f8031-65e8-4ceb-905e-72fcc50d2910 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2958343640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.2958343640 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3328628585 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 3980298056 ps |
| CPU time | 464.38 seconds |
| Started | Jun 30 08:07:55 PM PDT 24 |
| Finished | Jun 30 08:15:41 PM PDT 24 |
| Peak memory | 646840 kb |
| Host | smart-1ef542f8-2218-419a-a656-4c5dc396d644 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328628585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3328628585 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.1997086282 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 4688763140 ps |
| CPU time | 594.44 seconds |
| Started | Jun 30 08:07:54 PM PDT 24 |
| Finished | Jun 30 08:17:49 PM PDT 24 |
| Peak memory | 617264 kb |
| Host | smart-0aed4256-e6a7-4890-9088-5c049a9e3a21 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1997086282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.1997086282 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2882626556 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 3677989720 ps |
| CPU time | 413.92 seconds |
| Started | Jun 30 08:07:57 PM PDT 24 |
| Finished | Jun 30 08:14:52 PM PDT 24 |
| Peak memory | 642264 kb |
| Host | smart-4f75510e-b3b2-4cb5-9c35-0f3a059539af |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882626556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2882626556 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.734581468 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 3623448694 ps |
| CPU time | 484.48 seconds |
| Started | Jun 30 08:01:23 PM PDT 24 |
| Finished | Jun 30 08:09:29 PM PDT 24 |
| Peak memory | 642436 kb |
| Host | smart-a9c006e2-c421-4979-9b88-b8d67b18c2fd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734581468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw _alert_handler_lpg_sleep_mode_alerts.734581468 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.4125634192 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 16293455556 ps |
| CPU time | 3946.79 seconds |
| Started | Jun 30 08:01:18 PM PDT 24 |
| Finished | Jun 30 09:07:07 PM PDT 24 |
| Peak memory | 608404 kb |
| Host | smart-28a228d4-d143-4545-947f-ed0b0224a178 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125634192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.4125634192 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.828486805 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 11085628375 ps |
| CPU time | 968.93 seconds |
| Started | Jun 30 08:01:01 PM PDT 24 |
| Finished | Jun 30 08:17:11 PM PDT 24 |
| Peak memory | 621480 kb |
| Host | smart-0854f24f-bab5-460c-90f6-a356b464f480 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828486805 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.828486805 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2805100152 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 8184984224 ps |
| CPU time | 1851.91 seconds |
| Started | Jun 30 08:02:58 PM PDT 24 |
| Finished | Jun 30 08:33:50 PM PDT 24 |
| Peak memory | 618316 kb |
| Host | smart-bbdc4620-1aed-4c2f-b67b-9c86e1420ddb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2805100152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.2805100152 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1599664333 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 3523141304 ps |
| CPU time | 384.78 seconds |
| Started | Jun 30 08:07:18 PM PDT 24 |
| Finished | Jun 30 08:13:44 PM PDT 24 |
| Peak memory | 647104 kb |
| Host | smart-0af3ea20-79bb-407d-806e-3645e2474b09 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599664333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1599664333 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.40042039 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 3661175772 ps |
| CPU time | 459.32 seconds |
| Started | Jun 30 08:08:26 PM PDT 24 |
| Finished | Jun 30 08:16:06 PM PDT 24 |
| Peak memory | 646924 kb |
| Host | smart-3fb3e205-e3f4-4eff-b4e4-e7c7f0565333 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40042039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw _alert_handler_lpg_sleep_mode_alerts.40042039 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.2438013691 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 4563133962 ps |
| CPU time | 775.27 seconds |
| Started | Jun 30 08:06:47 PM PDT 24 |
| Finished | Jun 30 08:19:42 PM PDT 24 |
| Peak memory | 643460 kb |
| Host | smart-e672038d-4d03-4255-b885-d9124f4ece2c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2438013691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.2438013691 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.1709551933 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 4796643046 ps |
| CPU time | 603.24 seconds |
| Started | Jun 30 08:08:21 PM PDT 24 |
| Finished | Jun 30 08:18:25 PM PDT 24 |
| Peak memory | 643428 kb |
| Host | smart-6634896c-a9c3-4a78-b2b7-a5a1b7790b95 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1709551933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.1709551933 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3633165315 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 3666814158 ps |
| CPU time | 410.47 seconds |
| Started | Jun 30 08:07:48 PM PDT 24 |
| Finished | Jun 30 08:14:39 PM PDT 24 |
| Peak memory | 647132 kb |
| Host | smart-3a893c33-13c7-4232-a4da-b7493071b7e1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633165315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3633165315 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.1164008498 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 5044386400 ps |
| CPU time | 693.04 seconds |
| Started | Jun 30 08:07:24 PM PDT 24 |
| Finished | Jun 30 08:18:57 PM PDT 24 |
| Peak memory | 643376 kb |
| Host | smart-049952b7-5c95-4d2c-92cb-6b16905625ca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1164008498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.1164008498 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3600644706 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 3618085252 ps |
| CPU time | 357.84 seconds |
| Started | Jun 30 08:08:28 PM PDT 24 |
| Finished | Jun 30 08:14:26 PM PDT 24 |
| Peak memory | 642380 kb |
| Host | smart-de535de4-a5a2-4e75-bb11-8755797fe9be |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600644706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3600644706 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.3352838041 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 4897421488 ps |
| CPU time | 699.88 seconds |
| Started | Jun 30 08:07:54 PM PDT 24 |
| Finished | Jun 30 08:19:34 PM PDT 24 |
| Peak memory | 643536 kb |
| Host | smart-e0748556-3db0-4067-b375-137f68614e7c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3352838041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.3352838041 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2261899274 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 3673190690 ps |
| CPU time | 408.48 seconds |
| Started | Jun 30 08:07:38 PM PDT 24 |
| Finished | Jun 30 08:14:26 PM PDT 24 |
| Peak memory | 647304 kb |
| Host | smart-bb611c02-4e87-4289-8b89-c0b56f3bb5e8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261899274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2261899274 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.3140707794 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 5672028200 ps |
| CPU time | 850.72 seconds |
| Started | Jun 30 08:08:26 PM PDT 24 |
| Finished | Jun 30 08:22:37 PM PDT 24 |
| Peak memory | 647828 kb |
| Host | smart-ef22455c-b898-4444-a748-e1bc65bbf823 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3140707794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.3140707794 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.4025962906 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 3274393140 ps |
| CPU time | 412.07 seconds |
| Started | Jun 30 08:07:39 PM PDT 24 |
| Finished | Jun 30 08:14:31 PM PDT 24 |
| Peak memory | 642476 kb |
| Host | smart-3b877717-2e67-4473-a248-42f76b755d96 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025962906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4025962906 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3898371736 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 3455020304 ps |
| CPU time | 452.28 seconds |
| Started | Jun 30 08:08:23 PM PDT 24 |
| Finished | Jun 30 08:15:56 PM PDT 24 |
| Peak memory | 646884 kb |
| Host | smart-e29f5c46-f584-4740-84bb-9f4902d6cd97 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898371736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3898371736 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.1487200101 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 5133066508 ps |
| CPU time | 618.59 seconds |
| Started | Jun 30 08:08:45 PM PDT 24 |
| Finished | Jun 30 08:19:04 PM PDT 24 |
| Peak memory | 615124 kb |
| Host | smart-cbaf9bf5-d127-4741-8362-408fb5aa2bcf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1487200101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.1487200101 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1634832964 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 3830310810 ps |
| CPU time | 390.73 seconds |
| Started | Jun 30 08:03:00 PM PDT 24 |
| Finished | Jun 30 08:09:31 PM PDT 24 |
| Peak memory | 615172 kb |
| Host | smart-654e00f1-d0f3-4b24-82bd-75e16f6439f0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634832964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.1634832964 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2392090399 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 13045349976 ps |
| CPU time | 3671.25 seconds |
| Started | Jun 30 08:03:49 PM PDT 24 |
| Finished | Jun 30 09:05:01 PM PDT 24 |
| Peak memory | 608300 kb |
| Host | smart-1163c8ab-1d5a-4eb7-af09-43da6dff0ebf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392090399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.2392090399 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1229192695 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 12577820924 ps |
| CPU time | 881.08 seconds |
| Started | Jun 30 08:01:45 PM PDT 24 |
| Finished | Jun 30 08:16:27 PM PDT 24 |
| Peak memory | 619276 kb |
| Host | smart-4a8c87d6-f234-44b7-ba56-9f1f980a46e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229192695 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.1229192695 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.4029155943 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 8241718512 ps |
| CPU time | 1466.65 seconds |
| Started | Jun 30 08:01:09 PM PDT 24 |
| Finished | Jun 30 08:25:37 PM PDT 24 |
| Peak memory | 618884 kb |
| Host | smart-b9a394ea-e01c-4eec-96f4-f45594e796fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4029155943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.4029155943 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3105135463 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 3693401366 ps |
| CPU time | 325.95 seconds |
| Started | Jun 30 08:09:02 PM PDT 24 |
| Finished | Jun 30 08:14:28 PM PDT 24 |
| Peak memory | 646936 kb |
| Host | smart-0d8d043f-dbe7-410c-a4bc-6399a89624db |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105135463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3105135463 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.415018851 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 6409573656 ps |
| CPU time | 763.73 seconds |
| Started | Jun 30 08:08:42 PM PDT 24 |
| Finished | Jun 30 08:21:26 PM PDT 24 |
| Peak memory | 648224 kb |
| Host | smart-453110b0-09de-496f-8124-74b5824da9f4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 415018851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.415018851 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2952838774 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 3494731752 ps |
| CPU time | 339.75 seconds |
| Started | Jun 30 08:09:34 PM PDT 24 |
| Finished | Jun 30 08:15:14 PM PDT 24 |
| Peak memory | 647088 kb |
| Host | smart-93d42735-b492-4bfa-b6b9-1b924c253222 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952838774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2952838774 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.4247061283 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 5422946920 ps |
| CPU time | 806.15 seconds |
| Started | Jun 30 08:10:44 PM PDT 24 |
| Finished | Jun 30 08:24:10 PM PDT 24 |
| Peak memory | 643320 kb |
| Host | smart-32a883d3-d5d9-4112-bf25-9c9647ccabc3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4247061283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.4247061283 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1149241049 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 3600660512 ps |
| CPU time | 437.08 seconds |
| Started | Jun 30 08:09:42 PM PDT 24 |
| Finished | Jun 30 08:17:00 PM PDT 24 |
| Peak memory | 646868 kb |
| Host | smart-b889e50b-59a5-4c79-bebc-54bc60b4e826 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149241049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1149241049 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.884056478 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 5999214002 ps |
| CPU time | 616.68 seconds |
| Started | Jun 30 08:08:54 PM PDT 24 |
| Finished | Jun 30 08:19:11 PM PDT 24 |
| Peak memory | 643596 kb |
| Host | smart-feadb7b2-039d-42e4-ab03-2b22cea284ec |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 884056478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.884056478 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.980502574 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 3362202920 ps |
| CPU time | 438.52 seconds |
| Started | Jun 30 08:08:50 PM PDT 24 |
| Finished | Jun 30 08:16:09 PM PDT 24 |
| Peak memory | 647084 kb |
| Host | smart-7f633aa3-b566-41ca-a055-ed9d77baccf4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980502574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_s w_alert_handler_lpg_sleep_mode_alerts.980502574 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.3932948587 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 5961074344 ps |
| CPU time | 602.07 seconds |
| Started | Jun 30 08:09:04 PM PDT 24 |
| Finished | Jun 30 08:19:07 PM PDT 24 |
| Peak memory | 647832 kb |
| Host | smart-1eadc997-a7a0-4b0c-914b-2432d5d662bd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3932948587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.3932948587 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.2042567823 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 6493877448 ps |
| CPU time | 757.85 seconds |
| Started | Jun 30 08:08:53 PM PDT 24 |
| Finished | Jun 30 08:21:31 PM PDT 24 |
| Peak memory | 647904 kb |
| Host | smart-80351765-9e10-424f-9097-b359c707994c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2042567823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.2042567823 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3515938087 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 4273810936 ps |
| CPU time | 486.77 seconds |
| Started | Jun 30 08:09:17 PM PDT 24 |
| Finished | Jun 30 08:17:24 PM PDT 24 |
| Peak memory | 646816 kb |
| Host | smart-69bc62f8-1126-4d15-8d02-b818c05f6513 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515938087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3515938087 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.791363276 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 4897146492 ps |
| CPU time | 781.01 seconds |
| Started | Jun 30 08:09:18 PM PDT 24 |
| Finished | Jun 30 08:22:20 PM PDT 24 |
| Peak memory | 643504 kb |
| Host | smart-9be7639c-def9-489e-aacd-129565c43518 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 791363276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.791363276 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.906960428 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3691713728 ps |
| CPU time | 476.5 seconds |
| Started | Jun 30 08:09:22 PM PDT 24 |
| Finished | Jun 30 08:17:19 PM PDT 24 |
| Peak memory | 647160 kb |
| Host | smart-42eb71fb-d632-4250-be8e-ba1b56629d90 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906960428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_s w_alert_handler_lpg_sleep_mode_alerts.906960428 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.4063834294 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 5593187902 ps |
| CPU time | 602.48 seconds |
| Started | Jun 30 08:08:57 PM PDT 24 |
| Finished | Jun 30 08:19:00 PM PDT 24 |
| Peak memory | 643424 kb |
| Host | smart-c2b9f7db-91c6-4d7c-8320-c23ff53a3b87 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4063834294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.4063834294 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.592375352 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3396855720 ps |
| CPU time | 400.26 seconds |
| Started | Jun 30 08:09:41 PM PDT 24 |
| Finished | Jun 30 08:16:22 PM PDT 24 |
| Peak memory | 647016 kb |
| Host | smart-092d1326-2aff-4321-9034-1dfe67d4a436 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592375352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_s w_alert_handler_lpg_sleep_mode_alerts.592375352 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.4207087923 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 4612487548 ps |
| CPU time | 640.1 seconds |
| Started | Jun 30 08:09:14 PM PDT 24 |
| Finished | Jun 30 08:19:54 PM PDT 24 |
| Peak memory | 643800 kb |
| Host | smart-eed45626-1b4b-4d47-9596-5f2519bbb940 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4207087923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.4207087923 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3165213207 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 3202121868 ps |
| CPU time | 411.34 seconds |
| Started | Jun 30 08:09:22 PM PDT 24 |
| Finished | Jun 30 08:16:14 PM PDT 24 |
| Peak memory | 647292 kb |
| Host | smart-3a5ff5df-c36f-4555-ae95-9c6e8d417a00 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165213207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3165213207 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.3959828277 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 4621552808 ps |
| CPU time | 823.91 seconds |
| Started | Jun 30 08:09:54 PM PDT 24 |
| Finished | Jun 30 08:23:38 PM PDT 24 |
| Peak memory | 617252 kb |
| Host | smart-60ba2439-915a-41dc-a04a-955116e65bff |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3959828277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.3959828277 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.786288645 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 3710676144 ps |
| CPU time | 374.06 seconds |
| Started | Jun 30 08:03:38 PM PDT 24 |
| Finished | Jun 30 08:09:53 PM PDT 24 |
| Peak memory | 642244 kb |
| Host | smart-652aad7c-a3cc-4f6e-b98c-7be4e7ac285f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786288645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw _alert_handler_lpg_sleep_mode_alerts.786288645 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2024143158 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 15618153346 ps |
| CPU time | 4637.68 seconds |
| Started | Jun 30 08:03:45 PM PDT 24 |
| Finished | Jun 30 09:21:04 PM PDT 24 |
| Peak memory | 608444 kb |
| Host | smart-5e5bcadf-aae3-4584-baa3-9b6ecc44f716 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024143158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.2024143158 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1491080718 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 12590427463 ps |
| CPU time | 1263.04 seconds |
| Started | Jun 30 08:02:50 PM PDT 24 |
| Finished | Jun 30 08:23:54 PM PDT 24 |
| Peak memory | 619556 kb |
| Host | smart-fd717f7b-ae73-4d80-b8ac-595787256056 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491080718 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.1491080718 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3731917985 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 4095377256 ps |
| CPU time | 596.41 seconds |
| Started | Jun 30 08:00:59 PM PDT 24 |
| Finished | Jun 30 08:10:56 PM PDT 24 |
| Peak memory | 618256 kb |
| Host | smart-c74ee7f8-4782-4fc9-97d4-0b18f5fe5cfd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3731917985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.3731917985 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.2228412737 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 4358702268 ps |
| CPU time | 559.39 seconds |
| Started | Jun 30 08:09:53 PM PDT 24 |
| Finished | Jun 30 08:19:13 PM PDT 24 |
| Peak memory | 648092 kb |
| Host | smart-fe46325f-cc25-46f2-a88e-86523e62861f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2228412737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.2228412737 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1044086949 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 4290979060 ps |
| CPU time | 441.05 seconds |
| Started | Jun 30 08:10:03 PM PDT 24 |
| Finished | Jun 30 08:17:24 PM PDT 24 |
| Peak memory | 647148 kb |
| Host | smart-245da0fc-d816-4353-9b20-5db710afbb45 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044086949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1044086949 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2975425534 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 3106575656 ps |
| CPU time | 382.35 seconds |
| Started | Jun 30 08:10:10 PM PDT 24 |
| Finished | Jun 30 08:16:33 PM PDT 24 |
| Peak memory | 647108 kb |
| Host | smart-c5dcb3b9-e4ec-480b-af0c-6416784eb59c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975425534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2975425534 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.359249300 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 6088259620 ps |
| CPU time | 815.54 seconds |
| Started | Jun 30 08:09:50 PM PDT 24 |
| Finished | Jun 30 08:23:26 PM PDT 24 |
| Peak memory | 643360 kb |
| Host | smart-41b296e0-d86e-4a70-afa1-639731628668 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 359249300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.359249300 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2155543198 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 3376792712 ps |
| CPU time | 353.46 seconds |
| Started | Jun 30 08:09:59 PM PDT 24 |
| Finished | Jun 30 08:15:53 PM PDT 24 |
| Peak memory | 647280 kb |
| Host | smart-dbc7b817-b395-4354-9af6-4ce2fc3164bf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155543198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2155543198 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.629089759 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 5186739042 ps |
| CPU time | 525.35 seconds |
| Started | Jun 30 08:10:38 PM PDT 24 |
| Finished | Jun 30 08:19:24 PM PDT 24 |
| Peak memory | 644328 kb |
| Host | smart-a9ea3e08-e1a1-4c64-bb78-ca55a43abaf1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 629089759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.629089759 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1176930498 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 3502937144 ps |
| CPU time | 380.39 seconds |
| Started | Jun 30 08:10:22 PM PDT 24 |
| Finished | Jun 30 08:16:43 PM PDT 24 |
| Peak memory | 642336 kb |
| Host | smart-53ae1992-04fe-4f01-976a-d4ce1ba62ae5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176930498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1176930498 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.871830269 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 5745284400 ps |
| CPU time | 756.03 seconds |
| Started | Jun 30 08:09:55 PM PDT 24 |
| Finished | Jun 30 08:22:31 PM PDT 24 |
| Peak memory | 643528 kb |
| Host | smart-a50a5e8c-a182-4993-8995-745eab99b808 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 871830269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.871830269 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3321427097 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 4036799470 ps |
| CPU time | 461.74 seconds |
| Started | Jun 30 08:09:54 PM PDT 24 |
| Finished | Jun 30 08:17:37 PM PDT 24 |
| Peak memory | 647012 kb |
| Host | smart-edce2dc8-3959-4105-8281-f127352adf2b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321427097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3321427097 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.2229967059 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 5117092000 ps |
| CPU time | 701.15 seconds |
| Started | Jun 30 08:10:19 PM PDT 24 |
| Finished | Jun 30 08:22:01 PM PDT 24 |
| Peak memory | 643432 kb |
| Host | smart-114f7fa9-59da-426a-a954-3e4a863ce13b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2229967059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.2229967059 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3194797763 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 3088604456 ps |
| CPU time | 366.53 seconds |
| Started | Jun 30 08:10:43 PM PDT 24 |
| Finished | Jun 30 08:16:50 PM PDT 24 |
| Peak memory | 642144 kb |
| Host | smart-84737c59-bb3e-47ee-bc59-c17445f71198 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194797763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3194797763 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.1112335752 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 4671619916 ps |
| CPU time | 636.54 seconds |
| Started | Jun 30 08:09:50 PM PDT 24 |
| Finished | Jun 30 08:20:27 PM PDT 24 |
| Peak memory | 643392 kb |
| Host | smart-5f9ef980-a68d-43e8-9049-4bf0b2c932ea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1112335752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.1112335752 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.752133159 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 6000923410 ps |
| CPU time | 803.19 seconds |
| Started | Jun 30 08:10:15 PM PDT 24 |
| Finished | Jun 30 08:23:39 PM PDT 24 |
| Peak memory | 648280 kb |
| Host | smart-1559d703-301c-4dcd-ab6e-22ad7a65ef3d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 752133159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.752133159 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3251382615 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 3463478384 ps |
| CPU time | 344.92 seconds |
| Started | Jun 30 08:10:48 PM PDT 24 |
| Finished | Jun 30 08:16:35 PM PDT 24 |
| Peak memory | 642272 kb |
| Host | smart-9cb5f706-e445-48f7-bb95-62b4314dc8ef |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251382615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3251382615 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.1292594749 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 5635553178 ps |
| CPU time | 747.47 seconds |
| Started | Jun 30 08:10:05 PM PDT 24 |
| Finished | Jun 30 08:22:33 PM PDT 24 |
| Peak memory | 643520 kb |
| Host | smart-bd7c4527-b5b0-4f9d-8b8b-196dba5ddfc8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1292594749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.1292594749 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.283578546 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 4329173284 ps |
| CPU time | 550.38 seconds |
| Started | Jun 30 08:04:32 PM PDT 24 |
| Finished | Jun 30 08:13:44 PM PDT 24 |
| Peak memory | 647188 kb |
| Host | smart-f31779a3-2f3d-4a7b-803c-774d613ecd55 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283578546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw _alert_handler_lpg_sleep_mode_alerts.283578546 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.1103075259 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 4171214360 ps |
| CPU time | 516.67 seconds |
| Started | Jun 30 08:01:01 PM PDT 24 |
| Finished | Jun 30 08:09:39 PM PDT 24 |
| Peak memory | 647748 kb |
| Host | smart-4ad66aa2-0969-4635-90ab-e90baa080505 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1103075259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.1103075259 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.223199026 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 24776764804 ps |
| CPU time | 5855.74 seconds |
| Started | Jun 30 08:02:45 PM PDT 24 |
| Finished | Jun 30 09:40:22 PM PDT 24 |
| Peak memory | 608380 kb |
| Host | smart-eb1d646d-2f74-4a84-9176-eb6f5b6bef76 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223199026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.223199026 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3970688943 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 5763696113 ps |
| CPU time | 724.1 seconds |
| Started | Jun 30 08:01:52 PM PDT 24 |
| Finished | Jun 30 08:13:57 PM PDT 24 |
| Peak memory | 620264 kb |
| Host | smart-f163c4e2-5a1f-4b61-831f-5186a111de38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970688943 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.3970688943 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1007910720 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 3807535960 ps |
| CPU time | 858 seconds |
| Started | Jun 30 08:04:00 PM PDT 24 |
| Finished | Jun 30 08:18:19 PM PDT 24 |
| Peak memory | 618548 kb |
| Host | smart-3f4df16c-9395-47ee-b475-dc6edd328813 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1007910720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.1007910720 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.1739170188 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 5357689080 ps |
| CPU time | 698.94 seconds |
| Started | Jun 30 08:11:32 PM PDT 24 |
| Finished | Jun 30 08:23:12 PM PDT 24 |
| Peak memory | 643724 kb |
| Host | smart-5332c655-6901-4063-8408-ba0f61862cf9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1739170188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.1739170188 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.2706944541 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 5874597268 ps |
| CPU time | 508.5 seconds |
| Started | Jun 30 08:10:15 PM PDT 24 |
| Finished | Jun 30 08:18:44 PM PDT 24 |
| Peak memory | 644192 kb |
| Host | smart-d0f41bff-9260-44ae-87ee-c6774d03a6c1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2706944541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.2706944541 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.1792200146 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 4257217520 ps |
| CPU time | 486.08 seconds |
| Started | Jun 30 08:10:31 PM PDT 24 |
| Finished | Jun 30 08:18:37 PM PDT 24 |
| Peak memory | 643220 kb |
| Host | smart-9c0d081d-1657-41f7-833a-71e46a8500d4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1792200146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.1792200146 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.2769271526 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 5276038120 ps |
| CPU time | 661.73 seconds |
| Started | Jun 30 08:10:34 PM PDT 24 |
| Finished | Jun 30 08:21:37 PM PDT 24 |
| Peak memory | 643420 kb |
| Host | smart-dfe903df-a134-49e6-b1cf-7ec1b24aef45 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2769271526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.2769271526 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.2322553195 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 4502598530 ps |
| CPU time | 509.3 seconds |
| Started | Jun 30 08:11:19 PM PDT 24 |
| Finished | Jun 30 08:19:49 PM PDT 24 |
| Peak memory | 643360 kb |
| Host | smart-9a1fb00c-4ca4-4170-af6f-f4abf18a5938 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2322553195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.2322553195 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.2419608156 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 4386119178 ps |
| CPU time | 750.77 seconds |
| Started | Jun 30 08:10:55 PM PDT 24 |
| Finished | Jun 30 08:23:26 PM PDT 24 |
| Peak memory | 643740 kb |
| Host | smart-e929b318-23d5-4490-81bd-2fd0762e207a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2419608156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.2419608156 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.3840245946 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 5645348440 ps |
| CPU time | 827.65 seconds |
| Started | Jun 30 08:11:20 PM PDT 24 |
| Finished | Jun 30 08:25:08 PM PDT 24 |
| Peak memory | 643540 kb |
| Host | smart-52de5c98-bf5e-4950-9ef3-3fc14a64d027 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3840245946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.3840245946 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.523784982 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 5213782748 ps |
| CPU time | 783.83 seconds |
| Started | Jun 30 08:11:53 PM PDT 24 |
| Finished | Jun 30 08:24:57 PM PDT 24 |
| Peak memory | 643408 kb |
| Host | smart-86a9eff2-f595-415f-a399-31b18c3fcebd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 523784982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.523784982 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.2746117978 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 6632535324 ps |
| CPU time | 768.08 seconds |
| Started | Jun 30 08:11:37 PM PDT 24 |
| Finished | Jun 30 08:24:26 PM PDT 24 |
| Peak memory | 643536 kb |
| Host | smart-e3da07fc-c32e-42cb-b11c-937cca9648b6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2746117978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.2746117978 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3362211285 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 3805591696 ps |
| CPU time | 218.57 seconds |
| Started | Jun 30 08:30:15 PM PDT 24 |
| Finished | Jun 30 08:33:53 PM PDT 24 |
| Peak memory | 640320 kb |
| Host | smart-c36ec06b-decc-4a16-806a-7d7046fb90f7 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362211285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.3362211285 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3107679361 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4605600006 ps |
| CPU time | 244.45 seconds |
| Started | Jun 30 08:30:13 PM PDT 24 |
| Finished | Jun 30 08:34:18 PM PDT 24 |
| Peak memory | 640472 kb |
| Host | smart-ded9532a-b68a-44c8-8a91-d018758da1a7 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107679361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.3107679361 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1937758927 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 4963055070 ps |
| CPU time | 252.09 seconds |
| Started | Jun 30 08:30:13 PM PDT 24 |
| Finished | Jun 30 08:34:25 PM PDT 24 |
| Peak memory | 641912 kb |
| Host | smart-090fe036-6973-4b06-bd18-761bef5b31c1 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937758927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.1937758927 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1249374038 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 4526661118 ps |
| CPU time | 281.41 seconds |
| Started | Jun 30 08:30:19 PM PDT 24 |
| Finished | Jun 30 08:35:00 PM PDT 24 |
| Peak memory | 653440 kb |
| Host | smart-88cec7e4-d7b1-4565-a260-e35423c00856 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249374038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.1249374038 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.736990278 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3480848812 ps |
| CPU time | 216.68 seconds |
| Started | Jun 30 08:30:17 PM PDT 24 |
| Finished | Jun 30 08:33:54 PM PDT 24 |
| Peak memory | 640332 kb |
| Host | smart-379ef87a-4e25-400b-984c-6e5bfbaf60be |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736990278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 5.chip_padctrl_attributes.736990278 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2676152179 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4968851188 ps |
| CPU time | 253.09 seconds |
| Started | Jun 30 08:30:16 PM PDT 24 |
| Finished | Jun 30 08:34:29 PM PDT 24 |
| Peak memory | 640704 kb |
| Host | smart-bd4812f0-481b-45cb-94c2-73c4ea9f01c0 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676152179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.2676152179 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.555498105 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 6216213680 ps |
| CPU time | 272.73 seconds |
| Started | Jun 30 08:30:17 PM PDT 24 |
| Finished | Jun 30 08:34:50 PM PDT 24 |
| Peak memory | 649468 kb |
| Host | smart-dd83108e-f719-4424-b737-cce432c5930f |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555498105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 8.chip_padctrl_attributes.555498105 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2898827286 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 4897711064 ps |
| CPU time | 286.3 seconds |
| Started | Jun 30 08:30:17 PM PDT 24 |
| Finished | Jun 30 08:35:04 PM PDT 24 |
| Peak memory | 640364 kb |
| Host | smart-9aa3a48b-cd9f-4a1d-9258-aa219ad627ee |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898827286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.2898827286 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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