Unified Coverage Report :: Module :: hmac

Module : hmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.81			84.81

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_hmac	84.81			84.81

---

Module Instance : tb.dut.top_earlgrey.u_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.81			84.81

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.81			84.81

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	90.68		86.81			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : hmac

	Total	Covered	Percent
Totals	33	23	69.70
Total Bits	316	268	84.81
Total Bits 0->1	158	134	84.81
Total Bits 1->0	158	134	84.81

Ports	33	23	69.70
Port Bits	316	268	84.81
Port Bits 0->1	158	134	84.81
Port Bits 1->0	158	134	84.81

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T17,T18	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T18,*T76	Yes	T4,T18,T76	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[7:2]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
tl_i.a_address[11:8]	No	No		No		INPUT
tl_i.a_address[12]	Yes	Yes	*T4,*T76,*T77	Yes	T4,T76,T77	INPUT
tl_i.a_address[15:13]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T18,*T76	Yes	T4,T18,T76	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T4,*T18,*T76	Yes	T4,T18,T76	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T18,*T76	Yes	T4,T18,T76	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T18,*T76	Yes	T4,T18,T76	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[1:0]	Yes	Yes	*T169,*T4,*T18	Yes	T169,T4,T18	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T171,*T172,*T173	Yes	T171,T172,T173	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	INPUT
tl_i.a_valid	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	INPUT
tl_o.a_ready	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T4,*T18,T76	Yes	T4,T18,T76	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T169,*T4,*T18	Yes	T169,T4,T18	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T76,*T77	Yes	T4,T76,T77	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T165,T241,T33	Yes	T165,T241,T33	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T33,T242,T243	Yes	T33,T242,T243	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T33,T242,T243	Yes	T33,T242,T243	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T165,T241,T33	Yes	T165,T241,T33	OUTPUT
intr_hmac_done_o	Yes	Yes	T171,T172,T173	Yes	T171,T172,T173	OUTPUT
intr_fifo_empty_o	Yes	Yes	T225,T226,T227	Yes	T225,T226,T227	OUTPUT
intr_hmac_err_o	Yes	Yes	T225,T226,T227	Yes	T225,T226,T227	OUTPUT
idle_o[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T17,T18	OUTPUT

*Tests covering at least one bit in the range