| | | | | | | | |
| clk_ctrl_and_main_pd_sva_if |
100.00 |
|
|
100.00 |
|
|
|
| u_adc_ctrl_aon |
89.81 |
|
|
89.81 |
|
|
|
| u_aes |
96.62 |
|
|
96.62 |
|
|
|
| u_alert_handler |
97.21 |
|
|
97.21 |
|
|
|
| u_aon_timer_aon |
90.13 |
|
|
90.13 |
|
|
|
| u_clkmgr_aon |
94.77 |
|
|
94.77 |
|
|
|
| u_csrng |
96.93 |
|
|
96.93 |
|
|
|
| u_dft_tap_breakout |
100.00 |
100.00 |
|
100.00 |
|
|
|
| u_edn0 |
95.53 |
|
|
95.53 |
|
|
|
u_edn1 |
92.86 |
|
|
92.86 |
|
|
|
| u_entropy_src |
89.56 |
|
|
89.56 |
|
|
|
| u_flash_ctrl |
95.07 |
|
|
95.07 |
|
|
|
| u_gpio |
94.44 |
|
|
94.44 |
|
|
|
| u_hmac |
84.81 |
|
|
84.81 |
|
|
|
| u_i2c0 |
84.48 |
|
|
84.48 |
|
|
|
| u_i2c1 |
84.57 |
|
|
84.57 |
|
|
|
| u_i2c2 |
84.57 |
|
|
84.57 |
|
|
|
| u_keymgr |
89.29 |
|
|
89.29 |
|
|
|
| u_kmac |
99.29 |
|
|
99.29 |
|
|
|
| u_lc_ctrl |
92.66 |
|
|
92.66 |
|
|
|
| u_otbn |
98.03 |
|
|
98.03 |
|
|
|
| u_otp_ctrl |
84.60 |
|
|
84.60 |
|
|
|
| u_pattgen |
90.00 |
|
|
90.00 |
|
|
|
| u_pinmux_aon |
84.00 |
88.48 |
75.13 |
97.99 |
|
90.67 |
67.72 |
| gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| gen_wkup_detect[0].u_pinmux_wkup |
69.87 |
77.78 |
68.18 |
|
|
63.64 |
|
| u_prim_filter |
93.27 |
100.00 |
88.89 |
|
|
90.91 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[1].u_pinmux_wkup |
56.14 |
63.89 |
40.91 |
|
|
63.64 |
|
| u_prim_filter |
67.58 |
76.47 |
44.44 |
|
|
81.82 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[2].u_pinmux_wkup |
45.45 |
50.00 |
31.82 |
|
|
54.55 |
|
| u_prim_filter |
67.58 |
76.47 |
44.44 |
|
|
81.82 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[3].u_pinmux_wkup |
45.45 |
50.00 |
31.82 |
|
|
54.55 |
|
| u_prim_filter |
67.58 |
76.47 |
44.44 |
|
|
81.82 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[4].u_pinmux_wkup |
69.87 |
77.78 |
63.64 |
|
|
68.18 |
|
| u_prim_filter |
93.27 |
100.00 |
88.89 |
|
|
90.91 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[5].u_pinmux_wkup |
71.38 |
77.78 |
68.18 |
|
|
68.18 |
|
| u_prim_filter |
93.27 |
100.00 |
88.89 |
|
|
90.91 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[6].u_pinmux_wkup |
45.45 |
50.00 |
31.82 |
|
|
54.55 |
|
| u_prim_filter |
67.58 |
76.47 |
44.44 |
|
|
81.82 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[7].u_pinmux_wkup |
68.35 |
77.78 |
63.64 |
|
|
63.64 |
|
| u_prim_filter |
93.27 |
100.00 |
88.89 |
|
|
90.91 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_pinmux_strap_sampling |
98.82 |
99.62 |
95.65 |
|
|
100.00 |
100.00 |
| subtree... |
|
|
|
|
|
|
|
| u_reg |
78.60 |
87.75 |
74.48 |
|
|
94.23 |
57.94 |
| subtree... |
|
|
|
|
|
|
|
| u_usbdev_aon_wake |
98.43 |
100.00 |
95.59 |
|
|
98.11 |
100.00 |
| filter_activity |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| filter_bus_reset |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| filter_sense |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_pullup_en_cdc |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_pwm_aon |
88.89 |
|
|
88.89 |
|
|
|
| u_pwrmgr_aon |
92.64 |
|
|
92.64 |
|
|
|
| u_rom_ctrl |
94.62 |
|
|
94.62 |
|
|
|
| u_rstmgr_aon |
91.79 |
|
|
91.79 |
|
|
|
| u_rv_core_ibex |
88.99 |
94.18 |
75.50 |
89.86 |
|
93.28 |
92.14 |
| subtree... |
|
|
|
|
|
|
|
| u_rv_dm |
64.39 |
|
|
64.39 |
|
|
|
| u_rv_plic |
91.54 |
93.92 |
83.67 |
91.08 |
|
92.60 |
96.43 |
| gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| gen_target[0].u_target |
91.59 |
89.34 |
77.00 |
|
|
100.00 |
100.00 |
| u_prim_max_tree |
91.56 |
89.27 |
76.97 |
|
|
100.00 |
100.00 |
| u_gateway |
75.00 |
100.00 |
25.00 |
|
|
100.00 |
|
| u_prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_reg |
93.03 |
94.26 |
87.90 |
|
|
89.97 |
100.00 |
| subtree... |
|
|
|
|
|
|
|
| u_rv_timer |
89.73 |
|
|
89.73 |
|
|
|
| u_sensor_ctrl_aon |
90.72 |
93.15 |
86.56 |
78.52 |
|
95.36 |
100.00 |
| gen_alert_sync_assign[0].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[10].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[1].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[2].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[3].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[4].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[5].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[6].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[7].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[8].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[9].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| u_alert_n_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_alert_p_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_init_chg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| g_sync.u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_init_intr |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_io_intr |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_io_status_chg |
100.00 |
100.00 |
|
|
|
100.00 |
|
| g_sync.u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_prim_sec_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| u_reg |
93.42 |
92.68 |
86.00 |
|
|
95.02 |
100.00 |
| subtree... |
|
|
|
|
|
|
|
| u_wake_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_spi_device |
88.66 |
|
|
88.66 |
|
|
|
| u_spi_host0 |
84.66 |
|
|
84.66 |
|
|
|
| u_spi_host1 |
82.72 |
|
|
82.72 |
|
|
|
| u_sram_ctrl_main |
93.84 |
|
|
93.84 |
|
|
|
| u_sram_ctrl_ret_aon |
94.56 |
|
|
94.56 |
|
|
|
| u_sysrst_ctrl_aon |
91.02 |
|
|
91.02 |
|
|
|
| u_uart0 |
90.13 |
|
|
90.13 |
|
|
|
| u_uart1 |
90.20 |
|
|
90.20 |
|
|
|
| u_uart2 |
90.20 |
|
|
90.20 |
|
|
|
| u_uart3 |
90.26 |
|
|
90.26 |
|
|
|
| u_usbdev |
83.82 |
|
|
83.82 |
|
|
|
| u_xbar_main |
80.83 |
|
|
80.83 |
|
|
|
| u_xbar_peri |
89.94 |
|
|
89.94 |
|
|
|