Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : i2c
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.66 84.66

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_i2c0 84.48 84.48
tb.dut.top_earlgrey.u_i2c1 84.57 84.57
tb.dut.top_earlgrey.u_i2c2 84.57 84.57



Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.48 84.48


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.48 84.48


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.50 90.68 86.81 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.57 84.57


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.57 84.57


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.50 90.68 86.81 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.57 84.57


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.57 84.57


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.50 90.68 86.81 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : i2c
TotalCoveredPercent
Totals 54 40 74.07
Total Bits 352 298 84.66
Total Bits 0->1 176 149 84.66
Total Bits 1->0 176 149 84.66

Ports 54 40 74.07
Port Bits 352 298 84.66
Port Bits 0->1 176 149 84.66
Port Bits 1->0 176 149 84.66

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T228,T152,T225 Yes T228,T152,T225 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T228,T152,T225 Yes T228,T152,T225 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_address[18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T23,*T24,*T81 Yes T23,T24,T81 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T60,T61,T62 Yes T60,T61,T62 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T23,*T24,*T28 Yes T23,T24,T28 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_valid Yes Yes T228,T152,T166 Yes T228,T152,T166 INPUT
tl_o.a_ready Yes Yes T228,T152,T166 Yes T228,T152,T166 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T228,T225,T229 Yes T228,T225,T229 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T228,T152,T166 Yes T228,T152,T166 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T152,*T166,*T230 Yes T228,T152,T166 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T228,T152,T166 Yes T228,T152,T166 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T169,*T228,*T152 Yes T169,T228,T152 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T152,T166,T230 Yes T228,T152,T166 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T228,*T152,*T225 Yes T228,T152,T225 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T228,T152,T166 Yes T228,T152,T166 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T153,T231,T166 Yes T153,T231,T166 INPUT
alert_rx_i[0].ping_n Yes Yes T153,T232,T154 Yes T153,T154,T131 INPUT
alert_rx_i[0].ping_p Yes Yes T153,T154,T131 Yes T153,T232,T154 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T153,T231,T166 Yes T153,T231,T166 OUTPUT
cio_scl_i Yes Yes T228,T229,T233 Yes T228,T229,T233 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T229,T233,T234 Yes T229,T233,T234 OUTPUT
cio_sda_i Yes Yes T228,T229,T233 Yes T228,T229,T233 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T228,T229,T233 Yes T228,T229,T233 OUTPUT
intr_fmt_threshold_o Yes Yes T225,T229,T233 Yes T225,T229,T233 OUTPUT
intr_rx_threshold_o Yes Yes T225,T229,T233 Yes T225,T229,T233 OUTPUT
intr_acq_threshold_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_rx_overflow_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_controller_halt_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_scl_interference_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_sda_interference_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_stretch_timeout_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_sda_unstable_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_cmd_complete_o Yes Yes T228,T225,T229 Yes T228,T225,T229 OUTPUT
intr_tx_stretch_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_tx_threshold_o Yes Yes T225,T226,T169 Yes T225,T226,T169 OUTPUT
intr_acq_stretch_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_unexp_stop_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_host_timeout_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0
TotalCoveredPercent
Totals 54 40 74.07
Total Bits 348 294 84.48
Total Bits 0->1 174 147 84.48
Total Bits 1->0 174 147 84.48

Ports 54 40 74.07
Port Bits 348 294 84.48
Port Bits 0->1 174 147 84.48
Port Bits 1->0 174 147 84.48

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T152,T225,T233 Yes T152,T225,T233 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T152,T225,T233 Yes T152,T225,T233 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T23,*T24,*T81 Yes T23,T24,T81 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T60,T61,T62 Yes T60,T61,T62 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T23,*T24,*T28 Yes T23,T24,T28 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_valid Yes Yes T152,T166,T225 Yes T152,T166,T225 INPUT
tl_o.a_ready Yes Yes T152,T166,T225 Yes T152,T166,T225 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T225,T233,T234 Yes T225,T233,T234 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T152,T166,T225 Yes T152,T166,T225 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T152,*T166,*T230 Yes T152,T166,T225 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T152,T166,T225 Yes T152,T166,T225 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T169,*T152,*T225 Yes T169,T152,T225 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T152,T166,T230 Yes T152,T166,T225 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T152,*T225,*T233 Yes T152,T225,T233 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T152,T166,T225 Yes T152,T166,T225 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T153,T166,T235 Yes T153,T166,T235 INPUT
alert_rx_i[0].ping_n Yes Yes T153,T154,T33 Yes T153,T154,T33 INPUT
alert_rx_i[0].ping_p Yes Yes T153,T154,T33 Yes T153,T154,T33 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T153,T166,T235 Yes T153,T166,T235 OUTPUT
cio_scl_i Yes Yes T233,T234,T236 Yes T233,T234,T236 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T233,T234,T236 Yes T233,T234,T236 OUTPUT
cio_sda_i Yes Yes T233,T234,T236 Yes T233,T234,T236 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T233,T234,T236 Yes T233,T234,T236 OUTPUT
intr_fmt_threshold_o Yes Yes T225,T233,T234 Yes T225,T233,T234 OUTPUT
intr_rx_threshold_o Yes Yes T225,T233,T234 Yes T225,T233,T234 OUTPUT
intr_acq_threshold_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_rx_overflow_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_controller_halt_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_scl_interference_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_sda_interference_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_stretch_timeout_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_sda_unstable_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_cmd_complete_o Yes Yes T225,T233,T234 Yes T225,T233,T234 OUTPUT
intr_tx_stretch_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_tx_threshold_o Yes Yes T225,T226,T169 Yes T225,T226,T169 OUTPUT
intr_acq_stretch_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_unexp_stop_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_host_timeout_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1
TotalCoveredPercent
Totals 54 40 74.07
Total Bits 350 296 84.57
Total Bits 0->1 175 148 84.57
Total Bits 1->0 175 148 84.57

Ports 54 40 74.07
Port Bits 350 296 84.57
Port Bits 0->1 175 148 84.57
Port Bits 1->0 175 148 84.57

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T228,T152,T225 Yes T228,T152,T225 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T228,T152,T225 Yes T228,T152,T225 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_address[18:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T23,*T24,*T81 Yes T23,T24,T81 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T60,T61,T62 Yes T60,T61,T62 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T23,*T24,*T28 Yes T23,T24,T28 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_valid Yes Yes T228,T152,T166 Yes T228,T152,T166 INPUT
tl_o.a_ready Yes Yes T228,T152,T166 Yes T228,T152,T166 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T228,T225,T229 Yes T228,T225,T229 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T228,T152,T166 Yes T228,T152,T166 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T152,*T166,*T230 Yes T228,T152,T166 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T228,T152,T166 Yes T228,T152,T166 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T169,*T228,*T152 Yes T169,T228,T152 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T152,T166,T230 Yes T228,T152,T166 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T228,*T152,*T225 Yes T228,T152,T225 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T228,T152,T166 Yes T228,T152,T166 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T153,T166,T154 Yes T153,T166,T154 INPUT
alert_rx_i[0].ping_n Yes Yes T153,T154,T33 Yes T153,T154,T33 INPUT
alert_rx_i[0].ping_p Yes Yes T153,T154,T33 Yes T153,T154,T33 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T153,T166,T154 Yes T153,T166,T154 OUTPUT
cio_scl_i Yes Yes T228,T229,T237 Yes T228,T229,T237 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T229,T237,T169 Yes T229,T237,T169 OUTPUT
cio_sda_i Yes Yes T228,T229,T237 Yes T228,T229,T237 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T228,T229,T237 Yes T228,T229,T237 OUTPUT
intr_fmt_threshold_o Yes Yes T225,T229,T226 Yes T225,T229,T226 OUTPUT
intr_rx_threshold_o Yes Yes T225,T229,T226 Yes T225,T229,T226 OUTPUT
intr_acq_threshold_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_rx_overflow_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_controller_halt_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_scl_interference_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_sda_interference_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_stretch_timeout_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_sda_unstable_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_cmd_complete_o Yes Yes T228,T225,T229 Yes T228,T225,T229 OUTPUT
intr_tx_stretch_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_tx_threshold_o Yes Yes T225,T226,T169 Yes T225,T226,T169 OUTPUT
intr_acq_stretch_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_unexp_stop_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_host_timeout_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2
TotalCoveredPercent
Totals 54 40 74.07
Total Bits 350 296 84.57
Total Bits 0->1 175 148 84.57
Total Bits 1->0 175 148 84.57

Ports 54 40 74.07
Port Bits 350 296 84.57
Port Bits 0->1 175 148 84.57
Port Bits 1->0 175 148 84.57

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T152,T225,T226 Yes T152,T225,T226 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T152,T225,T226 Yes T152,T225,T226 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_address[16:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_address[18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T23,*T24,*T81 Yes T23,T24,T81 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T60,T61,T62 Yes T60,T61,T62 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T23,*T24,*T28 Yes T23,T24,T28 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_valid Yes Yes T152,T166,T225 Yes T152,T166,T225 INPUT
tl_o.a_ready Yes Yes T152,T166,T225 Yes T152,T166,T225 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T225,T226,T238 Yes T225,T226,T238 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T152,T166,T225 Yes T152,T166,T225 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T152,*T166,*T230 Yes T152,T166,T225 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T152,T166,T225 Yes T152,T166,T225 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T169,*T152,*T225 Yes T169,T152,T225 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T152,T166,T230 Yes T152,T166,T225 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T152,*T225,*T226 Yes T152,T225,T226 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T152,T166,T225 Yes T152,T166,T225 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T153,T231,T166 Yes T153,T231,T166 INPUT
alert_rx_i[0].ping_n Yes Yes T153,T232,T154 Yes T153,T154,T131 INPUT
alert_rx_i[0].ping_p Yes Yes T153,T154,T131 Yes T153,T232,T154 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T153,T231,T166 Yes T153,T231,T166 OUTPUT
cio_scl_i Yes Yes T238,T239,T240 Yes T238,T239,T240 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T238,T239,T169 Yes T238,T239,T169 OUTPUT
cio_sda_i Yes Yes T238,T239,T240 Yes T238,T239,T240 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T238,T239,T169 Yes T238,T239,T169 OUTPUT
intr_fmt_threshold_o Yes Yes T225,T226,T238 Yes T225,T226,T238 OUTPUT
intr_rx_threshold_o Yes Yes T225,T226,T238 Yes T225,T226,T238 OUTPUT
intr_acq_threshold_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_rx_overflow_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_controller_halt_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_scl_interference_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_sda_interference_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_stretch_timeout_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_sda_unstable_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_cmd_complete_o Yes Yes T225,T226,T238 Yes T225,T226,T238 OUTPUT
intr_tx_stretch_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_tx_threshold_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_acq_stretch_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_unexp_stop_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT
intr_host_timeout_o Yes Yes T225,T226,T227 Yes T225,T226,T227 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%