Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : spi_host
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.36 84.36

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_host_1.0/rtl/spi_host.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_spi_host1 82.72 82.72
tb.dut.top_earlgrey.u_spi_host0 84.66 84.66



Module Instance : tb.dut.top_earlgrey.u_spi_host1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.72 82.72


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.72 82.72


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.50 90.68 86.81 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_spi_host0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.66 84.66


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.66 84.66


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.50 90.68 86.81 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : spi_host
TotalCoveredPercent
Totals 46 32 69.57
Total Bits 358 302 84.36
Total Bits 0->1 179 151 84.36
Total Bits 1->0 179 151 84.36

Ports 46 32 69.57
Port Bits 358 302 84.36
Port Bits 0->1 179 151 84.36
Port Bits 1->0 179 151 84.36

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T152,*T166,*T157 Yes T152,T166,T157 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_i.a_mask[3:0] Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[5:2] Yes Yes *T152,*T166,*T157 Yes T152,T166,T157 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T152,*T157,*T167 Yes T152,T157,T167 INPUT
tl_i.a_address[19:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[21:20] Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_i.a_address[29:22] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T152,*T166,*T157 Yes T152,T166,T157 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[1:0] Yes Yes *T28,*T152,*T157 Yes T28,T152,T157 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T42,*T43,*T156 Yes T42,T43,T156 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T152,T157,T42 Yes T152,T157,T42 INPUT
tl_i.a_valid Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_o.a_ready Yes Yes T152,T166,T157 Yes T152,T166,T157 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T152,T157,T42 Yes T152,T157,T42 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T152,T166,T157 Yes T152,T166,T157 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T152,*T166,T42 Yes T152,T166,T157 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T152,T157,T42 Yes T152,T157,T42 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T28,*T152,*T157 Yes T28,T152,T157 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T152,T166,T42 Yes T152,T166,T157 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T152,*T157,*T42 Yes T152,T157,T42 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T152,T166,T157 Yes T152,T166,T157 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T153,T166,T154 Yes T153,T166,T154 INPUT
alert_rx_i[0].ping_n Yes Yes T153,T154,T131 Yes T153,T154,T131 INPUT
alert_rx_i[0].ping_p Yes Yes T153,T154,T131 Yes T153,T154,T131 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T153,T166,T154 Yes T153,T166,T154 OUTPUT
cio_sck_o Yes Yes T42,T43,T44 Yes T42,T43,T44 OUTPUT
cio_sck_en_o Yes Yes T42,T43,T155 Yes T42,T43,T44 OUTPUT
cio_csb_o Yes Yes T42,T43,T44 Yes T42,T43,T44 OUTPUT
cio_csb_en_o Yes Yes T42,T43,T155 Yes T42,T43,T44 OUTPUT
cio_sd_o[3:0] Yes Yes T42,T43,T44 Yes T42,T43,T44 OUTPUT
cio_sd_en_o[0] Yes Yes *T42,*T43,*T44 Yes T42,T43,T44 OUTPUT
cio_sd_en_o[3:1] No No No OUTPUT
cio_sd_i[3:0] Yes Yes T42,T43,T44 Yes T42,T43,T44 INPUT
passthrough_i.s_en[0] Yes Yes *T42,*T43,*T155 Yes T42,T43,T155 INPUT
passthrough_i.s_en[3:1] No No No INPUT
passthrough_i.s[3:0] Yes Yes T38,T83,T81 Yes T38,T83,T81 INPUT
passthrough_i.csb_en No No No INPUT
passthrough_i.csb Yes Yes T38,T83,T81 Yes T38,T83,T81 INPUT
passthrough_i.sck_en No No No INPUT
passthrough_i.sck Yes Yes T38,T83,T81 Yes T38,T83,T81 INPUT
passthrough_i.passthrough_en Yes Yes T42,T43,T156 Yes T42,T43,T155 INPUT
passthrough_o.s[3:0] Yes Yes T42,T43,T44 Yes T42,T43,T44 OUTPUT
intr_error_o Yes Yes T157,T158,T159 Yes T157,T158,T159 OUTPUT
intr_spi_event_o Yes Yes T157,T158,T159 Yes T157,T158,T159 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host1
TotalCoveredPercent
Totals 38 24 63.16
Total Bits 324 268 82.72
Total Bits 0->1 162 135 83.33
Total Bits 1->0 162 133 82.10

Ports 38 24 63.16
Port Bits 324 268 82.72
Port Bits 0->1 162 135 83.33
Port Bits 1->0 162 133 82.10

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T152,T157,T167 Yes T152,T157,T167 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T152,T157,T28 Yes T152,T157,T28 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T152,T157,T167 Yes T152,T157,T167 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T152,*T157,*T167 Yes T152,T157,T167 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T152,T157,T167 Yes T152,T157,T167 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T152,T157,T28 Yes T152,T157,T28 INPUT
tl_i.a_mask[3:0] Yes Yes T152,T157,T167 Yes T152,T157,T167 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[5:2] Yes Yes *T152,*T157,*T167 Yes T152,T157,T167 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T152,*T157,*T167 Yes T152,T157,T167 INPUT
tl_i.a_address[19:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[21:20] Yes Yes T152,T157,T167 Yes T152,T157,T167 INPUT
tl_i.a_address[29:22] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T152,*T157,*T167 Yes T152,T157,T167 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[1:0] Yes Yes *T28,*T152,*T157 Yes T28,T152,T157 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T152,T157,T167 Yes T152,T157,T167 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T152,T157,T167 Yes T152,T157,T167 INPUT
tl_i.a_valid Yes Yes T152,T157,T167 Yes T152,T157,T167 INPUT
tl_o.a_ready Yes Yes T152,T157,T167 Yes T152,T157,T167 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T152,T157,T28 Yes T152,T157,T28 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T152,T157,T167 Yes T152,T157,T167 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T152,T167,T28 Yes T152,T157,T167 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T152,T157,T28 Yes T152,T157,T28 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T28,*T152,*T157 Yes T28,T152,T157 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T152,T167,T28 Yes T152,T157,T167 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T152,*T157,*T167 Yes T152,T157,T167 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T152,T157,T167 Yes T152,T157,T167 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T153,T154,T33 Yes T153,T154,T33 INPUT
alert_rx_i[0].ping_n Yes Yes T153,T154,T33 Yes T153,T154,T33 INPUT
alert_rx_i[0].ping_p Yes Yes T153,T154,T33 Yes T153,T154,T33 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T153,T154,T33 Yes T153,T154,T33 OUTPUT
cio_sck_o Yes Yes T65,T66 Yes T65,T66 OUTPUT
cio_sck_en_o No No Yes T65,T66 OUTPUT
cio_csb_o Yes Yes T65,T66 Yes T65,T66 OUTPUT
cio_csb_en_o No No Yes T65,T66 OUTPUT
cio_sd_o[0] Yes Yes *T65,*T66 Yes T65,T66 OUTPUT
cio_sd_o[3:1] No No No OUTPUT
cio_sd_en_o[0] Yes Yes *T65,*T66 Yes T65,T66 OUTPUT
cio_sd_en_o[3:1] No No No OUTPUT
cio_sd_i[3:0] Yes Yes T65,T66,T60 Yes T44,T65,T66 INPUT
passthrough_i.s_en[3:0] Unreachable Unreachable Unreachable INPUT
passthrough_i.s[3:0] Unreachable Unreachable Unreachable INPUT
passthrough_i.csb_en Unreachable Unreachable Unreachable INPUT
passthrough_i.csb Unreachable Unreachable Unreachable INPUT
passthrough_i.sck_en Unreachable Unreachable Unreachable INPUT
passthrough_i.sck Unreachable Unreachable Unreachable INPUT
passthrough_i.passthrough_en Unreachable Unreachable Unreachable INPUT
passthrough_o.s[3:0] Unreachable Unreachable Unreachable OUTPUT
intr_error_o Yes Yes T157,T158,T159 Yes T157,T158,T159 OUTPUT
intr_spi_event_o Yes Yes T157,T158,T159 Yes T157,T158,T159 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host0
TotalCoveredPercent
Totals 44 31 70.45
Total Bits 352 298 84.66
Total Bits 0->1 176 149 84.66
Total Bits 1->0 176 149 84.66

Ports 44 31 70.45
Port Bits 352 298 84.66
Port Bits 0->1 176 149 84.66
Port Bits 1->0 176 149 84.66

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T152,*T166,*T157 Yes T152,T166,T157 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T152,*T166,*T157 Yes T152,T166,T157 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_i.a_mask[3:0] Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[5:2] Yes Yes *T152,*T166,*T157 Yes T152,T166,T157 INPUT
tl_i.a_address[19:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[21:20] Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_i.a_address[29:22] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T152,*T166,*T157 Yes T152,T166,T157 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[1:0] Yes Yes *T28,*T152,*T157 Yes T28,T152,T157 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T42,*T43,*T156 Yes T42,T43,T156 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T152,T157,T42 Yes T152,T157,T42 INPUT
tl_i.a_valid Yes Yes T152,T166,T157 Yes T152,T166,T157 INPUT
tl_o.a_ready Yes Yes T152,T166,T157 Yes T152,T166,T157 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T152,T157,T42 Yes T152,T157,T42 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T152,T166,T157 Yes T152,T166,T157 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T152,*T166,T42 Yes T152,T166,T157 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T152,T157,T42 Yes T152,T157,T42 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T28,*T152,*T42 Yes T28,T152,T157 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T152,T166,T42 Yes T152,T166,T157 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T152,*T157,*T42 Yes T152,T157,T42 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T152,T166,T157 Yes T152,T166,T157 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T153,T166,T154 Yes T153,T166,T154 INPUT
alert_rx_i[0].ping_n Yes Yes T153,T154,T131 Yes T153,T154,T131 INPUT
alert_rx_i[0].ping_p Yes Yes T153,T154,T131 Yes T153,T154,T131 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T153,T166,T154 Yes T153,T166,T154 OUTPUT
cio_sck_o Yes Yes T42,T43,T44 Yes T42,T43,T44 OUTPUT
cio_sck_en_o Yes Yes T42,T43,T155 Yes T42,T43,T44 OUTPUT
cio_csb_o Yes Yes T42,T43,T44 Yes T42,T43,T44 OUTPUT
cio_csb_en_o Yes Yes T42,T43,T155 Yes T42,T43,T44 OUTPUT
cio_sd_o[3:0] Yes Yes T42,T43,T44 Yes T42,T43,T44 OUTPUT
cio_sd_en_o[0] Yes Yes *T42,*T43,*T44 Yes T42,T43,T44 OUTPUT
cio_sd_en_o[3:1] No No No OUTPUT
cio_sd_i[3:0] Yes Yes T42,T43,T44 Yes T42,T43,T44 INPUT
passthrough_i.s_en[0] Yes Yes *T42,*T43,*T155 Yes T42,T43,T155 INPUT
passthrough_i.s_en[3:1] No No No INPUT
passthrough_i.s[3:0] Yes Yes T38,T83,T81 Yes T38,T83,T81 INPUT
passthrough_i.csb_en[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off.
passthrough_i.csb Yes Yes T38,T83,T81 Yes T38,T83,T81 INPUT
passthrough_i.sck_en[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off.
passthrough_i.sck Yes Yes T38,T83,T81 Yes T38,T83,T81 INPUT
passthrough_i.passthrough_en Yes Yes T42,T43,T156 Yes T42,T43,T155 INPUT
passthrough_o.s[3:0] Yes Yes T42,T43,T44 Yes T42,T43,T44 OUTPUT
intr_error_o Yes Yes T157,T158,T159 Yes T157,T158,T159 OUTPUT
intr_spi_event_o Yes Yes T157,T158,T159 Yes T157,T158,T159 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%