Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : gpio
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 94.44

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_gpio 94.44 94.44



Module Instance : tb.dut.top_earlgrey.u_gpio

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 94.44


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 94.44


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.50 90.68 86.81 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : gpio
TotalCoveredPercent
Totals 33 25 75.76
Total Bits 540 510 94.44
Total Bits 0->1 270 255 94.44
Total Bits 1->0 270 255 94.44

Ports 33 25 75.76
Port Bits 540 510 94.44
Port Bits 0->1 270 255 94.44
Port Bits 1->0 270 255 94.44

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T17,T18,T19 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[5:2] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_address[17:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_address[29:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T6,*T20 Yes T4,T6,T20 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T23,*T24,*T81 Yes T23,T24,T81 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T60,T61,T62 Yes T60,T61,T62 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T23,*T24,*T28 Yes T23,T24,T28 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_i.a_valid Yes Yes T4,T6,T20 Yes T4,T6,T20 INPUT
tl_o.a_ready Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T46,T225,T56 Yes T46,T225,T56 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T46,T225,T56 Yes T46,T225,T56 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T17,T18,T19 Yes T4,T6,T20 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T46,T225,T56 Yes T46,T225,T56 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T169,*T17,*T18 Yes T169,T6,T20 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T17,T18,T19 Yes T4,T6,T20 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T17,*T18,*T19 Yes T4,T6,T20 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T6,T20 Yes T4,T6,T20 OUTPUT
intr_gpio_o[31:0] Yes Yes T225,T56,T226 Yes T225,T56,T226 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T405,T406,T33 Yes T405,T406,T33 INPUT
alert_rx_i[0].ping_n Yes Yes T33,T34,T35 Yes T33,T34,T35 INPUT
alert_rx_i[0].ping_p Yes Yes T33,T34,T35 Yes T33,T34,T35 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T405,T406,T33 Yes T405,T406,T33 OUTPUT
cio_gpio_i[31:0] Yes Yes T46,T56,T57 Yes T46,T56,T57 INPUT
cio_gpio_o[31:0] Yes Yes T46,T56,T57 Yes T46,T56,T57 OUTPUT
cio_gpio_en_o[31:0] Yes Yes T56,T58,T59 Yes T46,T56,T57 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%