Toggle Coverage for Module :
pwm
| Total | Covered | Percent |
Totals |
32 |
24 |
75.00 |
Total Bits |
306 |
272 |
88.89 |
Total Bits 0->1 |
153 |
137 |
89.54 |
Total Bits 1->0 |
153 |
135 |
88.24 |
| | | |
Ports |
32 |
24 |
75.00 |
Port Bits |
306 |
272 |
88.89 |
Port Bits 0->1 |
153 |
137 |
89.54 |
Port Bits 1->0 |
153 |
135 |
88.24 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T17,T18,T19 |
Yes |
T4,T5,T6 |
INPUT |
clk_core_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_core_ni |
Yes |
Yes |
T17,T18,T19 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T6,T20 |
Yes |
T4,T6,T20 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T313,T314,T100 |
Yes |
T313,T314,T100 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T6,T20 |
Yes |
T4,T6,T20 |
INPUT |
tl_i.a_user.instr_type[0] |
Yes |
Yes |
*T4,*T6,*T20 |
Yes |
T4,T6,T20 |
INPUT |
tl_i.a_user.instr_type[2:1] |
No |
No |
|
No |
|
INPUT |
tl_i.a_user.instr_type[3] |
Yes |
Yes |
T4,T6,T20 |
Yes |
T4,T6,T20 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T313,T314,T100 |
Yes |
T313,T314,T100 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T6,T20 |
Yes |
T4,T6,T20 |
INPUT |
tl_i.a_address[1:0] |
No |
No |
|
No |
|
INPUT |
tl_i.a_address[6:2] |
Yes |
Yes |
T4,T6,T20 |
Yes |
T4,T6,T20 |
INPUT |
tl_i.a_address[15:7] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[16] |
Yes |
Yes |
*T4,*T6,*T20 |
Yes |
T4,T6,T20 |
INPUT |
tl_i.a_address[17] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[18] |
Yes |
Yes |
*T4,*T6,*T20 |
Yes |
T4,T6,T20 |
INPUT |
tl_i.a_address[21:19] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[22] |
Yes |
Yes |
*T4,*T6,*T20 |
Yes |
T4,T6,T20 |
INPUT |
tl_i.a_address[29:23] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T6,*T20 |
Yes |
T4,T6,T20 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T23,*T24,*T81 |
Yes |
T23,T24,T81 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T60,T61,T62 |
Yes |
T60,T61,T62 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[0] |
Yes |
Yes |
*T23,*T24,*T28 |
Yes |
T23,T24,T28 |
INPUT |
tl_i.a_opcode[1] |
No |
No |
|
No |
|
INPUT |
tl_i.a_opcode[2] |
Yes |
Yes |
T4,T6,T20 |
Yes |
T4,T6,T20 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T313,T314,T123 |
Yes |
T313,T314,T123 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T313,T314,T123 |
Yes |
T313,T314,T123 |
OUTPUT |
tl_o.d_error |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T313,T314,T100 |
Yes |
T313,T314,T100 |
OUTPUT |
tl_o.d_user.rsp_intg[1:0] |
Yes |
Yes |
T313,T314,T100 |
Yes |
T313,T314,T123 |
OUTPUT |
tl_o.d_user.rsp_intg[3:2] |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_user.rsp_intg[4] |
No |
No |
|
Yes |
T313,T314,T123 |
OUTPUT |
tl_o.d_user.rsp_intg[5] |
Yes |
Yes |
*T313,*T314,*T100 |
Yes |
T313,T314,T100 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T313,T314,T100 |
Yes |
T313,T314,T123 |
OUTPUT |
tl_o.d_sink |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_source[0] |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_source[1] |
Yes |
Yes |
*T313,*T314,*T100 |
Yes |
T313,T314,T123 |
OUTPUT |
tl_o.d_source[5:2] |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[0] |
No |
No |
|
No |
|
OUTPUT |
tl_o.d_size[1] |
No |
No |
|
Yes |
T313,T314,T123 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T313,*T314,*T100 |
Yes |
T313,T314,T100 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T313,T314,T123 |
Yes |
T313,T314,T123 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T131,T33,T123 |
Yes |
T131,T33,T123 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T131,T33,T199 |
Yes |
T131,T33,T199 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T131,T33,T199 |
Yes |
T131,T33,T199 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T131,T33,T123 |
Yes |
T131,T33,T123 |
OUTPUT |
cio_pwm_o[5:0] |
Yes |
Yes |
T313,T314,T100 |
Yes |
T313,T314,T100 |
OUTPUT |
cio_pwm_en_o[5:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
*Tests covering at least one bit in the range