Unified Coverage Report :: Module :: sram_ctrl

Module : sram_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.99			93.99

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sram_ctrl_main	93.84			93.84
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon	94.56			94.56

---

Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.84			93.84

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.84			93.84

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	90.68		86.81			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.56			94.56

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.56			94.56

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	90.68		86.81			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : sram_ctrl

	Total	Covered	Percent
Totals	66	46	69.70
Total Bits	1164	1094	93.99
Total Bits 0->1	582	547	93.99
Total Bits 1->0	582	547	93.99

Ports	66	46	69.70
Port Bits	1164	1094	93.99
Port Bits 0->1	582	547	93.99
Port Bits 1->0	582	547	93.99

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
ram_tl_i.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_address[1:0]	No	No		No		INPUT
ram_tl_i.a_address[16:2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_address[20:17]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[22:21]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_address[27:23]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[28]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_address[29]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[30]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[5:0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_opcode[1]	No	No		No		INPUT
ram_tl_i.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T17,T18,T19	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
ram_tl_o.d_user.rsp_intg[2:0]	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
ram_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
ram_tl_o.d_sink	No	No		No		OUTPUT
ram_tl_o.d_source[4:0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
ram_tl_o.d_source[5]	No	No		No		OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[0]	No	No		No		OUTPUT
ram_tl_o.d_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[5:2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_address[17:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:18]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_address[21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[22]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_address[23]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T4,*T76,*T77	Yes	T4,T76,T77	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	*T23,*T24,*T26	Yes	T23,T24,T26	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	INPUT
regs_tl_i.a_opcode[1]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_valid	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
regs_tl_o.a_ready	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T187,T94,T95	Yes	T187,T94,T95	OUTPUT
regs_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T187,T73,T94	Yes	T4,T76,T77	OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T187,*T73,T94	Yes	T4,T76,T77	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T187,T73,T94	Yes	T4,T76,T77	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[1:0]	Yes	Yes	*T28,*T187,*T73	Yes	T26,T28,T4	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T187,T73,T94	Yes	T4,T76,T77	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T187,*T94,*T95	Yes	T187,T188,T94	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T188,T33,T28	Yes	T188,T33,T28	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T33,T199,T34	Yes	T33,T199,T34	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T33,T199,T34	Yes	T33,T199,T34	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T188,T33,T28	Yes	T188,T33,T28	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T17,T19,T31	Yes	T17,T19,T31	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T4,T5,T6	Yes	T17,T18,T19	INPUT
sram_otp_key_o.req	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T4,T6,T21	Yes	T4,T6,T20	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
sram_otp_key_i.ack	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
cfg_i.rf_cfg.test	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
cfg_i.ram_cfg.test	No	No		No		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

	Total	Covered	Percent
Totals	62	40	64.52
Total Bits	1136	1066	93.84
Total Bits 0->1	568	533	93.84
Total Bits 1->0	568	533	93.84

Ports	62	40	64.52
Port Bits	1136	1066	93.84
Port Bits 0->1	568	533	93.84
Port Bits 1->0	568	533	93.84

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
ram_tl_i.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_address[1:0]	No	No		No		INPUT
ram_tl_i.a_address[16:2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_address[27:17]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[28]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_address[31:29]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[4:0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_source[5]	No	No		No		INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[0]	No	No		No		INPUT
ram_tl_i.a_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_opcode[1]	No	No		No		INPUT
ram_tl_i.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T17,T18,T19	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
ram_tl_o.d_user.rsp_intg[2:0]	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
ram_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
ram_tl_o.d_sink	No	No		No		OUTPUT
ram_tl_o.d_source[4:0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
ram_tl_o.d_source[5]	No	No		No		OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[0]	No	No		No		OUTPUT
ram_tl_o.d_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T4,T17,T18	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
regs_tl_i.a_user.cmd_intg[0]	Yes	Yes	*T4,*T76,*T77	Yes	T4,T76,T77	INPUT
regs_tl_i.a_user.cmd_intg[1]	No	No		No		INPUT
regs_tl_i.a_user.cmd_intg[6:2]	Yes	Yes	T187,T188,T94	Yes	T187,T188,T94	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T76,*T77	Yes	T4,T76,T77	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[5:2]	Yes	Yes	*T4,*T76,*T77	Yes	T4,T76,T77	INPUT
regs_tl_i.a_address[17:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:18]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
regs_tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T4,*T76,*T77	Yes	T4,T76,T77	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T4,*T76,*T77	Yes	T4,T76,T77	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[1:0]	Yes	Yes	*T26,*T28,*T4	Yes	T26,T28,T4	INPUT
regs_tl_i.a_source[5:2]	No	No		No		INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[0]	No	No		No		INPUT
regs_tl_i.a_size[1]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[1:0]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T187,T188,T94	Yes	T187,T188,T94	INPUT
regs_tl_i.a_valid	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
regs_tl_o.a_ready	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[5:0]	Yes	Yes	*T28,*T189,*T190	Yes	T28,T189,T190	OUTPUT
regs_tl_o.d_user.data_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T187,T73,T94	Yes	T4,T76,T77	OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T187,*T73,T94	Yes	T4,T76,T77	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T187,T73,T94	Yes	T4,T76,T77	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[1:0]	Yes	Yes	*T28,*T187,*T73	Yes	T26,T28,T4	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T187,T73,T94	Yes	T4,T76,T77	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T187,*T94,*T95	Yes	T187,T188,T94	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T188,T33,T123	Yes	T188,T33,T123	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T33,T199,T34	Yes	T33,T199,T34	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T33,T199,T34	Yes	T33,T199,T34	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T188,T33,T123	Yes	T188,T33,T123	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T17,T19,T31	Yes	T17,T19,T31	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T4,T5,T6	Yes	T17,T18,T19	INPUT
sram_otp_key_o.req	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T4,T6,T21	Yes	T4,T6,T20	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
sram_otp_key_i.ack	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.test	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.test	No	No		No		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

	Total	Covered	Percent
Totals	60	43	71.67
Total Bits	1102	1042	94.56
Total Bits 0->1	551	521	94.56
Total Bits 1->0	551	521	94.56

Ports	60	43	71.67
Port Bits	1102	1042	94.56
Port Bits 0->1	551	521	94.56
Port Bits 1->0	551	521	94.56

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
ram_tl_i.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T17,T18	Yes	T4,T17,T18	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
ram_tl_i.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_address[1:0]	No	No		No		INPUT
ram_tl_i.a_address[11:2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_address[20:12]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[22:21]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[30]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	INPUT
ram_tl_i.a_opcode[1]	No	No		No		INPUT
ram_tl_i.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_i.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
ram_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T17,T18,T19	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T17,T18	Yes	T4,T17,T18	OUTPUT
ram_tl_o.d_user.rsp_intg[2:0]	Yes	Yes	T4,T17,T18	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
ram_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T4,T17,T18	Yes	T4,T17,T18	OUTPUT
ram_tl_o.d_sink	No	No		No		OUTPUT
ram_tl_o.d_source[1:0]	Yes	Yes	*T23,*T24,*T254	Yes	T23,T24,T254	OUTPUT
ram_tl_o.d_source[5:2]	No	No		No		OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[0]	No	No		No		OUTPUT
ram_tl_o.d_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[5:2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_address[19:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_address[21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[22]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	INPUT
regs_tl_i.a_opcode[1]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
regs_tl_i.a_valid	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
regs_tl_o.a_ready	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T187,T94,T95	Yes	T187,T94,T95	OUTPUT
regs_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T187,T73,T94	Yes	T4,T76,T77	OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T73,*T74,*T75	Yes	T4,T76,T77	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T187,T73,T94	Yes	T4,T76,T77	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[1:0]	Yes	Yes	*T28,*T187,*T73	Yes	T28,T4,T77	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T73,T74,T75	Yes	T4,T76,T77	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T187,*T94,*T95	Yes	T187,T94,T95	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T33,T28,T123	Yes	T33,T28,T123	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T33,T28,T123	Yes	T33,T28,T123	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T17,T19,T31	Yes	T17,T19,T31	INPUT
lc_hw_debug_en_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
otp_en_sram_ifetch_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
sram_otp_key_o.req	Yes	Yes	T187,T94,T95	Yes	T187,T94,T95	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T4,T6,T21	Yes	T4,T6,T20	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
sram_otp_key_i.ack	Yes	Yes	T187,T94,T95	Yes	T187,T94,T95	INPUT
cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.test	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.test	No	No		No		INPUT

*Tests covering at least one bit in the range