Unified Coverage Report :: Module :: entropy_src

Module : entropy_src

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.46			84.46

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_entropy_src_0.1/rtl/entropy_src.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_entropy_src	89.56			89.56

---

Module Instance : tb.dut.top_earlgrey.u_entropy_src

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.56			89.56

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.56			89.56

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	90.68		86.81			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : entropy_src

	Total	Covered	Percent
Totals	65	43	66.15
Total Bits	1300	1098	84.46
Total Bits 0->1	650	549	84.46
Total Bits 1->0	650	549	84.46

Ports	65	43	66.15
Port Bits	1300	1098	84.46
Port Bits 0->1	650	549	84.46
Port Bits 1->0	650	549	84.46

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[7:2]	Yes	Yes	T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[16:8]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:17]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[1:0]	Yes	Yes	*T169,*T4,*T6	Yes	T169,T4,T6	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T101,T76	Yes	T4,T101,T76	INPUT
tl_i.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_o.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T4,T17,T18	Yes	T4,T6,T20	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T17,*T18,*T19	Yes	T4,T6,T20	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T17,T18	Yes	T4,T6,T20	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T169,*T4,*T17	Yes	T169,T4,T6	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T101,*T37,*T103	Yes	T4,T101,T76	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
otp_en_entropy_src_fw_read_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
otp_en_entropy_src_fw_over_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
rng_fips_o	Yes	Yes	T101,T37,T102	Yes	T101,T37,T103	OUTPUT
entropy_src_hw_if_i.es_req	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
entropy_src_hw_if_o.es_fips	Yes	Yes	T101,T37,T184	Yes	T101,T37,T103	OUTPUT
entropy_src_hw_if_o.es_bits[383:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
entropy_src_hw_if_o.es_ack	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
entropy_src_rng_o.rng_enable	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	OUTPUT
entropy_src_rng_i.rng_b[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
entropy_src_rng_i.rng_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
cs_aes_halt_o.cs_aes_halt_req	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
cs_aes_halt_i.cs_aes_halt_ack	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
entropy_src_xht_o.threshold_scope	No	No		No		OUTPUT
entropy_src_xht_o.window_wrap_pulse	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
entropy_src_xht_o.health_test_window[0]	No	No		No		OUTPUT
entropy_src_xht_o.health_test_window[1]	Yes	Yes	*T169	Yes	T169	OUTPUT
entropy_src_xht_o.health_test_window[2]	No	No		No		OUTPUT
entropy_src_xht_o.health_test_window[7:3]	Yes	Yes	*T169,*T101,*T37	Yes	T169,T101,T37	OUTPUT
entropy_src_xht_o.health_test_window[8]	No	No		No		OUTPUT
entropy_src_xht_o.health_test_window[9]	Yes	Yes	*T101,*T37,*T102	Yes	T101,T37,T103	OUTPUT
entropy_src_xht_o.health_test_window[10]	No	No		No		OUTPUT
entropy_src_xht_o.health_test_window[12:11]	Yes	Yes	T169	Yes	T169	OUTPUT
entropy_src_xht_o.health_test_window[13]	No	No		No		OUTPUT
entropy_src_xht_o.health_test_window[14]	Yes	Yes	*T169	Yes	T169	OUTPUT
entropy_src_xht_o.health_test_window[17:15]	No	No		No		OUTPUT
entropy_src_xht_o.thresh_lo[15:0]	No	No		No		OUTPUT
entropy_src_xht_o.thresh_hi[15:0]	No	No		No		OUTPUT
entropy_src_xht_o.active	No	No		No		OUTPUT
entropy_src_xht_o.clear	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
entropy_src_xht_o.rng_bit_sel[1:0]	No	No		No		OUTPUT
entropy_src_xht_o.rng_bit_en	No	No		No		OUTPUT
entropy_src_xht_o.entropy_bit_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
entropy_src_xht_o.entropy_bit[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
entropy_src_xht_i.test_fail_lo_pulse	No	No		No		INPUT
entropy_src_xht_i.test_fail_hi_pulse	No	No		No		INPUT
entropy_src_xht_i.continuous_test	No	No		No		INPUT
entropy_src_xht_i.test_cnt_lo[15:0]	No	No		No		INPUT
entropy_src_xht_i.test_cnt_hi[15:0]	No	No		No		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T33,T123,T34	Yes	T33,T123,T34	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T223,T224,T33	Yes	T223,T224,T33	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T33,T123,T34	Yes	T33,T123,T34	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T223,T224,T33	Yes	T223,T224,T33	OUTPUT
intr_es_entropy_valid_o	Yes	Yes	T225,T226,T227	Yes	T225,T226,T227	OUTPUT
intr_es_health_test_failed_o	Yes	Yes	T225,T226,T227	Yes	T225,T226,T227	OUTPUT
intr_es_observe_fifo_ready_o	Yes	Yes	T225,T226,T227	Yes	T225,T226,T227	OUTPUT
intr_es_fatal_err_o	Yes	Yes	T225,T226,T227	Yes	T225,T226,T227	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_entropy_src

	Total	Covered	Percent
Totals	58	43	74.14
Total Bits	1226	1098	89.56
Total Bits 0->1	613	549	89.56
Total Bits 1->0	613	549	89.56

Ports	58	43	74.14
Port Bits	1226	1098	89.56
Port Bits 0->1	613	549	89.56
Port Bits 1->0	613	549	89.56

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[7:2]	Yes	Yes	T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[16:8]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:17]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[1:0]	Yes	Yes	*T169,*T4,*T6	Yes	T169,T4,T6	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T101,T76	Yes	T4,T101,T76	INPUT
tl_i.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_o.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T4,T17,T18	Yes	T4,T6,T20	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T17,*T18,*T19	Yes	T4,T6,T20	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T17,T18	Yes	T4,T6,T20	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T169,*T4,*T17	Yes	T169,T4,T6	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T101,*T37,*T103	Yes	T4,T101,T76	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
otp_en_entropy_src_fw_read_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
otp_en_entropy_src_fw_over_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
rng_fips_o	Yes	Yes	T101,T37,T102	Yes	T101,T37,T103	OUTPUT
entropy_src_hw_if_i.es_req	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
entropy_src_hw_if_o.es_fips	Yes	Yes	T101,T37,T184	Yes	T101,T37,T103	OUTPUT
entropy_src_hw_if_o.es_bits[383:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
entropy_src_hw_if_o.es_ack	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
entropy_src_rng_o.rng_enable	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	OUTPUT
entropy_src_rng_i.rng_b[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
entropy_src_rng_i.rng_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
cs_aes_halt_o.cs_aes_halt_req	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
cs_aes_halt_i.cs_aes_halt_ack	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
entropy_src_xht_o.threshold_scope[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off / unconnected port.
entropy_src_xht_o.window_wrap_pulse	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
entropy_src_xht_o.health_test_window[0]	No	No		No		OUTPUT
entropy_src_xht_o.health_test_window[1]	Yes	Yes	*T169	Yes	T169	OUTPUT
entropy_src_xht_o.health_test_window[2]	No	No		No		OUTPUT
entropy_src_xht_o.health_test_window[7:3]	Yes	Yes	*T169,*T101,*T37	Yes	T169,T101,T37	OUTPUT
entropy_src_xht_o.health_test_window[8]	No	No		No		OUTPUT
entropy_src_xht_o.health_test_window[9]	Yes	Yes	*T101,*T37,*T102	Yes	T101,T37,T103	OUTPUT
entropy_src_xht_o.health_test_window[10]	No	No		No		OUTPUT
entropy_src_xht_o.health_test_window[12:11]	Yes	Yes	T169	Yes	T169	OUTPUT
entropy_src_xht_o.health_test_window[13]	No	No		No		OUTPUT
entropy_src_xht_o.health_test_window[14]	Yes	Yes	*T169	Yes	T169	OUTPUT
entropy_src_xht_o.health_test_window[17:15]	No	No		No		OUTPUT
entropy_src_xht_o.thresh_lo[15:0]	No	No		No		OUTPUT
entropy_src_xht_o.thresh_hi[15:0]	No	No		No		OUTPUT
entropy_src_xht_o.active[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off / unconnected port.
entropy_src_xht_o.clear	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
entropy_src_xht_o.rng_bit_sel[1:0]	No	No		No		OUTPUT
entropy_src_xht_o.rng_bit_en	No	No		No		OUTPUT
entropy_src_xht_o.entropy_bit_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
entropy_src_xht_o.entropy_bit[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
entropy_src_xht_i.test_fail_lo_pulse[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off / unconnected port.
entropy_src_xht_i.test_fail_hi_pulse[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off / unconnected port.
entropy_src_xht_i.continuous_test[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off / unconnected port.
entropy_src_xht_i.test_cnt_lo[15:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off / unconnected port.
entropy_src_xht_i.test_cnt_hi[15:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off / unconnected port.
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T33,T123,T34	Yes	T33,T123,T34	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T223,T224,T33	Yes	T223,T224,T33	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T33,T123,T34	Yes	T33,T123,T34	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T223,T224,T33	Yes	T223,T224,T33	OUTPUT
intr_es_entropy_valid_o	Yes	Yes	T225,T226,T227	Yes	T225,T226,T227	OUTPUT
intr_es_health_test_failed_o	Yes	Yes	T225,T226,T227	Yes	T225,T226,T227	OUTPUT
intr_es_observe_fifo_ready_o	Yes	Yes	T225,T226,T227	Yes	T225,T226,T227	OUTPUT
intr_es_fatal_err_o	Yes	Yes	T225,T226,T227	Yes	T225,T226,T227	OUTPUT

*Tests covering at least one bit in the range