Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.83			80.83

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	80.83			80.83

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.83			80.83

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.83			80.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	90.68		86.81			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	300	54.55
Total Bits	6824	5516	80.83
Total Bits 0->1	3412	2758	80.83
Total Bits 1->0	3412	2758	80.83

Ports	550	300	54.55
Port Bits	6824	5516	80.83
Port Bits 0->1	3412	2758	80.83
Port Bits 1->0	3412	2758	80.83

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[2:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__corei_i.a_source[5:3]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T19,T160,T161	Yes	T19,T160,T161	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[5:0]	Yes	Yes	*T19,*T160,*T161	Yes	T19,T160,T161	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_source[2:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:3]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[0]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T23,T24,T28	Yes	T23,T24,T28	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T23,T60,T62	Yes	T23,T60,T62	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T23,T60,T61	Yes	T23,T60,T61	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__cored_i.a_opcode[1]	No	No		No		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T17,T19,T160	Yes	T17,T19,T160	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[5:0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	No	No		No		OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T23,T24,T26	Yes	T23,T24,T26	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_rv_dm__sba_i.a_user.instr_type[0]	Yes	Yes	*T17,*T18,*T19	Yes	T4,T6,T20	INPUT
tl_rv_dm__sba_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_rv_dm__sba_i.a_user.instr_type[3]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T23,T24,T30	Yes	T23,T24,T30	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_size[1]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[1:0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_opcode[2]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T23,T24,T26	Yes	T23,T24,T26	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T23,T24,T30	Yes	T23,T24,T30	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[1:0]	Yes	Yes	T23,T24,*T26	Yes	T23,T24,T26	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[2]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[5:3]	Yes	Yes	T23,T24,T26	Yes	T23,T24,T26	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T23,T24,T30	Yes	T23,T24,T30	OUTPUT
tl_rv_dm__sba_o.d_sink	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[0]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_size[1]	Yes	Yes	T23,T24,T26	Yes	T23,T24,T26	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T23,*T24,*T30	Yes	T23,T24,T30	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T23,T24,T26	Yes	T23,T24,T26	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_valid	No	No		No		OUTPUT
tl_rv_dm__regs_i.a_ready	No	No		No		INPUT
tl_rv_dm__regs_i.d_error	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	No	No		No		INPUT
tl_rv_dm__regs_i.d_data[31:0]	No	No		No		INPUT
tl_rv_dm__regs_i.d_sink	No	No		No		INPUT
tl_rv_dm__regs_i.d_source[5:0]	No	No		No		INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	No	No		No		INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	No	No		No		INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	No	No		No		INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T26,T28,T27	Yes	T26,T28,T27	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T26,T28,T27	Yes	T26,T28,T27	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T26,T28,T27	Yes	T26,T28,T27	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T26,T28,T27	Yes	T26,T28,T27	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T26,T28,T27	Yes	T26,T28,T27	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[4:0]	Yes	Yes	*T26,*T27,*T22	Yes	T26,T27,T22	OUTPUT
tl_rv_dm__mem_o.a_source[5]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[0]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_size[1]	Yes	Yes	T26,T28,T27	Yes	T26,T28,T27	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_opcode[2]	Yes	Yes	T26,T28,T27	Yes	T26,T28,T27	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T26,T28,T27	Yes	T26,T28,T27	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T6,T20	Yes	T17,T18,T19	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T26,T27,T22	Yes	T26,T27,T22	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[2:0]	Yes	Yes	*T26,*T28,*T27	Yes	T26,T28,T27	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[5:4]	Yes	Yes	*T28,*T22,*T29	Yes	T26,T28,T27	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T17,T18,T19	INPUT
tl_rv_dm__mem_i.d_sink	No	No		No		INPUT
tl_rv_dm__mem_i.d_source[4:0]	Yes	Yes	*T26,*T27,*T22	Yes	T26,T27,T22	INPUT
tl_rv_dm__mem_i.d_source[5]	No	No		No		INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[0]	No	No		No		INPUT
tl_rv_dm__mem_i.d_size[1]	Yes	Yes	T28,T22,T29	Yes	T26,T28,T27	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T17,T18,T19	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T26,T28,T27	Yes	T26,T28,T27	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T4,T76,T38	Yes	T4,T76,T38	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T4,T76,T38	Yes	T4,T76,T38	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[4:0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_rom_ctrl__rom_o.a_source[5]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[0]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[4]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rom_ctrl__rom_i.d_sink	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_source[4:0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_rom_ctrl__rom_i.d_source[5]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[0]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[1:0]	Yes	Yes	T123,*T124,*T125	Yes	T123,T124,T125	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[2]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[5:3]	Yes	Yes	*T162,*T149,*T150	Yes	T162,T149,T150	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T162,T149,T150	Yes	T162,T149,T150	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[0]	Yes	Yes	*T162,*T149,*T150	Yes	T162,T149,T150	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3]	Yes	Yes	T162,T149,T150	Yes	T162,T149,T150	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[0]	Yes	Yes	*T123,*T124,*T125	Yes	T123,T124,T125	OUTPUT
tl_rom_ctrl__regs_o.a_data[31:1]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T162,T149,T150	Yes	T162,T149,T150	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[0]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_source[1]	Yes	Yes	*T162,*T149,*T150	Yes	T162,T149,T150	OUTPUT
tl_rom_ctrl__regs_o.a_source[5:2]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[0]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_size[1]	Yes	Yes	T162,T149,T150	Yes	T162,T149,T150	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2]	Yes	Yes	T162,T149,T150	Yes	T162,T149,T150	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T162,T149,T150	Yes	T162,T149,T150	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T162,T149,T150	Yes	T162,T149,T150	INPUT
tl_rom_ctrl__regs_i.d_error	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T162,T150,T163	Yes	T162,T150,T163	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[0]	No	No		Yes	T123,T124,T125	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[1]	No	Yes	*T123,*T124,*T125	No		INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	T149,T150,T164	Yes	T162,T149,T150	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T162,T150,T163	Yes	T162,T150,T163	INPUT
tl_rom_ctrl__regs_i.d_sink	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_source[0]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_source[1]	Yes	Yes	*T162,*T149,*T150	Yes	T162,T149,T150	INPUT
tl_rom_ctrl__regs_i.d_source[5:2]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[0]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_size[1]	Yes	Yes	T149,T150,T164	Yes	T162,T149,T150	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T149,*T150,*T164	Yes	T162,T149,T150	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T162,T149,T150	Yes	T162,T149,T150	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_peri_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_peri_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_peri_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_peri_o.a_opcode[1]	No	No		No		OUTPUT
tl_peri_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_peri_i.d_error	Yes	Yes	T19,T160,T165	Yes	T19,T160,T165	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_peri_i.d_user.rsp_intg[5:0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_peri_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_peri_i.d_sink	No	No		No		INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T152,T166,T157	Yes	T152,T166,T157	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T152,T166,T157	Yes	T152,T166,T157	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[0]	Yes	Yes	*T152,*T166,*T157	Yes	T152,T166,T157	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:2]	Yes	Yes	T152,T166,T157	Yes	T152,T166,T157	OUTPUT
tl_spi_host0_o.a_user.instr_type[0]	Yes	Yes	*T152,*T166,*T157	Yes	T152,T166,T157	OUTPUT
tl_spi_host0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_host0_o.a_user.instr_type[3]	Yes	Yes	T152,T166,T157	Yes	T152,T166,T157	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T152,T166,T157	Yes	T152,T166,T157	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T152,T166,T157	Yes	T152,T166,T157	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[1:0]	Yes	Yes	*T28,*T152,*T157	Yes	T28,T152,T157	OUTPUT
tl_spi_host0_o.a_source[5:2]	No	No		No		OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[0]	No	No		No		OUTPUT
tl_spi_host0_o.a_size[1]	Yes	Yes	T152,T166,T157	Yes	T152,T166,T157	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[0]	Yes	Yes	*T42,*T43,*T156	Yes	T42,T43,T156	OUTPUT
tl_spi_host0_o.a_opcode[1]	No	No		No		OUTPUT
tl_spi_host0_o.a_opcode[2]	Yes	Yes	T152,T157,T42	Yes	T152,T157,T42	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T152,T166,T157	Yes	T152,T166,T157	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T152,T166,T157	Yes	T152,T166,T157	INPUT
tl_spi_host0_i.d_error	No	No		No		INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T152,T157,T42	Yes	T152,T157,T42	INPUT
tl_spi_host0_i.d_user.rsp_intg[1:0]	Yes	Yes	T152,T166,T157	Yes	T152,T166,T157	INPUT
tl_spi_host0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_host0_i.d_user.rsp_intg[5:4]	Yes	Yes	T152,*T166,T42	Yes	T152,T166,T157	INPUT
tl_spi_host0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T152,T157,T42	Yes	T152,T157,T42	INPUT
tl_spi_host0_i.d_sink	No	No		No		INPUT
tl_spi_host0_i.d_source[1:0]	Yes	Yes	*T28,*T152,*T42	Yes	T28,T152,T157	INPUT
tl_spi_host0_i.d_source[5:2]	No	No		No		INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[0]	No	No		No		INPUT
tl_spi_host0_i.d_size[1]	Yes	Yes	T152,T166,T42	Yes	T152,T166,T157	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T152,*T157,*T42	Yes	T152,T157,T42	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T152,T166,T157	Yes	T152,T166,T157	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T152,T157,T167	Yes	T152,T157,T167	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T152,T157,T28	Yes	T152,T157,T28	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T152,T157,T167	Yes	T152,T157,T167	OUTPUT
tl_spi_host1_o.a_user.instr_type[0]	Yes	Yes	*T152,*T157,*T167	Yes	T152,T157,T167	OUTPUT
tl_spi_host1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_host1_o.a_user.instr_type[3]	Yes	Yes	T152,T157,T167	Yes	T152,T157,T167	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T152,T157,T28	Yes	T152,T157,T28	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T152,T157,T167	Yes	T152,T157,T167	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[1:0]	Yes	Yes	*T28,*T152,*T157	Yes	T28,T152,T157	OUTPUT
tl_spi_host1_o.a_source[5:2]	No	No		No		OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[0]	No	No		No		OUTPUT
tl_spi_host1_o.a_size[1]	Yes	Yes	T152,T157,T167	Yes	T152,T157,T167	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_spi_host1_o.a_opcode[2]	Yes	Yes	T152,T157,T167	Yes	T152,T157,T167	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T152,T157,T167	Yes	T152,T157,T167	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T152,T157,T167	Yes	T152,T157,T167	INPUT
tl_spi_host1_i.d_error	No	No		No		INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T152,T157,T28	Yes	T152,T157,T28	INPUT
tl_spi_host1_i.d_user.rsp_intg[1:0]	Yes	Yes	T152,T157,T167	Yes	T152,T157,T167	INPUT
tl_spi_host1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_host1_i.d_user.rsp_intg[5:4]	Yes	Yes	T152,T167,T28	Yes	T152,T157,T167	INPUT
tl_spi_host1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T152,T157,T28	Yes	T152,T157,T28	INPUT
tl_spi_host1_i.d_sink	No	No		No		INPUT
tl_spi_host1_i.d_source[1:0]	Yes	Yes	*T28,*T152,*T157	Yes	T28,T152,T157	INPUT
tl_spi_host1_i.d_source[5:2]	No	No		No		INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[0]	No	No		No		INPUT
tl_spi_host1_i.d_size[1]	Yes	Yes	T152,T167,T28	Yes	T152,T157,T167	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T152,*T157,*T167	Yes	T152,T157,T167	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T152,T157,T167	Yes	T152,T157,T167	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T152,T47,T48	Yes	T152,T47,T48	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T152,T47,T48	Yes	T152,T47,T48	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T152,T47,T48	Yes	T152,T47,T48	OUTPUT
tl_usbdev_o.a_user.instr_type[0]	Yes	Yes	*T152,*T47,*T48	Yes	T152,T47,T48	OUTPUT
tl_usbdev_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_usbdev_o.a_user.instr_type[3]	Yes	Yes	T152,T47,T48	Yes	T152,T47,T48	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T152,T47,T48	Yes	T152,T47,T48	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T152,T47,T48	Yes	T152,T47,T48	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[1:0]	Yes	Yes	*T168,*T169,*T152	Yes	T168,T169,T152	OUTPUT
tl_usbdev_o.a_source[5:2]	No	No		No		OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[0]	No	No		No		OUTPUT
tl_usbdev_o.a_size[1]	Yes	Yes	T152,T47,T48	Yes	T152,T47,T48	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_usbdev_o.a_opcode[2]	Yes	Yes	T152,T47,T170	Yes	T152,T47,T170	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T152,T47,T48	Yes	T152,T47,T48	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T152,T47,T48	Yes	T152,T47,T48	INPUT
tl_usbdev_i.d_error	No	No		No		INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T152,T47,T170	Yes	T152,T47,T170	INPUT
tl_usbdev_i.d_user.rsp_intg[1:0]	Yes	Yes	T152,T47,T170	Yes	T152,T47,T170	INPUT
tl_usbdev_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_usbdev_i.d_user.rsp_intg[5:4]	Yes	Yes	T152,T47,T48	Yes	T152,T47,T48	INPUT
tl_usbdev_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T152,T47,T48	Yes	T152,T47,T48	INPUT
tl_usbdev_i.d_sink	No	No		No		INPUT
tl_usbdev_i.d_source[1:0]	Yes	Yes	*T168,*T169,*T152	Yes	T168,T169,T152	INPUT
tl_usbdev_i.d_source[5:2]	No	No		No		INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[0]	No	No		No		INPUT
tl_usbdev_i.d_size[1]	Yes	Yes	T152,T47,T48	Yes	T152,T47,T48	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T152,*T47,*T48	Yes	T152,T47,T48	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T152,T47,T48	Yes	T152,T47,T48	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[1:0]	Yes	Yes	*T169,*T4,*T6	Yes	T169,T4,T6	OUTPUT
tl_flash_ctrl__core_o.a_source[5:2]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T17,T18,T19	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[2:0]	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[5:4]	Yes	Yes	T4,T17,T18	Yes	T4,T6,T20	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T17,T18	INPUT
tl_flash_ctrl__core_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[1:0]	Yes	Yes	*T169,*T4,*T6	Yes	T169,T4,T6	INPUT
tl_flash_ctrl__core_i.d_source[5:2]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[0]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_size[1]	Yes	Yes	T4,T17,T18	Yes	T4,T6,T20	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T169	Yes	T169	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T169	Yes	T169	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[0]	Yes	Yes	*T169	Yes	T169	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3]	Yes	Yes	T169	Yes	T169	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T169	Yes	T169	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T169	Yes	T169	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[0]	Yes	Yes	*T169	Yes	T169	OUTPUT
tl_flash_ctrl__prim_o.a_source[5:1]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_size[1]	Yes	Yes	T169	Yes	T169	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2]	Yes	Yes	T169	Yes	T169	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T169	Yes	T169	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T169	Yes	T169	INPUT
tl_flash_ctrl__prim_i.d_error	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[1:0]	Yes	Yes	T169	Yes	T169	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[5:4]	Yes	Yes	T169	Yes	T169	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T169	Yes	T169	INPUT
tl_flash_ctrl__prim_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_source[0]	Yes	Yes	*T169	Yes	T169	INPUT
tl_flash_ctrl__prim_i.d_source[5:1]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_size[1]	Yes	Yes	T169	Yes	T169	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T169	Yes	T169	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T169	Yes	T169	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__mem_o.a_source[1]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_source[4:2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__mem_o.a_source[5]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T6,T20	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T17,T18,T19	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[2:0]	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[4]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_flash_ctrl__mem_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_flash_ctrl__mem_i.d_source[1]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[4:2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_flash_ctrl__mem_i.d_source[5]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_hmac_o.d_ready	Yes	Yes	T4,T17,T18	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
tl_hmac_o.a_user.instr_type[0]	Yes	Yes	*T4,*T18,*T76	Yes	T4,T18,T76	OUTPUT
tl_hmac_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_hmac_o.a_user.instr_type[3]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[1:0]	Yes	Yes	*T169,*T4,*T18	Yes	T169,T4,T18	OUTPUT
tl_hmac_o.a_source[5:2]	No	No		No		OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[0]	No	No		No		OUTPUT
tl_hmac_o.a_size[1]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[0]	Yes	Yes	*T171,*T172,*T173	Yes	T171,T172,T173	OUTPUT
tl_hmac_o.a_opcode[1]	No	No		No		OUTPUT
tl_hmac_o.a_opcode[2]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	INPUT
tl_hmac_i.d_error	No	No		No		INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	INPUT
tl_hmac_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	INPUT
tl_hmac_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_hmac_i.d_user.rsp_intg[5:4]	Yes	Yes	T4,*T18,T76	Yes	T4,T18,T76	INPUT
tl_hmac_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
tl_hmac_i.d_sink	No	No		No		INPUT
tl_hmac_i.d_source[1:0]	Yes	Yes	*T169,*T4,*T18	Yes	T169,T4,T18	INPUT
tl_hmac_i.d_source[5:2]	No	No		No		INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[0]	No	No		No		INPUT
tl_hmac_i.d_size[1]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T4,*T76,*T77	Yes	T4,T76,T77	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	INPUT
tl_kmac_o.d_ready	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T37,T174,T175	Yes	T37,T174,T175	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T18,T37,T176	Yes	T18,T37,T176	OUTPUT
tl_kmac_o.a_user.instr_type[0]	Yes	Yes	*T18,*T37,*T176	Yes	T18,T37,T176	OUTPUT
tl_kmac_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_kmac_o.a_user.instr_type[3]	Yes	Yes	T18,T37,T176	Yes	T18,T37,T176	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T37,T174,T175	Yes	T37,T174,T175	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T18,T37,T176	Yes	T18,T37,T176	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[1:0]	Yes	Yes	*T28,*T169,*T37	Yes	T28,T169,T37	OUTPUT
tl_kmac_o.a_source[5:2]	No	No		No		OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[0]	No	No		No		OUTPUT
tl_kmac_o.a_size[1]	Yes	Yes	T18,T37,T176	Yes	T18,T37,T176	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[0]	Yes	Yes	*T174,*T175,*T177	Yes	T174,T175,T177	OUTPUT
tl_kmac_o.a_opcode[1]	No	No		No		OUTPUT
tl_kmac_o.a_opcode[2]	Yes	Yes	T18,T37,T176	Yes	T18,T37,T176	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T18,T37,T176	Yes	T18,T37,T176	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T18,T37,T176	Yes	T18,T37,T176	INPUT
tl_kmac_i.d_error	No	No		No		INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T18,T37,T176	Yes	T18,T37,T176	INPUT
tl_kmac_i.d_user.rsp_intg[1:0]	Yes	Yes	T18,T37,T176	Yes	T18,T37,T176	INPUT
tl_kmac_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_kmac_i.d_user.rsp_intg[5:4]	Yes	Yes	*T18,T37,T176	Yes	T18,T37,T176	INPUT
tl_kmac_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T37,T176,T174	Yes	T37,T176,T174	INPUT
tl_kmac_i.d_sink	No	No		No		INPUT
tl_kmac_i.d_source[1:0]	Yes	Yes	*T28,*T169,*T37	Yes	T28,T169,T37	INPUT
tl_kmac_i.d_source[5:2]	No	No		No		INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[0]	No	No		No		INPUT
tl_kmac_i.d_size[1]	Yes	Yes	T18,T37,T176	Yes	T18,T37,T176	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T37,*T176,*T174	Yes	T37,T176,T174	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T18,T37,T176	Yes	T18,T37,T176	INPUT
tl_aes_o.d_ready	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T178,T179,T180	Yes	T178,T179,T180	OUTPUT
tl_aes_o.a_user.cmd_intg[0]	Yes	Yes	*T178,*T179,*T180	Yes	T178,T179,T180	OUTPUT
tl_aes_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_aes_o.a_user.cmd_intg[6:2]	Yes	Yes	T18,T103,T178	Yes	T18,T103,T178	OUTPUT
tl_aes_o.a_user.instr_type[0]	Yes	Yes	*T18,*T103,*T178	Yes	T18,T103,T178	OUTPUT
tl_aes_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_aes_o.a_user.instr_type[3]	Yes	Yes	T18,T103,T178	Yes	T18,T103,T178	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T178,T179,T180	Yes	T178,T179,T180	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T18,T103,T178	Yes	T18,T103,T178	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[0]	No	No		No		OUTPUT
tl_aes_o.a_source[1]	Yes	Yes	*T103,*T178,*T181	Yes	T103,T178,T181	OUTPUT
tl_aes_o.a_source[5:2]	No	No		No		OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[0]	No	No		No		OUTPUT
tl_aes_o.a_size[1]	Yes	Yes	T18,T103,T178	Yes	T18,T103,T178	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_aes_o.a_opcode[2]	Yes	Yes	T18,T103,T178	Yes	T18,T103,T178	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T18,T103,T178	Yes	T18,T103,T178	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T18,T103,T178	Yes	T18,T103,T178	INPUT
tl_aes_i.d_error	No	No		No		INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T18,T103,T178	Yes	T18,T103,T178	INPUT
tl_aes_i.d_user.rsp_intg[1:0]	Yes	Yes	T103,T178,T181	Yes	T103,T178,T181	INPUT
tl_aes_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_aes_i.d_user.rsp_intg[5:4]	Yes	Yes	T18,*T182,*T183	Yes	T18,T103,T178	INPUT
tl_aes_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T18,T103,T178	Yes	T18,T103,T178	INPUT
tl_aes_i.d_sink	No	No		No		INPUT
tl_aes_i.d_source[0]	No	No		No		INPUT
tl_aes_i.d_source[1]	Yes	Yes	*T103,*T178,*T181	Yes	T103,T178,T181	INPUT
tl_aes_i.d_source[5:2]	No	No		No		INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[0]	No	No		No		INPUT
tl_aes_i.d_size[1]	Yes	Yes	T18,T182,T183	Yes	T18,T103,T178	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T18,*T103,*T178	Yes	T18,T103,T178	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T18,T103,T178	Yes	T18,T103,T178	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_entropy_src_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_entropy_src_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_entropy_src_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[1:0]	Yes	Yes	*T169,*T4,*T6	Yes	T169,T4,T6	OUTPUT
tl_entropy_src_o.a_source[5:2]	No	No		No		OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[0]	No	No		No		OUTPUT
tl_entropy_src_o.a_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_entropy_src_o.a_opcode[2]	Yes	Yes	T4,T101,T76	Yes	T4,T101,T76	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_entropy_src_i.d_error	No	No		No		INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_entropy_src_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T17,T18	Yes	T4,T6,T20	INPUT
tl_entropy_src_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_entropy_src_i.d_user.rsp_intg[5:4]	Yes	Yes	*T17,*T18,*T19	Yes	T4,T6,T20	INPUT
tl_entropy_src_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T4,T17,T18	Yes	T4,T6,T20	INPUT
tl_entropy_src_i.d_sink	No	No		No		INPUT
tl_entropy_src_i.d_source[1:0]	Yes	Yes	*T169,*T4,*T17	Yes	T169,T4,T6	INPUT
tl_entropy_src_i.d_source[5:2]	No	No		No		INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[0]	No	No		No		INPUT
tl_entropy_src_i.d_size[1]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T101,*T37,*T103	Yes	T4,T101,T76	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_csrng_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_csrng_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_csrng_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[1:0]	Yes	Yes	*T169,*T101,*T37	Yes	T169,T101,T37	OUTPUT
tl_csrng_o.a_source[5:2]	No	No		No		OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[0]	No	No		No		OUTPUT
tl_csrng_o.a_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_csrng_o.a_opcode[2]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_csrng_i.d_error	No	No		No		INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_csrng_i.d_user.rsp_intg[1:0]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_csrng_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_csrng_i.d_user.rsp_intg[5:4]	Yes	Yes	*T17,*T18,*T19	Yes	T4,T6,T20	INPUT
tl_csrng_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_csrng_i.d_sink	No	No		No		INPUT
tl_csrng_i.d_source[1:0]	Yes	Yes	*T169,*T101,*T37	Yes	T169,T101,T37	INPUT
tl_csrng_i.d_source[5:2]	No	No		No		INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[0]	No	No		No		INPUT
tl_csrng_i.d_size[1]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T101,*T37,*T103	Yes	T101,T37,T103	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_edn0_o.a_user.cmd_intg[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_edn0_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_edn0_o.a_user.cmd_intg[6:2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_edn0_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_edn0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_edn0_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[1:0]	Yes	Yes	*T169,*T4,*T6	Yes	T169,T4,T6	OUTPUT
tl_edn0_o.a_source[5:2]	No	No		No		OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[0]	No	No		No		OUTPUT
tl_edn0_o.a_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_edn0_o.a_opcode[2]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_edn0_i.d_error	No	No		No		INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_edn0_i.d_user.rsp_intg[1:0]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_edn0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_edn0_i.d_user.rsp_intg[5:4]	Yes	Yes	*T17,*T18,*T19	Yes	T4,T6,T20	INPUT
tl_edn0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_edn0_i.d_sink	No	No		No		INPUT
tl_edn0_i.d_source[1:0]	Yes	Yes	*T169,*T17,*T18	Yes	T169,T4,T6	INPUT
tl_edn0_i.d_source[5:2]	No	No		No		INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[0]	No	No		No		INPUT
tl_edn0_i.d_size[1]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T101,*T37,*T103	Yes	T101,T37,T103	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_edn1_o.d_ready	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_edn1_o.a_user.cmd_intg[0]	Yes	Yes	*T101,*T37,*T103	Yes	T101,T37,T103	OUTPUT
tl_edn1_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_edn1_o.a_user.cmd_intg[6:2]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_edn1_o.a_user.instr_type[0]	Yes	Yes	*T101,*T37,*T103	Yes	T101,T37,T103	OUTPUT
tl_edn1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_edn1_o.a_user.instr_type[3]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[1:0]	Yes	Yes	*T169,*T101,*T37	Yes	T169,T101,T37	OUTPUT
tl_edn1_o.a_source[5:2]	No	No		No		OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[0]	No	No		No		OUTPUT
tl_edn1_o.a_size[1]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_edn1_o.a_opcode[2]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_edn1_i.d_error	No	No		No		INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_edn1_i.d_user.rsp_intg[1:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_edn1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_edn1_i.d_user.rsp_intg[5:4]	Yes	Yes	T37,*T184,*T169	Yes	T101,T37,T103	INPUT
tl_edn1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_edn1_i.d_sink	No	No		No		INPUT
tl_edn1_i.d_source[1:0]	Yes	Yes	*T169,*T101,*T37	Yes	T169,T101,T37	INPUT
tl_edn1_i.d_source[5:2]	No	No		No		INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[0]	No	No		No		INPUT
tl_edn1_i.d_size[1]	Yes	Yes	T37,T184,T169	Yes	T101,T37,T103	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T101,*T37,*T103	Yes	T101,T37,T103	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T6,T20,T21	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	OUTPUT
tl_rv_plic_o.a_user.instr_type[0]	Yes	Yes	*T6,*T20,*T21	Yes	T6,T20,T21	OUTPUT
tl_rv_plic_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_plic_o.a_user.instr_type[3]	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[1:0]	Yes	Yes	*T28,*T6,*T20	Yes	T28,T6,T20	OUTPUT
tl_rv_plic_o.a_source[5:2]	No	No		No		OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[0]	No	No		No		OUTPUT
tl_rv_plic_o.a_size[1]	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_plic_o.a_opcode[2]	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	INPUT
tl_rv_plic_i.d_error	No	No		No		INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	INPUT
tl_rv_plic_i.d_user.rsp_intg[1:0]	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	INPUT
tl_rv_plic_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_plic_i.d_user.rsp_intg[5:4]	Yes	Yes	T17,T19,T31	Yes	T6,T20,T21	INPUT
tl_rv_plic_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	INPUT
tl_rv_plic_i.d_sink	No	No		No		INPUT
tl_rv_plic_i.d_source[1:0]	Yes	Yes	*T28,*T6,*T20	Yes	T28,T6,T20	INPUT
tl_rv_plic_i.d_source[5:2]	No	No		No		INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[0]	No	No		No		INPUT
tl_rv_plic_i.d_size[1]	Yes	Yes	T17,T19,T31	Yes	T6,T20,T21	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T6,*T20,*T21	Yes	T6,T20,T21	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	INPUT
tl_otbn_o.d_ready	Yes	Yes	T4,T17,T18	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T4,T101,T76	Yes	T4,T101,T76	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T18,T101	Yes	T4,T18,T101	OUTPUT
tl_otbn_o.a_user.instr_type[0]	Yes	Yes	*T4,*T18,*T101	Yes	T4,T18,T101	OUTPUT
tl_otbn_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otbn_o.a_user.instr_type[3]	Yes	Yes	T4,T18,T101	Yes	T4,T18,T101	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T4,T101,T76	Yes	T4,T101,T76	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T4,T18,T101	Yes	T4,T18,T101	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[1:0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_otbn_o.a_source[5:2]	No	No		No		OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[0]	No	No		No		OUTPUT
tl_otbn_o.a_size[1]	Yes	Yes	T4,T18,T101	Yes	T4,T18,T101	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_otbn_o.a_opcode[2]	Yes	Yes	T4,T18,T101	Yes	T4,T18,T101	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T4,T18,T101	Yes	T4,T18,T101	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T4,T18,T101	Yes	T4,T18,T101	INPUT
tl_otbn_i.d_error	No	No		No		INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T4,T101,T76	Yes	T4,T101,T76	INPUT
tl_otbn_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T101,T76	Yes	T4,T101,T76	INPUT
tl_otbn_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_otbn_i.d_user.rsp_intg[5:4]	Yes	Yes	T4,T101,T76	Yes	T4,T101,T76	INPUT
tl_otbn_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T4,T101,T76	Yes	T4,T101,T76	INPUT
tl_otbn_i.d_sink	No	No		No		INPUT
tl_otbn_i.d_source[1:0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	INPUT
tl_otbn_i.d_source[5:2]	No	No		No		INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[0]	No	No		No		INPUT
tl_otbn_i.d_size[1]	Yes	Yes	T4,T101,T76	Yes	T4,T101,T76	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T4,*T101,*T76	Yes	T4,T101,T76	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T4,T101,T76	Yes	T4,T101,T76	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T4,T17,T18	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T4,T76,T176	Yes	T4,T76,T176	OUTPUT
tl_keymgr_o.a_user.cmd_intg[0]	Yes	Yes	*T4,*T76,*T176	Yes	T4,T76,T176	OUTPUT
tl_keymgr_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:2]	Yes	Yes	T4,T76,T176	Yes	T4,T76,T176	OUTPUT
tl_keymgr_o.a_user.instr_type[0]	Yes	Yes	*T4,*T76,*T176	Yes	T4,T76,T176	OUTPUT
tl_keymgr_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_keymgr_o.a_user.instr_type[3]	Yes	Yes	T4,T76,T176	Yes	T4,T76,T176	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T4,T76,T176	Yes	T4,T76,T176	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T4,T76,T176	Yes	T4,T76,T176	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[1:0]	Yes	Yes	*T169,*T4,*T76	Yes	T169,T4,T76	OUTPUT
tl_keymgr_o.a_source[5:2]	No	No		No		OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[0]	No	No		No		OUTPUT
tl_keymgr_o.a_size[1]	Yes	Yes	T4,T76,T176	Yes	T4,T76,T176	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_keymgr_o.a_opcode[2]	Yes	Yes	T4,T76,T176	Yes	T4,T76,T176	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T4,T76,T176	Yes	T4,T76,T176	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T4,T76,T176	Yes	T4,T76,T176	INPUT
tl_keymgr_i.d_error	No	No		No		INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T176,T185,T25	Yes	T176,T185,T25	INPUT
tl_keymgr_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T76,T176	Yes	T4,T76,T176	INPUT
tl_keymgr_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_keymgr_i.d_user.rsp_intg[5:4]	Yes	Yes	T176,T25,T186	Yes	T4,T76,T176	INPUT
tl_keymgr_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T4,T76,T176	Yes	T4,T76,T176	INPUT
tl_keymgr_i.d_sink	No	No		No		INPUT
tl_keymgr_i.d_source[1:0]	Yes	Yes	*T169,*T4,*T76	Yes	T169,T4,T76	INPUT
tl_keymgr_i.d_source[5:2]	No	No		No		INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[0]	No	No		No		INPUT
tl_keymgr_i.d_size[1]	Yes	Yes	T176,T25,T186	Yes	T4,T76,T176	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T4,*T76,*T176	Yes	T4,T76,T176	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T4,T76,T176	Yes	T4,T76,T176	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[0]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[1]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:2]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[0]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__cfg_i.d_error	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T4,T17,T19	Yes	T4,T17,T19	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[5:4]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T4,T17,T19	Yes	T4,T17,T19	INPUT
tl_rv_core_ibex__cfg_i.d_sink	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_source[0]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_source[1]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:2]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[0]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_size[1]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T4,T17,T18	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[0]	Yes	Yes	*T4,*T76,*T77	Yes	T4,T76,T77	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:2]	Yes	Yes	T187,T188,T94	Yes	T187,T188,T94	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[0]	Yes	Yes	*T4,*T76,*T77	Yes	T4,T76,T77	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[1:0]	Yes	Yes	*T26,*T28,*T4	Yes	T26,T28,T4	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:2]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2]	Yes	Yes	T187,T188,T94	Yes	T187,T188,T94	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
tl_sram_ctrl_main__regs_i.d_error	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[5:0]	Yes	Yes	*T28,*T189,*T190	Yes	T28,T189,T190	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T187,T73,T94	Yes	T4,T76,T77	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	T187,*T73,T94	Yes	T4,T76,T77	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T187,T73,T94	Yes	T4,T76,T77	INPUT
tl_sram_ctrl_main__regs_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_source[1:0]	Yes	Yes	*T28,*T187,*T73	Yes	T26,T28,T4	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_size[1]	Yes	Yes	T187,T73,T94	Yes	T4,T76,T77	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T187,*T94,*T95	Yes	T187,T188,T94	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[4:0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[0]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[1]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T17,T18,T19	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[2:0]	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[5:4]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_sram_ctrl_main__ram_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_source[4:0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_sram_ctrl_main__ram_i.d_source[5]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range