Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.94			89.94

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	89.94			89.94

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.94			89.94

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.94			89.94

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	90.68		86.81			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	372	66.19
Total Bits	7060	6350	89.94
Total Bits 0->1	3530	3176	89.97
Total Bits 1->0	3530	3174	89.92

Ports	562	372	66.19
Port Bits	7060	6350	89.94
Port Bits 0->1	3530	3176	89.97
Port Bits 1->0	3530	3174	89.92

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_main_i.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_main_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_main_i.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	INPUT
tl_main_i.a_opcode[1]	No	No		No		INPUT
tl_main_i.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_main_o.d_error	Yes	Yes	T19,T160,T165	Yes	T19,T160,T165	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_main_o.d_user.rsp_intg[5:0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_main_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_main_o.d_sink	No	No		No		OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T4,T20,T21	Yes	T4,T20,T21	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart0_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_uart0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart0_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T4,T20,T21	Yes	T4,T20,T21	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_uart0_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart0_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T4,T20,T21	Yes	T4,T20,T21	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T4,T20,T21	Yes	T4,T20,T21	INPUT
tl_uart0_i.d_error	No	No		No		INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T4,T20,T21	Yes	T4,T20,T21	INPUT
tl_uart0_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T20,T21	Yes	T4,T20,T21	INPUT
tl_uart0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart0_i.d_user.rsp_intg[5:4]	Yes	Yes	*T166,T73,*T74	Yes	T4,T20,T21	INPUT
tl_uart0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T4,T20,T21	Yes	T4,T20,T21	INPUT
tl_uart0_i.d_sink	No	No		No		INPUT
tl_uart0_i.d_source[1:0]	Yes	Yes	*T168,*T169,*T4	Yes	T168,T169,T4	INPUT
tl_uart0_i.d_source[5:2]	No	No		No		INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[0]	No	No		No		INPUT
tl_uart0_i.d_size[1]	Yes	Yes	T166,T73,T74	Yes	T4,T20,T21	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T4,*T20,*T21	Yes	T4,T20,T21	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T4,T20,T21	Yes	T4,T20,T21	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T299,T170,T300	Yes	T299,T170,T300	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart1_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_uart1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart1_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T299,T170,T300	Yes	T299,T170,T300	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_uart1_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart1_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T166,T299,T170	Yes	T166,T299,T170	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T166,T299,T170	Yes	T166,T299,T170	INPUT
tl_uart1_i.d_error	No	No		No		INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T299,T170,T300	Yes	T299,T170,T300	INPUT
tl_uart1_i.d_user.rsp_intg[1:0]	Yes	Yes	T166,T299,T170	Yes	T166,T299,T170	INPUT
tl_uart1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart1_i.d_user.rsp_intg[5:4]	Yes	Yes	*T166,*T230,T168	Yes	T166,T299,T170	INPUT
tl_uart1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T166,T299,T170	Yes	T166,T299,T170	INPUT
tl_uart1_i.d_sink	No	No		No		INPUT
tl_uart1_i.d_source[1:0]	Yes	Yes	*T168,*T169,*T166	Yes	T168,T169,T166	INPUT
tl_uart1_i.d_source[5:2]	No	No		No		INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[0]	No	No		No		INPUT
tl_uart1_i.d_size[1]	Yes	Yes	T166,T230,T168	Yes	T166,T299,T170	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T299,*T170,*T300	Yes	T299,T170,T300	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T166,T299,T170	Yes	T166,T299,T170	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T82,T170,T335	Yes	T82,T170,T335	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart2_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_uart2_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart2_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T82,T170,T335	Yes	T82,T170,T335	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_uart2_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart2_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T82,T166,T170	Yes	T82,T166,T170	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T82,T166,T170	Yes	T82,T166,T170	INPUT
tl_uart2_i.d_error	No	No		No		INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T82,T170,T335	Yes	T82,T170,T335	INPUT
tl_uart2_i.d_user.rsp_intg[1:0]	Yes	Yes	T82,T166,T170	Yes	T82,T166,T170	INPUT
tl_uart2_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart2_i.d_user.rsp_intg[5:4]	Yes	Yes	*T166,*T230,T168	Yes	T82,T166,T170	INPUT
tl_uart2_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T82,T166,T170	Yes	T82,T166,T170	INPUT
tl_uart2_i.d_sink	No	No		No		INPUT
tl_uart2_i.d_source[1:0]	Yes	Yes	*T168,*T169,*T82	Yes	T168,T169,T82	INPUT
tl_uart2_i.d_source[5:2]	No	No		No		INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[0]	No	No		No		INPUT
tl_uart2_i.d_size[1]	Yes	Yes	T166,T230,T168	Yes	T82,T166,T170	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T82,*T170,*T335	Yes	T82,T170,T335	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T82,T166,T170	Yes	T82,T166,T170	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T6,T45,T298	Yes	T6,T45,T298	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart3_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_uart3_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart3_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T6,T45,T298	Yes	T6,T45,T298	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_uart3_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart3_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T6,T166,T45	Yes	T6,T166,T45	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T6,T166,T45	Yes	T6,T166,T45	INPUT
tl_uart3_i.d_error	No	No		No		INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T6,T45,T298	Yes	T6,T45,T298	INPUT
tl_uart3_i.d_user.rsp_intg[1:0]	Yes	Yes	T6,T166,T45	Yes	T6,T166,T45	INPUT
tl_uart3_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart3_i.d_user.rsp_intg[5:4]	Yes	Yes	*T166,*T230,T168	Yes	T6,T166,T45	INPUT
tl_uart3_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T6,T166,T45	Yes	T6,T166,T45	INPUT
tl_uart3_i.d_sink	No	No		No		INPUT
tl_uart3_i.d_source[1:0]	Yes	Yes	*T168,*T169,*T6	Yes	T168,T169,T6	INPUT
tl_uart3_i.d_source[5:2]	No	No		No		INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[0]	No	No		No		INPUT
tl_uart3_i.d_size[1]	Yes	Yes	T166,T230,T168	Yes	T6,T166,T45	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T6,*T45,*T298	Yes	T6,T45,T298	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T6,T166,T45	Yes	T6,T166,T45	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T152,T225,T233	Yes	T152,T225,T233	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_i2c0_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_i2c0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_i2c0_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T152,T225,T233	Yes	T152,T225,T233	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_i2c0_o.a_opcode[1]	No	No		No		OUTPUT
tl_i2c0_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T152,T166,T225	Yes	T152,T166,T225	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T152,T166,T225	Yes	T152,T166,T225	INPUT
tl_i2c0_i.d_error	No	No		No		INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T225,T233,T234	Yes	T225,T233,T234	INPUT
tl_i2c0_i.d_user.rsp_intg[1:0]	Yes	Yes	T152,T166,T225	Yes	T152,T166,T225	INPUT
tl_i2c0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_i2c0_i.d_user.rsp_intg[5:4]	Yes	Yes	T152,*T166,*T230	Yes	T152,T166,T225	INPUT
tl_i2c0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T152,T166,T225	Yes	T152,T166,T225	INPUT
tl_i2c0_i.d_sink	No	No		No		INPUT
tl_i2c0_i.d_source[1:0]	Yes	Yes	*T169,*T152,*T225	Yes	T169,T152,T225	INPUT
tl_i2c0_i.d_source[5:2]	No	No		No		INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[0]	No	No		No		INPUT
tl_i2c0_i.d_size[1]	Yes	Yes	T152,T166,T230	Yes	T152,T166,T225	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T152,*T225,*T233	Yes	T152,T225,T233	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T152,T166,T225	Yes	T152,T166,T225	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T228,T152,T225	Yes	T228,T152,T225	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_i2c1_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_i2c1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_i2c1_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T228,T152,T225	Yes	T228,T152,T225	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_i2c1_o.a_opcode[1]	No	No		No		OUTPUT
tl_i2c1_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T228,T152,T166	Yes	T228,T152,T166	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T228,T152,T166	Yes	T228,T152,T166	INPUT
tl_i2c1_i.d_error	No	No		No		INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T228,T225,T229	Yes	T228,T225,T229	INPUT
tl_i2c1_i.d_user.rsp_intg[1:0]	Yes	Yes	T228,T152,T166	Yes	T228,T152,T166	INPUT
tl_i2c1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_i2c1_i.d_user.rsp_intg[5:4]	Yes	Yes	T152,*T166,*T230	Yes	T228,T152,T166	INPUT
tl_i2c1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T228,T152,T166	Yes	T228,T152,T166	INPUT
tl_i2c1_i.d_sink	No	No		No		INPUT
tl_i2c1_i.d_source[1:0]	Yes	Yes	*T169,*T228,*T152	Yes	T169,T228,T152	INPUT
tl_i2c1_i.d_source[5:2]	No	No		No		INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[0]	No	No		No		INPUT
tl_i2c1_i.d_size[1]	Yes	Yes	T152,T166,T230	Yes	T228,T152,T166	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T228,*T152,*T225	Yes	T228,T152,T225	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T228,T152,T166	Yes	T228,T152,T166	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T152,T225,T226	Yes	T152,T225,T226	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_i2c2_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_i2c2_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_i2c2_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T152,T225,T226	Yes	T152,T225,T226	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_i2c2_o.a_opcode[1]	No	No		No		OUTPUT
tl_i2c2_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T152,T166,T225	Yes	T152,T166,T225	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T152,T166,T225	Yes	T152,T166,T225	INPUT
tl_i2c2_i.d_error	No	No		No		INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T225,T226,T238	Yes	T225,T226,T238	INPUT
tl_i2c2_i.d_user.rsp_intg[1:0]	Yes	Yes	T152,T166,T225	Yes	T152,T166,T225	INPUT
tl_i2c2_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_i2c2_i.d_user.rsp_intg[5:4]	Yes	Yes	T152,*T166,*T230	Yes	T152,T166,T225	INPUT
tl_i2c2_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T152,T166,T225	Yes	T152,T166,T225	INPUT
tl_i2c2_i.d_sink	No	No		No		INPUT
tl_i2c2_i.d_source[1:0]	Yes	Yes	*T169,*T152,*T225	Yes	T169,T152,T225	INPUT
tl_i2c2_i.d_source[5:2]	No	No		No		INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[0]	No	No		No		INPUT
tl_i2c2_i.d_size[1]	Yes	Yes	T152,T166,T230	Yes	T152,T166,T225	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T152,*T225,*T226	Yes	T152,T225,T226	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T152,T166,T225	Yes	T152,T166,T225	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T157,T28,T336	Yes	T157,T28,T336	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pattgen_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_pattgen_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pattgen_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T157,T28,T336	Yes	T157,T28,T336	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_pattgen_o.a_opcode[1]	No	No		No		OUTPUT
tl_pattgen_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T157,T28,T336	Yes	T157,T28,T336	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T157,T28,T336	Yes	T157,T28,T336	INPUT
tl_pattgen_i.d_error	No	No		No		INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T157,T28,T336	Yes	T157,T28,T336	INPUT
tl_pattgen_i.d_user.rsp_intg[1:0]	Yes	Yes	T157,T28,T336	Yes	T157,T28,T336	INPUT
tl_pattgen_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_pattgen_i.d_user.rsp_intg[5:4]	Yes	Yes	T28,*T157,*T336	Yes	T157,T28,T336	INPUT
tl_pattgen_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T157,T28,T336	Yes	T157,T28,T336	INPUT
tl_pattgen_i.d_sink	No	No		No		INPUT
tl_pattgen_i.d_source[1:0]	Yes	Yes	*T28,*T157,*T336	Yes	T28,T157,T336	INPUT
tl_pattgen_i.d_source[5:2]	No	No		No		INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[0]	No	No		No		INPUT
tl_pattgen_i.d_size[1]	Yes	Yes	T28	Yes	T157,T28,T336	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T157,*T28,*T336	Yes	T157,T28,T336	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T157,T28,T336	Yes	T157,T28,T336	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T313,T314,T100	Yes	T313,T314,T100	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pwm_aon_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_pwm_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pwm_aon_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T313,T314,T100	Yes	T313,T314,T100	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_pwm_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_pwm_aon_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T313,T314,T123	Yes	T313,T314,T123	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T313,T314,T123	Yes	T313,T314,T123	INPUT
tl_pwm_aon_i.d_error	No	No		No		INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T313,T314,T100	Yes	T313,T314,T100	INPUT
tl_pwm_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T313,T314,T100	Yes	T313,T314,T123	INPUT
tl_pwm_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_pwm_aon_i.d_user.rsp_intg[4]	No	No		Yes	T313,T314,T123	INPUT
tl_pwm_aon_i.d_user.rsp_intg[5]	Yes	Yes	*T313,*T314,*T100	Yes	T313,T314,T100	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T313,T314,T100	Yes	T313,T314,T123	INPUT
tl_pwm_aon_i.d_sink	No	No		No		INPUT
tl_pwm_aon_i.d_source[0]	No	No		No		INPUT
tl_pwm_aon_i.d_source[1]	Yes	Yes	*T313,*T314,*T100	Yes	T313,T314,T123	INPUT
tl_pwm_aon_i.d_source[5:2]	No	No		No		INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[0]	No	No		No		INPUT
tl_pwm_aon_i.d_size[1]	No	No		Yes	T313,T314,T123	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T313,*T314,*T100	Yes	T313,T314,T100	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T313,T314,T123	Yes	T313,T314,T123	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_gpio_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_gpio_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_gpio_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_gpio_o.a_opcode[1]	No	No		No		OUTPUT
tl_gpio_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_gpio_i.d_error	No	No		No		INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T46,T225,T56	Yes	T46,T225,T56	INPUT
tl_gpio_i.d_user.rsp_intg[1:0]	Yes	Yes	T46,T225,T56	Yes	T46,T225,T56	INPUT
tl_gpio_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_gpio_i.d_user.rsp_intg[5:4]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_gpio_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T46,T225,T56	Yes	T46,T225,T56	INPUT
tl_gpio_i.d_sink	No	No		No		INPUT
tl_gpio_i.d_source[1:0]	Yes	Yes	*T169,*T17,*T18	Yes	T169,T6,T20	INPUT
tl_gpio_i.d_source[5:2]	No	No		No		INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[0]	No	No		No		INPUT
tl_gpio_i.d_size[1]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T17,*T18,*T19	Yes	T4,T6,T20	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T38,T152,T83	Yes	T38,T152,T83	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_spi_device_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_spi_device_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_device_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T38,T152,T83	Yes	T38,T152,T83	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_spi_device_o.a_opcode[1]	No	No		No		OUTPUT
tl_spi_device_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T38,T152,T83	Yes	T38,T152,T83	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T38,T152,T83	Yes	T38,T152,T83	INPUT
tl_spi_device_i.d_error	No	No		No		INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T38,T152,T83	Yes	T38,T152,T83	INPUT
tl_spi_device_i.d_user.rsp_intg[1:0]	Yes	Yes	T38,T152,T83	Yes	T38,T152,T83	INPUT
tl_spi_device_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_device_i.d_user.rsp_intg[5:4]	Yes	Yes	T38,T152,T83	Yes	T38,T152,T83	INPUT
tl_spi_device_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T38,T152,T83	Yes	T38,T152,T83	INPUT
tl_spi_device_i.d_sink	No	No		No		INPUT
tl_spi_device_i.d_source[1:0]	Yes	Yes	*T28,*T38,*T152	Yes	T28,T38,T152	INPUT
tl_spi_device_i.d_source[5:2]	No	No		No		INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[0]	No	No		No		INPUT
tl_spi_device_i.d_size[1]	Yes	Yes	T38,T152,T83	Yes	T38,T152,T83	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T38,*T152,*T83	Yes	T38,T152,T83	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T38,T152,T83	Yes	T38,T152,T83	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T251,T274,T157	Yes	T251,T274,T157	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_timer_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_rv_timer_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_timer_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T251,T274,T157	Yes	T251,T274,T157	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_rv_timer_o.a_opcode[1]	No	No		No		OUTPUT
tl_rv_timer_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T251,T274,T157	Yes	T251,T274,T157	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T251,T274,T157	Yes	T251,T274,T157	INPUT
tl_rv_timer_i.d_error	No	No		No		INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T251,T274,T157	Yes	T251,T274,T157	INPUT
tl_rv_timer_i.d_user.rsp_intg[1:0]	Yes	Yes	T251,T274,T157	Yes	T251,T274,T157	INPUT
tl_rv_timer_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_timer_i.d_user.rsp_intg[5:4]	Yes	Yes	T28,*T251,*T274	Yes	T251,T274,T157	INPUT
tl_rv_timer_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T251,T274,T331	Yes	T251,T274,T157	INPUT
tl_rv_timer_i.d_sink	No	No		No		INPUT
tl_rv_timer_i.d_source[1:0]	Yes	Yes	*T28,*T251,*T274	Yes	T28,T251,T274	INPUT
tl_rv_timer_i.d_source[5:2]	No	No		No		INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[0]	No	No		No		INPUT
tl_rv_timer_i.d_size[1]	Yes	Yes	T28	Yes	T251,T274,T157	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T251,*T274,*T157	Yes	T251,T274,T157	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T251,T274,T157	Yes	T251,T274,T157	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T18,T251	Yes	T4,T18,T251	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T18,T251	Yes	T4,T18,T251	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_pwrmgr_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T4,T18,T251	Yes	T4,T18,T251	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T4,T18,T251	Yes	T4,T18,T251	INPUT
tl_pwrmgr_aon_i.d_error	No	No		No		INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T337,*T87,*T73	Yes	T4,T18,T251	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T18,T76	Yes	T4,T18,T76	INPUT
tl_pwrmgr_aon_i.d_sink	No	No		No		INPUT
tl_pwrmgr_aon_i.d_source[0]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_source[1]	Yes	Yes	*T4,*T18,*T76	Yes	T4,T18,T251	INPUT
tl_pwrmgr_aon_i.d_source[5:2]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[0]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_size[1]	Yes	Yes	T337,T87,T73	Yes	T4,T18,T251	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T18,*T76	Yes	T4,T18,T251	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T4,T18,T251	Yes	T4,T18,T251	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_rstmgr_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_rstmgr_aon_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rstmgr_aon_i.d_error	No	No		No		INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T17,T18	Yes	T4,T6,T20	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T17,T18	Yes	T4,T6,T20	INPUT
tl_rstmgr_aon_i.d_sink	No	No		No		INPUT
tl_rstmgr_aon_i.d_source[0]	No	No		No		INPUT
tl_rstmgr_aon_i.d_source[1]	Yes	Yes	*T4,*T17,*T18	Yes	T4,T6,T20	INPUT
tl_rstmgr_aon_i.d_source[5:2]	No	No		No		INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[0]	No	No		No		INPUT
tl_rstmgr_aon_i.d_size[1]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_clkmgr_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_clkmgr_aon_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_clkmgr_aon_i.d_error	No	No		No		INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T6,T20,T21	Yes	T4,T6,T20	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	*T17,T18,*T19	Yes	T4,T6,T20	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T6,T20,T21	Yes	T4,T6,T20	INPUT
tl_clkmgr_aon_i.d_sink	No	No		No		INPUT
tl_clkmgr_aon_i.d_source[0]	No	No		No		INPUT
tl_clkmgr_aon_i.d_source[1]	Yes	Yes	*T6,*T20,*T21	Yes	T4,T6,T20	INPUT
tl_clkmgr_aon_i.d_source[5:2]	No	No		No		INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[0]	No	No		No		INPUT
tl_clkmgr_aon_i.d_size[1]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T6,*T20,*T21	Yes	T6,T20,T21	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_pinmux_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_pinmux_aon_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_pinmux_aon_i.d_error	No	No		No		INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T6,T20,T21	Yes	T4,T6,T20	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[2]	No	No		No		INPUT
tl_pinmux_aon_i.d_user.rsp_intg[5:3]	Yes	Yes	*T60,*T61,*T62	Yes	T60,T61,T62	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T6,T20,T21	Yes	T4,T6,T20	INPUT
tl_pinmux_aon_i.d_sink	No	No		No		INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T28,*T4,*T6	Yes	T28,T4,T6	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T6,*T20,*T21	Yes	T6,T20,T21	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_otp_ctrl__core_o.a_opcode[1]	No	No		No		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_otp_ctrl__core_i.d_error	No	No		No		INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[5:4]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_otp_ctrl__core_i.d_sink	No	No		No		INPUT
tl_otp_ctrl__core_i.d_source[1:0]	Yes	Yes	*T81,*T28,*T197	Yes	T81,T28,T197	INPUT
tl_otp_ctrl__core_i.d_source[5:2]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[0]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T36,*T37,*T38	Yes	T36,T37,T38	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T28	Yes	T28	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T28	Yes	T28	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_otp_ctrl__prim_o.a_opcode[1]	No	No		No		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T28	Yes	T28	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T6,T20,T21	Yes	T6,T20,T21	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T6,T20,T21	Yes	T17,T18,T19	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T28	Yes	T28	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[2:0]	Yes	Yes	*T28,*T6,*T20	Yes	T28,T17,T18	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[5:4]	Yes	Yes	*T28,*T17,*T18	Yes	T28,T6,T20	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T6,T20,T21	Yes	T17,T18,T19	INPUT
tl_otp_ctrl__prim_i.d_sink	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_source[0]	Yes	Yes	*T28	Yes	T28	INPUT
tl_otp_ctrl__prim_i.d_source[5:1]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[0]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_size[1]	Yes	Yes	T28	Yes	T28	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T6,*T20,*T21	Yes	T17,T18,T19	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T28	Yes	T28	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T4,T82,T36	Yes	T4,T82,T36	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T4,T82,T36	Yes	T4,T82,T36	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_lc_ctrl_o.a_opcode[1]	No	No		No		OUTPUT
tl_lc_ctrl_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T4,T82,T36	Yes	T4,T82,T36	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T4,T82,T36	Yes	T4,T82,T36	INPUT
tl_lc_ctrl_i.d_error	No	No		No		INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T4,T36,T76	Yes	T4,T36,T76	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[1:0]	Yes	Yes	T36,T37,T78	Yes	T36,T37,T78	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_lc_ctrl_i.d_user.rsp_intg[5:4]	Yes	Yes	T36,T37,T38	Yes	T4,T82,T36	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T4,T36,T76	Yes	T4,T82,T36	INPUT
tl_lc_ctrl_i.d_sink	No	No		No		INPUT
tl_lc_ctrl_i.d_source[1:0]	Yes	Yes	*T28,*T22,*T29	Yes	T28,T22,T29	INPUT
tl_lc_ctrl_i.d_source[5:2]	No	No		No		INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[0]	No	No		No		INPUT
tl_lc_ctrl_i.d_size[1]	Yes	Yes	T36,T37,T38	Yes	T4,T82,T36	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T36,*T37,*T38	Yes	T4,T82,T36	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T4,T82,T36	Yes	T4,T82,T36	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_sensor_ctrl_aon_i.d_error	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T73,T191	Yes	T4,T73,T191	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T73,T191	Yes	T4,T73,T191	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[2]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[5:3]	Yes	Yes	*T60,*T61,*T62	Yes	T60,T61,T62	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T4,T17,T18	Yes	T4,T6,T20	INPUT
tl_sensor_ctrl_aon_i.d_sink	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T28,*T4,*T17	Yes	T28,T4,T6	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T4,*T17,*T18	Yes	T4,T6,T20	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T4,T17,T19	Yes	T4,T17,T19	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_alert_handler_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_alert_handler_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_alert_handler_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T4,T17,T19	Yes	T4,T17,T19	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_alert_handler_o.a_opcode[1]	No	No		No		OUTPUT
tl_alert_handler_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T4,T17,T19	Yes	T4,T17,T19	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T4,T17,T19	Yes	T4,T17,T19	INPUT
tl_alert_handler_i.d_error	No	No		No		INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T4,T17,T19	Yes	T4,T17,T19	INPUT
tl_alert_handler_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T17,T19	Yes	T4,T17,T19	INPUT
tl_alert_handler_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_alert_handler_i.d_user.rsp_intg[5:4]	Yes	Yes	T17,T19,T31	Yes	T4,T17,T19	INPUT
tl_alert_handler_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T4,T17,T19	Yes	T4,T17,T19	INPUT
tl_alert_handler_i.d_sink	No	No		No		INPUT
tl_alert_handler_i.d_source[0]	No	No		No		INPUT
tl_alert_handler_i.d_source[1]	Yes	Yes	*T4,*T17,*T19	Yes	T4,T17,T19	INPUT
tl_alert_handler_i.d_source[5:2]	No	No		No		INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[0]	No	No		No		INPUT
tl_alert_handler_i.d_size[1]	Yes	Yes	T17,T19,T31	Yes	T4,T17,T19	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T17,*T19,*T31	Yes	T4,T17,T19	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T4,T17,T19	Yes	T4,T17,T19	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T187,T94,T95	Yes	T187,T94,T95	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T187,T73,T94	Yes	T4,T76,T77	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	*T73,*T74,*T75	Yes	T4,T76,T77	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T187,T73,T94	Yes	T4,T76,T77	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[1:0]	Yes	Yes	*T28,*T187,*T73	Yes	T28,T4,T77	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1]	Yes	Yes	T73,T74,T75	Yes	T4,T76,T77	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T187,*T94,*T95	Yes	T187,T94,T95	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T4,T76,T77	Yes	T4,T76,T77	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T17,T18	Yes	T4,T17,T18	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T17,T18,T19	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T17,T18	Yes	T4,T17,T18	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[2:0]	Yes	Yes	T4,T17,T18	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[5:4]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T4,T17,T18	Yes	T4,T17,T18	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[1:0]	Yes	Yes	*T23,*T24,*T254	Yes	T23,T24,T254	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T17,T18	Yes	T4,T17,T18	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T4,T17,T18	Yes	T4,T17,T18	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_aon_timer_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_aon_timer_aon_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T4,T17,T18	Yes	T4,T17,T18	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T4,T17,T18	Yes	T4,T17,T18	INPUT
tl_aon_timer_aon_i.d_error	No	No		No		INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T17,T18	Yes	T4,T17,T18	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T17,T18,T19	Yes	T4,T17,T18	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T4,T17,T18	Yes	T4,T17,T18	INPUT
tl_aon_timer_aon_i.d_sink	No	No		No		INPUT
tl_aon_timer_aon_i.d_source[0]	No	No		Yes	T27,T338	INPUT
tl_aon_timer_aon_i.d_source[1]	Yes	Yes	*T4,*T17,*T18	Yes	T4,T17,T18	INPUT
tl_aon_timer_aon_i.d_source[5:2]	No	No		No		INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[0]	No	No		No		INPUT
tl_aon_timer_aon_i.d_size[1]	Yes	Yes	T17,T18,T19	Yes	T4,T17,T18	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T4,*T17,*T18	Yes	T4,T17,T18	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T4,T17,T18	Yes	T4,T17,T18	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T249,T337,T87	Yes	T249,T337,T87	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T249,T337,T87	Yes	T249,T337,T87	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T249,T337,T87	Yes	T249,T337,T87	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T249,T337,T87	Yes	T249,T337,T87	INPUT
tl_sysrst_ctrl_aon_i.d_error	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T249,T337,T87	Yes	T249,T337,T87	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T249,T337,T87	Yes	T249,T337,T87	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T249,T337,T87	Yes	T249,T337,T87	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T249,T337,T87	Yes	T249,T337,T87	INPUT
tl_sysrst_ctrl_aon_i.d_sink	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_source[1:0]	Yes	Yes	*T28,*T168,*T169	Yes	T28,T168,T169	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:2]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[0]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_size[1]	Yes	Yes	T249,T337,T87	Yes	T249,T337,T87	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T249,*T337,*T87	Yes	T249,T337,T87	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T249,T337,T87	Yes	T249,T337,T87	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T99,T8,T225	Yes	T99,T8,T225	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T99,T8,T225	Yes	T99,T8,T225	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_adc_ctrl_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T99,T8,T225	Yes	T99,T8,T225	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T99,T8,T225	Yes	T99,T8,T225	INPUT
tl_adc_ctrl_aon_i.d_error	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[4:0]	Yes	Yes	T99,*T225,*T226	Yes	T99,T8,T225	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[5]	No	Yes	*T99,*T8,*T9	No		INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6]	Yes	Yes	T99,T3,T7	Yes	T99,T3,T7	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T99,T8,T225	Yes	T99,T8,T225	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T8,T9,*T10	Yes	T99,T8,T225	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T99,T8,T9	Yes	T99,T8,T225	INPUT
tl_adc_ctrl_aon_i.d_sink	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_source[0]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_source[1]	Yes	Yes	*T99,*T225,*T100	Yes	T99,T8,T225	INPUT
tl_adc_ctrl_aon_i.d_source[5:2]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[0]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_size[1]	Yes	Yes	T8,T9,T10	Yes	T99,T8,T225	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T99,*T225,*T100	Yes	T99,T8,T225	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T99,T8,T225	Yes	T99,T8,T225	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_ast_o.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	OUTPUT
tl_ast_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_ast_o.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T23,*T24,*T81	Yes	T23,T24,T81	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[0]	Yes	Yes	*T23,*T24,*T28	Yes	T23,T24,T28	OUTPUT
tl_ast_o.a_opcode[1]	No	No		No		OUTPUT
tl_ast_o.a_opcode[2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_ast_i.d_error	No	No		No		INPUT
tl_ast_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_ast_i.d_user.rsp_intg[1:0]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_ast_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_ast_i.d_user.rsp_intg[4]	Yes	Yes	*T17,*T18,*T19	Yes	T4,T6,T20	INPUT
tl_ast_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_ast_i.d_sink	No	No		No		INPUT
tl_ast_i.d_source[0]	No	No		No		INPUT
tl_ast_i.d_source[5:1]	Yes	Yes	*T23,*T73,T24	Yes	T4,T76,T77	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[0]	No	No		No		INPUT
tl_ast_i.d_size[1]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	No	No		No		INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range