Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.62			95.62

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_edn1	92.86			92.86
tb.dut.top_earlgrey.u_edn0	95.53			95.53

---

Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86			92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86			92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	90.68		86.81			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.53			95.53

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.53			95.53

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	90.68		86.81			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	78	63	80.77
Total Bits	1210	1157	95.62
Total Bits 0->1	605	580	95.87
Total Bits 1->0	605	577	95.37

Ports	78	63	80.77
Port Bits	1210	1157	95.62
Port Bits 0->1	605	580	95.87
Port Bits 1->0	605	577	95.37

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_i.a_user.cmd_intg[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_user.cmd_intg[1]	No	No		No		INPUT
tl_i.a_user.cmd_intg[6:2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20:16]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[1:0]	Yes	Yes	*T169,*T4,*T6	Yes	T169,T4,T6	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_i.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_o.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T17,*T18,*T19	Yes	T4,T6,T20	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T169,*T17,*T18	Yes	T169,T4,T6	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T101,*T37,*T103	Yes	T101,T37,T103	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_i[0].edn_req	Yes	Yes	T101,T103,T176	Yes	T101,T103,T176	INPUT
edn_i[1].edn_req	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
edn_i[2].edn_req	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
edn_i[3].edn_req	Yes	Yes	T411,T412,T413	Yes	T411,T412,T413	INPUT
edn_i[4].edn_req	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
edn_i[5].edn_req	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
edn_i[6].edn_req	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
edn_i[7].edn_req	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T101,T103,T176	Yes	T101,T103,T176	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T101,T103,T181	Yes	T101,T103,T181	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T101,T103,T176	Yes	T101,T103,T176	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_o[1].edn_fips	No	No		Yes	T195,T196,T107	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T4,T19,T91	Yes	T4,T19,T91	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T104,T105,T106	Yes	T104,T107,T108	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T411,T412,T414	Yes	T411,T412,T413	OUTPUT
edn_o[3].edn_fips	No	No		Yes	T411,T413,T414	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T411,T412,T413	Yes	T411,T412,T413	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T31,T101,T36	Yes	T91,T31,T101	OUTPUT
edn_o[4].edn_fips	No	No		Yes	T181,T104,T107	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T103,T181,T179	Yes	T103,T181,T179	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T101,T103,T181	Yes	T101,T103,T195	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_o[7].edn_bus[31:0]	Yes	Yes	T4,T17,T19	Yes	T4,T21,T132	OUTPUT
edn_o[7].edn_fips	Yes	Yes	T101,T103,T181	Yes	T101,T103,T181	OUTPUT
edn_o[7].edn_ack	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T101,T415,T416	Yes	T101,T103,T195	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T103,T102,T181	Yes	T103,T102,T181	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T102,T307,T417	Yes	T102,T307,T417	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T131,T33,T418	Yes	T131,T33,T34	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T131,T33,T34	Yes	T131,T33,T418	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T144,T33,T419	Yes	T144,T33,T419	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T33,T378,T34	Yes	T33,T378,T34	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T33,T378,T34	Yes	T33,T378,T34	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T102,T307,T417	Yes	T102,T307,T417	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T144,T33,T419	Yes	T144,T33,T419	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T225,T360,T226	Yes	T225,T360,T226	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T225,T226,T227	Yes	T225,T226,T227	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1

	Total	Covered	Percent
Totals	50	37	74.00
Total Bits	714	663	92.86
Total Bits 0->1	357	332	93.00
Total Bits 1->0	357	331	92.72

Ports	50	37	74.00
Port Bits	714	663	92.86
Port Bits 0->1	357	332	93.00
Port Bits 1->0	357	331	92.72

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_i.a_user.cmd_intg[0]	Yes	Yes	*T101,*T37,*T103	Yes	T101,T37,T103	INPUT
tl_i.a_user.cmd_intg[1]	No	No		No		INPUT
tl_i.a_user.cmd_intg[6:2]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T101,*T37,*T103	Yes	T101,T37,T103	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T101,*T37,*T103	Yes	T101,T37,T103	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20:19]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T101,*T37,*T103	Yes	T101,T37,T103	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T101,*T37,*T103	Yes	T101,T37,T103	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[1:0]	Yes	Yes	*T169,*T101,*T37	Yes	T169,T101,T37	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_i.a_valid	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_o.a_ready	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T37,*T184,*T169	Yes	T101,T37,T103	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T169,*T101,*T37	Yes	T169,T101,T37	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T37,T184,T169	Yes	T101,T37,T103	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T101,*T37,*T103	Yes	T101,T37,T103	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
edn_i[0].edn_req	Yes	Yes	T101,T103,T181	Yes	T101,T103,T181	INPUT
edn_i[1].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[2].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[3].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[4].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[5].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[6].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[7].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_o[0].edn_bus[31:0]	Yes	Yes	T101,T103,T181	Yes	T101,T103,T181	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T101,T103,T181	Yes	T101,T103,T181	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T101,T103,T181	Yes	T101,T103,T181	OUTPUT
edn_o[1].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[1].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[1].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
csrng_cmd_o.genbits_ready	Yes	Yes	T101,T103,T102	Yes	T101,T103,T102	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T101,T103,T102	Yes	T101,T103,T102	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T101,T103,T102	Yes	T101,T103,T102	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T101,T103,T102	Yes	T101,T103,T102	INPUT
csrng_cmd_i.genbits_fips	No	No		Yes	T101,T415,T416	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T101,T103,T102	Yes	T101,T103,T102	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T101,T103,T102	Yes	T101,T103,T102	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T103,T181,T179	Yes	T103,T181,T179	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T131,T33,T123	Yes	T131,T33,T123	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T131,T33,T34	Yes	T131,T33,T34	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T131,T33,T34	Yes	T131,T33,T34	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T33,T378,T123	Yes	T33,T378,T123	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T33,T378,T34	Yes	T378,T34,T35	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T378,T34,T35	Yes	T33,T378,T34	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T131,T33,T123	Yes	T131,T33,T123	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T33,T378,T123	Yes	T33,T378,T123	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T225,T360,T226	Yes	T225,T360,T226	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T225,T226,T227	Yes	T225,T226,T227	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0

	Total	Covered	Percent
Totals	78	62	79.49
Total Bits	1208	1154	95.53
Total Bits 0->1	604	579	95.86
Total Bits 1->0	604	575	95.20

Ports	78	62	79.49
Port Bits	1208	1154	95.53
Port Bits 0->1	604	579	95.86
Port Bits 1->0	604	575	95.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T17,T18,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_i.a_user.cmd_intg[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_user.cmd_intg[1]	No	No		No		INPUT
tl_i.a_user.cmd_intg[6:2]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:16]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T6,*T20	Yes	T4,T6,T20	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[1:0]	Yes	Yes	*T169,*T4,*T6	Yes	T169,T4,T6	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	INPUT
tl_i.a_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_o.a_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T101,T37,T103	Yes	T101,T37,T103	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T17,*T18,*T19	Yes	T4,T6,T20	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T169,*T17,*T18	Yes	T169,T4,T6	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T101,*T37,*T103	Yes	T101,T37,T103	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_i[0].edn_req	Yes	Yes	T176,T25,T186	Yes	T176,T25,T186	INPUT
edn_i[1].edn_req	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
edn_i[2].edn_req	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
edn_i[3].edn_req	Yes	Yes	T411,T412,T413	Yes	T411,T412,T413	INPUT
edn_i[4].edn_req	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
edn_i[5].edn_req	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
edn_i[6].edn_req	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
edn_i[7].edn_req	Yes	Yes	T4,T6,T20	Yes	T4,T5,T6	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T176,T25,T186	Yes	T176,T25,T186	OUTPUT
edn_o[0].edn_fips	No	No		Yes	T305,T308,T317	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T176,T25,T186	Yes	T176,T25,T186	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_o[1].edn_fips	No	No		Yes	T195,T196,T107	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T4,T19,T91	Yes	T4,T19,T91	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T104,T105,T106	Yes	T104,T107,T108	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T411,T412,T414	Yes	T411,T412,T413	OUTPUT
edn_o[3].edn_fips	No	No		Yes	T411,T413,T414	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T411,T412,T413	Yes	T411,T412,T413	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T31,T101,T36	Yes	T91,T31,T101	OUTPUT
edn_o[4].edn_fips	No	No		Yes	T181,T104,T107	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T103,T181,T179	Yes	T103,T181,T179	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T101,T103,T181	Yes	T101,T103,T195	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
edn_o[7].edn_bus[31:0]	Yes	Yes	T4,T17,T19	Yes	T4,T21,T132	OUTPUT
edn_o[7].edn_fips	Yes	Yes	T101,T103,T181	Yes	T101,T103,T181	OUTPUT
edn_o[7].edn_ack	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T17,T18,T19	Yes	T4,T6,T20	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T101,T415,T416	Yes	T101,T103,T195	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T103,T102,T181	Yes	T103,T102,T181	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T102,T307,T417	Yes	T102,T307,T417	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T33,T418,T34	Yes	T34,T35,T402	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T34,T35,T402	Yes	T33,T418,T34	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T144,T33,T419	Yes	T144,T33,T419	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T102,T307,T417	Yes	T102,T307,T417	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T144,T33,T419	Yes	T144,T33,T419	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T225,T360,T226	Yes	T225,T360,T226	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T225,T226,T227	Yes	T225,T226,T227	OUTPUT

*Tests covering at least one bit in the range