| T407 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.783274222 |
|
|
Jul 04 08:19:49 PM PDT 24 |
Jul 04 08:32:25 PM PDT 24 |
6167726358 ps |
| T408 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1668216787 |
|
|
Jul 04 08:19:40 PM PDT 24 |
Jul 04 08:25:44 PM PDT 24 |
3961732256 ps |
| T220 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2069467747 |
|
|
Jul 04 07:48:16 PM PDT 24 |
Jul 04 08:14:59 PM PDT 24 |
8385636556 ps |
| T221 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3024382471 |
|
|
Jul 04 08:07:14 PM PDT 24 |
Jul 04 08:59:43 PM PDT 24 |
12122362060 ps |
| T409 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.4257149304 |
|
|
Jul 04 07:51:21 PM PDT 24 |
Jul 04 07:55:25 PM PDT 24 |
2448500600 ps |
| T164 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.748981100 |
|
|
Jul 04 08:19:55 PM PDT 24 |
Jul 04 08:30:56 PM PDT 24 |
5393775740 ps |
| T410 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2713124770 |
|
|
Jul 04 08:22:37 PM PDT 24 |
Jul 04 08:30:39 PM PDT 24 |
4062656412 ps |
| T341 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2357887805 |
|
|
Jul 04 08:02:21 PM PDT 24 |
Jul 04 08:14:59 PM PDT 24 |
3810609832 ps |
| T411 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3671807279 |
|
|
Jul 04 07:57:59 PM PDT 24 |
Jul 04 08:04:34 PM PDT 24 |
4102436336 ps |
| T911 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2200079387 |
|
|
Jul 04 08:04:55 PM PDT 24 |
Jul 04 08:42:29 PM PDT 24 |
29765046397 ps |
| T912 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.968309437 |
|
|
Jul 04 07:49:20 PM PDT 24 |
Jul 04 07:55:06 PM PDT 24 |
3623089350 ps |
| T57 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.1060137261 |
|
|
Jul 04 07:54:10 PM PDT 24 |
Jul 04 08:56:53 PM PDT 24 |
25646401920 ps |
| T356 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2717137636 |
|
|
Jul 04 07:54:00 PM PDT 24 |
Jul 04 08:04:55 PM PDT 24 |
3552459850 ps |
| T780 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1705319757 |
|
|
Jul 04 08:15:11 PM PDT 24 |
Jul 04 08:20:33 PM PDT 24 |
3144212272 ps |
| T775 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3709641700 |
|
|
Jul 04 08:14:29 PM PDT 24 |
Jul 04 08:21:24 PM PDT 24 |
4094820376 ps |
| T688 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.459086453 |
|
|
Jul 04 08:04:18 PM PDT 24 |
Jul 04 08:05:51 PM PDT 24 |
2186637720 ps |
| T913 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3275237853 |
|
|
Jul 04 07:57:11 PM PDT 24 |
Jul 04 08:47:30 PM PDT 24 |
11669169700 ps |
| T155 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.860897348 |
|
|
Jul 04 07:57:23 PM PDT 24 |
Jul 04 08:07:02 PM PDT 24 |
3737174020 ps |
| T400 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.774099882 |
|
|
Jul 04 08:06:54 PM PDT 24 |
Jul 04 08:10:57 PM PDT 24 |
2618940528 ps |
| T914 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3534580060 |
|
|
Jul 04 07:58:46 PM PDT 24 |
Jul 04 08:12:20 PM PDT 24 |
5134064320 ps |
| T32 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.4015327834 |
|
|
Jul 04 08:02:54 PM PDT 24 |
Jul 04 08:10:53 PM PDT 24 |
5038224496 ps |
| T915 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.2911587410 |
|
|
Jul 04 07:47:55 PM PDT 24 |
Jul 04 08:08:35 PM PDT 24 |
6135601096 ps |
| T916 |
/workspace/coverage/default/1.chip_sw_aes_enc.3795472593 |
|
|
Jul 04 07:57:08 PM PDT 24 |
Jul 04 08:03:29 PM PDT 24 |
3273274026 ps |
| T917 |
/workspace/coverage/default/1.rom_e2e_smoke.3236315223 |
|
|
Jul 04 08:06:54 PM PDT 24 |
Jul 04 09:03:19 PM PDT 24 |
14655588442 ps |
| T918 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1676946732 |
|
|
Jul 04 07:53:58 PM PDT 24 |
Jul 04 08:15:07 PM PDT 24 |
8357199676 ps |
| T748 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2122207656 |
|
|
Jul 04 08:18:30 PM PDT 24 |
Jul 04 08:29:47 PM PDT 24 |
6440428592 ps |
| T919 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.223573513 |
|
|
Jul 04 07:49:24 PM PDT 24 |
Jul 04 07:54:33 PM PDT 24 |
2716086810 ps |
| T920 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.267907908 |
|
|
Jul 04 07:58:13 PM PDT 24 |
Jul 04 09:04:13 PM PDT 24 |
15128430735 ps |
| T921 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.909382466 |
|
|
Jul 04 07:56:03 PM PDT 24 |
Jul 04 08:00:25 PM PDT 24 |
3142438840 ps |
| T26 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1995060230 |
|
|
Jul 04 07:52:22 PM PDT 24 |
Jul 04 08:04:03 PM PDT 24 |
6672774788 ps |
| T83 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.2164744314 |
|
|
Jul 04 07:55:08 PM PDT 24 |
Jul 04 07:59:54 PM PDT 24 |
3115081837 ps |
| T517 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3875434924 |
|
|
Jul 04 08:05:17 PM PDT 24 |
Jul 04 08:33:58 PM PDT 24 |
12615494133 ps |
| T151 |
/workspace/coverage/default/1.rom_raw_unlock.3518300613 |
|
|
Jul 04 08:01:23 PM PDT 24 |
Jul 04 08:05:37 PM PDT 24 |
4708681034 ps |
| T68 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.2789920431 |
|
|
Jul 04 08:11:31 PM PDT 24 |
Jul 04 08:26:17 PM PDT 24 |
7262447570 ps |
| T922 |
/workspace/coverage/default/0.rom_e2e_static_critical.456506917 |
|
|
Jul 04 07:56:29 PM PDT 24 |
Jul 04 09:21:25 PM PDT 24 |
16978021318 ps |
| T34 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.4151805280 |
|
|
Jul 04 08:06:44 PM PDT 24 |
Jul 04 08:11:09 PM PDT 24 |
3037654536 ps |
| T247 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.4203006430 |
|
|
Jul 04 08:06:39 PM PDT 24 |
Jul 04 08:10:40 PM PDT 24 |
3102863664 ps |
| T724 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.1725394818 |
|
|
Jul 04 08:15:31 PM PDT 24 |
Jul 04 08:24:34 PM PDT 24 |
5277882912 ps |
| T753 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2423969988 |
|
|
Jul 04 08:17:49 PM PDT 24 |
Jul 04 08:23:09 PM PDT 24 |
3785939204 ps |
| T923 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.779266001 |
|
|
Jul 04 08:09:35 PM PDT 24 |
Jul 04 08:14:46 PM PDT 24 |
3621895566 ps |
| T344 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2954615955 |
|
|
Jul 04 07:47:34 PM PDT 24 |
Jul 04 08:03:12 PM PDT 24 |
4895939760 ps |
| T99 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4167466190 |
|
|
Jul 04 08:00:28 PM PDT 24 |
Jul 04 08:31:31 PM PDT 24 |
20819670512 ps |
| T924 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2450181089 |
|
|
Jul 04 07:57:51 PM PDT 24 |
Jul 04 09:04:21 PM PDT 24 |
14673411730 ps |
| T925 |
/workspace/coverage/default/0.chip_sw_aes_entropy.2530393170 |
|
|
Jul 04 07:52:24 PM PDT 24 |
Jul 04 07:57:53 PM PDT 24 |
3512865832 ps |
| T760 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.472283391 |
|
|
Jul 04 08:20:02 PM PDT 24 |
Jul 04 08:26:10 PM PDT 24 |
3134795240 ps |
| T926 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.553929128 |
|
|
Jul 04 07:53:41 PM PDT 24 |
Jul 04 08:09:37 PM PDT 24 |
5559029410 ps |
| T927 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1448547697 |
|
|
Jul 04 07:50:38 PM PDT 24 |
Jul 04 08:00:16 PM PDT 24 |
4912007082 ps |
| T238 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.1621958253 |
|
|
Jul 04 08:18:33 PM PDT 24 |
Jul 04 08:29:38 PM PDT 24 |
4652860750 ps |
| T264 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.3385431568 |
|
|
Jul 04 08:13:46 PM PDT 24 |
Jul 04 09:21:19 PM PDT 24 |
15126878584 ps |
| T265 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.116913963 |
|
|
Jul 04 07:56:12 PM PDT 24 |
Jul 04 08:03:11 PM PDT 24 |
4052196486 ps |
| T266 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.2417034338 |
|
|
Jul 04 07:56:12 PM PDT 24 |
Jul 04 08:34:17 PM PDT 24 |
9012579290 ps |
| T267 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2885935447 |
|
|
Jul 04 07:59:12 PM PDT 24 |
Jul 04 08:06:31 PM PDT 24 |
5557383270 ps |
| T268 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.3312766337 |
|
|
Jul 04 08:15:41 PM PDT 24 |
Jul 04 08:25:47 PM PDT 24 |
3992841032 ps |
| T269 |
/workspace/coverage/default/2.rom_raw_unlock.3259182257 |
|
|
Jul 04 08:09:49 PM PDT 24 |
Jul 04 08:14:19 PM PDT 24 |
6473978927 ps |
| T270 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.711173552 |
|
|
Jul 04 08:06:41 PM PDT 24 |
Jul 04 08:22:09 PM PDT 24 |
7531979836 ps |
| T271 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.3507538091 |
|
|
Jul 04 07:47:30 PM PDT 24 |
Jul 04 07:59:46 PM PDT 24 |
4635603076 ps |
| T272 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.2689457727 |
|
|
Jul 04 07:48:49 PM PDT 24 |
Jul 04 08:08:37 PM PDT 24 |
4608406288 ps |
| T749 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1665605521 |
|
|
Jul 04 08:14:32 PM PDT 24 |
Jul 04 08:20:43 PM PDT 24 |
3503550796 ps |
| T928 |
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1072930336 |
|
|
Jul 04 08:12:51 PM PDT 24 |
Jul 04 09:14:41 PM PDT 24 |
18811647710 ps |
| T929 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.191051751 |
|
|
Jul 04 07:57:25 PM PDT 24 |
Jul 04 08:55:02 PM PDT 24 |
10785020992 ps |
| T133 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1442036933 |
|
|
Jul 04 08:12:04 PM PDT 24 |
Jul 04 08:29:02 PM PDT 24 |
9230844664 ps |
| T225 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.197086284 |
|
|
Jul 04 08:06:02 PM PDT 24 |
Jul 04 08:27:01 PM PDT 24 |
7147104136 ps |
| T723 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.4106972432 |
|
|
Jul 04 08:18:38 PM PDT 24 |
Jul 04 08:31:56 PM PDT 24 |
4521005200 ps |
| T930 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3851093006 |
|
|
Jul 04 08:06:28 PM PDT 24 |
Jul 04 08:14:32 PM PDT 24 |
4926979320 ps |
| T229 |
/workspace/coverage/default/2.chip_sw_flash_init.1084428991 |
|
|
Jul 04 08:02:50 PM PDT 24 |
Jul 04 08:28:30 PM PDT 24 |
16174228476 ps |
| T379 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3365098741 |
|
|
Jul 04 08:07:42 PM PDT 24 |
Jul 04 08:16:00 PM PDT 24 |
6525814408 ps |
| T931 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1776193438 |
|
|
Jul 04 08:07:42 PM PDT 24 |
Jul 04 08:16:42 PM PDT 24 |
4563572770 ps |
| T932 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2890585634 |
|
|
Jul 04 07:56:43 PM PDT 24 |
Jul 04 07:59:59 PM PDT 24 |
3304722710 ps |
| T933 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1462627962 |
|
|
Jul 04 07:48:33 PM PDT 24 |
Jul 04 07:56:36 PM PDT 24 |
7355970556 ps |
| T934 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2957989763 |
|
|
Jul 04 08:18:28 PM PDT 24 |
Jul 04 08:27:48 PM PDT 24 |
5771921720 ps |
| T317 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3301232279 |
|
|
Jul 04 08:19:11 PM PDT 24 |
Jul 04 08:25:58 PM PDT 24 |
3762149140 ps |
| T935 |
/workspace/coverage/default/0.chip_sw_example_rom.1089449253 |
|
|
Jul 04 07:45:35 PM PDT 24 |
Jul 04 07:47:50 PM PDT 24 |
2055018216 ps |
| T936 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.242559004 |
|
|
Jul 04 07:52:38 PM PDT 24 |
Jul 04 08:02:29 PM PDT 24 |
8986491094 ps |
| T937 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2332691355 |
|
|
Jul 04 07:59:56 PM PDT 24 |
Jul 04 08:21:08 PM PDT 24 |
7310362741 ps |
| T177 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.289638549 |
|
|
Jul 04 08:13:15 PM PDT 24 |
Jul 04 08:17:27 PM PDT 24 |
2916744570 ps |
| T197 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2939513634 |
|
|
Jul 04 07:47:02 PM PDT 24 |
Jul 04 11:47:53 PM PDT 24 |
78486373558 ps |
| T938 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.168484947 |
|
|
Jul 04 08:12:58 PM PDT 24 |
Jul 04 09:15:17 PM PDT 24 |
14042500698 ps |
| T939 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.74215481 |
|
|
Jul 04 08:03:29 PM PDT 24 |
Jul 04 08:22:52 PM PDT 24 |
8249937980 ps |
| T675 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1804816822 |
|
|
Jul 04 08:18:42 PM PDT 24 |
Jul 04 08:27:45 PM PDT 24 |
4902022030 ps |
| T436 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3815153596 |
|
|
Jul 04 07:57:55 PM PDT 24 |
Jul 04 08:15:12 PM PDT 24 |
6421792012 ps |
| T721 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2930717853 |
|
|
Jul 04 08:19:36 PM PDT 24 |
Jul 04 08:29:42 PM PDT 24 |
5082545124 ps |
| T39 |
/workspace/coverage/default/1.chip_sw_gpio.956990474 |
|
|
Jul 04 07:54:10 PM PDT 24 |
Jul 04 08:01:08 PM PDT 24 |
3584427796 ps |
| T940 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2931660024 |
|
|
Jul 04 07:49:30 PM PDT 24 |
Jul 04 07:59:30 PM PDT 24 |
5437739160 ps |
| T358 |
/workspace/coverage/default/2.chip_sival_flash_info_access.353787092 |
|
|
Jul 04 08:01:36 PM PDT 24 |
Jul 04 08:06:07 PM PDT 24 |
2831721250 ps |
| T941 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1247750619 |
|
|
Jul 04 07:53:21 PM PDT 24 |
Jul 04 08:16:44 PM PDT 24 |
7236801960 ps |
| T942 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2600770761 |
|
|
Jul 04 07:53:23 PM PDT 24 |
Jul 04 08:01:38 PM PDT 24 |
4316102773 ps |
| T943 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1230852254 |
|
|
Jul 04 07:55:19 PM PDT 24 |
Jul 04 08:02:59 PM PDT 24 |
5378882104 ps |
| T307 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1870696795 |
|
|
Jul 04 08:09:38 PM PDT 24 |
Jul 04 08:21:39 PM PDT 24 |
7879984964 ps |
| T243 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2792707902 |
|
|
Jul 04 08:16:49 PM PDT 24 |
Jul 04 08:22:27 PM PDT 24 |
4121495246 ps |
| T944 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.459948090 |
|
|
Jul 04 07:48:00 PM PDT 24 |
Jul 04 07:58:22 PM PDT 24 |
4021895334 ps |
| T945 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2290407646 |
|
|
Jul 04 08:07:04 PM PDT 24 |
Jul 04 08:31:17 PM PDT 24 |
13520288394 ps |
| T946 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3536529896 |
|
|
Jul 04 07:57:59 PM PDT 24 |
Jul 04 08:04:30 PM PDT 24 |
3375986980 ps |
| T798 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3094676862 |
|
|
Jul 04 08:19:51 PM PDT 24 |
Jul 04 08:28:05 PM PDT 24 |
4348290326 ps |
| T947 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.3093522121 |
|
|
Jul 04 08:11:07 PM PDT 24 |
Jul 04 08:18:32 PM PDT 24 |
3322161680 ps |
| T159 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1780919362 |
|
|
Jul 04 08:06:18 PM PDT 24 |
Jul 04 08:08:13 PM PDT 24 |
2184694048 ps |
| T729 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.383182747 |
|
|
Jul 04 08:17:21 PM PDT 24 |
Jul 04 08:22:24 PM PDT 24 |
3621988960 ps |
| T948 |
/workspace/coverage/default/2.rom_keymgr_functest.683610845 |
|
|
Jul 04 08:09:00 PM PDT 24 |
Jul 04 08:17:27 PM PDT 24 |
4219536048 ps |
| T949 |
/workspace/coverage/default/0.chip_sw_aes_enc.1894417453 |
|
|
Jul 04 07:52:28 PM PDT 24 |
Jul 04 07:57:41 PM PDT 24 |
2610657268 ps |
| T35 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3287061075 |
|
|
Jul 04 07:54:13 PM PDT 24 |
Jul 04 08:00:21 PM PDT 24 |
3765544904 ps |
| T72 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.3292056294 |
|
|
Jul 04 07:51:06 PM PDT 24 |
Jul 04 08:02:26 PM PDT 24 |
7188231541 ps |
| T348 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1472907437 |
|
|
Jul 04 08:11:38 PM PDT 24 |
Jul 04 08:15:25 PM PDT 24 |
2580210052 ps |
| T950 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2797157615 |
|
|
Jul 04 08:07:47 PM PDT 24 |
Jul 04 08:39:15 PM PDT 24 |
8901964008 ps |
| T354 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1608656912 |
|
|
Jul 04 07:48:40 PM PDT 24 |
Jul 04 08:00:23 PM PDT 24 |
3440246212 ps |
| T951 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3993894543 |
|
|
Jul 04 07:48:50 PM PDT 24 |
Jul 04 07:52:25 PM PDT 24 |
3355468097 ps |
| T952 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.4168388294 |
|
|
Jul 04 08:11:35 PM PDT 24 |
Jul 04 08:20:23 PM PDT 24 |
4059539456 ps |
| T382 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2539579015 |
|
|
Jul 04 08:20:29 PM PDT 24 |
Jul 04 08:31:32 PM PDT 24 |
4758337646 ps |
| T953 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2899738098 |
|
|
Jul 04 08:04:11 PM PDT 24 |
Jul 04 08:13:55 PM PDT 24 |
4813020104 ps |
| T693 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.683517228 |
|
|
Jul 04 07:48:58 PM PDT 24 |
Jul 04 07:54:43 PM PDT 24 |
3005863988 ps |
| T954 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3910716100 |
|
|
Jul 04 07:59:23 PM PDT 24 |
Jul 04 08:06:26 PM PDT 24 |
5393457196 ps |
| T397 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.2517462731 |
|
|
Jul 04 07:49:25 PM PDT 24 |
Jul 04 07:59:43 PM PDT 24 |
3040098654 ps |
| T955 |
/workspace/coverage/default/1.chip_sw_example_flash.2562800405 |
|
|
Jul 04 07:53:40 PM PDT 24 |
Jul 04 07:57:19 PM PDT 24 |
2359308308 ps |
| T956 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2200672756 |
|
|
Jul 04 08:05:27 PM PDT 24 |
Jul 04 08:16:21 PM PDT 24 |
5347444320 ps |
| T314 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.860868869 |
|
|
Jul 04 07:50:38 PM PDT 24 |
Jul 04 08:03:13 PM PDT 24 |
4665096680 ps |
| T957 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1865401135 |
|
|
Jul 04 07:54:51 PM PDT 24 |
Jul 04 08:04:58 PM PDT 24 |
4966695240 ps |
| T36 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.948146244 |
|
|
Jul 04 07:48:20 PM PDT 24 |
Jul 04 09:00:11 PM PDT 24 |
18487154040 ps |
| T958 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.2151978088 |
|
|
Jul 04 08:01:06 PM PDT 24 |
Jul 04 08:08:03 PM PDT 24 |
2927184760 ps |
| T959 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.970281678 |
|
|
Jul 04 07:52:01 PM PDT 24 |
Jul 04 08:12:45 PM PDT 24 |
7005657849 ps |
| T960 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.3876089646 |
|
|
Jul 04 08:05:06 PM PDT 24 |
Jul 04 08:13:31 PM PDT 24 |
4067165728 ps |
| T961 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2932205418 |
|
|
Jul 04 08:13:11 PM PDT 24 |
Jul 04 08:53:57 PM PDT 24 |
13424381846 ps |
| T962 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1949846816 |
|
|
Jul 04 07:54:55 PM PDT 24 |
Jul 04 08:18:39 PM PDT 24 |
7268112688 ps |
| T963 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3427927837 |
|
|
Jul 04 07:53:06 PM PDT 24 |
Jul 04 07:57:31 PM PDT 24 |
2565869120 ps |
| T964 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2171460480 |
|
|
Jul 04 07:48:26 PM PDT 24 |
Jul 04 07:56:27 PM PDT 24 |
6039591223 ps |
| T751 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3388104726 |
|
|
Jul 04 08:16:37 PM PDT 24 |
Jul 04 08:22:32 PM PDT 24 |
4178415992 ps |
| T965 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3570715025 |
|
|
Jul 04 07:56:05 PM PDT 24 |
Jul 04 08:47:59 PM PDT 24 |
14870287490 ps |
| T100 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1834887636 |
|
|
Jul 04 08:07:44 PM PDT 24 |
Jul 04 08:41:36 PM PDT 24 |
24651437854 ps |
| T966 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1609021168 |
|
|
Jul 04 07:51:08 PM PDT 24 |
Jul 04 08:24:28 PM PDT 24 |
8587439591 ps |
| T967 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.962804246 |
|
|
Jul 04 08:06:02 PM PDT 24 |
Jul 04 09:00:01 PM PDT 24 |
15085956036 ps |
| T968 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2336475796 |
|
|
Jul 04 07:47:54 PM PDT 24 |
Jul 04 07:57:53 PM PDT 24 |
5145640534 ps |
| T714 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1929690985 |
|
|
Jul 04 08:18:51 PM PDT 24 |
Jul 04 08:24:02 PM PDT 24 |
3677083040 ps |
| T969 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.690168958 |
|
|
Jul 04 08:07:22 PM PDT 24 |
Jul 04 08:13:10 PM PDT 24 |
3366344344 ps |
| T730 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2964680701 |
|
|
Jul 04 07:58:55 PM PDT 24 |
Jul 04 08:06:21 PM PDT 24 |
3813035383 ps |
| T805 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3679018048 |
|
|
Jul 04 08:19:51 PM PDT 24 |
Jul 04 08:25:44 PM PDT 24 |
3657288824 ps |
| T239 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.815965684 |
|
|
Jul 04 08:06:00 PM PDT 24 |
Jul 04 08:18:49 PM PDT 24 |
6216521400 ps |
| T970 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.208615885 |
|
|
Jul 04 08:10:06 PM PDT 24 |
Jul 04 08:14:36 PM PDT 24 |
2635239368 ps |
| T689 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.2364822922 |
|
|
Jul 04 08:01:42 PM PDT 24 |
Jul 04 08:03:36 PM PDT 24 |
2494569893 ps |
| T178 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.942401851 |
|
|
Jul 04 08:07:56 PM PDT 24 |
Jul 04 08:13:24 PM PDT 24 |
3453461834 ps |
| T971 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3783697316 |
|
|
Jul 04 07:55:56 PM PDT 24 |
Jul 04 08:33:34 PM PDT 24 |
8545473928 ps |
| T248 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.2880657092 |
|
|
Jul 04 07:58:30 PM PDT 24 |
Jul 04 08:02:32 PM PDT 24 |
3406768798 ps |
| T230 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.597968475 |
|
|
Jul 04 07:50:57 PM PDT 24 |
Jul 04 08:25:55 PM PDT 24 |
21383053195 ps |
| T972 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1720268137 |
|
|
Jul 04 08:08:59 PM PDT 24 |
Jul 04 08:20:34 PM PDT 24 |
4288239802 ps |
| T973 |
/workspace/coverage/default/0.chip_sw_hmac_oneshot.2577753723 |
|
|
Jul 04 07:49:24 PM PDT 24 |
Jul 04 07:56:27 PM PDT 24 |
3081608084 ps |
| T974 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3087755833 |
|
|
Jul 04 08:13:17 PM PDT 24 |
Jul 04 08:24:09 PM PDT 24 |
4735571012 ps |
| T975 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2934870313 |
|
|
Jul 04 07:46:35 PM PDT 24 |
Jul 04 07:59:00 PM PDT 24 |
10264218862 ps |
| T976 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1250798461 |
|
|
Jul 04 07:52:45 PM PDT 24 |
Jul 04 08:02:21 PM PDT 24 |
4415347126 ps |
| T977 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1755327014 |
|
|
Jul 04 07:49:57 PM PDT 24 |
Jul 04 08:17:01 PM PDT 24 |
6681736782 ps |
| T198 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2434271084 |
|
|
Jul 04 08:05:53 PM PDT 24 |
Jul 04 11:02:23 PM PDT 24 |
58121413540 ps |
| T234 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1926655721 |
|
|
Jul 04 07:49:35 PM PDT 24 |
Jul 04 07:58:35 PM PDT 24 |
4434620290 ps |
| T180 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.134110200 |
|
|
Jul 04 07:48:46 PM PDT 24 |
Jul 04 09:30:06 PM PDT 24 |
42555925425 ps |
| T719 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1884842495 |
|
|
Jul 04 08:21:18 PM PDT 24 |
Jul 04 08:27:29 PM PDT 24 |
3689488460 ps |
| T339 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.369053228 |
|
|
Jul 04 08:13:59 PM PDT 24 |
Jul 04 08:23:09 PM PDT 24 |
3832288572 ps |
| T282 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3915330957 |
|
|
Jul 04 08:13:00 PM PDT 24 |
Jul 04 08:26:03 PM PDT 24 |
5413893028 ps |
| T978 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1881914954 |
|
|
Jul 04 08:13:51 PM PDT 24 |
Jul 04 08:30:53 PM PDT 24 |
14046699880 ps |
| T141 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3866450141 |
|
|
Jul 04 07:52:14 PM PDT 24 |
Jul 04 07:56:56 PM PDT 24 |
2572374934 ps |
| T979 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3869720165 |
|
|
Jul 04 08:05:54 PM PDT 24 |
Jul 04 09:04:13 PM PDT 24 |
15450455380 ps |
| T715 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.900927091 |
|
|
Jul 04 08:17:54 PM PDT 24 |
Jul 04 08:25:26 PM PDT 24 |
4141649762 ps |
| T372 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.781266911 |
|
|
Jul 04 07:57:03 PM PDT 24 |
Jul 04 08:29:15 PM PDT 24 |
21095050228 ps |
| T283 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.527359798 |
|
|
Jul 04 08:01:45 PM PDT 24 |
Jul 04 08:13:58 PM PDT 24 |
5057984262 ps |
| T396 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3492239284 |
|
|
Jul 04 08:01:32 PM PDT 24 |
Jul 04 09:43:21 PM PDT 24 |
18666217376 ps |
| T37 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3246764656 |
|
|
Jul 04 07:48:25 PM PDT 24 |
Jul 04 09:41:59 PM PDT 24 |
31757060440 ps |
| T254 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3481149173 |
|
|
Jul 04 08:13:37 PM PDT 24 |
Jul 04 08:21:38 PM PDT 24 |
4863351176 ps |
| T727 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1402560299 |
|
|
Jul 04 08:19:26 PM PDT 24 |
Jul 04 08:29:50 PM PDT 24 |
6193414832 ps |
| T222 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2262267018 |
|
|
Jul 04 07:50:32 PM PDT 24 |
Jul 04 08:28:46 PM PDT 24 |
10010345532 ps |
| T980 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2472296770 |
|
|
Jul 04 07:47:00 PM PDT 24 |
Jul 04 08:09:45 PM PDT 24 |
9037734208 ps |
| T404 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1900970987 |
|
|
Jul 04 07:56:55 PM PDT 24 |
Jul 04 08:00:30 PM PDT 24 |
3744472716 ps |
| T340 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.3694330348 |
|
|
Jul 04 08:03:52 PM PDT 24 |
Jul 04 08:14:08 PM PDT 24 |
4298788294 ps |
| T981 |
/workspace/coverage/default/1.chip_sw_example_rom.506697880 |
|
|
Jul 04 07:50:53 PM PDT 24 |
Jul 04 07:53:09 PM PDT 24 |
1957857414 ps |
| T982 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1351330411 |
|
|
Jul 04 07:58:23 PM PDT 24 |
Jul 04 08:03:48 PM PDT 24 |
3576589916 ps |
| T983 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3720641122 |
|
|
Jul 04 07:58:53 PM PDT 24 |
Jul 04 09:00:37 PM PDT 24 |
14551802800 ps |
| T728 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2163501469 |
|
|
Jul 04 07:54:24 PM PDT 24 |
Jul 04 08:10:20 PM PDT 24 |
6756125076 ps |
| T984 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.207618629 |
|
|
Jul 04 08:07:05 PM PDT 24 |
Jul 04 08:24:33 PM PDT 24 |
5355447240 ps |
| T204 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.4164451778 |
|
|
Jul 04 07:55:01 PM PDT 24 |
Jul 04 08:48:39 PM PDT 24 |
20350836317 ps |
| T54 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.1010169790 |
|
|
Jul 04 08:04:50 PM PDT 24 |
Jul 04 08:10:30 PM PDT 24 |
2682569833 ps |
| T686 |
/workspace/coverage/default/2.chip_tap_straps_dev.2109013545 |
|
|
Jul 04 08:12:53 PM PDT 24 |
Jul 04 08:41:20 PM PDT 24 |
18094624448 ps |
| T985 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3679335508 |
|
|
Jul 04 08:10:45 PM PDT 24 |
Jul 04 08:30:36 PM PDT 24 |
9377489293 ps |
| T986 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2482788546 |
|
|
Jul 04 08:04:53 PM PDT 24 |
Jul 04 08:34:45 PM PDT 24 |
12577459041 ps |
| T101 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2696005229 |
|
|
Jul 04 08:01:59 PM PDT 24 |
Jul 04 08:11:11 PM PDT 24 |
7041501300 ps |
| T987 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3188953837 |
|
|
Jul 04 07:52:34 PM PDT 24 |
Jul 04 08:07:21 PM PDT 24 |
9035620152 ps |
| T128 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.434087274 |
|
|
Jul 04 08:09:17 PM PDT 24 |
Jul 04 08:16:36 PM PDT 24 |
5085054662 ps |
| T988 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1530003048 |
|
|
Jul 04 08:08:51 PM PDT 24 |
Jul 04 08:18:16 PM PDT 24 |
5882667392 ps |
| T240 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.1435977939 |
|
|
Jul 04 08:14:35 PM PDT 24 |
Jul 04 08:22:48 PM PDT 24 |
5125751878 ps |
| T989 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2381566021 |
|
|
Jul 04 08:07:42 PM PDT 24 |
Jul 04 08:33:18 PM PDT 24 |
7368010976 ps |
| T990 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1009830906 |
|
|
Jul 04 08:12:48 PM PDT 24 |
Jul 04 08:26:04 PM PDT 24 |
4082088056 ps |
| T991 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.165425773 |
|
|
Jul 04 07:55:24 PM PDT 24 |
Jul 04 08:00:05 PM PDT 24 |
2858294440 ps |
| T129 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3591308815 |
|
|
Jul 04 08:12:15 PM PDT 24 |
Jul 04 08:20:36 PM PDT 24 |
7152888024 ps |
| T297 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3259089542 |
|
|
Jul 04 07:52:14 PM PDT 24 |
Jul 04 07:57:36 PM PDT 24 |
2873370911 ps |
| T992 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.31792465 |
|
|
Jul 04 07:57:01 PM PDT 24 |
Jul 04 08:05:28 PM PDT 24 |
4298397500 ps |
| T694 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2873362989 |
|
|
Jul 04 08:04:24 PM PDT 24 |
Jul 04 08:09:08 PM PDT 24 |
2553469760 ps |
| T993 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.270281304 |
|
|
Jul 04 07:52:58 PM PDT 24 |
Jul 04 07:57:52 PM PDT 24 |
6151979884 ps |
| T716 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2612560085 |
|
|
Jul 04 08:17:44 PM PDT 24 |
Jul 04 08:24:55 PM PDT 24 |
3716320740 ps |
| T329 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.4220170552 |
|
|
Jul 04 08:10:55 PM PDT 24 |
Jul 04 08:27:29 PM PDT 24 |
6432142604 ps |
| T712 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.4049286456 |
|
|
Jul 04 08:18:00 PM PDT 24 |
Jul 04 08:30:26 PM PDT 24 |
6199625016 ps |
| T223 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2504070127 |
|
|
Jul 04 08:07:45 PM PDT 24 |
Jul 04 08:47:06 PM PDT 24 |
12931147496 ps |
| T355 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4166042783 |
|
|
Jul 04 08:14:16 PM PDT 24 |
Jul 04 08:24:47 PM PDT 24 |
4950933288 ps |
| T994 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2772309859 |
|
|
Jul 04 07:50:57 PM PDT 24 |
Jul 04 07:54:47 PM PDT 24 |
2715774088 ps |
| T995 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.1912996437 |
|
|
Jul 04 07:59:47 PM PDT 24 |
Jul 04 09:27:13 PM PDT 24 |
15879006360 ps |
| T996 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.320007590 |
|
|
Jul 04 08:08:49 PM PDT 24 |
Jul 04 08:16:58 PM PDT 24 |
5136163368 ps |
| T997 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.336474150 |
|
|
Jul 04 08:11:17 PM PDT 24 |
Jul 04 08:20:14 PM PDT 24 |
6321737824 ps |
| T998 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3174096931 |
|
|
Jul 04 07:51:37 PM PDT 24 |
Jul 04 08:06:20 PM PDT 24 |
9456912404 ps |
| T999 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3221994864 |
|
|
Jul 04 08:13:21 PM PDT 24 |
Jul 04 08:22:43 PM PDT 24 |
4403805328 ps |
| T765 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1903767929 |
|
|
Jul 04 08:20:07 PM PDT 24 |
Jul 04 08:28:04 PM PDT 24 |
4572933300 ps |
| T778 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2880552706 |
|
|
Jul 04 08:19:13 PM PDT 24 |
Jul 04 08:25:57 PM PDT 24 |
4240070246 ps |
| T1000 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1314009770 |
|
|
Jul 04 07:57:06 PM PDT 24 |
Jul 04 08:24:31 PM PDT 24 |
8816824880 ps |
| T9 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.1433137060 |
|
|
Jul 04 08:09:34 PM PDT 24 |
Jul 04 08:14:46 PM PDT 24 |
4000684704 ps |
| T1001 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3881578568 |
|
|
Jul 04 07:56:06 PM PDT 24 |
Jul 04 08:44:27 PM PDT 24 |
11289712424 ps |
| T1002 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2348142440 |
|
|
Jul 04 07:56:28 PM PDT 24 |
Jul 04 08:03:56 PM PDT 24 |
4219980136 ps |
| T1003 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3107447514 |
|
|
Jul 04 08:08:14 PM PDT 24 |
Jul 04 08:40:03 PM PDT 24 |
12213553560 ps |
| T806 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2795093234 |
|
|
Jul 04 08:20:56 PM PDT 24 |
Jul 04 08:29:34 PM PDT 24 |
4422949400 ps |
| T1004 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.318020294 |
|
|
Jul 04 07:58:04 PM PDT 24 |
Jul 04 08:19:49 PM PDT 24 |
11035313640 ps |
| T1005 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2454519200 |
|
|
Jul 04 08:12:10 PM PDT 24 |
Jul 04 08:59:39 PM PDT 24 |
12125032000 ps |
| T1006 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2971929336 |
|
|
Jul 04 07:59:01 PM PDT 24 |
Jul 04 09:55:20 PM PDT 24 |
24837771124 ps |
| T231 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2434272322 |
|
|
Jul 04 07:49:29 PM PDT 24 |
Jul 04 09:20:38 PM PDT 24 |
47105464321 ps |
| T706 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.338051687 |
|
|
Jul 04 08:22:47 PM PDT 24 |
Jul 04 08:36:38 PM PDT 24 |
10561307214 ps |
| T149 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3929134187 |
|
|
Jul 04 08:05:10 PM PDT 24 |
Jul 04 08:53:27 PM PDT 24 |
16790366210 ps |
| T11 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.77725550 |
|
|
Jul 04 07:52:46 PM PDT 24 |
Jul 04 07:56:57 PM PDT 24 |
3374757516 ps |
| T165 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1923572601 |
|
|
Jul 04 08:20:37 PM PDT 24 |
Jul 04 08:28:50 PM PDT 24 |
5601231668 ps |
| T666 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2983669877 |
|
|
Jul 04 08:07:17 PM PDT 24 |
Jul 04 11:52:06 PM PDT 24 |
255942963000 ps |
| T768 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3974742231 |
|
|
Jul 04 08:16:24 PM PDT 24 |
Jul 04 08:25:01 PM PDT 24 |
3770621560 ps |
| T1007 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1137962977 |
|
|
Jul 04 08:03:17 PM PDT 24 |
Jul 04 08:26:06 PM PDT 24 |
8558552860 ps |
| T796 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.3824490360 |
|
|
Jul 04 08:17:35 PM PDT 24 |
Jul 04 08:29:03 PM PDT 24 |
5927794072 ps |
| T1008 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.40540029 |
|
|
Jul 04 07:48:24 PM PDT 24 |
Jul 04 07:55:33 PM PDT 24 |
4834750050 ps |
| T761 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1485366113 |
|
|
Jul 04 08:15:03 PM PDT 24 |
Jul 04 08:21:55 PM PDT 24 |
3507326120 ps |
| T794 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2072940953 |
|
|
Jul 04 07:55:38 PM PDT 24 |
Jul 04 08:02:52 PM PDT 24 |
4168983936 ps |
| T1009 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.47581719 |
|
|
Jul 04 07:49:10 PM PDT 24 |
Jul 04 07:56:53 PM PDT 24 |
8123022476 ps |
| T196 |
/workspace/coverage/default/1.chip_jtag_mem_access.3518917399 |
|
|
Jul 04 07:51:17 PM PDT 24 |
Jul 04 08:18:31 PM PDT 24 |
13898811945 ps |
| T284 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1246900966 |
|
|
Jul 04 07:50:21 PM PDT 24 |
Jul 04 07:59:20 PM PDT 24 |
3771035592 ps |
| T1010 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.297682046 |
|
|
Jul 04 07:49:23 PM PDT 24 |
Jul 04 07:58:13 PM PDT 24 |
5700321235 ps |
| T150 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2590348610 |
|
|
Jul 04 08:01:33 PM PDT 24 |
Jul 04 09:08:17 PM PDT 24 |
25116217927 ps |
| T1011 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1269429857 |
|
|
Jul 04 08:02:52 PM PDT 24 |
Jul 04 08:08:00 PM PDT 24 |
2710586468 ps |
| T260 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2942558410 |
|
|
Jul 04 08:13:44 PM PDT 24 |
Jul 04 08:25:35 PM PDT 24 |
5933905634 ps |
| T1012 |
/workspace/coverage/default/0.chip_sw_example_flash.967216536 |
|
|
Jul 04 07:48:14 PM PDT 24 |
Jul 04 07:51:30 PM PDT 24 |
2452266010 ps |
| T662 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.3857865744 |
|
|
Jul 04 08:06:59 PM PDT 24 |
Jul 04 08:18:02 PM PDT 24 |
2632067600 ps |
| T1013 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4157449954 |
|
|
Jul 04 07:51:16 PM PDT 24 |
Jul 04 08:01:26 PM PDT 24 |
4158326104 ps |
| T1014 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.339053895 |
|
|
Jul 04 07:51:17 PM PDT 24 |
Jul 04 08:20:28 PM PDT 24 |
13174396540 ps |
| T345 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1636397343 |
|
|
Jul 04 07:55:32 PM PDT 24 |
Jul 04 08:09:16 PM PDT 24 |
4963754132 ps |
| T1015 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2195407211 |
|
|
Jul 04 07:49:15 PM PDT 24 |
Jul 04 08:02:47 PM PDT 24 |
4934480682 ps |
| T1016 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.65915418 |
|
|
Jul 04 08:12:26 PM PDT 24 |
Jul 04 08:22:05 PM PDT 24 |
4311768724 ps |
| T1017 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2808354306 |
|
|
Jul 04 07:54:13 PM PDT 24 |
Jul 04 07:58:02 PM PDT 24 |
3698921250 ps |
| T244 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.1968887292 |
|
|
Jul 04 08:14:20 PM PDT 24 |
Jul 04 08:25:58 PM PDT 24 |
5747795824 ps |
| T1018 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1947509380 |
|
|
Jul 04 07:47:42 PM PDT 24 |
Jul 04 08:10:36 PM PDT 24 |
7865441914 ps |
| T1019 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.1662117496 |
|
|
Jul 04 07:49:01 PM PDT 24 |
Jul 04 07:54:46 PM PDT 24 |
3313598030 ps |
| T743 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2662992216 |
|
|
Jul 04 08:17:04 PM PDT 24 |
Jul 04 08:23:49 PM PDT 24 |
4161573752 ps |
| T754 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.3087520329 |
|
|
Jul 04 08:15:23 PM PDT 24 |
Jul 04 08:24:59 PM PDT 24 |
4213455712 ps |
| T1020 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3930846863 |
|
|
Jul 04 07:59:46 PM PDT 24 |
Jul 04 08:04:38 PM PDT 24 |
2877677611 ps |
| T332 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.534317035 |
|
|
Jul 04 07:58:34 PM PDT 24 |
Jul 04 08:14:13 PM PDT 24 |
4939306898 ps |
| T1021 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3499896624 |
|
|
Jul 04 07:57:50 PM PDT 24 |
Jul 04 08:01:20 PM PDT 24 |
2827527290 ps |
| T167 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.4238551327 |
|
|
Jul 04 07:48:31 PM PDT 24 |
Jul 04 07:58:55 PM PDT 24 |
5568744728 ps |
| T399 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1452661478 |
|
|
Jul 04 08:11:03 PM PDT 24 |
Jul 04 08:17:58 PM PDT 24 |
4943339812 ps |
| T1022 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1560115963 |
|
|
Jul 04 07:57:31 PM PDT 24 |
Jul 04 08:57:59 PM PDT 24 |
14793205440 ps |
| T285 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2759558769 |
|
|
Jul 04 07:56:28 PM PDT 24 |
Jul 04 08:09:24 PM PDT 24 |
5888678008 ps |
| T795 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2375730496 |
|
|
Jul 04 08:18:26 PM PDT 24 |
Jul 04 08:27:12 PM PDT 24 |
4503484516 ps |