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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.99 95.38 93.61 95.44 94.39 97.53 99.58


Total test records in report: 2901
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T1023 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2565239292 Jul 04 08:07:22 PM PDT 24 Jul 04 08:26:47 PM PDT 24 7307768056 ps
T236 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3410473392 Jul 04 08:04:07 PM PDT 24 Jul 04 09:37:25 PM PDT 24 49876175115 ps
T1024 /workspace/coverage/default/1.chip_sw_hmac_multistream.446312099 Jul 04 07:56:03 PM PDT 24 Jul 04 08:24:39 PM PDT 24 7958841914 ps
T1025 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.748774105 Jul 04 07:54:51 PM PDT 24 Jul 04 08:08:29 PM PDT 24 4526874410 ps
T1026 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2945951043 Jul 04 07:58:31 PM PDT 24 Jul 04 08:09:37 PM PDT 24 4092961880 ps
T722 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3630130640 Jul 04 08:20:10 PM PDT 24 Jul 04 08:27:09 PM PDT 24 4360844712 ps
T1027 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3149394880 Jul 04 07:50:27 PM PDT 24 Jul 04 08:01:20 PM PDT 24 3943878952 ps
T1028 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.263382692 Jul 04 07:51:32 PM PDT 24 Jul 04 08:03:53 PM PDT 24 6499795286 ps
T1029 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.626168763 Jul 04 08:16:12 PM PDT 24 Jul 04 08:22:43 PM PDT 24 3683344408 ps
T1030 /workspace/coverage/default/2.chip_sw_example_manufacturer.672234848 Jul 04 08:03:20 PM PDT 24 Jul 04 08:07:01 PM PDT 24 2866745736 ps
T683 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3725063163 Jul 04 08:01:02 PM PDT 24 Jul 04 08:12:09 PM PDT 24 5525189304 ps
T1031 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1923455614 Jul 04 07:52:53 PM PDT 24 Jul 04 08:03:45 PM PDT 24 5838378544 ps
T740 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.715550867 Jul 04 08:20:20 PM PDT 24 Jul 04 08:27:00 PM PDT 24 3769482100 ps
T1032 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2592818800 Jul 04 07:56:15 PM PDT 24 Jul 04 08:52:50 PM PDT 24 14072393039 ps
T1033 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1954279356 Jul 04 07:56:22 PM PDT 24 Jul 04 09:07:57 PM PDT 24 18743375512 ps
T665 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2017941023 Jul 04 08:11:05 PM PDT 24 Jul 04 09:11:00 PM PDT 24 24546942648 ps
T1034 /workspace/coverage/default/0.chip_sival_flash_info_access.808521042 Jul 04 07:47:19 PM PDT 24 Jul 04 07:51:30 PM PDT 24 2729625644 ps
T1035 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2420880317 Jul 04 08:09:41 PM PDT 24 Jul 04 08:16:22 PM PDT 24 4824130120 ps
T337 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3893192994 Jul 04 07:57:23 PM PDT 24 Jul 04 08:23:06 PM PDT 24 5960278474 ps
T1036 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2661352583 Jul 04 07:51:18 PM PDT 24 Jul 04 07:55:05 PM PDT 24 2789119404 ps
T1037 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1238335616 Jul 04 08:09:07 PM PDT 24 Jul 04 08:17:55 PM PDT 24 4534704000 ps
T745 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.428522082 Jul 04 08:17:35 PM PDT 24 Jul 04 08:24:48 PM PDT 24 4006342630 ps
T1038 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2855175727 Jul 04 07:59:07 PM PDT 24 Jul 04 08:11:31 PM PDT 24 5331068437 ps
T1039 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2393680960 Jul 04 08:02:32 PM PDT 24 Jul 04 08:06:22 PM PDT 24 3029309184 ps
T750 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2533299421 Jul 04 08:20:01 PM PDT 24 Jul 04 08:26:12 PM PDT 24 3059308400 ps
T1040 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2263980483 Jul 04 07:47:41 PM PDT 24 Jul 04 07:56:58 PM PDT 24 9232542010 ps
T334 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2046916585 Jul 04 07:52:40 PM PDT 24 Jul 04 08:06:29 PM PDT 24 4974212912 ps
T1041 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.859100042 Jul 04 07:50:13 PM PDT 24 Jul 04 07:59:30 PM PDT 24 4441512078 ps
T1042 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1636782148 Jul 04 07:51:13 PM PDT 24 Jul 04 07:57:53 PM PDT 24 5522789654 ps
T786 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.721100031 Jul 04 08:13:10 PM PDT 24 Jul 04 08:18:01 PM PDT 24 3824293000 ps
T235 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2977195237 Jul 04 08:03:42 PM PDT 24 Jul 04 09:29:27 PM PDT 24 46244323789 ps
T785 /workspace/coverage/default/96.chip_sw_all_escalation_resets.2757924092 Jul 04 08:19:57 PM PDT 24 Jul 04 08:29:17 PM PDT 24 4841162176 ps
T1043 /workspace/coverage/default/1.chip_sw_edn_auto_mode.3579986178 Jul 04 07:56:01 PM PDT 24 Jul 04 08:17:02 PM PDT 24 4053757548 ps
T513 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1674694079 Jul 04 07:50:02 PM PDT 24 Jul 04 08:07:23 PM PDT 24 5260850448 ps
T74 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.186232976 Jul 04 07:48:12 PM PDT 24 Jul 04 07:54:53 PM PDT 24 3460863354 ps
T1044 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2878041225 Jul 04 07:47:49 PM PDT 24 Jul 04 07:55:31 PM PDT 24 4167524650 ps
T514 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3336779107 Jul 04 07:55:54 PM PDT 24 Jul 04 08:11:49 PM PDT 24 5069489464 ps
T755 /workspace/coverage/default/39.chip_sw_all_escalation_resets.2449023747 Jul 04 08:15:57 PM PDT 24 Jul 04 08:26:53 PM PDT 24 5072647596 ps
T1045 /workspace/coverage/default/0.chip_sw_edn_kat.1548068655 Jul 04 07:48:37 PM PDT 24 Jul 04 07:59:27 PM PDT 24 3428704396 ps
T746 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.411447307 Jul 04 08:13:46 PM PDT 24 Jul 04 08:21:31 PM PDT 24 3828110580 ps
T1046 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.34151059 Jul 04 07:50:09 PM PDT 24 Jul 04 08:32:14 PM PDT 24 28778421100 ps
T87 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.673236681 Jul 04 08:19:54 PM PDT 24 Jul 04 08:26:27 PM PDT 24 3724632322 ps
T90 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.489979441 Jul 04 08:04:14 PM PDT 24 Jul 04 08:22:33 PM PDT 24 8299330598 ps
T91 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.934190447 Jul 04 07:48:50 PM PDT 24 Jul 04 08:08:52 PM PDT 24 9202783176 ps
T92 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4239879380 Jul 04 07:48:58 PM PDT 24 Jul 04 07:55:57 PM PDT 24 3199665064 ps
T93 /workspace/coverage/default/2.chip_sw_aes_enc.1005154947 Jul 04 08:06:01 PM PDT 24 Jul 04 08:10:48 PM PDT 24 3410507076 ps
T94 /workspace/coverage/default/67.chip_sw_all_escalation_resets.66698796 Jul 04 08:18:13 PM PDT 24 Jul 04 08:26:19 PM PDT 24 4848315192 ps
T95 /workspace/coverage/default/1.chip_sw_flash_init.3920662280 Jul 04 07:53:22 PM PDT 24 Jul 04 08:29:45 PM PDT 24 24867400494 ps
T96 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2884453181 Jul 04 07:51:41 PM PDT 24 Jul 04 08:53:23 PM PDT 24 24786175741 ps
T97 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.715234883 Jul 04 07:50:27 PM PDT 24 Jul 04 07:53:10 PM PDT 24 3124674292 ps
T98 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3639646685 Jul 04 08:07:14 PM PDT 24 Jul 04 08:17:25 PM PDT 24 6268391362 ps
T1047 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2329271087 Jul 04 08:09:20 PM PDT 24 Jul 04 08:20:53 PM PDT 24 5174739602 ps
T1048 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2667085771 Jul 04 08:07:41 PM PDT 24 Jul 04 08:30:23 PM PDT 24 9414583960 ps
T1049 /workspace/coverage/default/2.chip_sw_csrng_kat_test.2573441930 Jul 04 08:06:06 PM PDT 24 Jul 04 08:11:44 PM PDT 24 2799676312 ps
T1050 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.389945019 Jul 04 07:48:56 PM PDT 24 Jul 04 07:59:48 PM PDT 24 3440169100 ps
T298 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2130725969 Jul 04 07:48:57 PM PDT 24 Jul 04 07:53:30 PM PDT 24 2995290200 ps
T226 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3118098407 Jul 04 07:49:02 PM PDT 24 Jul 04 09:06:11 PM PDT 24 17389242298 ps
T763 /workspace/coverage/default/72.chip_sw_all_escalation_resets.1576082451 Jul 04 08:19:11 PM PDT 24 Jul 04 08:29:09 PM PDT 24 4917603176 ps
T134 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1019891912 Jul 04 07:57:38 PM PDT 24 Jul 04 08:19:14 PM PDT 24 8972903000 ps
T1051 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2451173009 Jul 04 07:55:23 PM PDT 24 Jul 04 08:47:58 PM PDT 24 36178289861 ps
T374 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3056219945 Jul 04 08:02:37 PM PDT 24 Jul 04 08:15:19 PM PDT 24 4271628574 ps
T758 /workspace/coverage/default/40.chip_sw_all_escalation_resets.2001566449 Jul 04 08:18:07 PM PDT 24 Jul 04 08:28:26 PM PDT 24 4350688450 ps
T1052 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2116386717 Jul 04 08:12:29 PM PDT 24 Jul 04 08:21:13 PM PDT 24 8079813704 ps
T731 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1591381544 Jul 04 08:07:50 PM PDT 24 Jul 04 08:14:59 PM PDT 24 4341800502 ps
T1053 /workspace/coverage/default/2.chip_sw_otbn_randomness.178711339 Jul 04 08:05:10 PM PDT 24 Jul 04 08:21:53 PM PDT 24 5658116842 ps
T1054 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.4271249468 Jul 04 07:47:39 PM PDT 24 Jul 04 07:53:13 PM PDT 24 3321571208 ps
T690 /workspace/coverage/default/2.rom_volatile_raw_unlock.2178754136 Jul 04 08:11:19 PM PDT 24 Jul 04 08:13:03 PM PDT 24 2789371678 ps
T200 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1151838936 Jul 04 07:48:19 PM PDT 24 Jul 04 07:58:56 PM PDT 24 4059429710 ps
T380 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3897863230 Jul 04 07:50:41 PM PDT 24 Jul 04 07:57:39 PM PDT 24 5727988488 ps
T1055 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1912325985 Jul 04 07:47:52 PM PDT 24 Jul 04 08:53:29 PM PDT 24 18901213896 ps
T359 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1159670405 Jul 04 07:47:29 PM PDT 24 Jul 04 08:24:09 PM PDT 24 8898342121 ps
T1056 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.970629041 Jul 04 08:10:11 PM PDT 24 Jul 04 08:15:49 PM PDT 24 3660584664 ps
T342 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3288492407 Jul 04 07:47:21 PM PDT 24 Jul 04 08:04:30 PM PDT 24 5232517000 ps
T1057 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3274537328 Jul 04 08:11:35 PM PDT 24 Jul 04 08:23:26 PM PDT 24 10843025840 ps
T1058 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3230231566 Jul 04 07:49:36 PM PDT 24 Jul 04 07:53:39 PM PDT 24 3249083096 ps
T1059 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3651862894 Jul 04 08:12:31 PM PDT 24 Jul 04 08:24:47 PM PDT 24 3983744080 ps
T1060 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2293794511 Jul 04 08:04:48 PM PDT 24 Jul 04 08:56:24 PM PDT 24 20244030447 ps
T259 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.762784405 Jul 04 07:57:29 PM PDT 24 Jul 04 08:20:45 PM PDT 24 11972662876 ps
T335 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3672902807 Jul 04 07:54:03 PM PDT 24 Jul 04 08:26:49 PM PDT 24 14217617980 ps
T766 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2332682330 Jul 04 08:14:33 PM PDT 24 Jul 04 08:22:45 PM PDT 24 3307995304 ps
T782 /workspace/coverage/default/31.chip_sw_all_escalation_resets.3215644631 Jul 04 08:14:55 PM PDT 24 Jul 04 08:25:36 PM PDT 24 6442258600 ps
T401 /workspace/coverage/default/1.chip_sw_kmac_app_rom.3314134574 Jul 04 07:58:04 PM PDT 24 Jul 04 08:01:00 PM PDT 24 2992837572 ps
T1061 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3196838545 Jul 04 07:59:48 PM PDT 24 Jul 04 08:03:30 PM PDT 24 3109858173 ps
T1062 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.39052679 Jul 04 08:09:59 PM PDT 24 Jul 04 08:14:13 PM PDT 24 3087135119 ps
T1063 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.649991948 Jul 04 07:47:51 PM PDT 24 Jul 04 08:04:55 PM PDT 24 6811334018 ps
T725 /workspace/coverage/default/23.chip_sw_all_escalation_resets.4156783354 Jul 04 08:14:25 PM PDT 24 Jul 04 08:25:02 PM PDT 24 4706268204 ps
T349 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.372900750 Jul 04 08:03:37 PM PDT 24 Jul 04 08:14:05 PM PDT 24 4099105576 ps
T1064 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3760420049 Jul 04 08:12:27 PM PDT 24 Jul 04 08:22:58 PM PDT 24 4448068536 ps
T764 /workspace/coverage/default/9.chip_sw_all_escalation_resets.3541626037 Jul 04 08:15:25 PM PDT 24 Jul 04 08:25:26 PM PDT 24 5767035616 ps
T807 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4229909145 Jul 04 08:20:28 PM PDT 24 Jul 04 08:27:58 PM PDT 24 4135479752 ps
T1065 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2527604647 Jul 04 08:11:21 PM PDT 24 Jul 04 08:16:05 PM PDT 24 2907078520 ps
T1066 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2795934568 Jul 04 07:46:58 PM PDT 24 Jul 04 07:56:32 PM PDT 24 4745791768 ps
T691 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2626629577 Jul 04 07:47:22 PM PDT 24 Jul 04 07:49:50 PM PDT 24 3413282410 ps
T779 /workspace/coverage/default/73.chip_sw_all_escalation_resets.2906954573 Jul 04 08:19:23 PM PDT 24 Jul 04 08:25:59 PM PDT 24 4491648784 ps
T1067 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1640024323 Jul 04 07:57:11 PM PDT 24 Jul 04 08:09:59 PM PDT 24 5845835383 ps
T776 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1997239706 Jul 04 08:15:38 PM PDT 24 Jul 04 08:21:35 PM PDT 24 3660323352 ps
T1068 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2479238191 Jul 04 07:48:30 PM PDT 24 Jul 04 07:52:48 PM PDT 24 3061801814 ps
T717 /workspace/coverage/default/65.chip_sw_all_escalation_resets.2400655348 Jul 04 08:17:54 PM PDT 24 Jul 04 08:27:02 PM PDT 24 4708861064 ps
T291 /workspace/coverage/default/41.chip_sw_all_escalation_resets.19682356 Jul 04 08:17:29 PM PDT 24 Jul 04 08:27:39 PM PDT 24 4425744220 ps
T1069 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.108590041 Jul 04 07:49:55 PM PDT 24 Jul 04 08:29:46 PM PDT 24 11530748228 ps
T383 /workspace/coverage/default/52.chip_sw_all_escalation_resets.729195040 Jul 04 08:18:37 PM PDT 24 Jul 04 08:28:06 PM PDT 24 5847707958 ps
T1070 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3631456194 Jul 04 08:15:10 PM PDT 24 Jul 04 08:21:39 PM PDT 24 5315561567 ps
T1071 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.14884308 Jul 04 08:10:08 PM PDT 24 Jul 04 08:16:28 PM PDT 24 3151846216 ps
T1072 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3220841869 Jul 04 07:58:51 PM PDT 24 Jul 04 08:07:18 PM PDT 24 3283294396 ps
T1073 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2383616166 Jul 04 08:01:00 PM PDT 24 Jul 04 08:19:20 PM PDT 24 5917845576 ps
T718 /workspace/coverage/default/35.chip_sw_all_escalation_resets.2701965834 Jul 04 08:18:18 PM PDT 24 Jul 04 08:28:24 PM PDT 24 5046754514 ps
T1074 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.219460683 Jul 04 08:04:38 PM PDT 24 Jul 04 08:16:32 PM PDT 24 4555788022 ps
T1075 /workspace/coverage/default/2.chip_sw_aes_entropy.3596985580 Jul 04 08:05:35 PM PDT 24 Jul 04 08:09:38 PM PDT 24 3132676664 ps
T360 /workspace/coverage/default/3.chip_sw_uart_tx_rx.505191249 Jul 04 08:11:42 PM PDT 24 Jul 04 08:20:57 PM PDT 24 4428642640 ps
T1076 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1895209256 Jul 04 08:08:27 PM PDT 24 Jul 04 08:19:02 PM PDT 24 5212382670 ps
T1077 /workspace/coverage/default/1.chip_sw_edn_kat.3174051209 Jul 04 07:57:19 PM PDT 24 Jul 04 08:09:16 PM PDT 24 2921601680 ps
T27 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.891526016 Jul 04 08:05:05 PM PDT 24 Jul 04 08:16:15 PM PDT 24 4396371860 ps
T1078 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1457862116 Jul 04 08:14:18 PM PDT 24 Jul 04 09:11:05 PM PDT 24 15574490862 ps
T747 /workspace/coverage/default/49.chip_sw_all_escalation_resets.831974451 Jul 04 08:16:57 PM PDT 24 Jul 04 08:28:48 PM PDT 24 5520063380 ps
T431 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3220983916 Jul 04 07:52:50 PM PDT 24 Jul 04 08:33:34 PM PDT 24 32245542664 ps
T351 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2608245764 Jul 04 07:50:10 PM PDT 24 Jul 04 07:57:01 PM PDT 24 4563875632 ps
T1079 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3104596952 Jul 04 07:59:49 PM PDT 24 Jul 04 09:03:53 PM PDT 24 14692646569 ps
T201 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3782154840 Jul 04 08:07:38 PM PDT 24 Jul 04 08:38:58 PM PDT 24 24657714958 ps
T292 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.400452023 Jul 04 08:20:33 PM PDT 24 Jul 04 08:26:52 PM PDT 24 4059943448 ps
T797 /workspace/coverage/default/46.chip_sw_all_escalation_resets.1673457938 Jul 04 08:16:27 PM PDT 24 Jul 04 08:25:01 PM PDT 24 4501582454 ps
T75 /workspace/coverage/default/0.chip_sw_usbdev_pullup.2407618178 Jul 04 07:47:22 PM PDT 24 Jul 04 07:52:56 PM PDT 24 3044953852 ps
T1080 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.702620445 Jul 04 07:48:36 PM PDT 24 Jul 04 08:03:40 PM PDT 24 7232734110 ps
T1081 /workspace/coverage/default/1.chip_sw_flash_crash_alert.71278208 Jul 04 08:01:02 PM PDT 24 Jul 04 08:14:55 PM PDT 24 6113702608 ps
T1082 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3847753145 Jul 04 07:53:27 PM PDT 24 Jul 04 08:02:09 PM PDT 24 7835708859 ps
T1083 /workspace/coverage/default/32.chip_sw_all_escalation_resets.158172339 Jul 04 08:17:23 PM PDT 24 Jul 04 08:27:39 PM PDT 24 5948254080 ps
T69 /workspace/coverage/default/1.chip_tap_straps_rma.1194519862 Jul 04 07:59:54 PM PDT 24 Jul 04 08:08:44 PM PDT 24 4815659733 ps
T1084 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.4229780547 Jul 04 08:13:45 PM PDT 24 Jul 04 08:20:30 PM PDT 24 3094124906 ps
T1085 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3635774370 Jul 04 07:49:49 PM PDT 24 Jul 04 07:53:51 PM PDT 24 3143554600 ps
T135 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3253546836 Jul 04 08:06:47 PM PDT 24 Jul 04 08:17:19 PM PDT 24 3865319420 ps
T1086 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3686974856 Jul 04 07:52:56 PM PDT 24 Jul 04 08:01:03 PM PDT 24 4985332248 ps
T1087 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.330382027 Jul 04 07:47:48 PM PDT 24 Jul 04 08:06:57 PM PDT 24 6164881459 ps
T110 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.2116496576 Jul 04 07:59:54 PM PDT 24 Jul 04 08:34:27 PM PDT 24 15698384399 ps
T1088 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1544107306 Jul 04 07:56:25 PM PDT 24 Jul 04 09:30:48 PM PDT 24 23782298136 ps
T695 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.241031726 Jul 04 07:55:46 PM PDT 24 Jul 04 08:00:50 PM PDT 24 3647601842 ps
T1089 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1994760266 Jul 04 08:01:57 PM PDT 24 Jul 04 08:13:19 PM PDT 24 4331937400 ps
T1090 /workspace/coverage/default/2.chip_sw_hmac_enc.2456832363 Jul 04 08:06:21 PM PDT 24 Jul 04 08:10:59 PM PDT 24 3470663664 ps
T1091 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1357671875 Jul 04 08:11:38 PM PDT 24 Jul 04 08:17:32 PM PDT 24 3179136048 ps
T1092 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.688404435 Jul 04 07:56:08 PM PDT 24 Jul 04 08:50:04 PM PDT 24 11704315502 ps
T769 /workspace/coverage/default/76.chip_sw_all_escalation_resets.2551017663 Jul 04 08:18:48 PM PDT 24 Jul 04 08:28:44 PM PDT 24 5620438432 ps
T1093 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2426947241 Jul 04 08:13:30 PM PDT 24 Jul 04 08:35:20 PM PDT 24 8213663612 ps
T1094 /workspace/coverage/default/2.rom_e2e_static_critical.239900019 Jul 04 08:14:06 PM PDT 24 Jul 04 09:20:54 PM PDT 24 16751928650 ps
T373 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.564181485 Jul 04 08:03:45 PM PDT 24 Jul 04 08:09:49 PM PDT 24 3370987730 ps
T704 /workspace/coverage/default/2.chip_sw_power_sleep_load.1779599223 Jul 04 08:10:19 PM PDT 24 Jul 04 08:17:41 PM PDT 24 4227231540 ps
T1095 /workspace/coverage/default/0.chip_sw_power_idle_load.702435166 Jul 04 07:51:28 PM PDT 24 Jul 04 08:01:48 PM PDT 24 4060041656 ps
T343 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2414269595 Jul 04 08:02:48 PM PDT 24 Jul 04 08:18:15 PM PDT 24 4467238652 ps
T381 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3833414099 Jul 04 08:00:21 PM PDT 24 Jul 04 08:10:22 PM PDT 24 6755427352 ps
T1096 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.4016792047 Jul 04 07:56:52 PM PDT 24 Jul 04 09:30:04 PM PDT 24 22407770559 ps
T1097 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.133949660 Jul 04 07:49:46 PM PDT 24 Jul 04 08:12:18 PM PDT 24 7096572646 ps
T1098 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2689955784 Jul 04 08:10:58 PM PDT 24 Jul 04 08:21:26 PM PDT 24 7655849580 ps
T1099 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3578449616 Jul 04 07:53:07 PM PDT 24 Jul 04 08:04:45 PM PDT 24 6545379152 ps
T227 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1746675784 Jul 04 07:57:14 PM PDT 24 Jul 04 08:47:21 PM PDT 24 12548517216 ps
T1100 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1455808073 Jul 04 07:53:04 PM PDT 24 Jul 04 10:39:59 PM PDT 24 57906348278 ps
T15 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1585876830 Jul 04 07:51:55 PM PDT 24 Jul 04 08:28:47 PM PDT 24 26328382696 ps
T202 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1076808966 Jul 04 08:05:12 PM PDT 24 Jul 04 08:15:32 PM PDT 24 5023511973 ps
T1101 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2333513755 Jul 04 08:03:04 PM PDT 24 Jul 04 08:19:19 PM PDT 24 5931465567 ps
T1102 /workspace/coverage/default/1.rom_e2e_shutdown_output.1505954678 Jul 04 08:06:34 PM PDT 24 Jul 04 09:10:35 PM PDT 24 27897231899 ps
T515 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2531252672 Jul 04 08:06:26 PM PDT 24 Jul 04 08:18:46 PM PDT 24 4267109680 ps
T1103 /workspace/coverage/default/1.chip_tap_straps_testunlock0.4281814893 Jul 04 07:59:16 PM PDT 24 Jul 04 08:04:24 PM PDT 24 4469204573 ps
T1104 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.771333865 Jul 04 08:11:33 PM PDT 24 Jul 04 08:41:24 PM PDT 24 13469646611 ps
T684 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4278576936 Jul 04 07:50:15 PM PDT 24 Jul 04 08:01:38 PM PDT 24 6069128639 ps
T403 /workspace/coverage/default/48.chip_sw_all_escalation_resets.1922946450 Jul 04 08:16:28 PM PDT 24 Jul 04 08:27:10 PM PDT 24 4695812408 ps
T1105 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2248072869 Jul 04 08:08:52 PM PDT 24 Jul 04 08:20:33 PM PDT 24 3982013080 ps
T1106 /workspace/coverage/default/0.chip_sw_aes_smoketest.2038861804 Jul 04 07:53:16 PM PDT 24 Jul 04 07:59:00 PM PDT 24 3252636746 ps
T692 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3031099385 Jul 04 07:47:09 PM PDT 24 Jul 04 07:49:28 PM PDT 24 2367245514 ps
T1107 /workspace/coverage/default/1.chip_sw_csrng_smoketest.3991384462 Jul 04 08:03:12 PM PDT 24 Jul 04 08:08:21 PM PDT 24 3241833120 ps
T1108 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1240219108 Jul 04 07:54:28 PM PDT 24 Jul 04 08:03:59 PM PDT 24 7011210964 ps
T1109 /workspace/coverage/default/2.chip_sw_aes_idle.1441994019 Jul 04 08:06:22 PM PDT 24 Jul 04 08:10:40 PM PDT 24 2880681250 ps
T1110 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.705293037 Jul 04 07:51:55 PM PDT 24 Jul 04 10:56:28 PM PDT 24 65730212312 ps
T1111 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2215745662 Jul 04 07:47:36 PM PDT 24 Jul 04 08:15:53 PM PDT 24 9123721840 ps
T1112 /workspace/coverage/default/2.chip_sw_kmac_smoketest.2488344975 Jul 04 08:10:28 PM PDT 24 Jul 04 08:15:48 PM PDT 24 3611950658 ps
T1113 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.205025779 Jul 04 08:00:57 PM PDT 24 Jul 04 08:06:22 PM PDT 24 3104105060 ps
T752 /workspace/coverage/default/87.chip_sw_all_escalation_resets.797210914 Jul 04 08:20:47 PM PDT 24 Jul 04 08:31:20 PM PDT 24 6833131648 ps
T1114 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1910804533 Jul 04 07:51:04 PM PDT 24 Jul 04 09:04:24 PM PDT 24 17331676998 ps
T759 /workspace/coverage/default/59.chip_sw_all_escalation_resets.3609697110 Jul 04 08:20:07 PM PDT 24 Jul 04 08:30:12 PM PDT 24 4652181220 ps
T744 /workspace/coverage/default/19.chip_sw_all_escalation_resets.605988692 Jul 04 08:14:26 PM PDT 24 Jul 04 08:25:07 PM PDT 24 4588590442 ps
T261 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3085515892 Jul 04 07:47:44 PM PDT 24 Jul 04 07:55:45 PM PDT 24 4882482654 ps
T777 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1538385746 Jul 04 08:17:15 PM PDT 24 Jul 04 08:24:34 PM PDT 24 3944364308 ps
T65 /workspace/coverage/default/0.chip_sw_alert_test.2188932062 Jul 04 07:48:18 PM PDT 24 Jul 04 07:53:11 PM PDT 24 2897554120 ps
T1115 /workspace/coverage/default/0.chip_tap_straps_dev.1073801620 Jul 04 07:50:13 PM PDT 24 Jul 04 07:57:32 PM PDT 24 4607489825 ps
T1116 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1564163316 Jul 04 08:08:43 PM PDT 24 Jul 04 08:17:52 PM PDT 24 3484155156 ps
T767 /workspace/coverage/default/0.chip_sw_all_escalation_resets.3026156027 Jul 04 07:46:28 PM PDT 24 Jul 04 07:59:12 PM PDT 24 5006204552 ps
T1117 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3922553944 Jul 04 08:11:44 PM PDT 24 Jul 04 08:16:50 PM PDT 24 3687529156 ps
T810 /workspace/coverage/default/34.chip_sw_all_escalation_resets.2328423422 Jul 04 08:15:16 PM PDT 24 Jul 04 08:26:50 PM PDT 24 5699263216 ps
T146 /workspace/coverage/default/0.chip_sw_usbdev_dpi.2206671960 Jul 04 07:47:03 PM PDT 24 Jul 04 08:34:48 PM PDT 24 11504740970 ps
T773 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2289368220 Jul 04 08:13:40 PM PDT 24 Jul 04 08:19:29 PM PDT 24 4345131682 ps
T1118 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.833632806 Jul 04 07:54:25 PM PDT 24 Jul 04 08:06:29 PM PDT 24 4941591057 ps
T384 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3180627017 Jul 04 08:18:10 PM PDT 24 Jul 04 08:24:18 PM PDT 24 3765239000 ps
T1119 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2076467134 Jul 04 08:09:39 PM PDT 24 Jul 04 08:12:46 PM PDT 24 2169953149 ps
T40 /workspace/coverage/default/0.chip_sw_gpio.3756525640 Jul 04 07:48:45 PM PDT 24 Jul 04 07:57:13 PM PDT 24 4318245621 ps
T793 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.264997783 Jul 04 08:13:58 PM PDT 24 Jul 04 08:20:56 PM PDT 24 3946229304 ps
T1120 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.879036379 Jul 04 08:07:07 PM PDT 24 Jul 04 08:10:50 PM PDT 24 2527327848 ps
T130 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2993869262 Jul 04 07:57:42 PM PDT 24 Jul 04 08:05:31 PM PDT 24 4574859350 ps
T1121 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2622302242 Jul 04 08:10:42 PM PDT 24 Jul 04 08:15:02 PM PDT 24 2816014577 ps
T1122 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3610936397 Jul 04 07:57:45 PM PDT 24 Jul 04 08:12:17 PM PDT 24 9113920810 ps
T735 /workspace/coverage/default/84.chip_sw_all_escalation_resets.546538423 Jul 04 08:18:47 PM PDT 24 Jul 04 08:30:30 PM PDT 24 4896682860 ps
T1123 /workspace/coverage/default/1.chip_tap_straps_prod.569045764 Jul 04 07:59:33 PM PDT 24 Jul 04 08:18:15 PM PDT 24 10973061378 ps
T696 /workspace/coverage/default/0.chip_sw_plic_sw_irq.236462573 Jul 04 07:49:21 PM PDT 24 Jul 04 07:52:17 PM PDT 24 2855219494 ps
T308 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.4010428704 Jul 04 07:49:42 PM PDT 24 Jul 04 08:05:16 PM PDT 24 7745864018 ps
T1124 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3698862450 Jul 04 08:04:34 PM PDT 24 Jul 04 08:13:50 PM PDT 24 3760685240 ps
T1125 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3385799507 Jul 04 08:09:14 PM PDT 24 Jul 04 08:35:07 PM PDT 24 10726390380 ps
T1126 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3488548198 Jul 04 08:06:38 PM PDT 24 Jul 04 08:12:51 PM PDT 24 3059782825 ps
T1127 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.259878635 Jul 04 08:05:59 PM PDT 24 Jul 04 08:20:33 PM PDT 24 9933178880 ps
T1128 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3940160997 Jul 04 07:54:18 PM PDT 24 Jul 04 08:52:14 PM PDT 24 14541982854 ps
T402 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.483485325 Jul 04 07:49:06 PM PDT 24 Jul 04 07:57:46 PM PDT 24 9184968094 ps
T1129 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1813969992 Jul 04 08:05:56 PM PDT 24 Jul 04 08:31:30 PM PDT 24 8628010963 ps
T24 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1568527089 Jul 04 07:47:26 PM PDT 24 Jul 04 07:52:53 PM PDT 24 2917522077 ps
T330 /workspace/coverage/default/0.chip_plic_all_irqs_0.373545640 Jul 04 07:49:36 PM PDT 24 Jul 04 08:13:08 PM PDT 24 6436659080 ps
T770 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2462043548 Jul 04 08:17:40 PM PDT 24 Jul 04 08:23:34 PM PDT 24 4413555314 ps
T1130 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3116945084 Jul 04 07:50:06 PM PDT 24 Jul 04 07:53:18 PM PDT 24 2738446176 ps
T385 /workspace/coverage/default/29.chip_sw_all_escalation_resets.3652467498 Jul 04 08:15:54 PM PDT 24 Jul 04 08:25:33 PM PDT 24 4012214760 ps
T1131 /workspace/coverage/default/2.chip_sw_kmac_idle.2960636398 Jul 04 08:08:11 PM PDT 24 Jul 04 08:12:39 PM PDT 24 2910827750 ps
T1132 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2601684219 Jul 04 07:56:58 PM PDT 24 Jul 04 08:07:44 PM PDT 24 5495703702 ps
T1133 /workspace/coverage/default/1.chip_sw_otbn_randomness.3541498613 Jul 04 07:56:14 PM PDT 24 Jul 04 08:15:06 PM PDT 24 6380942946 ps
T276 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3389151025 Jul 04 07:48:25 PM PDT 24 Jul 04 08:01:56 PM PDT 24 5225697800 ps
T1134 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1834354058 Jul 04 08:09:06 PM PDT 24 Jul 04 08:17:24 PM PDT 24 3813900894 ps
T1135 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1328735005 Jul 04 07:54:16 PM PDT 24 Jul 04 09:36:25 PM PDT 24 47802729606 ps
T1136 /workspace/coverage/default/4.chip_sw_uart_tx_rx.2602134120 Jul 04 08:11:28 PM PDT 24 Jul 04 08:22:47 PM PDT 24 4285999384 ps
T783 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1199919790 Jul 04 08:15:28 PM PDT 24 Jul 04 08:21:58 PM PDT 24 3371406560 ps
T1137 /workspace/coverage/default/0.chip_sw_aes_idle.1189429773 Jul 04 07:51:09 PM PDT 24 Jul 04 07:56:21 PM PDT 24 3282035250 ps
T1138 /workspace/coverage/default/1.chip_sw_aes_smoketest.869140818 Jul 04 08:03:02 PM PDT 24 Jul 04 08:07:01 PM PDT 24 2512391704 ps
T1139 /workspace/coverage/default/1.chip_sw_rv_timer_irq.3539207046 Jul 04 07:54:59 PM PDT 24 Jul 04 08:00:40 PM PDT 24 3077863480 ps
T1140 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3969456109 Jul 04 07:48:42 PM PDT 24 Jul 04 11:05:39 PM PDT 24 256017375976 ps
T338 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.738060409 Jul 04 08:08:15 PM PDT 24 Jul 04 08:37:06 PM PDT 24 8390395030 ps
T241 /workspace/coverage/default/1.chip_sw_alert_test.2357127205 Jul 04 07:56:44 PM PDT 24 Jul 04 08:02:16 PM PDT 24 3456148298 ps
T1141 /workspace/coverage/default/0.chip_sw_kmac_app_rom.2936950892 Jul 04 07:49:18 PM PDT 24 Jul 04 07:54:24 PM PDT 24 2807837848 ps
T232 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2872205278 Jul 04 07:47:31 PM PDT 24 Jul 04 09:19:32 PM PDT 24 47767095120 ps
T1142 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.4221254371 Jul 04 07:55:38 PM PDT 24 Jul 04 09:33:13 PM PDT 24 23243766670 ps
T1143 /workspace/coverage/default/0.chip_sw_kmac_idle.129956320 Jul 04 07:50:04 PM PDT 24 Jul 04 07:54:16 PM PDT 24 3209473638 ps
T803 /workspace/coverage/default/44.chip_sw_all_escalation_resets.2483392703 Jul 04 08:17:02 PM PDT 24 Jul 04 08:28:40 PM PDT 24 6002999956 ps
T1144 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1741961391 Jul 04 08:02:53 PM PDT 24 Jul 04 08:11:11 PM PDT 24 3910944848 ps
T1145 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1162934839 Jul 04 07:57:47 PM PDT 24 Jul 04 08:32:39 PM PDT 24 27452164528 ps
T1146 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3915720902 Jul 04 07:47:30 PM PDT 24 Jul 04 08:25:15 PM PDT 24 33923354910 ps
T1147 /workspace/coverage/default/1.chip_sw_aes_entropy.944211280 Jul 04 07:55:58 PM PDT 24 Jul 04 08:00:50 PM PDT 24 2855745880 ps
T1148 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3919853092 Jul 04 08:15:49 PM PDT 24 Jul 04 08:33:43 PM PDT 24 9949283956 ps
T1149 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2040541644 Jul 04 07:53:01 PM PDT 24 Jul 04 07:58:33 PM PDT 24 3063175700 ps
T192 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2486819733 Jul 04 07:53:29 PM PDT 24 Jul 04 08:02:14 PM PDT 24 4535502002 ps
T762 /workspace/coverage/default/93.chip_sw_all_escalation_resets.2461482976 Jul 04 08:20:15 PM PDT 24 Jul 04 08:31:53 PM PDT 24 4918096460 ps
T1150 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3759580954 Jul 04 07:59:49 PM PDT 24 Jul 04 09:18:13 PM PDT 24 14663296019 ps
T16 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3161965681 Jul 04 08:09:15 PM PDT 24 Jul 04 08:34:27 PM PDT 24 20274101880 ps
T1151 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1281753286 Jul 04 07:48:50 PM PDT 24 Jul 04 07:58:37 PM PDT 24 3531128876 ps
T1152 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1985823034 Jul 04 08:08:15 PM PDT 24 Jul 04 08:18:20 PM PDT 24 4209199720 ps
T1153 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3389974224 Jul 04 07:58:41 PM PDT 24 Jul 04 08:12:14 PM PDT 24 4980475590 ps
T233 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1469435356 Jul 04 07:58:49 PM PDT 24 Jul 04 08:34:34 PM PDT 24 24327294921 ps
T1154 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.575647689 Jul 04 08:11:14 PM PDT 24 Jul 04 08:58:55 PM PDT 24 12893532925 ps
T1155 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.4131360114 Jul 04 07:48:00 PM PDT 24 Jul 04 11:15:30 PM PDT 24 65547165311 ps
T781 /workspace/coverage/default/62.chip_sw_all_escalation_resets.850671753 Jul 04 08:17:54 PM PDT 24 Jul 04 08:27:53 PM PDT 24 4638617848 ps
T1156 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1504088892 Jul 04 08:12:58 PM PDT 24 Jul 04 08:23:27 PM PDT 24 3566787360 ps
T1157 /workspace/coverage/default/16.chip_sw_all_escalation_resets.2108837413 Jul 04 08:13:47 PM PDT 24 Jul 04 08:26:01 PM PDT 24 6085891668 ps
T1158 /workspace/coverage/default/1.chip_sw_kmac_idle.2520027190 Jul 04 07:57:22 PM PDT 24 Jul 04 08:00:54 PM PDT 24 2862681640 ps
T1159 /workspace/coverage/default/1.chip_sw_hmac_oneshot.1951697238 Jul 04 07:58:07 PM PDT 24 Jul 04 08:03:34 PM PDT 24 3252204720 ps
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