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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.99 95.38 93.61 95.44 94.39 97.53 99.58


Total test records in report: 2901
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T1160 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3807597488 Jul 04 08:06:12 PM PDT 24 Jul 04 08:14:11 PM PDT 24 8753935836 ps
T318 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.867559597 Jul 04 07:48:07 PM PDT 24 Jul 04 07:55:16 PM PDT 24 3643039100 ps
T1161 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1389554168 Jul 04 07:48:20 PM PDT 24 Jul 04 08:23:03 PM PDT 24 10000169576 ps
T1162 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.692174081 Jul 04 08:01:23 PM PDT 24 Jul 04 08:06:00 PM PDT 24 2915222690 ps
T1163 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.327089800 Jul 04 08:07:27 PM PDT 24 Jul 04 09:03:34 PM PDT 24 14723275098 ps
T1164 /workspace/coverage/default/0.rom_e2e_asm_init_rma.4162246708 Jul 04 07:56:46 PM PDT 24 Jul 04 08:59:55 PM PDT 24 14196985524 ps
T1165 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3867399142 Jul 04 07:58:56 PM PDT 24 Jul 04 08:11:32 PM PDT 24 3852593088 ps
T1166 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.273265509 Jul 04 07:56:23 PM PDT 24 Jul 04 08:00:52 PM PDT 24 2515409160 ps
T370 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2280947734 Jul 04 07:49:39 PM PDT 24 Jul 04 08:02:40 PM PDT 24 18893376528 ps
T1167 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1771013268 Jul 04 07:58:41 PM PDT 24 Jul 04 08:09:19 PM PDT 24 8452291206 ps
T1168 /workspace/coverage/default/1.chip_sw_kmac_entropy.2372910581 Jul 04 07:58:03 PM PDT 24 Jul 04 08:03:12 PM PDT 24 3687013398 ps
T1169 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.17509616 Jul 04 08:17:51 PM PDT 24 Jul 04 08:24:22 PM PDT 24 3898262984 ps
T1170 /workspace/coverage/default/1.rom_e2e_static_critical.1479942367 Jul 04 08:07:07 PM PDT 24 Jul 04 09:18:24 PM PDT 24 17093402512 ps
T319 /workspace/coverage/default/57.chip_sw_all_escalation_resets.534872744 Jul 04 08:16:24 PM PDT 24 Jul 04 08:24:45 PM PDT 24 4375183994 ps
T1171 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3693241859 Jul 04 07:52:23 PM PDT 24 Jul 04 08:38:13 PM PDT 24 31965894023 ps
T1172 /workspace/coverage/default/1.rom_e2e_asm_init_prod.3920882856 Jul 04 08:05:03 PM PDT 24 Jul 04 09:08:46 PM PDT 24 15381256802 ps
T791 /workspace/coverage/default/69.chip_sw_all_escalation_resets.3805557333 Jul 04 08:19:57 PM PDT 24 Jul 04 08:30:15 PM PDT 24 5657389030 ps
T17 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1651159890 Jul 04 08:00:13 PM PDT 24 Jul 04 08:31:44 PM PDT 24 21411112342 ps
T1173 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3494017724 Jul 04 08:14:32 PM PDT 24 Jul 04 08:25:17 PM PDT 24 3987887624 ps
T1174 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2620332592 Jul 04 07:53:33 PM PDT 24 Jul 04 07:55:38 PM PDT 24 2734345255 ps
T1175 /workspace/coverage/default/0.chip_sw_csrng_smoketest.2804123816 Jul 04 07:50:58 PM PDT 24 Jul 04 07:54:45 PM PDT 24 3126035866 ps
T1176 /workspace/coverage/default/0.chip_tap_straps_prod.1387604697 Jul 04 07:49:43 PM PDT 24 Jul 04 07:52:12 PM PDT 24 2351769965 ps
T1177 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3101874497 Jul 04 07:58:45 PM PDT 24 Jul 04 08:31:28 PM PDT 24 9541757586 ps
T46 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.986202518 Jul 04 07:48:45 PM PDT 24 Jul 04 07:53:33 PM PDT 24 3443552136 ps
T1178 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3953202487 Jul 04 08:06:29 PM PDT 24 Jul 04 08:09:25 PM PDT 24 2691693284 ps
T1179 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2234996222 Jul 04 07:57:51 PM PDT 24 Jul 04 08:16:49 PM PDT 24 5860779172 ps
T1180 /workspace/coverage/default/0.chip_sw_uart_tx_rx.81926382 Jul 04 07:46:22 PM PDT 24 Jul 04 07:57:01 PM PDT 24 4433414712 ps
T193 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.554931317 Jul 04 07:47:50 PM PDT 24 Jul 04 07:59:34 PM PDT 24 5138491251 ps
T1181 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2891690983 Jul 04 07:50:30 PM PDT 24 Jul 04 07:59:41 PM PDT 24 7847105288 ps
T168 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3712759854 Jul 04 07:58:57 PM PDT 24 Jul 04 08:08:06 PM PDT 24 5559153356 ps
T1182 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.748725732 Jul 04 08:16:39 PM PDT 24 Jul 04 08:22:12 PM PDT 24 3285293256 ps
T224 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1276709197 Jul 04 07:57:10 PM PDT 24 Jul 04 08:29:07 PM PDT 24 7861903896 ps
T1183 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3473626123 Jul 04 07:48:20 PM PDT 24 Jul 04 07:57:31 PM PDT 24 4660969700 ps
T1184 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.266862905 Jul 04 07:50:08 PM PDT 24 Jul 04 07:53:31 PM PDT 24 2725150772 ps
T1185 /workspace/coverage/default/2.chip_tap_straps_testunlock0.979764501 Jul 04 08:08:13 PM PDT 24 Jul 04 08:14:29 PM PDT 24 4123120908 ps
T346 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4269258826 Jul 04 08:04:59 PM PDT 24 Jul 04 08:21:05 PM PDT 24 4654679320 ps
T195 /workspace/coverage/default/0.chip_jtag_mem_access.1554428784 Jul 04 07:41:15 PM PDT 24 Jul 04 08:09:09 PM PDT 24 13383377030 ps
T1186 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1453024048 Jul 04 08:07:27 PM PDT 24 Jul 04 08:13:32 PM PDT 24 2727967780 ps
T1187 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1124527213 Jul 04 08:10:50 PM PDT 24 Jul 04 08:20:39 PM PDT 24 6666828780 ps
T1188 /workspace/coverage/default/0.chip_sw_power_sleep_load.3491756276 Jul 04 07:51:58 PM PDT 24 Jul 04 08:06:34 PM PDT 24 11743890284 ps
T1189 /workspace/coverage/default/1.chip_sw_hmac_smoketest.2611700948 Jul 04 08:01:19 PM PDT 24 Jul 04 08:07:10 PM PDT 24 2845066658 ps
T293 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1214834962 Jul 04 08:20:21 PM PDT 24 Jul 04 08:28:18 PM PDT 24 3543333920 ps
T1190 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2648713601 Jul 04 08:14:10 PM PDT 24 Jul 04 09:29:46 PM PDT 24 20838380040 ps
T757 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3274240841 Jul 04 08:18:47 PM PDT 24 Jul 04 08:25:05 PM PDT 24 4153921324 ps
T1191 /workspace/coverage/default/0.chip_sw_csrng_kat_test.3473543728 Jul 04 07:48:53 PM PDT 24 Jul 04 07:52:37 PM PDT 24 2610645820 ps
T802 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2894044456 Jul 04 08:26:03 PM PDT 24 Jul 04 08:32:10 PM PDT 24 3559699590 ps
T789 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.71137709 Jul 04 08:18:29 PM PDT 24 Jul 04 08:24:49 PM PDT 24 3799723150 ps
T1192 /workspace/coverage/default/0.chip_sw_hmac_smoketest.464430374 Jul 04 07:51:55 PM PDT 24 Jul 04 07:57:43 PM PDT 24 3642340090 ps
T1193 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3454253093 Jul 04 08:10:20 PM PDT 24 Jul 04 08:21:53 PM PDT 24 5609191394 ps
T1194 /workspace/coverage/default/4.chip_tap_straps_prod.4123552232 Jul 04 08:11:55 PM PDT 24 Jul 04 08:14:58 PM PDT 24 3200045928 ps
T1195 /workspace/coverage/default/55.chip_sw_all_escalation_resets.3647596080 Jul 04 08:18:06 PM PDT 24 Jul 04 08:28:08 PM PDT 24 6438694806 ps
T1196 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1095450450 Jul 04 08:04:39 PM PDT 24 Jul 04 09:21:17 PM PDT 24 46350748638 ps
T1197 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2414632968 Jul 04 07:47:43 PM PDT 24 Jul 04 07:49:25 PM PDT 24 2259794411 ps
T1198 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1185580625 Jul 04 08:16:30 PM PDT 24 Jul 04 08:23:05 PM PDT 24 3190410124 ps
T1199 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1692724216 Jul 04 08:00:07 PM PDT 24 Jul 04 09:51:33 PM PDT 24 24408491202 ps
T366 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2686639794 Jul 04 08:07:53 PM PDT 24 Jul 04 08:11:06 PM PDT 24 2961497952 ps
T1200 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3621285625 Jul 04 07:46:10 PM PDT 24 Jul 04 10:34:09 PM PDT 24 59571474410 ps
T1201 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2165504872 Jul 04 08:06:44 PM PDT 24 Jul 04 08:08:33 PM PDT 24 2959360894 ps
T1202 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.363234625 Jul 04 07:48:49 PM PDT 24 Jul 04 09:15:31 PM PDT 24 47384924300 ps
T1203 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3782879635 Jul 04 07:53:57 PM PDT 24 Jul 04 08:03:31 PM PDT 24 5818390526 ps
T1204 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.541623373 Jul 04 08:00:59 PM PDT 24 Jul 04 08:18:18 PM PDT 24 6829075106 ps
T1205 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.434779035 Jul 04 07:54:50 PM PDT 24 Jul 04 09:01:11 PM PDT 24 15435839000 ps
T1206 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1995767674 Jul 04 07:47:57 PM PDT 24 Jul 04 09:06:07 PM PDT 24 28059237860 ps
T1207 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2959592284 Jul 04 07:56:27 PM PDT 24 Jul 04 08:15:32 PM PDT 24 10948818466 ps
T771 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1293704287 Jul 04 08:20:24 PM PDT 24 Jul 04 08:26:34 PM PDT 24 3715173828 ps
T1208 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2029413079 Jul 04 08:13:38 PM PDT 24 Jul 04 08:38:05 PM PDT 24 8715667788 ps
T1209 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2276252973 Jul 04 07:51:41 PM PDT 24 Jul 04 07:58:05 PM PDT 24 3506379241 ps
T156 /workspace/coverage/default/2.chip_plic_all_irqs_10.3336075570 Jul 04 08:07:03 PM PDT 24 Jul 04 08:16:32 PM PDT 24 3237025700 ps
T1210 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.526078407 Jul 04 07:54:10 PM PDT 24 Jul 04 08:53:39 PM PDT 24 14581458104 ps
T299 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3070358858 Jul 04 08:01:22 PM PDT 24 Jul 04 08:05:43 PM PDT 24 3014915175 ps
T736 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1145015318 Jul 04 08:14:57 PM PDT 24 Jul 04 08:23:56 PM PDT 24 4394828490 ps
T1211 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2767180966 Jul 04 08:14:54 PM PDT 24 Jul 04 08:37:04 PM PDT 24 8295527000 ps
T1212 /workspace/coverage/default/0.chip_sw_kmac_smoketest.313719982 Jul 04 07:51:56 PM PDT 24 Jul 04 07:55:50 PM PDT 24 2231790026 ps
T1213 /workspace/coverage/default/0.rom_e2e_smoke.2221933423 Jul 04 07:56:51 PM PDT 24 Jul 04 08:56:51 PM PDT 24 14857910844 ps
T1214 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2137518774 Jul 04 07:49:44 PM PDT 24 Jul 04 08:30:12 PM PDT 24 9277666296 ps
T1215 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2976054456 Jul 04 08:00:19 PM PDT 24 Jul 04 08:10:25 PM PDT 24 4556243450 ps
T1216 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.70603928 Jul 04 07:56:03 PM PDT 24 Jul 04 07:58:13 PM PDT 24 2611883561 ps
T1217 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2744206867 Jul 04 07:57:55 PM PDT 24 Jul 04 08:30:05 PM PDT 24 10442716976 ps
T1218 /workspace/coverage/default/2.chip_sw_edn_sw_mode.3402829438 Jul 04 08:07:36 PM PDT 24 Jul 04 08:32:07 PM PDT 24 7097534518 ps
T1219 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.4246228621 Jul 04 08:01:21 PM PDT 24 Jul 04 08:09:03 PM PDT 24 3787160560 ps
T1220 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1145814570 Jul 04 07:48:43 PM PDT 24 Jul 04 08:06:16 PM PDT 24 5990098043 ps
T50 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3169049499 Jul 04 07:48:34 PM PDT 24 Jul 04 07:59:48 PM PDT 24 6869163296 ps
T1221 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1505131115 Jul 04 08:01:30 PM PDT 24 Jul 04 09:44:05 PM PDT 24 17526567894 ps
T1222 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1810782938 Jul 04 08:23:02 PM PDT 24 Jul 04 08:45:46 PM PDT 24 7931200128 ps
T804 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1227757263 Jul 04 08:17:37 PM PDT 24 Jul 04 08:23:06 PM PDT 24 3732715332 ps
T203 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1381774409 Jul 04 07:46:35 PM PDT 24 Jul 04 08:15:50 PM PDT 24 22592489320 ps
T1223 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3545250907 Jul 04 08:09:55 PM PDT 24 Jul 04 08:13:12 PM PDT 24 2934844318 ps
T1224 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1733047612 Jul 04 08:13:10 PM PDT 24 Jul 04 08:48:39 PM PDT 24 12682749844 ps
T111 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.806752544 Jul 04 08:00:39 PM PDT 24 Jul 04 11:28:35 PM PDT 24 86231798963 ps
T1225 /workspace/coverage/default/1.chip_sw_gpio_smoketest.3566400543 Jul 04 08:02:04 PM PDT 24 Jul 04 08:07:16 PM PDT 24 2944407852 ps
T1226 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3709231374 Jul 04 07:52:32 PM PDT 24 Jul 04 07:59:41 PM PDT 24 3405323552 ps
T1227 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.767765547 Jul 04 07:50:35 PM PDT 24 Jul 04 07:56:53 PM PDT 24 3790026297 ps
T47 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1160674814 Jul 04 08:05:09 PM PDT 24 Jul 04 08:09:16 PM PDT 24 3152464564 ps
T756 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2366745669 Jul 04 08:20:22 PM PDT 24 Jul 04 08:26:47 PM PDT 24 4139341934 ps
T1228 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1153422085 Jul 04 07:50:19 PM PDT 24 Jul 04 08:47:11 PM PDT 24 20340816225 ps
T790 /workspace/coverage/default/22.chip_sw_all_escalation_resets.1799108413 Jul 04 08:15:10 PM PDT 24 Jul 04 08:23:09 PM PDT 24 5538153204 ps
T663 /workspace/coverage/default/1.chip_sw_edn_boot_mode.2880194856 Jul 04 07:55:00 PM PDT 24 Jul 04 08:04:47 PM PDT 24 3483078288 ps
T12 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.3869952415 Jul 04 07:48:20 PM PDT 24 Jul 04 07:53:35 PM PDT 24 3752408806 ps
T1229 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2298587392 Jul 04 07:54:59 PM PDT 24 Jul 04 08:07:47 PM PDT 24 4358048194 ps
T1230 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.188141250 Jul 04 07:55:50 PM PDT 24 Jul 04 08:01:07 PM PDT 24 3123154454 ps
T1231 /workspace/coverage/default/1.chip_sw_power_idle_load.2765340903 Jul 04 07:59:16 PM PDT 24 Jul 04 08:08:57 PM PDT 24 4792525000 ps
T1232 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2598761672 Jul 04 08:15:03 PM PDT 24 Jul 04 08:22:54 PM PDT 24 3144687736 ps
T1233 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2028096819 Jul 04 07:47:12 PM PDT 24 Jul 04 08:01:37 PM PDT 24 6523312215 ps
T1234 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3476540209 Jul 04 08:02:56 PM PDT 24 Jul 04 08:10:58 PM PDT 24 4105588956 ps
T1235 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.242060997 Jul 04 07:51:43 PM PDT 24 Jul 04 08:00:23 PM PDT 24 4039113980 ps
T1236 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.79691977 Jul 04 07:56:42 PM PDT 24 Jul 04 08:40:59 PM PDT 24 12039565360 ps
T1237 /workspace/coverage/default/2.chip_tap_straps_prod.2111732658 Jul 04 08:09:15 PM PDT 24 Jul 04 08:12:21 PM PDT 24 3346415783 ps
T1238 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2491941338 Jul 04 07:58:06 PM PDT 24 Jul 04 08:08:45 PM PDT 24 4364239878 ps
T51 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2627534383 Jul 04 08:05:13 PM PDT 24 Jul 04 08:11:28 PM PDT 24 6624774468 ps
T1239 /workspace/coverage/default/2.chip_sw_edn_auto_mode.3840687150 Jul 04 08:06:36 PM PDT 24 Jul 04 08:40:56 PM PDT 24 6850030988 ps
T1240 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2651379548 Jul 04 07:57:48 PM PDT 24 Jul 04 08:28:27 PM PDT 24 9130470156 ps
T1241 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.328163251 Jul 04 07:58:31 PM PDT 24 Jul 04 08:09:05 PM PDT 24 3584671596 ps
T1242 /workspace/coverage/default/0.chip_sw_aes_masking_off.605747820 Jul 04 07:49:57 PM PDT 24 Jul 04 07:55:50 PM PDT 24 3292412071 ps
T1243 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.4015845163 Jul 04 08:01:34 PM PDT 24 Jul 04 08:06:39 PM PDT 24 3381688941 ps
T386 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3489602358 Jul 04 08:16:26 PM PDT 24 Jul 04 08:23:51 PM PDT 24 3874443540 ps
T1244 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3587234739 Jul 04 08:12:51 PM PDT 24 Jul 04 09:12:27 PM PDT 24 13743326500 ps
T741 /workspace/coverage/default/64.chip_sw_all_escalation_resets.971977669 Jul 04 08:17:15 PM PDT 24 Jul 04 08:27:45 PM PDT 24 5098967138 ps
T1245 /workspace/coverage/default/2.chip_sw_power_idle_load.1115391349 Jul 04 08:10:31 PM PDT 24 Jul 04 08:22:36 PM PDT 24 4895520680 ps
T1246 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1210443959 Jul 04 07:52:25 PM PDT 24 Jul 04 08:13:02 PM PDT 24 8584916184 ps
T1247 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2950156337 Jul 04 07:48:50 PM PDT 24 Jul 04 08:11:07 PM PDT 24 5443509192 ps
T262 /workspace/coverage/default/3.chip_sw_all_escalation_resets.1470064782 Jul 04 08:10:43 PM PDT 24 Jul 04 08:23:15 PM PDT 24 5469684216 ps
T1248 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3755689598 Jul 04 08:01:33 PM PDT 24 Jul 04 08:04:39 PM PDT 24 2505272512 ps
T1249 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.715131995 Jul 04 08:04:31 PM PDT 24 Jul 04 08:08:34 PM PDT 24 2936471940 ps
T1250 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2362674973 Jul 04 07:55:59 PM PDT 24 Jul 04 07:59:42 PM PDT 24 2809712910 ps
T687 /workspace/coverage/default/3.chip_tap_straps_dev.867981878 Jul 04 08:11:17 PM PDT 24 Jul 04 08:33:33 PM PDT 24 12163641889 ps
T1251 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2400824870 Jul 04 08:17:46 PM PDT 24 Jul 04 08:25:36 PM PDT 24 4281167676 ps
T1252 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1098004644 Jul 04 08:09:13 PM PDT 24 Jul 04 08:51:00 PM PDT 24 24810259450 ps
T1253 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1100576665 Jul 04 07:56:05 PM PDT 24 Jul 04 09:08:53 PM PDT 24 17190396720 ps
T676 /workspace/coverage/default/1.chip_sw_all_escalation_resets.2350806679 Jul 04 07:53:19 PM PDT 24 Jul 04 08:04:34 PM PDT 24 4276341624 ps
T88 /workspace/coverage/default/50.chip_sw_all_escalation_resets.1239308047 Jul 04 08:18:00 PM PDT 24 Jul 04 08:28:11 PM PDT 24 5568599250 ps
T1254 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.545752686 Jul 04 08:14:11 PM PDT 24 Jul 04 09:06:37 PM PDT 24 14388953576 ps
T738 /workspace/coverage/default/92.chip_sw_all_escalation_resets.2182397763 Jul 04 08:19:35 PM PDT 24 Jul 04 08:28:53 PM PDT 24 4717214304 ps
T13 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.2331137627 Jul 04 07:48:26 PM PDT 24 Jul 04 07:53:44 PM PDT 24 3586472456 ps
T413 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.968254411 Jul 04 07:50:25 PM PDT 24 Jul 05 01:09:50 AM PDT 24 133903218760 ps
T414 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3795567111 Jul 04 08:07:01 PM PDT 24 Jul 04 08:48:07 PM PDT 24 21771969631 ps
T415 /workspace/coverage/default/71.chip_sw_all_escalation_resets.2312504184 Jul 04 08:19:27 PM PDT 24 Jul 04 08:29:35 PM PDT 24 6166068430 ps
T416 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1856157195 Jul 04 08:27:02 PM PDT 24 Jul 04 08:34:09 PM PDT 24 3712801582 ps
T417 /workspace/coverage/default/0.chip_sw_uart_smoketest.417829728 Jul 04 07:51:00 PM PDT 24 Jul 04 07:55:54 PM PDT 24 2745124484 ps
T418 /workspace/coverage/default/2.chip_sw_kmac_entropy.3761775214 Jul 04 08:04:06 PM PDT 24 Jul 04 08:07:46 PM PDT 24 2739679488 ps
T419 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3926972146 Jul 04 08:12:36 PM PDT 24 Jul 04 08:23:15 PM PDT 24 3794706347 ps
T420 /workspace/coverage/default/2.chip_tap_straps_rma.2326401970 Jul 04 08:09:45 PM PDT 24 Jul 04 08:16:52 PM PDT 24 3981360443 ps
T421 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.4287623622 Jul 04 07:47:59 PM PDT 24 Jul 04 07:51:56 PM PDT 24 2859862871 ps
T1255 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1350271898 Jul 04 07:48:38 PM PDT 24 Jul 04 07:53:47 PM PDT 24 3432033372 ps
T361 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3560548018 Jul 04 07:48:56 PM PDT 24 Jul 04 08:02:31 PM PDT 24 4770867968 ps
T1256 /workspace/coverage/default/0.chip_sw_otbn_smoketest.481563967 Jul 04 07:53:45 PM PDT 24 Jul 04 08:10:38 PM PDT 24 5207446714 ps
T1257 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.966524117 Jul 04 08:09:07 PM PDT 24 Jul 04 08:16:57 PM PDT 24 3183963136 ps
T352 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3768160385 Jul 04 07:59:38 PM PDT 24 Jul 04 08:06:52 PM PDT 24 3943335200 ps
T1258 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.4021211209 Jul 04 07:53:51 PM PDT 24 Jul 04 08:00:17 PM PDT 24 3578743768 ps
T1259 /workspace/coverage/default/3.chip_tap_straps_testunlock0.634658734 Jul 04 08:11:50 PM PDT 24 Jul 04 08:14:31 PM PDT 24 3460714718 ps
T181 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.233094132 Jul 04 07:52:43 PM PDT 24 Jul 04 09:19:04 PM PDT 24 43170462657 ps
T1260 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3189540638 Jul 04 08:06:55 PM PDT 24 Jul 04 08:17:22 PM PDT 24 5996620250 ps
T1261 /workspace/coverage/default/2.chip_sw_hmac_multistream.760533182 Jul 04 08:08:24 PM PDT 24 Jul 04 08:33:28 PM PDT 24 7086064624 ps
T1262 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3452675799 Jul 04 07:53:38 PM PDT 24 Jul 04 08:58:30 PM PDT 24 14302240422 ps
T685 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.191228800 Jul 04 08:13:28 PM PDT 24 Jul 04 08:22:19 PM PDT 24 6048668950 ps
T387 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2894929876 Jul 04 08:18:48 PM PDT 24 Jul 04 08:26:41 PM PDT 24 3779422998 ps
T1263 /workspace/coverage/default/0.chip_sw_rv_timer_irq.2247186555 Jul 04 07:47:27 PM PDT 24 Jul 04 07:50:56 PM PDT 24 2891151574 ps
T1264 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.604002061 Jul 04 07:55:54 PM PDT 24 Jul 04 08:12:24 PM PDT 24 5615655168 ps
T1265 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3775019425 Jul 04 07:50:27 PM PDT 24 Jul 04 07:56:27 PM PDT 24 3580075096 ps
T1266 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.305855788 Jul 04 07:47:36 PM PDT 24 Jul 04 08:00:17 PM PDT 24 5955860640 ps
T1267 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1837538612 Jul 04 08:00:09 PM PDT 24 Jul 04 08:34:50 PM PDT 24 11278702223 ps
T1268 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1645683704 Jul 04 08:11:47 PM PDT 24 Jul 04 08:28:46 PM PDT 24 11192506637 ps
T371 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.362330332 Jul 04 07:53:50 PM PDT 24 Jul 04 08:02:51 PM PDT 24 17364243002 ps
T1269 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.297796519 Jul 04 07:49:56 PM PDT 24 Jul 04 08:00:00 PM PDT 24 4285813900 ps
T1270 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3280230817 Jul 04 07:54:32 PM PDT 24 Jul 04 08:03:42 PM PDT 24 5321716940 ps
T1271 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1517508789 Jul 04 08:06:49 PM PDT 24 Jul 04 08:14:27 PM PDT 24 4411521320 ps
T1272 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2152776946 Jul 04 08:10:49 PM PDT 24 Jul 04 08:27:08 PM PDT 24 5342023626 ps
T1273 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1846001604 Jul 04 08:13:51 PM PDT 24 Jul 04 08:23:46 PM PDT 24 6549440334 ps
T1274 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1217539324 Jul 04 07:48:05 PM PDT 24 Jul 04 07:49:53 PM PDT 24 2498929371 ps
T1275 /workspace/coverage/default/1.chip_sw_otbn_smoketest.454381882 Jul 04 08:02:16 PM PDT 24 Jul 04 08:28:51 PM PDT 24 7261193240 ps
T194 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3877513517 Jul 04 07:47:16 PM PDT 24 Jul 04 07:56:08 PM PDT 24 4399629894 ps
T1276 /workspace/coverage/default/2.chip_sw_csrng_smoketest.1426597551 Jul 04 08:11:10 PM PDT 24 Jul 04 08:14:27 PM PDT 24 2537164940 ps
T14 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.2606381839 Jul 04 07:52:43 PM PDT 24 Jul 04 07:57:05 PM PDT 24 3090659094 ps
T1277 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.271277508 Jul 04 07:49:39 PM PDT 24 Jul 04 07:53:50 PM PDT 24 3148911950 ps
T1278 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3685332799 Jul 04 07:58:17 PM PDT 24 Jul 04 08:04:09 PM PDT 24 2879725702 ps
T336 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3360232861 Jul 04 07:50:27 PM PDT 24 Jul 04 08:26:58 PM PDT 24 14747060544 ps
T1279 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3812285602 Jul 04 08:06:34 PM PDT 24 Jul 04 08:30:28 PM PDT 24 12209216624 ps
T1280 /workspace/coverage/default/0.rom_e2e_asm_init_dev.1110480319 Jul 04 07:56:17 PM PDT 24 Jul 04 09:13:10 PM PDT 24 15517011920 ps
T1281 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2346042682 Jul 04 08:09:40 PM PDT 24 Jul 04 08:15:08 PM PDT 24 3498228200 ps
T1282 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3347872428 Jul 04 07:55:14 PM PDT 24 Jul 04 08:01:56 PM PDT 24 3930429493 ps
T1283 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3659633062 Jul 04 08:05:26 PM PDT 24 Jul 04 08:16:39 PM PDT 24 7418609724 ps
T1284 /workspace/coverage/default/2.chip_sw_rv_timer_irq.682539552 Jul 04 08:05:39 PM PDT 24 Jul 04 08:09:58 PM PDT 24 3182229752 ps
T1285 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2494712900 Jul 04 07:55:44 PM PDT 24 Jul 04 08:06:27 PM PDT 24 4387590741 ps
T1286 /workspace/coverage/default/0.rom_keymgr_functest.1731081220 Jul 04 07:51:19 PM PDT 24 Jul 04 08:00:02 PM PDT 24 4866775618 ps
T1287 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.375940877 Jul 04 08:12:11 PM PDT 24 Jul 04 08:21:59 PM PDT 24 6965004038 ps
T1288 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2663026853 Jul 04 07:49:31 PM PDT 24 Jul 04 07:59:34 PM PDT 24 5271403740 ps
T1289 /workspace/coverage/default/38.chip_sw_all_escalation_resets.3247123305 Jul 04 08:16:28 PM PDT 24 Jul 04 08:28:32 PM PDT 24 5387627032 ps
T800 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2302359121 Jul 04 08:18:55 PM PDT 24 Jul 04 08:25:54 PM PDT 24 4162066654 ps
T787 /workspace/coverage/default/80.chip_sw_all_escalation_resets.551040122 Jul 04 08:18:59 PM PDT 24 Jul 04 08:30:36 PM PDT 24 5539814572 ps
T1290 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1396368278 Jul 04 08:04:57 PM PDT 24 Jul 04 08:13:19 PM PDT 24 18516005452 ps
T1291 /workspace/coverage/default/2.rom_e2e_asm_init_rma.450799378 Jul 04 08:13:50 PM PDT 24 Jul 04 09:04:54 PM PDT 24 15610495480 ps
T1292 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.905036856 Jul 04 07:53:36 PM PDT 24 Jul 04 07:56:45 PM PDT 24 2768647864 ps
T1293 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2435582103 Jul 04 08:13:01 PM PDT 24 Jul 04 08:21:31 PM PDT 24 7300689166 ps
T809 /workspace/coverage/default/47.chip_sw_all_escalation_resets.872545682 Jul 04 08:17:29 PM PDT 24 Jul 04 08:25:01 PM PDT 24 4838722572 ps
T788 /workspace/coverage/default/90.chip_sw_all_escalation_resets.2959585627 Jul 04 08:19:54 PM PDT 24 Jul 04 08:28:49 PM PDT 24 5536387176 ps
T1294 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2845949287 Jul 04 07:48:39 PM PDT 24 Jul 04 07:57:54 PM PDT 24 3754419752 ps
T1295 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3772606215 Jul 04 07:51:43 PM PDT 24 Jul 04 07:59:16 PM PDT 24 4558380440 ps
T1296 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1793495142 Jul 04 08:05:10 PM PDT 24 Jul 04 08:14:37 PM PDT 24 6291213576 ps
T1297 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.898930955 Jul 04 08:01:05 PM PDT 24 Jul 04 08:10:48 PM PDT 24 5538531720 ps
T772 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2848617428 Jul 04 08:21:38 PM PDT 24 Jul 04 08:31:56 PM PDT 24 5657088808 ps
T1298 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2881982235 Jul 04 07:59:50 PM PDT 24 Jul 04 09:19:40 PM PDT 24 15163161382 ps
T1299 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1044688364 Jul 04 08:05:28 PM PDT 24 Jul 04 08:21:23 PM PDT 24 5467272616 ps
T1300 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.2886831406 Jul 04 08:03:19 PM PDT 24 Jul 04 08:22:07 PM PDT 24 6222029718 ps
T1301 /workspace/coverage/default/2.rom_e2e_smoke.216751281 Jul 04 08:14:09 PM PDT 24 Jul 04 09:08:08 PM PDT 24 15143023026 ps
T1302 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1793239040 Jul 04 08:06:33 PM PDT 24 Jul 04 09:03:33 PM PDT 24 18463763068 ps
T1303 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3751995443 Jul 04 07:54:46 PM PDT 24 Jul 04 08:11:40 PM PDT 24 6541097407 ps
T1304 /workspace/coverage/default/1.chip_sw_uart_tx_rx.1518551071 Jul 04 07:52:56 PM PDT 24 Jul 04 08:03:26 PM PDT 24 4447953016 ps
T1305 /workspace/coverage/default/1.chip_tap_straps_dev.1520314400 Jul 04 07:59:33 PM PDT 24 Jul 04 08:02:40 PM PDT 24 2288627689 ps
T739 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3297584808 Jul 04 08:12:02 PM PDT 24 Jul 04 08:18:29 PM PDT 24 3604190828 ps
T1306 /workspace/coverage/default/2.chip_sw_example_flash.3443974471 Jul 04 08:03:46 PM PDT 24 Jul 04 08:08:58 PM PDT 24 2882550824 ps
T1307 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3260330439 Jul 04 07:49:26 PM PDT 24 Jul 04 08:01:37 PM PDT 24 5616032865 ps
T1308 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.291817639 Jul 04 08:08:04 PM PDT 24 Jul 04 08:12:29 PM PDT 24 3570374347 ps
T1309 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1923077820 Jul 04 07:48:13 PM PDT 24 Jul 04 07:58:57 PM PDT 24 3972719976 ps
T1310 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.4189313647 Jul 04 07:51:07 PM PDT 24 Jul 04 08:01:37 PM PDT 24 4944226596 ps
T137 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3568882519 Jul 04 07:48:23 PM PDT 24 Jul 04 07:56:08 PM PDT 24 5305732856 ps
T1311 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.4057235837 Jul 04 07:55:44 PM PDT 24 Jul 04 08:33:48 PM PDT 24 33198790236 ps
T1312 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1461414140 Jul 04 08:01:36 PM PDT 24 Jul 04 08:07:22 PM PDT 24 3088655220 ps
T1313 /workspace/coverage/default/0.chip_sw_hmac_multistream.428288441 Jul 04 07:51:57 PM PDT 24 Jul 04 08:23:01 PM PDT 24 7546380920 ps
T1314 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3155271014 Jul 04 08:12:26 PM PDT 24 Jul 04 08:16:06 PM PDT 24 2330660342 ps
T1315 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3964248800 Jul 04 07:57:38 PM PDT 24 Jul 04 08:05:50 PM PDT 24 4931849224 ps
T1316 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.958872781 Jul 04 08:06:13 PM PDT 24 Jul 04 09:02:25 PM PDT 24 15549835950 ps
T263 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1549829340 Jul 04 07:57:52 PM PDT 24 Jul 04 08:15:22 PM PDT 24 7264665964 ps
T774 /workspace/coverage/default/15.chip_sw_all_escalation_resets.1990710263 Jul 04 08:14:34 PM PDT 24 Jul 04 08:23:18 PM PDT 24 6191570328 ps
T801 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3812364589 Jul 04 08:16:59 PM PDT 24 Jul 04 08:23:57 PM PDT 24 3783506144 ps
T1317 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1925676842 Jul 04 07:55:30 PM PDT 24 Jul 04 09:03:13 PM PDT 24 14009898134 ps
T1318 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.4137977151 Jul 04 08:15:11 PM PDT 24 Jul 04 08:54:11 PM PDT 24 13258442850 ps
T362 /workspace/coverage/default/0.chip_sw_pattgen_ios.3782040285 Jul 04 07:46:07 PM PDT 24 Jul 04 07:51:58 PM PDT 24 2849451758 ps
T89 /workspace/coverage/default/82.chip_sw_all_escalation_resets.1504842588 Jul 04 08:21:17 PM PDT 24 Jul 04 08:30:35 PM PDT 24 4750478640 ps
T1319 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.496648428 Jul 04 08:03:27 PM PDT 24 Jul 04 08:17:51 PM PDT 24 4528654984 ps
T784 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3163218569 Jul 04 08:18:06 PM PDT 24 Jul 04 08:26:03 PM PDT 24 3619616312 ps
T1320 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1916681761 Jul 04 08:16:59 PM PDT 24 Jul 04 08:22:20 PM PDT 24 3400885878 ps
T1321 /workspace/coverage/default/2.chip_sw_example_concurrency.2637554848 Jul 04 08:01:40 PM PDT 24 Jul 04 08:04:42 PM PDT 24 2883058960 ps
T808 /workspace/coverage/default/61.chip_sw_all_escalation_resets.114765388 Jul 04 08:17:48 PM PDT 24 Jul 04 08:31:38 PM PDT 24 5887031902 ps
T1322 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3474061726 Jul 04 08:12:52 PM PDT 24 Jul 04 10:00:50 PM PDT 24 29638454332 ps
T1323 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1894017473 Jul 04 07:52:49 PM PDT 24 Jul 04 08:04:36 PM PDT 24 4290711665 ps
T1324 /workspace/coverage/default/1.chip_sw_hmac_enc.595327900 Jul 04 07:57:36 PM PDT 24 Jul 04 08:01:29 PM PDT 24 2795591792 ps
T1325 /workspace/coverage/default/99.chip_sw_all_escalation_resets.1096271074 Jul 04 08:22:43 PM PDT 24 Jul 04 08:30:53 PM PDT 24 5742016950 ps
T1326 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1701214550 Jul 04 08:14:03 PM PDT 24 Jul 04 08:37:32 PM PDT 24 8722718292 ps
T1327 /workspace/coverage/default/2.chip_sw_example_rom.3997419268 Jul 04 08:03:15 PM PDT 24 Jul 04 08:05:18 PM PDT 24 1952232712 ps
T169 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1318645613 Jul 04 08:07:24 PM PDT 24 Jul 04 08:16:35 PM PDT 24 5028302004 ps
T1328 /workspace/coverage/default/0.chip_sw_example_manufacturer.3972151515 Jul 04 07:46:28 PM PDT 24 Jul 04 07:50:29 PM PDT 24 3275575260 ps
T1329 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3076641028 Jul 04 08:08:33 PM PDT 24 Jul 04 08:15:27 PM PDT 24 3807715240 ps
T742 /workspace/coverage/default/30.chip_sw_all_escalation_resets.607202350 Jul 04 08:15:28 PM PDT 24 Jul 04 08:24:17 PM PDT 24 4315392198 ps
T333 /workspace/coverage/default/1.chip_plic_all_irqs_0.2130110860 Jul 04 07:57:03 PM PDT 24 Jul 04 08:20:44 PM PDT 24 6020804024 ps
T1330 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1279662291 Jul 04 07:50:23 PM PDT 24 Jul 04 07:53:41 PM PDT 24 2760292648 ps
T1331 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3484831217 Jul 04 08:19:52 PM PDT 24 Jul 04 08:25:36 PM PDT 24 4321026408 ps
T1332 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.684711472 Jul 04 08:03:45 PM PDT 24 Jul 04 11:56:43 PM PDT 24 79247926350 ps
T1333 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3101559530 Jul 04 08:17:52 PM PDT 24 Jul 04 08:24:49 PM PDT 24 3903318570 ps
T1334 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.417925641 Jul 04 07:54:40 PM PDT 24 Jul 04 08:03:08 PM PDT 24 4952869180 ps
T1335 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3341720431 Jul 04 07:55:05 PM PDT 24 Jul 04 09:03:32 PM PDT 24 16284931072 ps
T48 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2380036948 Jul 04 07:53:39 PM PDT 24 Jul 04 07:59:50 PM PDT 24 3187661816 ps
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