| T239 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.651487880 |
|
|
Jul 06 07:31:55 PM PDT 24 |
Jul 06 08:31:12 PM PDT 24 |
12357941000 ps |
| T261 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3903492960 |
|
|
Jul 06 07:36:49 PM PDT 24 |
Jul 06 07:48:03 PM PDT 24 |
6579823544 ps |
| T894 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.3226015158 |
|
|
Jul 06 07:32:38 PM PDT 24 |
Jul 06 07:53:11 PM PDT 24 |
6816628360 ps |
| T78 |
/workspace/coverage/default/2.chip_jtag_mem_access.228925252 |
|
|
Jul 06 07:43:35 PM PDT 24 |
Jul 06 08:05:59 PM PDT 24 |
13772673386 ps |
| T329 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.2422398499 |
|
|
Jul 06 07:38:56 PM PDT 24 |
Jul 06 08:09:53 PM PDT 24 |
6800916464 ps |
| T359 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1241899693 |
|
|
Jul 06 07:57:52 PM PDT 24 |
Jul 06 08:25:51 PM PDT 24 |
7570230304 ps |
| T781 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2867517972 |
|
|
Jul 06 08:04:25 PM PDT 24 |
Jul 06 08:11:48 PM PDT 24 |
3530242376 ps |
| T38 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.3870228144 |
|
|
Jul 06 07:44:59 PM PDT 24 |
Jul 06 07:51:46 PM PDT 24 |
2963625485 ps |
| T787 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4238744963 |
|
|
Jul 06 07:56:29 PM PDT 24 |
Jul 06 08:04:26 PM PDT 24 |
3706605384 ps |
| T660 |
/workspace/coverage/default/0.chip_sw_power_idle_load.4261800363 |
|
|
Jul 06 07:31:08 PM PDT 24 |
Jul 06 07:42:10 PM PDT 24 |
4146107020 ps |
| T895 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2798600182 |
|
|
Jul 06 07:34:44 PM PDT 24 |
Jul 06 07:39:55 PM PDT 24 |
3637660200 ps |
| T697 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3012212536 |
|
|
Jul 06 08:04:32 PM PDT 24 |
Jul 06 08:12:04 PM PDT 24 |
3642873086 ps |
| T896 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.518780566 |
|
|
Jul 06 07:46:05 PM PDT 24 |
Jul 06 07:49:59 PM PDT 24 |
2480942243 ps |
| T690 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1514148462 |
|
|
Jul 06 08:04:26 PM PDT 24 |
Jul 06 08:12:36 PM PDT 24 |
3398106254 ps |
| T897 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.326150455 |
|
|
Jul 06 07:31:33 PM PDT 24 |
Jul 06 07:35:34 PM PDT 24 |
3374599864 ps |
| T291 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1552955599 |
|
|
Jul 06 07:39:31 PM PDT 24 |
Jul 06 07:47:44 PM PDT 24 |
3807373144 ps |
| T365 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.1611893892 |
|
|
Jul 06 08:01:17 PM PDT 24 |
Jul 06 08:10:22 PM PDT 24 |
4402582962 ps |
| T898 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.3102950649 |
|
|
Jul 06 07:37:47 PM PDT 24 |
Jul 06 07:44:01 PM PDT 24 |
3233729087 ps |
| T899 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3480415803 |
|
|
Jul 06 07:29:26 PM PDT 24 |
Jul 06 07:37:22 PM PDT 24 |
5441998682 ps |
| T35 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.287209116 |
|
|
Jul 06 07:47:53 PM PDT 24 |
Jul 06 08:15:05 PM PDT 24 |
22832850040 ps |
| T727 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.163949658 |
|
|
Jul 06 08:00:15 PM PDT 24 |
Jul 06 08:13:12 PM PDT 24 |
5034833848 ps |
| T341 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2846694075 |
|
|
Jul 06 07:38:57 PM PDT 24 |
Jul 06 07:49:19 PM PDT 24 |
3895406456 ps |
| T246 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1570383529 |
|
|
Jul 06 07:30:28 PM PDT 24 |
Jul 06 07:52:46 PM PDT 24 |
8357106228 ps |
| T147 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2561732275 |
|
|
Jul 06 07:28:24 PM PDT 24 |
Jul 06 07:38:04 PM PDT 24 |
9082436024 ps |
| T10 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1638843982 |
|
|
Jul 06 07:41:14 PM PDT 24 |
Jul 06 08:06:20 PM PDT 24 |
20748635340 ps |
| T900 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.843988433 |
|
|
Jul 06 07:28:18 PM PDT 24 |
Jul 06 07:59:28 PM PDT 24 |
7905164396 ps |
| T901 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.551339822 |
|
|
Jul 06 07:44:55 PM PDT 24 |
Jul 06 07:56:33 PM PDT 24 |
7021313264 ps |
| T902 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1286873240 |
|
|
Jul 06 07:52:14 PM PDT 24 |
Jul 06 08:01:11 PM PDT 24 |
3985857752 ps |
| T391 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.339692350 |
|
|
Jul 06 07:38:15 PM PDT 24 |
Jul 06 09:21:59 PM PDT 24 |
24334899112 ps |
| T755 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.679304149 |
|
|
Jul 06 07:59:26 PM PDT 24 |
Jul 06 08:11:23 PM PDT 24 |
4399829896 ps |
| T264 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.1769469002 |
|
|
Jul 06 07:40:12 PM PDT 24 |
Jul 06 07:44:47 PM PDT 24 |
2482786870 ps |
| T262 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3410703521 |
|
|
Jul 06 08:05:15 PM PDT 24 |
Jul 06 08:18:04 PM PDT 24 |
4137919200 ps |
| T903 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1634997267 |
|
|
Jul 06 07:35:31 PM PDT 24 |
Jul 06 07:40:36 PM PDT 24 |
5362380966 ps |
| T413 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3334208772 |
|
|
Jul 06 07:49:18 PM PDT 24 |
Jul 06 07:58:49 PM PDT 24 |
8350880926 ps |
| T395 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.209154905 |
|
|
Jul 06 07:38:04 PM PDT 24 |
Jul 06 07:47:23 PM PDT 24 |
6906725680 ps |
| T7 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2106409666 |
|
|
Jul 06 07:42:27 PM PDT 24 |
Jul 06 07:50:26 PM PDT 24 |
4560978784 ps |
| T435 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.671130312 |
|
|
Jul 06 07:50:17 PM PDT 24 |
Jul 06 07:53:28 PM PDT 24 |
2764071800 ps |
| T436 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1536508927 |
|
|
Jul 06 07:35:39 PM PDT 24 |
Jul 06 08:44:29 PM PDT 24 |
15479051096 ps |
| T123 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.217355365 |
|
|
Jul 06 07:40:54 PM PDT 24 |
Jul 06 07:50:59 PM PDT 24 |
4665351780 ps |
| T437 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.448000679 |
|
|
Jul 06 07:47:01 PM PDT 24 |
Jul 06 08:04:06 PM PDT 24 |
5461729768 ps |
| T438 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3447290865 |
|
|
Jul 06 07:50:40 PM PDT 24 |
Jul 06 08:04:29 PM PDT 24 |
4192169384 ps |
| T243 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.770923566 |
|
|
Jul 06 07:42:37 PM PDT 24 |
Jul 06 07:54:36 PM PDT 24 |
6061255032 ps |
| T337 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2486907124 |
|
|
Jul 06 07:33:22 PM PDT 24 |
Jul 06 07:38:46 PM PDT 24 |
2775913280 ps |
| T439 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.2225968760 |
|
|
Jul 06 07:57:53 PM PDT 24 |
Jul 06 08:09:48 PM PDT 24 |
5636294486 ps |
| T440 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.631434760 |
|
|
Jul 06 07:56:38 PM PDT 24 |
Jul 06 08:02:29 PM PDT 24 |
4166290304 ps |
| T904 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1014116094 |
|
|
Jul 06 07:41:00 PM PDT 24 |
Jul 06 07:47:25 PM PDT 24 |
4360248816 ps |
| T242 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1709659765 |
|
|
Jul 06 07:37:16 PM PDT 24 |
Jul 06 08:47:49 PM PDT 24 |
16005443260 ps |
| T704 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1661303930 |
|
|
Jul 06 08:04:35 PM PDT 24 |
Jul 06 08:10:42 PM PDT 24 |
3328442928 ps |
| T905 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3905772709 |
|
|
Jul 06 07:34:29 PM PDT 24 |
Jul 06 08:18:42 PM PDT 24 |
25430400828 ps |
| T906 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3193756489 |
|
|
Jul 06 07:56:06 PM PDT 24 |
Jul 06 09:17:35 PM PDT 24 |
21317852862 ps |
| T907 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.4240553167 |
|
|
Jul 06 07:30:51 PM PDT 24 |
Jul 06 07:41:55 PM PDT 24 |
4209458050 ps |
| T222 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.130796796 |
|
|
Jul 06 07:35:22 PM PDT 24 |
Jul 06 08:35:55 PM PDT 24 |
20279453395 ps |
| T908 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3938310383 |
|
|
Jul 06 07:36:51 PM PDT 24 |
Jul 06 08:41:55 PM PDT 24 |
17196869410 ps |
| T745 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3632698624 |
|
|
Jul 06 07:59:48 PM PDT 24 |
Jul 06 08:05:12 PM PDT 24 |
4049964476 ps |
| T331 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.184189435 |
|
|
Jul 06 07:56:28 PM PDT 24 |
Jul 06 08:21:56 PM PDT 24 |
8640286200 ps |
| T333 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.530506433 |
|
|
Jul 06 07:32:47 PM PDT 24 |
Jul 06 07:48:20 PM PDT 24 |
5935655398 ps |
| T909 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3040240192 |
|
|
Jul 06 07:46:32 PM PDT 24 |
Jul 06 08:07:55 PM PDT 24 |
8126964628 ps |
| T910 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2434580305 |
|
|
Jul 06 07:33:43 PM PDT 24 |
Jul 06 07:56:29 PM PDT 24 |
8823351372 ps |
| T217 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1333045403 |
|
|
Jul 06 07:30:28 PM PDT 24 |
Jul 06 07:36:08 PM PDT 24 |
2857156627 ps |
| T248 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1993818129 |
|
|
Jul 06 07:28:33 PM PDT 24 |
Jul 06 09:04:55 PM PDT 24 |
46676967788 ps |
| T911 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2233846981 |
|
|
Jul 06 07:29:13 PM PDT 24 |
Jul 06 07:37:42 PM PDT 24 |
7345145580 ps |
| T87 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1112718472 |
|
|
Jul 06 07:57:09 PM PDT 24 |
Jul 06 08:03:50 PM PDT 24 |
3439806930 ps |
| T91 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2054452668 |
|
|
Jul 06 07:55:48 PM PDT 24 |
Jul 06 08:06:12 PM PDT 24 |
5203806900 ps |
| T92 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.51017004 |
|
|
Jul 06 07:54:07 PM PDT 24 |
Jul 06 08:07:08 PM PDT 24 |
4480541802 ps |
| T93 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.2844609632 |
|
|
Jul 06 08:03:01 PM PDT 24 |
Jul 06 08:13:10 PM PDT 24 |
4467315930 ps |
| T94 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1656869753 |
|
|
Jul 06 07:39:30 PM PDT 24 |
Jul 06 07:57:14 PM PDT 24 |
10339640350 ps |
| T95 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3148845952 |
|
|
Jul 06 07:29:04 PM PDT 24 |
Jul 06 07:53:23 PM PDT 24 |
6009574280 ps |
| T96 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.771183468 |
|
|
Jul 06 08:04:43 PM PDT 24 |
Jul 06 08:14:40 PM PDT 24 |
4753906690 ps |
| T97 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.4142188142 |
|
|
Jul 06 07:56:16 PM PDT 24 |
Jul 06 08:18:43 PM PDT 24 |
11957226636 ps |
| T98 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2726099331 |
|
|
Jul 06 07:41:31 PM PDT 24 |
Jul 06 07:45:57 PM PDT 24 |
2949562958 ps |
| T99 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.476997259 |
|
|
Jul 06 07:49:37 PM PDT 24 |
Jul 06 07:55:00 PM PDT 24 |
3069446372 ps |
| T258 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1538977 |
|
|
Jul 06 07:54:22 PM PDT 24 |
Jul 06 07:59:26 PM PDT 24 |
3420727294 ps |
| T300 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1257613379 |
|
|
Jul 06 07:43:46 PM PDT 24 |
Jul 06 07:48:55 PM PDT 24 |
3025270460 ps |
| T301 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3598600979 |
|
|
Jul 06 07:52:10 PM PDT 24 |
Jul 06 08:05:15 PM PDT 24 |
4286929864 ps |
| T302 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.3736022418 |
|
|
Jul 06 08:00:15 PM PDT 24 |
Jul 06 08:09:21 PM PDT 24 |
4755863496 ps |
| T83 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.286088269 |
|
|
Jul 06 07:28:17 PM PDT 24 |
Jul 06 11:14:32 PM PDT 24 |
255776656050 ps |
| T303 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3337692888 |
|
|
Jul 06 08:03:52 PM PDT 24 |
Jul 06 08:14:49 PM PDT 24 |
5365381240 ps |
| T304 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.4033625405 |
|
|
Jul 06 07:47:06 PM PDT 24 |
Jul 06 07:55:01 PM PDT 24 |
5504692984 ps |
| T305 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2607325852 |
|
|
Jul 06 07:33:30 PM PDT 24 |
Jul 06 08:08:12 PM PDT 24 |
7511976896 ps |
| T912 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3426803081 |
|
|
Jul 06 07:33:44 PM PDT 24 |
Jul 06 07:57:35 PM PDT 24 |
8123424020 ps |
| T399 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2591238165 |
|
|
Jul 06 07:34:27 PM PDT 24 |
Jul 06 07:41:04 PM PDT 24 |
2791345808 ps |
| T913 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.512994575 |
|
|
Jul 06 07:36:48 PM PDT 24 |
Jul 06 08:00:24 PM PDT 24 |
5869946056 ps |
| T266 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2324100885 |
|
|
Jul 06 07:32:54 PM PDT 24 |
Jul 06 07:38:50 PM PDT 24 |
3531861722 ps |
| T914 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.4118190793 |
|
|
Jul 06 07:37:46 PM PDT 24 |
Jul 06 07:41:20 PM PDT 24 |
2743118640 ps |
| T218 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3041441729 |
|
|
Jul 06 07:31:53 PM PDT 24 |
Jul 06 07:38:24 PM PDT 24 |
3502739320 ps |
| T100 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3322319294 |
|
|
Jul 06 07:51:17 PM PDT 24 |
Jul 06 08:27:21 PM PDT 24 |
21517921718 ps |
| T915 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1831279978 |
|
|
Jul 06 07:39:05 PM PDT 24 |
Jul 06 07:47:14 PM PDT 24 |
3774881132 ps |
| T148 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3821263818 |
|
|
Jul 06 07:49:26 PM PDT 24 |
Jul 06 07:54:40 PM PDT 24 |
2637044938 ps |
| T916 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1185931835 |
|
|
Jul 06 07:51:16 PM PDT 24 |
Jul 06 08:00:52 PM PDT 24 |
5726181276 ps |
| T917 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.745499883 |
|
|
Jul 06 07:28:59 PM PDT 24 |
Jul 06 09:03:30 PM PDT 24 |
44831264680 ps |
| T542 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3010006921 |
|
|
Jul 06 07:35:31 PM PDT 24 |
Jul 06 07:57:40 PM PDT 24 |
8478382187 ps |
| T918 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.2182288126 |
|
|
Jul 06 07:37:00 PM PDT 24 |
Jul 06 07:43:29 PM PDT 24 |
4139947518 ps |
| T919 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3650794802 |
|
|
Jul 06 07:46:11 PM PDT 24 |
Jul 06 07:52:56 PM PDT 24 |
6076525528 ps |
| T920 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.1941185619 |
|
|
Jul 06 07:49:18 PM PDT 24 |
Jul 06 09:03:53 PM PDT 24 |
15429291428 ps |
| T921 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2710013850 |
|
|
Jul 06 07:30:02 PM PDT 24 |
Jul 06 07:40:35 PM PDT 24 |
5213522520 ps |
| T922 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2392297538 |
|
|
Jul 06 07:55:04 PM PDT 24 |
Jul 06 08:06:31 PM PDT 24 |
10834509342 ps |
| T711 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2964200002 |
|
|
Jul 06 07:56:59 PM PDT 24 |
Jul 06 08:02:59 PM PDT 24 |
3681450054 ps |
| T706 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1769063609 |
|
|
Jul 06 08:03:41 PM PDT 24 |
Jul 06 08:11:13 PM PDT 24 |
3681611918 ps |
| T742 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3147643299 |
|
|
Jul 06 07:56:15 PM PDT 24 |
Jul 06 08:09:16 PM PDT 24 |
5876237606 ps |
| T84 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.2981472484 |
|
|
Jul 06 07:29:00 PM PDT 24 |
Jul 06 10:48:16 PM PDT 24 |
64707741548 ps |
| T746 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2858320910 |
|
|
Jul 06 07:58:34 PM PDT 24 |
Jul 06 08:07:14 PM PDT 24 |
3766139734 ps |
| T79 |
/workspace/coverage/default/0.chip_jtag_mem_access.3427181341 |
|
|
Jul 06 07:21:08 PM PDT 24 |
Jul 06 07:52:14 PM PDT 24 |
13563046346 ps |
| T26 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.223792101 |
|
|
Jul 06 07:45:28 PM PDT 24 |
Jul 06 07:59:51 PM PDT 24 |
7336453410 ps |
| T923 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.659288536 |
|
|
Jul 06 07:34:50 PM PDT 24 |
Jul 06 08:11:54 PM PDT 24 |
27217858635 ps |
| T924 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.7695919 |
|
|
Jul 06 07:50:38 PM PDT 24 |
Jul 06 07:58:03 PM PDT 24 |
4866812350 ps |
| T543 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4155818341 |
|
|
Jul 06 07:46:33 PM PDT 24 |
Jul 06 08:20:28 PM PDT 24 |
11080549716 ps |
| T925 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.155363407 |
|
|
Jul 06 07:53:31 PM PDT 24 |
Jul 06 08:03:05 PM PDT 24 |
4101336958 ps |
| T926 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.261182020 |
|
|
Jul 06 07:59:09 PM PDT 24 |
Jul 06 08:55:00 PM PDT 24 |
15045063796 ps |
| T692 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3838416115 |
|
|
Jul 06 07:59:21 PM PDT 24 |
Jul 06 08:05:31 PM PDT 24 |
3999833808 ps |
| T927 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.4092449717 |
|
|
Jul 06 07:56:49 PM PDT 24 |
Jul 06 08:13:27 PM PDT 24 |
11023745423 ps |
| T392 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3365607298 |
|
|
Jul 06 07:34:08 PM PDT 24 |
Jul 06 08:58:24 PM PDT 24 |
18637812532 ps |
| T928 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.512641710 |
|
|
Jul 06 07:47:38 PM PDT 24 |
Jul 06 08:45:59 PM PDT 24 |
20865916670 ps |
| T761 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1353482007 |
|
|
Jul 06 08:06:24 PM PDT 24 |
Jul 06 08:12:22 PM PDT 24 |
4120182692 ps |
| T929 |
/workspace/coverage/default/1.chip_sw_example_concurrency.2505671586 |
|
|
Jul 06 07:36:05 PM PDT 24 |
Jul 06 07:40:28 PM PDT 24 |
2986193750 ps |
| T930 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.442909286 |
|
|
Jul 06 07:38:50 PM PDT 24 |
Jul 06 08:53:41 PM PDT 24 |
15767440648 ps |
| T332 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.25705700 |
|
|
Jul 06 07:55:28 PM PDT 24 |
Jul 06 08:06:59 PM PDT 24 |
3783051380 ps |
| T931 |
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2428671230 |
|
|
Jul 06 07:56:24 PM PDT 24 |
Jul 06 08:46:17 PM PDT 24 |
13392059096 ps |
| T932 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.39719729 |
|
|
Jul 06 07:36:25 PM PDT 24 |
Jul 06 08:59:21 PM PDT 24 |
14938167356 ps |
| T933 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.3295986896 |
|
|
Jul 06 07:38:11 PM PDT 24 |
Jul 06 08:03:47 PM PDT 24 |
4548672636 ps |
| T934 |
/workspace/coverage/default/2.chip_sw_hmac_oneshot.3015420616 |
|
|
Jul 06 07:48:46 PM PDT 24 |
Jul 06 07:54:50 PM PDT 24 |
2923362344 ps |
| T51 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.1334518918 |
|
|
Jul 06 07:30:28 PM PDT 24 |
Jul 06 07:37:47 PM PDT 24 |
3181843007 ps |
| T935 |
/workspace/coverage/default/1.chip_sw_aes_entropy.1882975633 |
|
|
Jul 06 07:37:18 PM PDT 24 |
Jul 06 07:41:31 PM PDT 24 |
2845589500 ps |
| T936 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3993985449 |
|
|
Jul 06 07:33:09 PM PDT 24 |
Jul 06 07:53:01 PM PDT 24 |
6210254635 ps |
| T937 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.4162931144 |
|
|
Jul 06 07:49:09 PM PDT 24 |
Jul 06 08:07:37 PM PDT 24 |
6405430740 ps |
| T938 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.3592650982 |
|
|
Jul 06 07:54:07 PM PDT 24 |
Jul 06 08:01:03 PM PDT 24 |
3448193192 ps |
| T357 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3345190800 |
|
|
Jul 06 07:46:21 PM PDT 24 |
Jul 06 07:58:10 PM PDT 24 |
3967857733 ps |
| T939 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3077327712 |
|
|
Jul 06 07:32:50 PM PDT 24 |
Jul 06 07:53:54 PM PDT 24 |
7032109124 ps |
| T46 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2237931576 |
|
|
Jul 06 07:46:18 PM PDT 24 |
Jul 06 07:50:46 PM PDT 24 |
3008978000 ps |
| T353 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.2344284273 |
|
|
Jul 06 07:33:27 PM PDT 24 |
Jul 06 07:43:46 PM PDT 24 |
4531284142 ps |
| T252 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3211413102 |
|
|
Jul 06 07:34:36 PM PDT 24 |
Jul 06 09:18:44 PM PDT 24 |
50347614540 ps |
| T940 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1712983109 |
|
|
Jul 06 07:53:40 PM PDT 24 |
Jul 06 08:00:13 PM PDT 24 |
3703562064 ps |
| T702 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1906084706 |
|
|
Jul 06 08:05:26 PM PDT 24 |
Jul 06 08:12:04 PM PDT 24 |
3690033238 ps |
| T338 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.4269238584 |
|
|
Jul 06 07:33:06 PM PDT 24 |
Jul 06 08:02:58 PM PDT 24 |
8276713864 ps |
| T751 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2038362924 |
|
|
Jul 06 08:03:00 PM PDT 24 |
Jul 06 08:10:50 PM PDT 24 |
3807507192 ps |
| T48 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4152636741 |
|
|
Jul 06 07:37:52 PM PDT 24 |
Jul 06 07:47:00 PM PDT 24 |
5428353960 ps |
| T364 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2674458196 |
|
|
Jul 06 08:07:32 PM PDT 24 |
Jul 06 08:20:30 PM PDT 24 |
4746803920 ps |
| T941 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1461657850 |
|
|
Jul 06 07:30:45 PM PDT 24 |
Jul 06 08:07:27 PM PDT 24 |
8225442240 ps |
| T414 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.496236165 |
|
|
Jul 06 07:53:21 PM PDT 24 |
Jul 06 07:58:21 PM PDT 24 |
3050440304 ps |
| T685 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2127551754 |
|
|
Jul 06 08:01:34 PM PDT 24 |
Jul 06 08:08:13 PM PDT 24 |
4445308018 ps |
| T250 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.330843013 |
|
|
Jul 06 07:28:15 PM PDT 24 |
Jul 06 09:07:10 PM PDT 24 |
46555969944 ps |
| T453 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3799416614 |
|
|
Jul 06 07:38:10 PM PDT 24 |
Jul 06 07:59:06 PM PDT 24 |
6224127462 ps |
| T253 |
/workspace/coverage/default/0.chip_sw_flash_init.607150224 |
|
|
Jul 06 07:29:24 PM PDT 24 |
Jul 06 08:18:35 PM PDT 24 |
23752031970 ps |
| T708 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.948842586 |
|
|
Jul 06 07:56:09 PM PDT 24 |
Jul 06 08:03:45 PM PDT 24 |
3424465956 ps |
| T942 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3973907147 |
|
|
Jul 06 07:41:10 PM PDT 24 |
Jul 06 07:45:38 PM PDT 24 |
2798733679 ps |
| T792 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.42640107 |
|
|
Jul 06 08:04:31 PM PDT 24 |
Jul 06 08:17:09 PM PDT 24 |
5609940750 ps |
| T943 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.62518534 |
|
|
Jul 06 07:34:40 PM PDT 24 |
Jul 06 09:06:33 PM PDT 24 |
18587785839 ps |
| T944 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.3113388635 |
|
|
Jul 06 07:46:36 PM PDT 24 |
Jul 06 07:51:57 PM PDT 24 |
3288314504 ps |
| T691 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.876723664 |
|
|
Jul 06 08:02:07 PM PDT 24 |
Jul 06 08:08:58 PM PDT 24 |
3566073688 ps |
| T945 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.483409902 |
|
|
Jul 06 07:48:22 PM PDT 24 |
Jul 06 07:55:43 PM PDT 24 |
5073467374 ps |
| T39 |
/workspace/coverage/default/2.chip_sw_gpio.3513670555 |
|
|
Jul 06 07:44:39 PM PDT 24 |
Jul 06 07:52:10 PM PDT 24 |
3683477146 ps |
| T946 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1993135430 |
|
|
Jul 06 07:41:26 PM PDT 24 |
Jul 06 07:48:54 PM PDT 24 |
5747507356 ps |
| T947 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3782265736 |
|
|
Jul 06 07:46:00 PM PDT 24 |
Jul 06 08:00:11 PM PDT 24 |
4731769720 ps |
| T948 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.597961727 |
|
|
Jul 06 07:45:39 PM PDT 24 |
Jul 06 07:59:20 PM PDT 24 |
13284551858 ps |
| T949 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.1107453941 |
|
|
Jul 06 07:52:13 PM PDT 24 |
Jul 06 07:56:43 PM PDT 24 |
3319261662 ps |
| T950 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.127841074 |
|
|
Jul 06 07:42:26 PM PDT 24 |
Jul 06 07:47:54 PM PDT 24 |
3319582657 ps |
| T951 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1979556227 |
|
|
Jul 06 07:48:59 PM PDT 24 |
Jul 06 08:31:34 PM PDT 24 |
11185145126 ps |
| T952 |
/workspace/coverage/default/0.chip_sw_edn_kat.2687841905 |
|
|
Jul 06 07:29:09 PM PDT 24 |
Jul 06 07:40:28 PM PDT 24 |
3431171168 ps |
| T953 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.754201877 |
|
|
Jul 06 07:31:50 PM PDT 24 |
Jul 06 07:35:53 PM PDT 24 |
2353503170 ps |
| T268 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1383296118 |
|
|
Jul 06 07:50:48 PM PDT 24 |
Jul 06 08:00:55 PM PDT 24 |
4535057076 ps |
| T747 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2329797170 |
|
|
Jul 06 07:48:40 PM PDT 24 |
Jul 06 07:56:12 PM PDT 24 |
4349541212 ps |
| T193 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1065622352 |
|
|
Jul 06 07:51:40 PM PDT 24 |
Jul 06 07:55:53 PM PDT 24 |
2886805972 ps |
| T954 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2457198939 |
|
|
Jul 06 07:36:16 PM PDT 24 |
Jul 06 08:28:10 PM PDT 24 |
11148144656 ps |
| T955 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3120674443 |
|
|
Jul 06 07:37:27 PM PDT 24 |
Jul 06 08:41:48 PM PDT 24 |
15410635262 ps |
| T325 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.3093165153 |
|
|
Jul 06 07:30:24 PM PDT 24 |
Jul 06 07:54:20 PM PDT 24 |
6848911388 ps |
| T956 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3700131785 |
|
|
Jul 06 07:29:18 PM PDT 24 |
Jul 06 07:42:07 PM PDT 24 |
5052022160 ps |
| T957 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2421841573 |
|
|
Jul 06 07:51:53 PM PDT 24 |
Jul 06 08:03:59 PM PDT 24 |
6833910648 ps |
| T958 |
/workspace/coverage/default/1.chip_tap_straps_prod.1095564725 |
|
|
Jul 06 07:41:17 PM PDT 24 |
Jul 06 07:44:08 PM PDT 24 |
2830230460 ps |
| T699 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2872098762 |
|
|
Jul 06 08:00:38 PM PDT 24 |
Jul 06 08:08:20 PM PDT 24 |
4008806784 ps |
| T959 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2501589947 |
|
|
Jul 06 07:35:33 PM PDT 24 |
Jul 06 08:41:37 PM PDT 24 |
14685835842 ps |
| T960 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.710493299 |
|
|
Jul 06 07:37:53 PM PDT 24 |
Jul 06 07:42:42 PM PDT 24 |
3430584048 ps |
| T381 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2248458934 |
|
|
Jul 06 08:01:52 PM PDT 24 |
Jul 06 08:09:04 PM PDT 24 |
3969238930 ps |
| T292 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.424508456 |
|
|
Jul 06 07:52:21 PM PDT 24 |
Jul 06 08:03:28 PM PDT 24 |
4561656228 ps |
| T383 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1607532333 |
|
|
Jul 06 07:40:43 PM PDT 24 |
Jul 06 07:46:08 PM PDT 24 |
3611991122 ps |
| T384 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1050108084 |
|
|
Jul 06 08:01:19 PM PDT 24 |
Jul 06 08:14:13 PM PDT 24 |
6129239168 ps |
| T385 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.128832718 |
|
|
Jul 06 07:35:44 PM PDT 24 |
Jul 06 08:48:51 PM PDT 24 |
15245439830 ps |
| T219 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2834460901 |
|
|
Jul 06 07:47:56 PM PDT 24 |
Jul 06 07:54:00 PM PDT 24 |
3398754424 ps |
| T386 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3952831246 |
|
|
Jul 06 07:32:19 PM PDT 24 |
Jul 06 07:51:49 PM PDT 24 |
11214754976 ps |
| T306 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2779614502 |
|
|
Jul 06 07:31:53 PM PDT 24 |
Jul 06 07:48:29 PM PDT 24 |
9949687318 ps |
| T293 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1520418396 |
|
|
Jul 06 07:41:16 PM PDT 24 |
Jul 06 07:49:56 PM PDT 24 |
4729431544 ps |
| T165 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3423903176 |
|
|
Jul 06 07:49:21 PM PDT 24 |
Jul 06 08:20:51 PM PDT 24 |
14273943580 ps |
| T36 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3347786648 |
|
|
Jul 06 07:30:47 PM PDT 24 |
Jul 06 09:37:07 PM PDT 24 |
31720946610 ps |
| T961 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.1859883857 |
|
|
Jul 06 07:49:40 PM PDT 24 |
Jul 06 08:46:59 PM PDT 24 |
22952205508 ps |
| T962 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.4249054443 |
|
|
Jul 06 07:50:31 PM PDT 24 |
Jul 06 07:57:43 PM PDT 24 |
5610395760 ps |
| T963 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.561884507 |
|
|
Jul 06 07:52:23 PM PDT 24 |
Jul 06 07:56:54 PM PDT 24 |
2912118083 ps |
| T220 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.801409419 |
|
|
Jul 06 07:28:53 PM PDT 24 |
Jul 06 07:42:20 PM PDT 24 |
5609136920 ps |
| T964 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.253293164 |
|
|
Jul 06 07:48:49 PM PDT 24 |
Jul 06 08:58:22 PM PDT 24 |
14917754891 ps |
| T965 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3671854366 |
|
|
Jul 06 07:36:38 PM PDT 24 |
Jul 06 07:56:47 PM PDT 24 |
5277460000 ps |
| T330 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.3522220743 |
|
|
Jul 06 07:27:35 PM PDT 24 |
Jul 06 07:39:17 PM PDT 24 |
3648051840 ps |
| T966 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1355747169 |
|
|
Jul 06 07:28:01 PM PDT 24 |
Jul 06 07:51:41 PM PDT 24 |
11625425512 ps |
| T967 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1051233797 |
|
|
Jul 06 07:30:24 PM PDT 24 |
Jul 06 08:03:09 PM PDT 24 |
7843260580 ps |
| T968 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2733159095 |
|
|
Jul 06 07:28:20 PM PDT 24 |
Jul 06 07:39:39 PM PDT 24 |
4538329342 ps |
| T969 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2740387949 |
|
|
Jul 06 07:48:41 PM PDT 24 |
Jul 06 07:53:43 PM PDT 24 |
3342047012 ps |
| T970 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.447159690 |
|
|
Jul 06 07:48:24 PM PDT 24 |
Jul 06 08:57:41 PM PDT 24 |
15661150308 ps |
| T971 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3224142883 |
|
|
Jul 06 07:58:28 PM PDT 24 |
Jul 06 08:34:19 PM PDT 24 |
8911509260 ps |
| T40 |
/workspace/coverage/default/0.chip_sw_gpio.2740169354 |
|
|
Jul 06 07:32:39 PM PDT 24 |
Jul 06 07:39:15 PM PDT 24 |
4367160440 ps |
| T11 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2566565119 |
|
|
Jul 06 07:52:18 PM PDT 24 |
Jul 06 08:18:49 PM PDT 24 |
23230178568 ps |
| T327 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2725950683 |
|
|
Jul 06 07:29:36 PM PDT 24 |
Jul 06 08:08:13 PM PDT 24 |
14318399480 ps |
| T415 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.173240645 |
|
|
Jul 06 07:32:10 PM PDT 24 |
Jul 06 07:35:40 PM PDT 24 |
3073064016 ps |
| T113 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.843924215 |
|
|
Jul 06 07:29:35 PM PDT 24 |
Jul 06 08:44:05 PM PDT 24 |
22497559042 ps |
| T194 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3115734401 |
|
|
Jul 06 07:29:48 PM PDT 24 |
Jul 06 07:35:20 PM PDT 24 |
3007799945 ps |
| T177 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3449850696 |
|
|
Jul 06 08:03:40 PM PDT 24 |
Jul 06 08:15:04 PM PDT 24 |
6077745580 ps |
| T972 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2886986309 |
|
|
Jul 06 07:55:13 PM PDT 24 |
Jul 06 08:05:19 PM PDT 24 |
4479347640 ps |
| T251 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2868324173 |
|
|
Jul 06 07:51:53 PM PDT 24 |
Jul 06 08:30:57 PM PDT 24 |
20747102940 ps |
| T667 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2784704561 |
|
|
Jul 06 07:36:14 PM PDT 24 |
Jul 06 07:41:51 PM PDT 24 |
2965140746 ps |
| T973 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4133432721 |
|
|
Jul 06 07:50:38 PM PDT 24 |
Jul 06 08:03:28 PM PDT 24 |
4170908340 ps |
| T767 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3099710199 |
|
|
Jul 06 08:00:24 PM PDT 24 |
Jul 06 08:06:02 PM PDT 24 |
4153505578 ps |
| T974 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.3734102902 |
|
|
Jul 06 07:51:25 PM PDT 24 |
Jul 06 08:10:48 PM PDT 24 |
4626910608 ps |
| T975 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.4246825400 |
|
|
Jul 06 07:54:13 PM PDT 24 |
Jul 06 07:57:30 PM PDT 24 |
2207615052 ps |
| T68 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.2610230014 |
|
|
Jul 06 07:28:45 PM PDT 24 |
Jul 06 07:31:36 PM PDT 24 |
2465284339 ps |
| T976 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3506592928 |
|
|
Jul 06 07:49:13 PM PDT 24 |
Jul 06 08:03:06 PM PDT 24 |
6624209915 ps |
| T715 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.269983693 |
|
|
Jul 06 07:56:27 PM PDT 24 |
Jul 06 08:06:27 PM PDT 24 |
6180960000 ps |
| T977 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.1951199419 |
|
|
Jul 06 07:43:21 PM PDT 24 |
Jul 06 08:24:39 PM PDT 24 |
11025787120 ps |
| T978 |
/workspace/coverage/default/2.chip_sw_example_concurrency.4235986329 |
|
|
Jul 06 07:44:27 PM PDT 24 |
Jul 06 07:48:08 PM PDT 24 |
2225434486 ps |
| T785 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.131263120 |
|
|
Jul 06 08:01:27 PM PDT 24 |
Jul 06 08:11:04 PM PDT 24 |
6226666040 ps |
| T979 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3290373749 |
|
|
Jul 06 07:38:18 PM PDT 24 |
Jul 06 09:20:30 PM PDT 24 |
23152605105 ps |
| T354 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.3829586337 |
|
|
Jul 06 07:30:39 PM PDT 24 |
Jul 06 07:42:58 PM PDT 24 |
4257929160 ps |
| T8 |
/workspace/coverage/default/2.chip_jtag_csr_rw.3718397271 |
|
|
Jul 06 07:44:15 PM PDT 24 |
Jul 06 08:25:56 PM PDT 24 |
23012377820 ps |
| T426 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3101502352 |
|
|
Jul 06 07:44:04 PM PDT 24 |
Jul 06 08:29:27 PM PDT 24 |
12834847078 ps |
| T167 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.762364957 |
|
|
Jul 06 07:49:25 PM PDT 24 |
Jul 06 07:54:35 PM PDT 24 |
3247435367 ps |
| T427 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.827857402 |
|
|
Jul 06 07:56:36 PM PDT 24 |
Jul 06 08:03:26 PM PDT 24 |
6025460159 ps |
| T428 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3718333284 |
|
|
Jul 06 07:46:53 PM PDT 24 |
Jul 06 08:38:46 PM PDT 24 |
32867434202 ps |
| T429 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.4215843883 |
|
|
Jul 06 07:36:05 PM PDT 24 |
Jul 06 07:42:42 PM PDT 24 |
3062636256 ps |
| T350 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.1766494952 |
|
|
Jul 06 07:54:23 PM PDT 24 |
Jul 06 08:05:35 PM PDT 24 |
4264254850 ps |
| T430 |
/workspace/coverage/default/1.chip_sw_kmac_idle.1289463642 |
|
|
Jul 06 07:40:14 PM PDT 24 |
Jul 06 07:43:31 PM PDT 24 |
3032500324 ps |
| T138 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.464162550 |
|
|
Jul 06 07:55:42 PM PDT 24 |
Jul 06 08:13:24 PM PDT 24 |
6292744856 ps |
| T431 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.822360463 |
|
|
Jul 06 07:59:55 PM PDT 24 |
Jul 06 08:12:28 PM PDT 24 |
6248080806 ps |
| T157 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3663457481 |
|
|
Jul 06 07:34:56 PM PDT 24 |
Jul 06 10:36:27 PM PDT 24 |
59505604983 ps |
| T247 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.4266903220 |
|
|
Jul 06 07:50:02 PM PDT 24 |
Jul 06 08:54:18 PM PDT 24 |
13743827408 ps |
| T980 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.559806672 |
|
|
Jul 06 07:39:16 PM PDT 24 |
Jul 06 08:18:44 PM PDT 24 |
8190446740 ps |
| T981 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1148512077 |
|
|
Jul 06 07:40:02 PM PDT 24 |
Jul 06 07:50:35 PM PDT 24 |
3688538512 ps |
| T982 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3759049929 |
|
|
Jul 06 07:49:42 PM PDT 24 |
Jul 06 08:40:06 PM PDT 24 |
11982388978 ps |
| T983 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2350458351 |
|
|
Jul 06 07:50:55 PM PDT 24 |
Jul 06 07:59:19 PM PDT 24 |
2739441316 ps |
| T16 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3958275994 |
|
|
Jul 06 07:44:59 PM PDT 24 |
Jul 06 07:54:50 PM PDT 24 |
6486848252 ps |
| T984 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.905558501 |
|
|
Jul 06 07:43:19 PM PDT 24 |
Jul 06 07:49:47 PM PDT 24 |
3120528588 ps |
| T269 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2978636065 |
|
|
Jul 06 07:29:55 PM PDT 24 |
Jul 06 08:21:26 PM PDT 24 |
28568382989 ps |
| T985 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3111730049 |
|
|
Jul 06 07:28:32 PM PDT 24 |
Jul 06 07:36:51 PM PDT 24 |
6313509916 ps |
| T393 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1520812549 |
|
|
Jul 06 07:41:39 PM PDT 24 |
Jul 06 07:45:51 PM PDT 24 |
2179886258 ps |
| T986 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1584057876 |
|
|
Jul 06 07:49:55 PM PDT 24 |
Jul 06 08:00:37 PM PDT 24 |
6576606680 ps |
| T987 |
/workspace/coverage/default/2.chip_sw_aes_enc.4064464696 |
|
|
Jul 06 07:49:17 PM PDT 24 |
Jul 06 07:53:18 PM PDT 24 |
2395379790 ps |
| T988 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.635026187 |
|
|
Jul 06 07:31:34 PM PDT 24 |
Jul 06 07:41:26 PM PDT 24 |
4034570357 ps |
| T366 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.565337683 |
|
|
Jul 06 07:48:16 PM PDT 24 |
Jul 06 08:00:24 PM PDT 24 |
20133432236 ps |
| T254 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.765424594 |
|
|
Jul 06 07:37:54 PM PDT 24 |
Jul 06 09:18:00 PM PDT 24 |
47080079135 ps |
| T989 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2021568760 |
|
|
Jul 06 07:46:35 PM PDT 24 |
Jul 06 07:59:26 PM PDT 24 |
10092520287 ps |
| T990 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.375294980 |
|
|
Jul 06 07:36:33 PM PDT 24 |
Jul 06 07:49:28 PM PDT 24 |
4557729500 ps |
| T657 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.2258320440 |
|
|
Jul 06 07:58:17 PM PDT 24 |
Jul 06 08:13:43 PM PDT 24 |
5242734422 ps |
| T991 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1680619386 |
|
|
Jul 06 07:29:14 PM PDT 24 |
Jul 06 07:40:50 PM PDT 24 |
3626520952 ps |
| T992 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1925528587 |
|
|
Jul 06 07:44:25 PM PDT 24 |
Jul 06 08:34:26 PM PDT 24 |
13319119990 ps |
| T993 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.3038256268 |
|
|
Jul 06 07:37:14 PM PDT 24 |
Jul 06 07:44:15 PM PDT 24 |
4732896628 ps |
| T723 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3162060584 |
|
|
Jul 06 08:04:05 PM PDT 24 |
Jul 06 08:13:41 PM PDT 24 |
6117287680 ps |
| T994 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3748238093 |
|
|
Jul 06 07:31:23 PM PDT 24 |
Jul 06 09:06:04 PM PDT 24 |
44662504091 ps |