| T1134 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3385736854 |
|
|
Jul 06 07:37:50 PM PDT 24 |
Jul 06 08:19:35 PM PDT 24 |
10300082756 ps |
| T1135 |
/workspace/coverage/default/2.chip_sw_hmac_multistream.1891619326 |
|
|
Jul 06 07:51:04 PM PDT 24 |
Jul 06 08:22:16 PM PDT 24 |
7474981448 ps |
| T722 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1614032564 |
|
|
Jul 06 07:59:27 PM PDT 24 |
Jul 06 08:06:39 PM PDT 24 |
4227636772 ps |
| T1136 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.4222149431 |
|
|
Jul 06 07:44:05 PM PDT 24 |
Jul 06 07:49:12 PM PDT 24 |
2773715808 ps |
| T1137 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2327058098 |
|
|
Jul 06 07:39:12 PM PDT 24 |
Jul 06 07:52:21 PM PDT 24 |
9540670520 ps |
| T1138 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.4216444169 |
|
|
Jul 06 07:45:29 PM PDT 24 |
Jul 06 07:50:08 PM PDT 24 |
2995075996 ps |
| T1139 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.242307322 |
|
|
Jul 06 07:33:55 PM PDT 24 |
Jul 06 07:56:11 PM PDT 24 |
12777681652 ps |
| T1140 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.221119659 |
|
|
Jul 06 07:59:01 PM PDT 24 |
Jul 06 08:05:03 PM PDT 24 |
4008399152 ps |
| T790 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.3314432492 |
|
|
Jul 06 07:58:19 PM PDT 24 |
Jul 06 08:08:15 PM PDT 24 |
5271479708 ps |
| T1141 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1276119729 |
|
|
Jul 06 07:56:46 PM PDT 24 |
Jul 06 08:59:21 PM PDT 24 |
14876034320 ps |
| T1142 |
/workspace/coverage/default/0.chip_sw_hmac_multistream.1554863514 |
|
|
Jul 06 07:30:30 PM PDT 24 |
Jul 06 08:05:51 PM PDT 24 |
8956876618 ps |
| T1143 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3165316870 |
|
|
Jul 06 07:44:57 PM PDT 24 |
Jul 06 07:56:52 PM PDT 24 |
4462341250 ps |
| T1144 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.556067243 |
|
|
Jul 06 07:28:15 PM PDT 24 |
Jul 06 07:46:47 PM PDT 24 |
5745934851 ps |
| T653 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2343415539 |
|
|
Jul 06 07:29:23 PM PDT 24 |
Jul 06 07:37:42 PM PDT 24 |
4478684730 ps |
| T313 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2733007134 |
|
|
Jul 06 07:30:49 PM PDT 24 |
Jul 06 07:41:17 PM PDT 24 |
5274967736 ps |
| T754 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1088139065 |
|
|
Jul 06 08:03:03 PM PDT 24 |
Jul 06 08:14:10 PM PDT 24 |
5366368060 ps |
| T1145 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.4232784395 |
|
|
Jul 06 07:40:36 PM PDT 24 |
Jul 06 07:45:35 PM PDT 24 |
2979485614 ps |
| T61 |
/workspace/coverage/default/1.chip_sw_alert_test.2905736195 |
|
|
Jul 06 07:36:07 PM PDT 24 |
Jul 06 07:42:03 PM PDT 24 |
3352666816 ps |
| T1146 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3730685873 |
|
|
Jul 06 07:56:51 PM PDT 24 |
Jul 06 09:24:24 PM PDT 24 |
25837014795 ps |
| T1147 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.31135839 |
|
|
Jul 06 07:33:21 PM PDT 24 |
Jul 06 07:43:46 PM PDT 24 |
3974021916 ps |
| T244 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.602730997 |
|
|
Jul 06 07:31:35 PM PDT 24 |
Jul 06 07:59:12 PM PDT 24 |
9331351928 ps |
| T1148 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.271744391 |
|
|
Jul 06 08:02:48 PM PDT 24 |
Jul 06 08:13:42 PM PDT 24 |
5183295208 ps |
| T788 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115277716 |
|
|
Jul 06 08:00:17 PM PDT 24 |
Jul 06 08:07:09 PM PDT 24 |
3820024624 ps |
| T1149 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.2653893777 |
|
|
Jul 06 07:37:44 PM PDT 24 |
Jul 06 07:41:18 PM PDT 24 |
2477373528 ps |
| T1150 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2907275005 |
|
|
Jul 06 07:34:51 PM PDT 24 |
Jul 06 07:43:42 PM PDT 24 |
5116538700 ps |
| T1151 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2300611518 |
|
|
Jul 06 07:53:11 PM PDT 24 |
Jul 06 07:59:03 PM PDT 24 |
4872315880 ps |
| T1152 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.4210876299 |
|
|
Jul 06 07:49:42 PM PDT 24 |
Jul 06 07:54:41 PM PDT 24 |
3186397851 ps |
| T1153 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3925752193 |
|
|
Jul 06 07:31:40 PM PDT 24 |
Jul 06 08:15:45 PM PDT 24 |
11205499048 ps |
| T1154 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.2519807995 |
|
|
Jul 06 07:56:19 PM PDT 24 |
Jul 06 08:02:13 PM PDT 24 |
2653056240 ps |
| T1155 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1266691204 |
|
|
Jul 06 07:26:56 PM PDT 24 |
Jul 06 08:02:32 PM PDT 24 |
10433621514 ps |
| T779 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2786774894 |
|
|
Jul 06 08:03:36 PM PDT 24 |
Jul 06 08:08:57 PM PDT 24 |
3633514832 ps |
| T1156 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2929725536 |
|
|
Jul 06 08:04:43 PM PDT 24 |
Jul 06 08:14:43 PM PDT 24 |
5310821024 ps |
| T433 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2584556174 |
|
|
Jul 06 07:41:09 PM PDT 24 |
Jul 06 07:48:22 PM PDT 24 |
7258733224 ps |
| T1157 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.716353356 |
|
|
Jul 06 07:55:26 PM PDT 24 |
Jul 06 08:23:06 PM PDT 24 |
7915441865 ps |
| T1158 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1169343727 |
|
|
Jul 06 07:29:56 PM PDT 24 |
Jul 06 07:36:40 PM PDT 24 |
3000012696 ps |
| T1159 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.329629697 |
|
|
Jul 06 07:52:04 PM PDT 24 |
Jul 06 08:13:36 PM PDT 24 |
8212897494 ps |
| T9 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4244548502 |
|
|
Jul 06 07:51:29 PM PDT 24 |
Jul 06 08:00:32 PM PDT 24 |
5039939950 ps |
| T1160 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.198383510 |
|
|
Jul 06 07:36:34 PM PDT 24 |
Jul 06 07:40:19 PM PDT 24 |
2622810751 ps |
| T1161 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.749363152 |
|
|
Jul 06 07:27:57 PM PDT 24 |
Jul 06 07:30:31 PM PDT 24 |
2976350169 ps |
| T1162 |
/workspace/coverage/default/2.chip_sw_edn_kat.427298371 |
|
|
Jul 06 07:51:32 PM PDT 24 |
Jul 06 08:01:35 PM PDT 24 |
3314637580 ps |
| T1163 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.471735576 |
|
|
Jul 06 07:47:25 PM PDT 24 |
Jul 06 08:31:22 PM PDT 24 |
24179405300 ps |
| T1164 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4000434080 |
|
|
Jul 06 07:50:31 PM PDT 24 |
Jul 06 08:01:18 PM PDT 24 |
4282159450 ps |
| T1165 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3196671137 |
|
|
Jul 06 07:56:59 PM PDT 24 |
Jul 06 08:54:30 PM PDT 24 |
15301717932 ps |
| T1166 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2378675803 |
|
|
Jul 06 07:37:22 PM PDT 24 |
Jul 06 08:36:34 PM PDT 24 |
36481985300 ps |
| T1167 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.4036451416 |
|
|
Jul 06 07:37:48 PM PDT 24 |
Jul 06 08:34:48 PM PDT 24 |
11441164880 ps |
| T1168 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3803408246 |
|
|
Jul 06 07:32:16 PM PDT 24 |
Jul 06 07:40:00 PM PDT 24 |
6302676612 ps |
| T1169 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2419102640 |
|
|
Jul 06 07:56:24 PM PDT 24 |
Jul 06 08:09:18 PM PDT 24 |
11738008205 ps |
| T1170 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1310789816 |
|
|
Jul 06 07:31:35 PM PDT 24 |
Jul 06 07:41:43 PM PDT 24 |
4619702570 ps |
| T1171 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3607675879 |
|
|
Jul 06 07:45:47 PM PDT 24 |
Jul 06 08:06:45 PM PDT 24 |
5087633282 ps |
| T1172 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.718330674 |
|
|
Jul 06 07:29:01 PM PDT 24 |
Jul 06 07:39:07 PM PDT 24 |
4828576355 ps |
| T336 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.2174933391 |
|
|
Jul 06 07:39:23 PM PDT 24 |
Jul 06 07:52:31 PM PDT 24 |
4332153592 ps |
| T1173 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.3313178256 |
|
|
Jul 06 07:31:36 PM PDT 24 |
Jul 06 07:36:32 PM PDT 24 |
2637524350 ps |
| T1174 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1245925854 |
|
|
Jul 06 07:59:25 PM PDT 24 |
Jul 06 08:07:21 PM PDT 24 |
4332995056 ps |
| T255 |
/workspace/coverage/default/1.chip_sw_flash_init.1502443179 |
|
|
Jul 06 07:33:43 PM PDT 24 |
Jul 06 08:07:53 PM PDT 24 |
15653273240 ps |
| T757 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.640781339 |
|
|
Jul 06 08:02:39 PM PDT 24 |
Jul 06 08:11:11 PM PDT 24 |
5256326710 ps |
| T740 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2442429574 |
|
|
Jul 06 08:04:00 PM PDT 24 |
Jul 06 08:11:43 PM PDT 24 |
3890068880 ps |
| T1175 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2226001198 |
|
|
Jul 06 07:30:35 PM PDT 24 |
Jul 06 08:08:59 PM PDT 24 |
20700650540 ps |
| T181 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3567592731 |
|
|
Jul 06 07:42:26 PM PDT 24 |
Jul 06 07:48:44 PM PDT 24 |
4738246116 ps |
| T731 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.1526560403 |
|
|
Jul 06 08:00:38 PM PDT 24 |
Jul 06 08:11:51 PM PDT 24 |
4049598124 ps |
| T739 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.544480693 |
|
|
Jul 06 07:58:53 PM PDT 24 |
Jul 06 08:08:41 PM PDT 24 |
5606495110 ps |
| T1176 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2156123454 |
|
|
Jul 06 07:42:54 PM PDT 24 |
Jul 06 08:00:57 PM PDT 24 |
7963200790 ps |
| T1177 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4120026240 |
|
|
Jul 06 07:31:12 PM PDT 24 |
Jul 06 08:49:39 PM PDT 24 |
24973156476 ps |
| T345 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1367705315 |
|
|
Jul 06 07:33:53 PM PDT 24 |
Jul 06 07:40:34 PM PDT 24 |
4311087270 ps |
| T1178 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1553739040 |
|
|
Jul 06 07:50:38 PM PDT 24 |
Jul 06 08:59:46 PM PDT 24 |
17169435720 ps |
| T257 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.994744070 |
|
|
Jul 06 07:45:48 PM PDT 24 |
Jul 06 07:55:28 PM PDT 24 |
4749437472 ps |
| T658 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3354375052 |
|
|
Jul 06 08:05:08 PM PDT 24 |
Jul 06 08:15:03 PM PDT 24 |
4491961700 ps |
| T1179 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.4288677916 |
|
|
Jul 06 07:50:09 PM PDT 24 |
Jul 06 08:03:04 PM PDT 24 |
7480174112 ps |
| T780 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.3539282121 |
|
|
Jul 06 07:54:26 PM PDT 24 |
Jul 06 08:04:58 PM PDT 24 |
5662797376 ps |
| T1180 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2137612543 |
|
|
Jul 06 07:35:37 PM PDT 24 |
Jul 06 07:43:32 PM PDT 24 |
3611944356 ps |
| T1181 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.522293107 |
|
|
Jul 06 07:56:34 PM PDT 24 |
Jul 06 08:08:31 PM PDT 24 |
4259685120 ps |
| T1182 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.4166826350 |
|
|
Jul 06 07:28:30 PM PDT 24 |
Jul 06 07:33:16 PM PDT 24 |
3270258746 ps |
| T1183 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.524343896 |
|
|
Jul 06 07:49:02 PM PDT 24 |
Jul 06 08:04:25 PM PDT 24 |
5567276580 ps |
| T1184 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.550455363 |
|
|
Jul 06 07:44:21 PM PDT 24 |
Jul 06 07:54:37 PM PDT 24 |
3560638210 ps |
| T1185 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4175029794 |
|
|
Jul 06 07:35:46 PM PDT 24 |
Jul 06 08:53:03 PM PDT 24 |
15127866372 ps |
| T1186 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1547508735 |
|
|
Jul 06 07:35:07 PM PDT 24 |
Jul 06 08:47:42 PM PDT 24 |
14587125688 ps |
| T1187 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1610713154 |
|
|
Jul 06 07:53:46 PM PDT 24 |
Jul 06 09:50:31 PM PDT 24 |
29869558516 ps |
| T361 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.768130654 |
|
|
Jul 06 07:45:10 PM PDT 24 |
Jul 06 07:57:30 PM PDT 24 |
5146991978 ps |
| T1188 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1560767021 |
|
|
Jul 06 08:05:23 PM PDT 24 |
Jul 06 08:15:32 PM PDT 24 |
5165819888 ps |
| T1189 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2561579185 |
|
|
Jul 06 07:50:51 PM PDT 24 |
Jul 06 07:58:19 PM PDT 24 |
3263648535 ps |
| T674 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.1698816581 |
|
|
Jul 06 07:43:14 PM PDT 24 |
Jul 06 07:51:19 PM PDT 24 |
4024165408 ps |
| T1190 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1494858729 |
|
|
Jul 06 07:27:29 PM PDT 24 |
Jul 06 07:49:53 PM PDT 24 |
6374244230 ps |
| T719 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.507981129 |
|
|
Jul 06 08:02:12 PM PDT 24 |
Jul 06 08:12:48 PM PDT 24 |
4103309366 ps |
| T249 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.597129813 |
|
|
Jul 06 07:46:37 PM PDT 24 |
Jul 06 09:09:42 PM PDT 24 |
49120057400 ps |
| T678 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.146494717 |
|
|
Jul 06 07:48:16 PM PDT 24 |
Jul 06 08:03:52 PM PDT 24 |
4493895088 ps |
| T763 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3990234485 |
|
|
Jul 06 08:03:30 PM PDT 24 |
Jul 06 08:10:09 PM PDT 24 |
3441740456 ps |
| T273 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.714687367 |
|
|
Jul 06 07:46:11 PM PDT 24 |
Jul 06 07:56:49 PM PDT 24 |
6508823512 ps |
| T1191 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1476264961 |
|
|
Jul 06 07:40:53 PM PDT 24 |
Jul 06 08:00:10 PM PDT 24 |
13663465018 ps |
| T1192 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2095118640 |
|
|
Jul 06 07:57:01 PM PDT 24 |
Jul 06 08:03:00 PM PDT 24 |
4733049193 ps |
| T1193 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.568161129 |
|
|
Jul 06 07:36:06 PM PDT 24 |
Jul 06 08:43:19 PM PDT 24 |
13842338104 ps |
| T736 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3494340419 |
|
|
Jul 06 08:05:55 PM PDT 24 |
Jul 06 08:13:33 PM PDT 24 |
4495805136 ps |
| T1194 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3638504568 |
|
|
Jul 06 07:39:52 PM PDT 24 |
Jul 06 07:49:08 PM PDT 24 |
3644814756 ps |
| T1195 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.2955674697 |
|
|
Jul 06 08:06:24 PM PDT 24 |
Jul 06 08:16:08 PM PDT 24 |
5821444606 ps |
| T1196 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.804827514 |
|
|
Jul 06 07:30:40 PM PDT 24 |
Jul 06 07:35:20 PM PDT 24 |
2544864360 ps |
| T1197 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.396475551 |
|
|
Jul 06 07:48:52 PM PDT 24 |
Jul 06 08:00:24 PM PDT 24 |
4091047128 ps |
| T1198 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2435044149 |
|
|
Jul 06 07:33:13 PM PDT 24 |
Jul 06 07:44:31 PM PDT 24 |
5466554800 ps |
| T1199 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1376637301 |
|
|
Jul 06 07:31:50 PM PDT 24 |
Jul 06 07:40:32 PM PDT 24 |
6455737550 ps |
| T1200 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.2221024558 |
|
|
Jul 06 07:29:59 PM PDT 24 |
Jul 06 07:47:26 PM PDT 24 |
5809749240 ps |
| T1201 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3628650787 |
|
|
Jul 06 07:36:27 PM PDT 24 |
Jul 06 07:42:23 PM PDT 24 |
3066281077 ps |
| T772 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.326414446 |
|
|
Jul 06 08:04:15 PM PDT 24 |
Jul 06 08:10:59 PM PDT 24 |
3847527728 ps |
| T1202 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.3632844406 |
|
|
Jul 06 07:36:05 PM PDT 24 |
Jul 06 07:42:25 PM PDT 24 |
4239505836 ps |
| T1203 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3295217569 |
|
|
Jul 06 08:02:18 PM PDT 24 |
Jul 06 08:09:30 PM PDT 24 |
3771167560 ps |
| T328 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1401231084 |
|
|
Jul 06 07:36:14 PM PDT 24 |
Jul 06 08:08:32 PM PDT 24 |
11175664832 ps |
| T49 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1845631271 |
|
|
Jul 06 07:47:30 PM PDT 24 |
Jul 06 07:54:55 PM PDT 24 |
6221377768 ps |
| T1204 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3745601573 |
|
|
Jul 06 07:39:00 PM PDT 24 |
Jul 06 11:24:26 PM PDT 24 |
254859013530 ps |
| T164 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.3860041535 |
|
|
Jul 06 07:49:57 PM PDT 24 |
Jul 06 07:59:17 PM PDT 24 |
3748550550 ps |
| T50 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2496983779 |
|
|
Jul 06 07:28:59 PM PDT 24 |
Jul 06 07:37:22 PM PDT 24 |
6300914868 ps |
| T1205 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3300505429 |
|
|
Jul 06 07:56:57 PM PDT 24 |
Jul 06 08:04:49 PM PDT 24 |
5171065298 ps |
| T1206 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.985581950 |
|
|
Jul 06 07:30:48 PM PDT 24 |
Jul 06 08:23:25 PM PDT 24 |
11744753928 ps |
| T1207 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.869345605 |
|
|
Jul 06 07:32:15 PM PDT 24 |
Jul 06 07:42:26 PM PDT 24 |
5830672018 ps |
| T1208 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.62484810 |
|
|
Jul 06 07:56:18 PM PDT 24 |
Jul 06 08:07:18 PM PDT 24 |
4511068808 ps |
| T749 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1302556652 |
|
|
Jul 06 08:03:26 PM PDT 24 |
Jul 06 08:11:02 PM PDT 24 |
4016741500 ps |
| T771 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3144509412 |
|
|
Jul 06 08:01:44 PM PDT 24 |
Jul 06 08:10:02 PM PDT 24 |
4190304984 ps |
| T1209 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.189719909 |
|
|
Jul 06 07:32:36 PM PDT 24 |
Jul 06 07:38:29 PM PDT 24 |
2751453464 ps |
| T764 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2556907250 |
|
|
Jul 06 08:07:25 PM PDT 24 |
Jul 06 08:20:19 PM PDT 24 |
6294835100 ps |
| T1210 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1087156616 |
|
|
Jul 06 07:55:03 PM PDT 24 |
Jul 06 08:02:42 PM PDT 24 |
6190638796 ps |
| T1211 |
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2414730275 |
|
|
Jul 06 07:56:00 PM PDT 24 |
Jul 06 08:37:01 PM PDT 24 |
9561833960 ps |
| T1212 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2904037494 |
|
|
Jul 06 07:39:44 PM PDT 24 |
Jul 06 07:47:43 PM PDT 24 |
3585356776 ps |
| T360 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2501671036 |
|
|
Jul 06 07:28:13 PM PDT 24 |
Jul 06 07:40:23 PM PDT 24 |
4550662076 ps |
| T1213 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2706599014 |
|
|
Jul 06 07:31:44 PM PDT 24 |
Jul 06 07:47:49 PM PDT 24 |
9037170904 ps |
| T1214 |
/workspace/coverage/default/0.chip_sw_aes_entropy.3494416944 |
|
|
Jul 06 07:29:59 PM PDT 24 |
Jul 06 07:35:58 PM PDT 24 |
3150697528 ps |
| T1215 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2192936567 |
|
|
Jul 06 07:30:36 PM PDT 24 |
Jul 06 11:38:14 PM PDT 24 |
78625465368 ps |
| T1216 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3151082433 |
|
|
Jul 06 07:55:12 PM PDT 24 |
Jul 06 08:24:10 PM PDT 24 |
8578759732 ps |
| T1217 |
/workspace/coverage/default/0.chip_sw_example_flash.3509373420 |
|
|
Jul 06 07:28:33 PM PDT 24 |
Jul 06 07:31:36 PM PDT 24 |
2867126410 ps |
| T1218 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2361414318 |
|
|
Jul 06 07:44:44 PM PDT 24 |
Jul 06 10:33:54 PM PDT 24 |
59152481276 ps |
| T1219 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.347161233 |
|
|
Jul 06 07:29:33 PM PDT 24 |
Jul 06 07:35:49 PM PDT 24 |
5216210172 ps |
| T1220 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3681982964 |
|
|
Jul 06 07:46:22 PM PDT 24 |
Jul 06 07:50:35 PM PDT 24 |
2873267942 ps |
| T1221 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1588788301 |
|
|
Jul 06 07:37:04 PM PDT 24 |
Jul 06 08:04:16 PM PDT 24 |
5976396032 ps |
| T1222 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.1059741477 |
|
|
Jul 06 07:58:41 PM PDT 24 |
Jul 06 08:11:46 PM PDT 24 |
4857847960 ps |
| T1223 |
/workspace/coverage/default/0.chip_sw_aes_enc.2436131941 |
|
|
Jul 06 07:28:35 PM PDT 24 |
Jul 06 07:32:16 PM PDT 24 |
3195544160 ps |
| T1224 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.232803848 |
|
|
Jul 06 07:30:43 PM PDT 24 |
Jul 06 07:35:06 PM PDT 24 |
2937583728 ps |
| T1225 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1703669399 |
|
|
Jul 06 07:28:48 PM PDT 24 |
Jul 06 07:40:01 PM PDT 24 |
5166719400 ps |
| T786 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3513021026 |
|
|
Jul 06 08:04:47 PM PDT 24 |
Jul 06 08:17:10 PM PDT 24 |
5899845780 ps |
| T1226 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.4118724929 |
|
|
Jul 06 07:30:23 PM PDT 24 |
Jul 06 07:32:55 PM PDT 24 |
2651371386 ps |
| T680 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.769782284 |
|
|
Jul 06 07:31:01 PM PDT 24 |
Jul 06 08:29:39 PM PDT 24 |
24487955131 ps |
| T1227 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3921449861 |
|
|
Jul 06 07:36:29 PM PDT 24 |
Jul 06 07:52:26 PM PDT 24 |
5924134794 ps |
| T1228 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3697154485 |
|
|
Jul 06 07:35:54 PM PDT 24 |
Jul 06 07:46:34 PM PDT 24 |
5717746348 ps |
| T372 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3747288579 |
|
|
Jul 06 07:48:54 PM PDT 24 |
Jul 06 08:16:18 PM PDT 24 |
6144293528 ps |
| T1229 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3978946194 |
|
|
Jul 06 07:38:09 PM PDT 24 |
Jul 06 08:26:45 PM PDT 24 |
10428612782 ps |
| T22 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3523854057 |
|
|
Jul 06 07:33:28 PM PDT 24 |
Jul 06 07:39:36 PM PDT 24 |
3346006431 ps |
| T1230 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.581471226 |
|
|
Jul 06 07:58:59 PM PDT 24 |
Jul 06 08:14:38 PM PDT 24 |
6445332000 ps |
| T1231 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3412080043 |
|
|
Jul 06 07:45:17 PM PDT 24 |
Jul 07 12:00:39 AM PDT 24 |
79236757736 ps |
| T1232 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1114689290 |
|
|
Jul 06 07:29:12 PM PDT 24 |
Jul 06 08:27:31 PM PDT 24 |
44076890905 ps |
| T1233 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1047194128 |
|
|
Jul 06 07:49:25 PM PDT 24 |
Jul 06 07:59:00 PM PDT 24 |
4420413258 ps |
| T1234 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.3455791671 |
|
|
Jul 06 07:30:03 PM PDT 24 |
Jul 06 07:31:48 PM PDT 24 |
2492415032 ps |
| T1235 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3205653884 |
|
|
Jul 06 07:33:05 PM PDT 24 |
Jul 06 07:38:00 PM PDT 24 |
2790574462 ps |
| T53 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.562145868 |
|
|
Jul 06 07:47:43 PM PDT 24 |
Jul 06 07:53:59 PM PDT 24 |
3230811829 ps |
| T1236 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3020012410 |
|
|
Jul 06 07:32:23 PM PDT 24 |
Jul 06 08:18:10 PM PDT 24 |
12651512396 ps |
| T1237 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.4096941786 |
|
|
Jul 06 07:39:46 PM PDT 24 |
Jul 06 08:08:02 PM PDT 24 |
8250330740 ps |
| T768 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3536780105 |
|
|
Jul 06 08:05:34 PM PDT 24 |
Jul 06 08:17:25 PM PDT 24 |
5039781708 ps |
| T773 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.3144668015 |
|
|
Jul 06 08:01:27 PM PDT 24 |
Jul 06 08:13:55 PM PDT 24 |
6504489128 ps |
| T1238 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2764209123 |
|
|
Jul 06 07:32:35 PM PDT 24 |
Jul 06 07:41:40 PM PDT 24 |
5839789947 ps |
| T1239 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2452259188 |
|
|
Jul 06 07:58:12 PM PDT 24 |
Jul 06 08:05:15 PM PDT 24 |
3887994080 ps |
| T1240 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2912207848 |
|
|
Jul 06 07:29:19 PM PDT 24 |
Jul 06 07:34:33 PM PDT 24 |
3008566816 ps |
| T1241 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4074609156 |
|
|
Jul 06 07:38:28 PM PDT 24 |
Jul 06 07:48:32 PM PDT 24 |
4823242448 ps |
| T47 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1657172402 |
|
|
Jul 06 07:33:53 PM PDT 24 |
Jul 06 07:39:21 PM PDT 24 |
3321926688 ps |
| T1242 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.538393213 |
|
|
Jul 06 07:30:58 PM PDT 24 |
Jul 06 07:35:41 PM PDT 24 |
3155642152 ps |
| T1243 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2845310509 |
|
|
Jul 06 07:48:35 PM PDT 24 |
Jul 06 07:50:51 PM PDT 24 |
3102293890 ps |
| T1244 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2181505186 |
|
|
Jul 06 07:33:14 PM PDT 24 |
Jul 06 07:46:58 PM PDT 24 |
4110595523 ps |
| T1245 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2049714759 |
|
|
Jul 06 07:48:06 PM PDT 24 |
Jul 06 08:16:55 PM PDT 24 |
17742718956 ps |
| T1246 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.980464628 |
|
|
Jul 06 07:32:19 PM PDT 24 |
Jul 06 07:38:06 PM PDT 24 |
3171041537 ps |
| T1247 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2381959540 |
|
|
Jul 06 07:33:47 PM PDT 24 |
Jul 06 08:17:59 PM PDT 24 |
28133644324 ps |
| T1248 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.1081041144 |
|
|
Jul 06 07:57:02 PM PDT 24 |
Jul 06 08:55:51 PM PDT 24 |
15438027454 ps |
| T1249 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3729242554 |
|
|
Jul 06 07:56:07 PM PDT 24 |
Jul 06 08:03:51 PM PDT 24 |
7155711416 ps |
| T1250 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2870311391 |
|
|
Jul 06 07:54:13 PM PDT 24 |
Jul 06 08:02:46 PM PDT 24 |
4200410576 ps |
| T1251 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1489068170 |
|
|
Jul 06 07:53:23 PM PDT 24 |
Jul 06 08:14:35 PM PDT 24 |
13311752406 ps |
| T299 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1682161939 |
|
|
Jul 06 07:32:05 PM PDT 24 |
Jul 06 07:38:13 PM PDT 24 |
3725549792 ps |
| T1252 |
/workspace/coverage/default/2.chip_sw_aes_idle.2402056920 |
|
|
Jul 06 07:48:40 PM PDT 24 |
Jul 06 07:52:42 PM PDT 24 |
2691429784 ps |
| T12 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2611601198 |
|
|
Jul 06 07:36:26 PM PDT 24 |
Jul 06 07:45:26 PM PDT 24 |
4887949150 ps |
| T1253 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.325036659 |
|
|
Jul 06 07:39:00 PM PDT 24 |
Jul 06 08:28:58 PM PDT 24 |
28467908254 ps |
| T1254 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2453707681 |
|
|
Jul 06 07:48:41 PM PDT 24 |
Jul 06 08:01:09 PM PDT 24 |
3726530454 ps |
| T1255 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.3062739097 |
|
|
Jul 06 07:34:12 PM PDT 24 |
Jul 06 07:39:41 PM PDT 24 |
2683807440 ps |
| T1256 |
/workspace/coverage/default/1.chip_sw_hmac_oneshot.2839230050 |
|
|
Jul 06 07:38:37 PM PDT 24 |
Jul 06 07:43:20 PM PDT 24 |
3330595784 ps |
| T1257 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1633145745 |
|
|
Jul 06 07:41:01 PM PDT 24 |
Jul 06 07:51:35 PM PDT 24 |
4617787200 ps |
| T1258 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1966569770 |
|
|
Jul 06 07:34:56 PM PDT 24 |
Jul 06 08:05:25 PM PDT 24 |
24241739436 ps |
| T721 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.800329304 |
|
|
Jul 06 08:02:24 PM PDT 24 |
Jul 06 08:08:41 PM PDT 24 |
3173173500 ps |
| T1259 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2018429917 |
|
|
Jul 06 07:34:05 PM PDT 24 |
Jul 06 07:46:58 PM PDT 24 |
4673419240 ps |
| T1260 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.602272385 |
|
|
Jul 06 07:35:47 PM PDT 24 |
Jul 06 08:45:56 PM PDT 24 |
15024679329 ps |
| T1261 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1288540302 |
|
|
Jul 06 07:50:26 PM PDT 24 |
Jul 06 08:04:10 PM PDT 24 |
4558369726 ps |
| T1262 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3359762885 |
|
|
Jul 06 07:40:45 PM PDT 24 |
Jul 06 07:56:30 PM PDT 24 |
10455421200 ps |
| T140 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1988679004 |
|
|
Jul 06 07:55:07 PM PDT 24 |
Jul 06 08:11:01 PM PDT 24 |
6763717310 ps |
| T1263 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.802268625 |
|
|
Jul 06 07:36:25 PM PDT 24 |
Jul 06 07:42:25 PM PDT 24 |
3546299496 ps |
| T1264 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2513781607 |
|
|
Jul 06 07:39:24 PM PDT 24 |
Jul 06 07:43:47 PM PDT 24 |
2942351650 ps |
| T1265 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3025777556 |
|
|
Jul 06 07:28:46 PM PDT 24 |
Jul 06 07:39:24 PM PDT 24 |
5498105000 ps |
| T1266 |
/workspace/coverage/default/2.chip_sw_hmac_enc.2570142794 |
|
|
Jul 06 07:49:19 PM PDT 24 |
Jul 06 07:53:59 PM PDT 24 |
2729541164 ps |
| T1267 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2508323410 |
|
|
Jul 06 07:38:41 PM PDT 24 |
Jul 06 08:43:52 PM PDT 24 |
14602830644 ps |
| T1268 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3767815532 |
|
|
Jul 06 07:29:21 PM PDT 24 |
Jul 06 07:42:07 PM PDT 24 |
7462652364 ps |
| T1269 |
/workspace/coverage/default/1.chip_sw_example_flash.3949177768 |
|
|
Jul 06 07:32:03 PM PDT 24 |
Jul 06 07:34:37 PM PDT 24 |
2558734718 ps |
| T320 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.4210711920 |
|
|
Jul 06 07:44:26 PM PDT 24 |
Jul 06 07:54:20 PM PDT 24 |
4146309676 ps |
| T1270 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3814705677 |
|
|
Jul 06 08:03:38 PM PDT 24 |
Jul 06 08:13:41 PM PDT 24 |
6063456200 ps |
| T141 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.633254552 |
|
|
Jul 06 07:51:14 PM PDT 24 |
Jul 06 07:59:15 PM PDT 24 |
5706612136 ps |
| T1271 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.23822141 |
|
|
Jul 06 07:54:04 PM PDT 24 |
Jul 06 07:57:53 PM PDT 24 |
2609989379 ps |
| T1272 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1084694959 |
|
|
Jul 06 07:36:48 PM PDT 24 |
Jul 06 07:45:18 PM PDT 24 |
4353516293 ps |
| T1273 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2204637978 |
|
|
Jul 06 08:03:57 PM PDT 24 |
Jul 06 08:12:09 PM PDT 24 |
4698166444 ps |
| T245 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3277483391 |
|
|
Jul 06 07:54:02 PM PDT 24 |
Jul 06 08:30:21 PM PDT 24 |
11854315324 ps |
| T1274 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3311281434 |
|
|
Jul 06 07:32:45 PM PDT 24 |
Jul 06 07:43:19 PM PDT 24 |
4259601832 ps |
| T1275 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.734935909 |
|
|
Jul 06 07:47:36 PM PDT 24 |
Jul 06 07:51:44 PM PDT 24 |
2795264673 ps |
| T1276 |
/workspace/coverage/default/2.chip_sw_power_idle_load.4111300044 |
|
|
Jul 06 07:52:59 PM PDT 24 |
Jul 06 08:04:26 PM PDT 24 |
4199193968 ps |
| T434 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3787772082 |
|
|
Jul 06 07:32:46 PM PDT 24 |
Jul 06 07:41:21 PM PDT 24 |
7776394192 ps |
| T1277 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.701787739 |
|
|
Jul 06 07:53:09 PM PDT 24 |
Jul 06 07:57:40 PM PDT 24 |
2972589536 ps |
| T1278 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1530185027 |
|
|
Jul 06 07:36:49 PM PDT 24 |
Jul 06 07:43:50 PM PDT 24 |
4439597992 ps |
| T645 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.347118728 |
|
|
Jul 06 07:38:32 PM PDT 24 |
Jul 06 07:48:53 PM PDT 24 |
3235835826 ps |
| T1279 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1209414843 |
|
|
Jul 06 07:38:15 PM PDT 24 |
Jul 06 09:09:32 PM PDT 24 |
15715279100 ps |
| T1280 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1408484105 |
|
|
Jul 06 07:57:35 PM PDT 24 |
Jul 06 08:22:29 PM PDT 24 |
8237306172 ps |
| T714 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.75155972 |
|
|
Jul 06 08:05:37 PM PDT 24 |
Jul 06 08:11:49 PM PDT 24 |
3814049092 ps |
| T1281 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4052159217 |
|
|
Jul 06 07:51:36 PM PDT 24 |
Jul 06 08:02:52 PM PDT 24 |
4461496562 ps |
| T145 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1889846932 |
|
|
Jul 06 07:39:15 PM PDT 24 |
Jul 06 07:46:28 PM PDT 24 |
3895707608 ps |
| T1282 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2154659959 |
|
|
Jul 06 07:34:16 PM PDT 24 |
Jul 06 07:43:48 PM PDT 24 |
6295015580 ps |
| T1283 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.970347353 |
|
|
Jul 06 07:55:49 PM PDT 24 |
Jul 06 07:59:42 PM PDT 24 |
2521358902 ps |
| T1284 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3021770099 |
|
|
Jul 06 07:35:03 PM PDT 24 |
Jul 06 08:33:07 PM PDT 24 |
14414940955 ps |
| T23 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3018609135 |
|
|
Jul 06 07:35:27 PM PDT 24 |
Jul 06 07:40:07 PM PDT 24 |
2637026884 ps |
| T274 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.953992498 |
|
|
Jul 06 07:56:08 PM PDT 24 |
Jul 06 08:05:13 PM PDT 24 |
5738328260 ps |
| T1285 |
/workspace/coverage/default/2.rom_keymgr_functest.2453329287 |
|
|
Jul 06 07:53:17 PM PDT 24 |
Jul 06 08:08:10 PM PDT 24 |
4206720668 ps |
| T210 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3699395684 |
|
|
Jul 06 07:34:50 PM PDT 24 |
Jul 06 07:47:19 PM PDT 24 |
7337847659 ps |
| T1286 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3430517887 |
|
|
Jul 06 07:54:48 PM PDT 24 |
Jul 06 07:58:26 PM PDT 24 |
2621834249 ps |
| T1287 |
/workspace/coverage/default/2.chip_sw_example_flash.218946318 |
|
|
Jul 06 07:44:53 PM PDT 24 |
Jul 06 07:47:41 PM PDT 24 |
2226741680 ps |
| T1288 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3354798439 |
|
|
Jul 06 07:38:46 PM PDT 24 |
Jul 06 11:14:31 PM PDT 24 |
78468517178 ps |
| T1289 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3415373460 |
|
|
Jul 06 07:28:19 PM PDT 24 |
Jul 06 07:40:11 PM PDT 24 |
4697413914 ps |
| T1290 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.1909403070 |
|
|
Jul 06 07:27:12 PM PDT 24 |
Jul 06 07:45:51 PM PDT 24 |
6077676688 ps |
| T1291 |
/workspace/coverage/default/2.chip_sw_flash_init.3820606620 |
|
|
Jul 06 07:45:02 PM PDT 24 |
Jul 06 08:18:44 PM PDT 24 |
21870630974 ps |
| T1292 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.229121020 |
|
|
Jul 06 07:48:45 PM PDT 24 |
Jul 06 08:54:17 PM PDT 24 |
15426068886 ps |
| T1293 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1050712936 |
|
|
Jul 06 07:56:42 PM PDT 24 |
Jul 06 08:16:33 PM PDT 24 |
12428411228 ps |
| T1294 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3361102601 |
|
|
Jul 06 07:46:00 PM PDT 24 |
Jul 06 09:26:06 PM PDT 24 |
50959943006 ps |
| T1295 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2985174242 |
|
|
Jul 06 07:46:41 PM PDT 24 |
Jul 06 07:51:15 PM PDT 24 |
2535409768 ps |
| T1296 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3660856364 |
|
|
Jul 06 07:32:27 PM PDT 24 |
Jul 06 07:58:44 PM PDT 24 |
15740832720 ps |
| T1297 |
/workspace/coverage/default/0.chip_tap_straps_rma.3824644874 |
|
|
Jul 06 07:31:35 PM PDT 24 |
Jul 06 07:38:05 PM PDT 24 |
4123685945 ps |
| T62 |
/workspace/coverage/default/2.chip_sw_alert_test.2282299703 |
|
|
Jul 06 07:49:26 PM PDT 24 |
Jul 06 07:55:20 PM PDT 24 |
2856010536 ps |
| T774 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3976500045 |
|
|
Jul 06 07:55:52 PM PDT 24 |
Jul 06 08:02:31 PM PDT 24 |
3753460510 ps |
| T1298 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2790455028 |
|
|
Jul 06 07:39:52 PM PDT 24 |
Jul 06 07:45:12 PM PDT 24 |
3478492878 ps |
| T1299 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.957056109 |
|
|
Jul 06 07:50:57 PM PDT 24 |
Jul 06 08:12:23 PM PDT 24 |
7128578449 ps |
| T1300 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2017814369 |
|
|
Jul 06 07:37:47 PM PDT 24 |
Jul 06 07:58:11 PM PDT 24 |
7309317984 ps |
| T688 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1375148315 |
|
|
Jul 06 08:05:08 PM PDT 24 |
Jul 06 08:17:49 PM PDT 24 |
5784318640 ps |
| T394 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.640868823 |
|
|
Jul 06 07:35:48 PM PDT 24 |
Jul 06 07:38:48 PM PDT 24 |
2255792930 ps |
| T775 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.4054064177 |
|
|
Jul 06 08:01:09 PM PDT 24 |
Jul 06 08:11:35 PM PDT 24 |
5023717288 ps |
| T89 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.754000261 |
|
|
Jul 06 07:59:42 PM PDT 24 |
Jul 06 08:05:41 PM PDT 24 |
3924449440 ps |
| T782 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1718324491 |
|
|
Jul 06 08:00:04 PM PDT 24 |
Jul 06 08:06:50 PM PDT 24 |
3934998160 ps |
| T1301 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.2937319295 |
|
|
Jul 06 07:48:09 PM PDT 24 |
Jul 06 07:51:02 PM PDT 24 |
1939871280 ps |
| T1302 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.635860893 |
|
|
Jul 06 07:31:16 PM PDT 24 |
Jul 06 08:00:26 PM PDT 24 |
12475608316 ps |
| T1303 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4062655625 |
|
|
Jul 06 08:04:52 PM PDT 24 |
Jul 06 08:13:36 PM PDT 24 |
3527771910 ps |
| T211 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3369748139 |
|
|
Jul 06 07:28:45 PM PDT 24 |
Jul 06 07:39:18 PM PDT 24 |
4419398870 ps |
| T1304 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3643937097 |
|
|
Jul 06 07:33:40 PM PDT 24 |
Jul 06 07:43:20 PM PDT 24 |
3991269646 ps |
| T1305 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.912667504 |
|
|
Jul 06 07:30:11 PM PDT 24 |
Jul 06 08:12:58 PM PDT 24 |
12900837518 ps |
| T686 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3176547854 |
|
|
Jul 06 07:58:03 PM PDT 24 |
Jul 06 08:05:27 PM PDT 24 |
3481355832 ps |
| T1306 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1374232948 |
|
|
Jul 06 07:52:50 PM PDT 24 |
Jul 06 08:02:01 PM PDT 24 |
5736456746 ps |
| T1307 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4125093319 |
|
|
Jul 06 07:49:44 PM PDT 24 |
Jul 06 11:22:50 PM PDT 24 |
255284736000 ps |
| T1308 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3847290666 |
|
|
Jul 06 07:56:42 PM PDT 24 |
Jul 06 08:05:13 PM PDT 24 |
3657151022 ps |
| T1309 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.307376114 |
|
|
Jul 06 07:39:37 PM PDT 24 |
Jul 06 07:49:43 PM PDT 24 |
5130950852 ps |
| T1310 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.261271027 |
|
|
Jul 06 07:55:29 PM PDT 24 |
Jul 06 08:38:22 PM PDT 24 |
12928265472 ps |
| T1311 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.130553346 |
|
|
Jul 06 07:32:22 PM PDT 24 |
Jul 06 07:48:50 PM PDT 24 |
10688588882 ps |
| T1312 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.4272885510 |
|
|
Jul 06 07:30:50 PM PDT 24 |
Jul 06 07:44:18 PM PDT 24 |
8587716570 ps |
| T734 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.44344951 |
|
|
Jul 06 08:04:21 PM PDT 24 |
Jul 06 08:15:43 PM PDT 24 |
5069851720 ps |