| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.25 | 95.60 | 94.21 | 95.46 | 95.03 | 97.53 | 99.64 |
| T2761 | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.3384895303 | Jul 06 08:12:48 PM PDT 24 | Jul 06 08:14:44 PM PDT 24 | 2655836552 ps | ||
| T2762 | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.2409152384 | Jul 06 08:15:23 PM PDT 24 | Jul 06 08:25:03 PM PDT 24 | 12850616593 ps | ||
| T2763 | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.3008095422 | Jul 06 08:21:14 PM PDT 24 | Jul 06 08:31:17 PM PDT 24 | 34297461389 ps | ||
| T2764 | /workspace/coverage/cover_reg_top/91.xbar_same_source.1121011525 | Jul 06 08:22:48 PM PDT 24 | Jul 06 08:23:48 PM PDT 24 | 1832252743 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/30.xbar_same_source.1761051737 | Jul 06 08:12:11 PM PDT 24 | Jul 06 08:13:40 PM PDT 24 | 2505738692 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/9.xbar_stress_all.4207989351 | Jul 06 08:05:48 PM PDT 24 | Jul 06 08:09:14 PM PDT 24 | 2257480082 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.500763235 | Jul 06 08:18:00 PM PDT 24 | Jul 06 08:18:13 PM PDT 24 | 77049611 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.119365320 | Jul 06 08:12:50 PM PDT 24 | Jul 06 08:29:23 PM PDT 24 | 51707620932 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/65.xbar_random.657448882 | Jul 06 08:18:16 PM PDT 24 | Jul 06 08:19:47 PM PDT 24 | 2486199197 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/92.xbar_error_random.11863561 | Jul 06 08:22:57 PM PDT 24 | Jul 06 08:24:12 PM PDT 24 | 2002157540 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.2312427599 | Jul 06 08:10:24 PM PDT 24 | Jul 06 08:29:50 PM PDT 24 | 65660529748 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/52.xbar_random.986955277 | Jul 06 08:16:09 PM PDT 24 | Jul 06 08:16:48 PM PDT 24 | 406405153 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.4257284231 | Jul 06 08:07:55 PM PDT 24 | Jul 06 08:08:02 PM PDT 24 | 46714571 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3290786803 | Jul 06 08:21:53 PM PDT 24 | Jul 06 08:45:40 PM PDT 24 | 85650269028 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1304063660 | Jul 06 08:03:41 PM PDT 24 | Jul 06 08:17:19 PM PDT 24 | 8583181888 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.575436858 | Jul 06 08:16:28 PM PDT 24 | Jul 06 08:18:10 PM PDT 24 | 8791547350 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.3750145208 | Jul 06 08:12:47 PM PDT 24 | Jul 06 08:17:11 PM PDT 24 | 3522030090 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2384910297 | Jul 06 08:08:20 PM PDT 24 | Jul 06 08:21:20 PM PDT 24 | 74049794936 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/46.xbar_same_source.3482422243 | Jul 06 08:15:08 PM PDT 24 | Jul 06 08:15:47 PM PDT 24 | 1127591132 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.4255513394 | Jul 06 08:13:35 PM PDT 24 | Jul 06 08:23:56 PM PDT 24 | 57560094730 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/50.xbar_stress_all.3430978176 | Jul 06 08:15:52 PM PDT 24 | Jul 06 08:17:08 PM PDT 24 | 872210740 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/85.xbar_random.3759431224 | Jul 06 08:21:52 PM PDT 24 | Jul 06 08:22:43 PM PDT 24 | 1451012304 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/53.xbar_error_random.1899745866 | Jul 06 08:16:18 PM PDT 24 | Jul 06 08:17:41 PM PDT 24 | 2187082712 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/8.chip_csr_rw.2482710821 | Jul 06 08:05:23 PM PDT 24 | Jul 06 08:11:35 PM PDT 24 | 4024597672 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/18.xbar_error_random.34399024 | Jul 06 08:09:09 PM PDT 24 | Jul 06 08:09:18 PM PDT 24 | 70205638 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2793403742 | Jul 06 08:00:11 PM PDT 24 | Jul 06 08:16:04 PM PDT 24 | 95708390174 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.1571620662 | Jul 06 08:19:46 PM PDT 24 | Jul 06 08:21:03 PM PDT 24 | 1917242155 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.2359422343 | Jul 06 08:07:58 PM PDT 24 | Jul 06 08:42:37 PM PDT 24 | 121587090572 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/0.chip_tl_errors.3164967640 | Jul 06 07:58:33 PM PDT 24 | Jul 06 08:05:47 PM PDT 24 | 4172825471 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.508244388 | Jul 06 08:18:03 PM PDT 24 | Jul 06 08:18:10 PM PDT 24 | 40942886 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.1479747911 | Jul 06 08:06:05 PM PDT 24 | Jul 06 08:08:38 PM PDT 24 | 3088027028 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.3975617143 | Jul 06 08:10:24 PM PDT 24 | Jul 06 08:10:34 PM PDT 24 | 67948977 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.3629728138 | Jul 06 08:21:32 PM PDT 24 | Jul 06 08:55:26 PM PDT 24 | 122918041610 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.3011198446 | Jul 06 08:10:54 PM PDT 24 | Jul 06 08:11:59 PM PDT 24 | 659717063 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/92.xbar_random.374326313 | Jul 06 08:22:57 PM PDT 24 | Jul 06 08:24:18 PM PDT 24 | 2049713110 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3941596448 | Jul 06 08:06:55 PM PDT 24 | Jul 06 08:07:31 PM PDT 24 | 339839944 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/94.xbar_random.2974244622 | Jul 06 08:23:25 PM PDT 24 | Jul 06 08:24:06 PM PDT 24 | 535755707 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/34.xbar_same_source.3232883655 | Jul 06 08:12:57 PM PDT 24 | Jul 06 08:13:42 PM PDT 24 | 569665287 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/98.xbar_stress_all.970355963 | Jul 06 08:23:55 PM PDT 24 | Jul 06 08:25:22 PM PDT 24 | 1240120602 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.232382909 | Jul 06 08:19:16 PM PDT 24 | Jul 06 08:20:46 PM PDT 24 | 1105270267 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/36.xbar_same_source.3850042836 | Jul 06 08:13:20 PM PDT 24 | Jul 06 08:13:48 PM PDT 24 | 826644737 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/83.xbar_stress_all.2503316678 | Jul 06 08:21:38 PM PDT 24 | Jul 06 08:24:02 PM PDT 24 | 3365276353 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.2753044241 | Jul 06 08:08:07 PM PDT 24 | Jul 06 08:08:39 PM PDT 24 | 345129385 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.3821948235 | Jul 06 08:11:54 PM PDT 24 | Jul 06 08:28:38 PM PDT 24 | 54247136469 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.248392992 | Jul 06 08:20:47 PM PDT 24 | Jul 06 08:21:02 PM PDT 24 | 130034363 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.3675456750 | Jul 06 08:17:08 PM PDT 24 | Jul 06 08:20:20 PM PDT 24 | 2545371791 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/90.xbar_random.1622012103 | Jul 06 08:22:28 PM PDT 24 | Jul 06 08:23:12 PM PDT 24 | 452076335 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3493288476 | Jul 06 08:06:45 PM PDT 24 | Jul 06 08:43:04 PM PDT 24 | 122855140435 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/73.xbar_random.1245851632 | Jul 06 08:19:38 PM PDT 24 | Jul 06 08:20:22 PM PDT 24 | 533379387 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/14.xbar_error_random.3208171113 | Jul 06 08:07:38 PM PDT 24 | Jul 06 08:09:03 PM PDT 24 | 1993785314 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.358836741 | Jul 06 08:18:22 PM PDT 24 | Jul 06 08:30:16 PM PDT 24 | 43766225618 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.263968228 | Jul 06 08:19:22 PM PDT 24 | Jul 06 08:27:43 PM PDT 24 | 7243552164 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/36.xbar_smoke.2997994041 | Jul 06 08:13:20 PM PDT 24 | Jul 06 08:13:26 PM PDT 24 | 47942758 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.3060155070 | Jul 06 08:11:06 PM PDT 24 | Jul 06 08:12:43 PM PDT 24 | 8985116838 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1141569180 | Jul 06 08:09:20 PM PDT 24 | Jul 06 08:23:40 PM PDT 24 | 14885606705 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2935556385 | Jul 06 08:14:12 PM PDT 24 | Jul 06 08:20:46 PM PDT 24 | 3473569029 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.3880106505 | Jul 06 08:20:15 PM PDT 24 | Jul 06 08:20:58 PM PDT 24 | 959793069 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/20.xbar_same_source.466896280 | Jul 06 08:09:49 PM PDT 24 | Jul 06 08:10:23 PM PDT 24 | 429799904 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.2450940122 | Jul 06 08:13:35 PM PDT 24 | Jul 06 08:32:57 PM PDT 24 | 61505842152 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.436937609 | Jul 06 08:18:30 PM PDT 24 | Jul 06 08:19:47 PM PDT 24 | 7389171982 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.2404128591 | Jul 06 08:20:26 PM PDT 24 | Jul 06 08:21:12 PM PDT 24 | 1103440548 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1046321686 | Jul 06 08:03:09 PM PDT 24 | Jul 06 08:05:40 PM PDT 24 | 494370422 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.380282893 | Jul 06 08:05:17 PM PDT 24 | Jul 06 08:11:17 PM PDT 24 | 8646993209 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/71.xbar_smoke.2441102422 | Jul 06 08:19:19 PM PDT 24 | Jul 06 08:19:29 PM PDT 24 | 177069578 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.220972275 | Jul 06 08:11:48 PM PDT 24 | Jul 06 08:24:39 PM PDT 24 | 7908399289 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.919453724 | Jul 06 07:59:30 PM PDT 24 | Jul 06 08:01:15 PM PDT 24 | 1110150323 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.3035968734 | Jul 06 08:11:35 PM PDT 24 | Jul 06 08:12:47 PM PDT 24 | 6599341608 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.1774180170 | Jul 06 08:13:02 PM PDT 24 | Jul 06 08:13:23 PM PDT 24 | 29781023 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.3756892109 | Jul 06 08:19:37 PM PDT 24 | Jul 06 08:19:54 PM PDT 24 | 288332628 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/76.xbar_random.3323623483 | Jul 06 08:20:15 PM PDT 24 | Jul 06 08:20:49 PM PDT 24 | 801097299 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/66.xbar_error_random.1655472664 | Jul 06 08:18:29 PM PDT 24 | Jul 06 08:18:38 PM PDT 24 | 123952396 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.595866138 | Jul 06 08:13:37 PM PDT 24 | Jul 06 08:13:44 PM PDT 24 | 43283675 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.2742017316 | Jul 06 08:22:31 PM PDT 24 | Jul 06 08:23:12 PM PDT 24 | 412618746 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.4064311285 | Jul 06 08:21:52 PM PDT 24 | Jul 06 08:27:45 PM PDT 24 | 2116974418 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.3073465059 | Jul 06 08:14:32 PM PDT 24 | Jul 06 08:26:54 PM PDT 24 | 15434970753 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.3795929432 | Jul 06 08:02:35 PM PDT 24 | Jul 06 08:03:50 PM PDT 24 | 1596461872 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.3973602801 | Jul 06 08:10:56 PM PDT 24 | Jul 06 08:11:45 PM PDT 24 | 483265674 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.863680663 | Jul 06 08:05:38 PM PDT 24 | Jul 06 08:06:34 PM PDT 24 | 559619529 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.713750390 | Jul 06 08:14:38 PM PDT 24 | Jul 06 08:16:55 PM PDT 24 | 1102867425 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/31.xbar_error_random.327819234 | Jul 06 08:12:28 PM PDT 24 | Jul 06 08:13:40 PM PDT 24 | 2175954631 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2383462598 | Jul 06 08:22:21 PM PDT 24 | Jul 06 08:22:58 PM PDT 24 | 849650876 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.5613666 | Jul 06 08:20:15 PM PDT 24 | Jul 06 08:21:17 PM PDT 24 | 3594928183 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.2251786715 | Jul 06 08:11:59 PM PDT 24 | Jul 06 08:13:36 PM PDT 24 | 5247179857 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.71798734 | Jul 06 08:20:39 PM PDT 24 | Jul 06 08:21:08 PM PDT 24 | 67197498 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1387607457 | Jul 06 08:08:47 PM PDT 24 | Jul 06 08:16:37 PM PDT 24 | 3449690759 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/55.xbar_stress_all.1592026295 | Jul 06 08:16:35 PM PDT 24 | Jul 06 08:21:15 PM PDT 24 | 2600714429 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.1801105617 | Jul 06 08:03:52 PM PDT 24 | Jul 06 08:03:59 PM PDT 24 | 43400142 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.707742081 | Jul 06 08:07:07 PM PDT 24 | Jul 06 08:32:58 PM PDT 24 | 14949510680 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/7.xbar_smoke.3303841835 | Jul 06 08:04:32 PM PDT 24 | Jul 06 08:04:39 PM PDT 24 | 49583308 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.2195521623 | Jul 06 08:16:44 PM PDT 24 | Jul 06 08:18:52 PM PDT 24 | 2889856983 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.3437261508 | Jul 06 08:15:06 PM PDT 24 | Jul 06 08:15:13 PM PDT 24 | 46261443 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.2478553435 | Jul 06 08:08:25 PM PDT 24 | Jul 06 08:08:53 PM PDT 24 | 243956442 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.438888354 | Jul 06 08:13:16 PM PDT 24 | Jul 06 08:13:30 PM PDT 24 | 7626519 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.2512135378 | Jul 06 08:19:00 PM PDT 24 | Jul 06 08:19:45 PM PDT 24 | 438091299 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.1447111136 | Jul 06 08:13:14 PM PDT 24 | Jul 06 08:20:24 PM PDT 24 | 12172529845 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/75.xbar_error_random.3943972899 | Jul 06 08:20:00 PM PDT 24 | Jul 06 08:21:05 PM PDT 24 | 1723302953 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.4180660260 | Jul 06 08:23:47 PM PDT 24 | Jul 06 08:25:14 PM PDT 24 | 4974840297 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.2130402114 | Jul 06 08:11:19 PM PDT 24 | Jul 06 08:12:41 PM PDT 24 | 7863674748 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.153669590 | Jul 06 08:12:03 PM PDT 24 | Jul 06 08:22:17 PM PDT 24 | 14029099371 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.1292545601 | Jul 06 08:15:27 PM PDT 24 | Jul 06 08:16:13 PM PDT 24 | 493025506 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.2642607319 | Jul 06 08:17:44 PM PDT 24 | Jul 06 08:18:12 PM PDT 24 | 238831567 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.2105717269 | Jul 06 08:03:05 PM PDT 24 | Jul 06 10:13:37 PM PDT 24 | 55250118596 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/99.xbar_error_random.586488185 | Jul 06 08:24:06 PM PDT 24 | Jul 06 08:25:10 PM PDT 24 | 1769219740 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/17.xbar_smoke.2392109191 | Jul 06 08:08:37 PM PDT 24 | Jul 06 08:08:43 PM PDT 24 | 44585760 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/23.xbar_smoke.1068607625 | Jul 06 08:10:26 PM PDT 24 | Jul 06 08:10:36 PM PDT 24 | 203410030 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.1811270966 | Jul 06 08:09:24 PM PDT 24 | Jul 06 08:45:20 PM PDT 24 | 122488082167 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/86.xbar_stress_all.2783452551 | Jul 06 08:22:01 PM PDT 24 | Jul 06 08:26:02 PM PDT 24 | 6037445185 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2471606109 | Jul 06 08:23:19 PM PDT 24 | Jul 06 08:29:05 PM PDT 24 | 7970676141 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/34.xbar_smoke.2240069436 | Jul 06 08:12:55 PM PDT 24 | Jul 06 08:13:04 PM PDT 24 | 206083196 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/97.xbar_smoke.2817570470 | Jul 06 08:23:46 PM PDT 24 | Jul 06 08:23:52 PM PDT 24 | 38377266 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3979805562 | Jul 06 08:06:42 PM PDT 24 | Jul 06 08:08:34 PM PDT 24 | 6152822347 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.260931646 | Jul 06 08:20:10 PM PDT 24 | Jul 06 08:20:35 PM PDT 24 | 256859216 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/72.xbar_stress_all.3036160343 | Jul 06 08:19:32 PM PDT 24 | Jul 06 08:23:03 PM PDT 24 | 5430613836 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/43.xbar_random.352843968 | Jul 06 08:14:36 PM PDT 24 | Jul 06 08:15:18 PM PDT 24 | 1060811917 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.1182311409 | Jul 06 08:08:07 PM PDT 24 | Jul 06 08:34:00 PM PDT 24 | 15891053723 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/50.xbar_random.4062432914 | Jul 06 08:15:48 PM PDT 24 | Jul 06 08:16:18 PM PDT 24 | 266495937 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.848955190 | Jul 06 08:05:38 PM PDT 24 | Jul 06 08:06:07 PM PDT 24 | 208881758 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.1742899136 | Jul 06 08:07:54 PM PDT 24 | Jul 06 08:08:02 PM PDT 24 | 82696596 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.2891844746 | Jul 06 08:12:52 PM PDT 24 | Jul 06 08:13:25 PM PDT 24 | 704578178 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/47.xbar_smoke.661247994 | Jul 06 08:15:12 PM PDT 24 | Jul 06 08:15:20 PM PDT 24 | 48927531 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/80.xbar_same_source.845925779 | Jul 06 08:20:57 PM PDT 24 | Jul 06 08:21:35 PM PDT 24 | 465336034 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/6.xbar_same_source.363944485 | Jul 06 08:04:13 PM PDT 24 | Jul 06 08:04:50 PM PDT 24 | 404930573 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/27.xbar_error_random.2238700857 | Jul 06 08:11:43 PM PDT 24 | Jul 06 08:12:08 PM PDT 24 | 251625095 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/8.xbar_error_random.1756940337 | Jul 06 08:05:08 PM PDT 24 | Jul 06 08:06:20 PM PDT 24 | 2030388047 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.2512095497 | Jul 06 08:12:27 PM PDT 24 | Jul 06 08:22:38 PM PDT 24 | 58978887614 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/44.xbar_smoke.3422716347 | Jul 06 08:14:46 PM PDT 24 | Jul 06 08:14:55 PM PDT 24 | 199796205 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/56.xbar_error_random.3381324071 | Jul 06 08:16:45 PM PDT 24 | Jul 06 08:17:17 PM PDT 24 | 949117108 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.800155443 | Jul 06 08:01:49 PM PDT 24 | Jul 06 08:02:45 PM PDT 24 | 726962678 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.1211342562 | Jul 06 08:18:30 PM PDT 24 | Jul 06 08:20:20 PM PDT 24 | 5877006790 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.3550957843 | Jul 06 08:22:22 PM PDT 24 | Jul 06 08:22:37 PM PDT 24 | 110749928 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.1615569212 | Jul 06 08:20:57 PM PDT 24 | Jul 06 08:22:02 PM PDT 24 | 6006142656 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/17.xbar_random.3850486997 | Jul 06 08:08:41 PM PDT 24 | Jul 06 08:08:54 PM PDT 24 | 90836361 ps | ||
| T2893 | /workspace/coverage/cover_reg_top/62.xbar_same_source.1418414649 | Jul 06 08:17:47 PM PDT 24 | Jul 06 08:18:47 PM PDT 24 | 1727429949 ps | ||
| T2894 | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.4115733853 | Jul 06 08:13:10 PM PDT 24 | Jul 06 08:13:16 PM PDT 24 | 38952095 ps | ||
| T2895 | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.363426740 | Jul 06 08:10:29 PM PDT 24 | Jul 06 08:11:20 PM PDT 24 | 1158360307 ps | ||
| T2896 | /workspace/coverage/cover_reg_top/14.xbar_same_source.877218108 | Jul 06 08:07:38 PM PDT 24 | Jul 06 08:08:21 PM PDT 24 | 536333050 ps | ||
| T2897 | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.1529414573 | Jul 06 08:04:59 PM PDT 24 | Jul 06 08:06:00 PM PDT 24 | 5604362437 ps | ||
| T2898 | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.994553640 | Jul 06 08:14:14 PM PDT 24 | Jul 06 08:22:35 PM PDT 24 | 12258910383 ps | ||
| T2899 | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.264673534 | Jul 06 08:06:35 PM PDT 24 | Jul 06 08:12:40 PM PDT 24 | 8834388446 ps | ||
| T2900 | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.50054127 | Jul 06 08:04:39 PM PDT 24 | Jul 06 08:06:25 PM PDT 24 | 5691755076 ps | ||
| T2901 | /workspace/coverage/cover_reg_top/42.xbar_smoke.1827514821 | Jul 06 08:14:24 PM PDT 24 | Jul 06 08:14:33 PM PDT 24 | 162454869 ps | ||
| T2902 | /workspace/coverage/cover_reg_top/55.xbar_smoke.769390889 | Jul 06 08:16:29 PM PDT 24 | Jul 06 08:16:38 PM PDT 24 | 196869791 ps | ||
| T2903 | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.524863565 | Jul 06 08:16:04 PM PDT 24 | Jul 06 08:22:33 PM PDT 24 | 4233995016 ps | ||
| T2904 | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1877098838 | Jul 06 07:58:41 PM PDT 24 | Jul 06 07:58:49 PM PDT 24 | 48419285 ps | ||
| T41 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1060577918 | Jul 06 07:20:31 PM PDT 24 | Jul 06 07:24:41 PM PDT 24 | 4121794150 ps | ||
| T42 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1437215675 | Jul 06 07:20:34 PM PDT 24 | Jul 06 07:23:47 PM PDT 24 | 4106531850 ps | ||
| T43 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1607215817 | Jul 06 07:20:34 PM PDT 24 | Jul 06 07:24:35 PM PDT 24 | 4420035378 ps | ||
| T44 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.574690393 | Jul 06 07:20:35 PM PDT 24 | Jul 06 07:26:26 PM PDT 24 | 5568512954 ps | ||
| T201 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2173966058 | Jul 06 07:20:23 PM PDT 24 | Jul 06 07:25:34 PM PDT 24 | 4509411720 ps | ||
| T202 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2146837834 | Jul 06 07:20:32 PM PDT 24 | Jul 06 07:24:50 PM PDT 24 | 4981859741 ps | ||
| T203 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3457965336 | Jul 06 07:20:38 PM PDT 24 | Jul 06 07:24:27 PM PDT 24 | 4523026300 ps | ||
| T204 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3501073323 | Jul 06 07:20:31 PM PDT 24 | Jul 06 07:24:45 PM PDT 24 | 3913272400 ps | ||
| T205 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.248489283 | Jul 06 07:20:32 PM PDT 24 | Jul 06 07:25:35 PM PDT 24 | 4720816882 ps | ||
| T206 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3261427342 | Jul 06 07:20:22 PM PDT 24 | Jul 06 07:24:57 PM PDT 24 | 4429056640 ps |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2820483862 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 4703273822 ps |
| CPU time | 773 seconds |
| Started | Jul 06 07:27:40 PM PDT 24 |
| Finished | Jul 06 07:40:34 PM PDT 24 |
| Peak memory | 611072 kb |
| Host | smart-38c9e3c5-d810-4de9-919d-9d5f58f1d955 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2820483862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.2820483862 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.3718397271 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 23012377820 ps |
| CPU time | 2500.14 seconds |
| Started | Jul 06 07:44:15 PM PDT 24 |
| Finished | Jul 06 08:25:56 PM PDT 24 |
| Peak memory | 607816 kb |
| Host | smart-6bc03b8f-edac-46c0-8082-7b3148c035eb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718397271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.3718397271 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.4013730044 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 87564391750 ps |
| CPU time | 1503.45 seconds |
| Started | Jul 06 08:20:53 PM PDT 24 |
| Finished | Jul 06 08:45:57 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-1cdc029f-8816-47bf-9b3d-0cfc057e1653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013730044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.4013730044 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.2272962855 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 5223322604 ps |
| CPU time | 917.03 seconds |
| Started | Jul 06 07:50:34 PM PDT 24 |
| Finished | Jul 06 08:05:52 PM PDT 24 |
| Peak memory | 609148 kb |
| Host | smart-0df7a20d-9ccc-4778-a17d-076610f37b1b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272962855 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.2272962855 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1060577918 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4121794150 ps |
| CPU time | 249.29 seconds |
| Started | Jul 06 07:20:31 PM PDT 24 |
| Finished | Jul 06 07:24:41 PM PDT 24 |
| Peak memory | 657060 kb |
| Host | smart-a97be439-885a-4531-96f6-dac3d1207dfd |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060577918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.1060577918 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.291489683 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 3028143792 ps |
| CPU time | 269.02 seconds |
| Started | Jul 06 08:13:47 PM PDT 24 |
| Finished | Jul 06 08:18:17 PM PDT 24 |
| Peak memory | 576820 kb |
| Host | smart-684de56f-cdd3-458a-bec5-086128de31e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291489683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.291489683 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.4233608114 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 95187648945 ps |
| CPU time | 1613.36 seconds |
| Started | Jul 06 08:22:36 PM PDT 24 |
| Finished | Jul 06 08:49:30 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-127d839f-af62-4bb8-b531-051daf961e4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233608114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_ device_slow_rsp.4233608114 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.886907778 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 6063948100 ps |
| CPU time | 925.63 seconds |
| Started | Jul 06 08:04:23 PM PDT 24 |
| Finished | Jul 06 08:19:49 PM PDT 24 |
| Peak memory | 598008 kb |
| Host | smart-61794064-995c-4ea2-8c46-c5bc857059c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886907778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.886907778 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1471963848 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 15645844427 ps |
| CPU time | 3877.3 seconds |
| Started | Jul 06 07:58:40 PM PDT 24 |
| Finished | Jul 06 09:03:18 PM PDT 24 |
| Peak memory | 610184 kb |
| Host | smart-ab6a993c-adc3-41e7-9906-1a0723692910 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471963848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.1471963848 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1798890447 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 126099125876 ps |
| CPU time | 2125.02 seconds |
| Started | Jul 06 08:23:43 PM PDT 24 |
| Finished | Jul 06 08:59:09 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-d35ec31f-df94-4b18-a6dc-6199d06f6a1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798890447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.1798890447 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3972021921 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 8921590568 ps |
| CPU time | 1852.94 seconds |
| Started | Jul 06 07:49:05 PM PDT 24 |
| Finished | Jul 06 08:19:58 PM PDT 24 |
| Peak memory | 617584 kb |
| Host | smart-642f3aa5-a7ba-4e26-8c12-2c0fdc311ff2 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3972021921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.3972021921 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.3075734140 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 5836322294 ps |
| CPU time | 1139.64 seconds |
| Started | Jul 06 07:50:05 PM PDT 24 |
| Finished | Jul 06 08:09:06 PM PDT 24 |
| Peak memory | 609208 kb |
| Host | smart-742cf675-21cf-499d-8c59-bb6fa696a43c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075734140 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.3075734140 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2282699470 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 142084627736 ps |
| CPU time | 2520.25 seconds |
| Started | Jul 06 08:13:44 PM PDT 24 |
| Finished | Jul 06 08:55:45 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-50ac7894-0da8-4f96-9666-74c0fefbc10c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282699470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.2282699470 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.805254253 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26370399782 ps |
| CPU time | 2244.65 seconds |
| Started | Jul 06 07:32:36 PM PDT 24 |
| Finished | Jul 06 08:10:01 PM PDT 24 |
| Peak memory | 619944 kb |
| Host | smart-94f6ed0d-590d-4007-9cdf-67facac0f706 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=805254253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testunl ocks.805254253 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2772909415 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 77798928432 ps |
| CPU time | 1361.41 seconds |
| Started | Jul 06 08:20:35 PM PDT 24 |
| Finished | Jul 06 08:43:17 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-b2ad75f8-1aee-41cf-9a34-8513e3108627 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772909415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.2772909415 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.1228411915 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2689185600 ps |
| CPU time | 315.96 seconds |
| Started | Jul 06 07:31:49 PM PDT 24 |
| Finished | Jul 06 07:37:05 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-a0fd6933-4835-4ce8-82af-c9eaf5295be9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228411915 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.1228411915 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3936322249 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 19068300340 ps |
| CPU time | 870.09 seconds |
| Started | Jul 06 08:17:31 PM PDT 24 |
| Finished | Jul 06 08:32:02 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-c03ed3cb-ca4c-42eb-90b7-b1e0679d3b6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936322249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.3936322249 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.2480230210 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4144598416 ps |
| CPU time | 595.28 seconds |
| Started | Jul 06 07:34:29 PM PDT 24 |
| Finished | Jul 06 07:44:25 PM PDT 24 |
| Peak memory | 609476 kb |
| Host | smart-8c26096e-c259-4914-8f44-baeb62490624 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480230210 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.2480230210 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1682161939 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 3725549792 ps |
| CPU time | 367.15 seconds |
| Started | Jul 06 07:32:05 PM PDT 24 |
| Finished | Jul 06 07:38:13 PM PDT 24 |
| Peak memory | 608584 kb |
| Host | smart-93d1703e-adb4-40e9-93da-89a1066e53bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1682161939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.1682161939 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.694758463 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3405058648 ps |
| CPU time | 238.47 seconds |
| Started | Jul 06 07:43:46 PM PDT 24 |
| Finished | Jul 06 07:47:45 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-6374ff82-7ed1-463c-9944-e10fb688eaa1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6947 58463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.694758463 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.217497403 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 6048456708 ps |
| CPU time | 645.14 seconds |
| Started | Jul 06 08:05:28 PM PDT 24 |
| Finished | Jul 06 08:16:14 PM PDT 24 |
| Peak memory | 603648 kb |
| Host | smart-6f8d56e2-0890-4eba-b802-060252ec8329 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217497403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.217497403 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.651487880 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 12357941000 ps |
| CPU time | 3556.21 seconds |
| Started | Jul 06 07:31:55 PM PDT 24 |
| Finished | Jul 06 08:31:12 PM PDT 24 |
| Peak memory | 610764 kb |
| Host | smart-eb867c8b-bba8-4237-9f02-7b1c352cdb60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65148 7880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.651487880 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.604580485 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 4588516784 ps |
| CPU time | 601.76 seconds |
| Started | Jul 06 07:39:34 PM PDT 24 |
| Finished | Jul 06 07:49:36 PM PDT 24 |
| Peak memory | 608920 kb |
| Host | smart-a08dc4dd-1e69-4675-9606-95d8897c171d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604580485 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_10.604580485 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1168122574 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 27088173210 ps |
| CPU time | 2157.6 seconds |
| Started | Jul 06 07:34:30 PM PDT 24 |
| Finished | Jul 06 08:10:29 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-1dd1eb02-3573-43aa-a98c-d7e370b91412 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1168122574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1168122574 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1253493550 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 5546731696 ps |
| CPU time | 1423.73 seconds |
| Started | Jul 06 07:50:12 PM PDT 24 |
| Finished | Jul 06 08:13:57 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-58b9386b-5816-4c83-bdf2-54e04e6cb542 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1253493550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.1253493550 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.206837347 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 8537546912 ps |
| CPU time | 724.15 seconds |
| Started | Jul 06 07:39:24 PM PDT 24 |
| Finished | Jul 06 07:51:29 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-d875b165-caf7-4e52-a469-4c42cb8e2e1d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206837347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sle ep_sram_ret_contents_no_scramble.206837347 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3404014491 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5093632196 ps |
| CPU time | 722.91 seconds |
| Started | Jul 06 07:38:37 PM PDT 24 |
| Finished | Jul 06 07:50:41 PM PDT 24 |
| Peak memory | 624744 kb |
| Host | smart-507ba18a-aba2-42a8-833c-41fea2161f1b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404014491 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.3404014491 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.1346821044 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 3452952737 ps |
| CPU time | 144.38 seconds |
| Started | Jul 06 08:16:17 PM PDT 24 |
| Finished | Jul 06 08:18:42 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-a7983a47-3831-44c5-9d29-07ee0d7dfe85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346821044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .1346821044 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.217174602 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 5086322071 ps |
| CPU time | 487.37 seconds |
| Started | Jul 06 07:46:19 PM PDT 24 |
| Finished | Jul 06 07:54:29 PM PDT 24 |
| Peak memory | 613848 kb |
| Host | smart-3a1ca70f-d20e-4714-9d2f-9479e1d3aadd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217174602 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.217174602 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.841263953 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 46590547360 ps |
| CPU time | 5831.93 seconds |
| Started | Jul 06 07:29:58 PM PDT 24 |
| Finished | Jul 06 09:07:11 PM PDT 24 |
| Peak memory | 620284 kb |
| Host | smart-e9624f6f-f320-4154-bd19-c3ac99a35e58 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841263953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_lc_walkthrough_dev.841263953 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2760200147 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 87924043912 ps |
| CPU time | 1611.36 seconds |
| Started | Jul 06 08:19:20 PM PDT 24 |
| Finished | Jul 06 08:46:14 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-b638e395-06b1-4035-9a95-b9f624c7abac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760200147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.2760200147 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3358866850 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 4844532712 ps |
| CPU time | 361.13 seconds |
| Started | Jul 06 07:36:06 PM PDT 24 |
| Finished | Jul 06 07:42:08 PM PDT 24 |
| Peak memory | 610464 kb |
| Host | smart-fa24e7aa-d8df-4472-bc7d-fc8350a69a77 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33588668 50 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3358866850 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1723199797 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 16904933607 ps |
| CPU time | 1775.39 seconds |
| Started | Jul 06 08:06:40 PM PDT 24 |
| Finished | Jul 06 08:36:16 PM PDT 24 |
| Peak memory | 592804 kb |
| Host | smart-fab5a940-941e-4cb1-9e6e-e4fdccdea876 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723199797 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.1723199797 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.690428466 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2905346583 ps |
| CPU time | 391.94 seconds |
| Started | Jul 06 07:31:26 PM PDT 24 |
| Finished | Jul 06 07:37:59 PM PDT 24 |
| Peak memory | 609804 kb |
| Host | smart-57448ad1-959f-4891-bb11-82b7a6dd7278 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=690428466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.690428466 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2487754970 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 23682600739 ps |
| CPU time | 433.46 seconds |
| Started | Jul 06 08:01:53 PM PDT 24 |
| Finished | Jul 06 08:09:06 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-c143c285-aef6-4681-b010-1d4b0a398aba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487754970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.2487754970 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.2241530140 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 55427894149 ps |
| CPU time | 551.9 seconds |
| Started | Jul 06 08:21:26 PM PDT 24 |
| Finished | Jul 06 08:30:38 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-e8865b5d-b542-4adb-b052-c2a783388838 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241530140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.2241530140 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.669455007 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 4156493160 ps |
| CPU time | 481.99 seconds |
| Started | Jul 06 08:02:50 PM PDT 24 |
| Finished | Jul 06 08:10:52 PM PDT 24 |
| Peak memory | 648856 kb |
| Host | smart-6570fe0a-7c33-482a-863b-e0967c091130 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669455007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_s w_alert_handler_lpg_sleep_mode_alerts.669455007 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1537451350 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 5758487684 ps |
| CPU time | 568.46 seconds |
| Started | Jul 06 07:53:41 PM PDT 24 |
| Finished | Jul 06 08:03:10 PM PDT 24 |
| Peak memory | 609752 kb |
| Host | smart-d523b59c-5531-4e0d-83a5-8c66ca5c8c24 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537451350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.1537451350 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.745499883 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 44831264680 ps |
| CPU time | 5670.59 seconds |
| Started | Jul 06 07:28:59 PM PDT 24 |
| Finished | Jul 06 09:03:30 PM PDT 24 |
| Peak memory | 620784 kb |
| Host | smart-4b5ed29a-50de-4320-8449-35824eaf1da9 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=745499883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.745499883 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3018609135 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2637026884 ps |
| CPU time | 279.76 seconds |
| Started | Jul 06 07:35:27 PM PDT 24 |
| Finished | Jul 06 07:40:07 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-9914247d-b630-42b8-8a6c-e4818b6f0596 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018 609135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.3018609135 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.1177748826 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 5397632636 ps |
| CPU time | 957.91 seconds |
| Started | Jul 06 07:27:03 PM PDT 24 |
| Finished | Jul 06 07:43:01 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-494969aa-6d2f-44df-aff4-501cdda863b2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177748826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.1177748826 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.1813302514 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 6494688608 ps |
| CPU time | 635.65 seconds |
| Started | Jul 06 07:39:13 PM PDT 24 |
| Finished | Jul 06 07:49:49 PM PDT 24 |
| Peak memory | 631816 kb |
| Host | smart-541d5d14-ba39-4b97-b0dd-95f5c935bfa5 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813302514 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.1813302514 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.3088426105 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 13687223216 ps |
| CPU time | 1524.4 seconds |
| Started | Jul 06 07:21:07 PM PDT 24 |
| Finished | Jul 06 07:46:33 PM PDT 24 |
| Peak memory | 607828 kb |
| Host | smart-44dda0da-1a6a-4fc4-973f-10ec32d4cf01 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088426105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.3088426105 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.690566737 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 5100995666 ps |
| CPU time | 505.32 seconds |
| Started | Jul 06 07:56:16 PM PDT 24 |
| Finished | Jul 06 08:04:42 PM PDT 24 |
| Peak memory | 650472 kb |
| Host | smart-dce5571d-826d-496d-8a7b-99e6f0ecc8dd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 690566737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.690566737 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3523854057 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3346006431 ps |
| CPU time | 367.02 seconds |
| Started | Jul 06 07:33:28 PM PDT 24 |
| Finished | Jul 06 07:39:36 PM PDT 24 |
| Peak memory | 609216 kb |
| Host | smart-c53057e1-6b6f-40bb-9771-5ae550b24438 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523 854057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.3523854057 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1880296174 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 5499655990 ps |
| CPU time | 589.56 seconds |
| Started | Jul 06 07:27:39 PM PDT 24 |
| Finished | Jul 06 07:37:30 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-4311b921-5113-46d2-9beb-4cb8b404a6c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18802 96174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.1880296174 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.1950022635 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 4188947968 ps |
| CPU time | 540.03 seconds |
| Started | Jul 06 08:07:14 PM PDT 24 |
| Finished | Jul 06 08:16:14 PM PDT 24 |
| Peak memory | 603548 kb |
| Host | smart-50bea68a-7224-49b6-abdf-7c9163fa3617 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950022635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.1950022635 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.616821987 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4636695280 ps |
| CPU time | 390.92 seconds |
| Started | Jul 06 07:28:15 PM PDT 24 |
| Finished | Jul 06 07:34:47 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-a9558451-67b2-4cc4-9429-1b1623d09dc4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616821987 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.616821987 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.941251929 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 23763511793 ps |
| CPU time | 4135.85 seconds |
| Started | Jul 06 07:34:16 PM PDT 24 |
| Finished | Jul 06 08:43:13 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-25e08f34-89e3-408b-a479-3dc707ed6177 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941251929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.941251929 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.994744070 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 4749437472 ps |
| CPU time | 578.84 seconds |
| Started | Jul 06 07:45:48 PM PDT 24 |
| Finished | Jul 06 07:55:28 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-94f83310-584a-4d87-8c1e-25e9e51057dd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99 4744070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.994744070 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.3111885572 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 8103834311 ps |
| CPU time | 505.96 seconds |
| Started | Jul 06 08:20:48 PM PDT 24 |
| Finished | Jul 06 08:29:15 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-bb9b0a50-fd90-4f92-ae55-0fcef3a01ca9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111885572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.3111885572 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.3509702920 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 5521586480 ps |
| CPU time | 513.77 seconds |
| Started | Jul 06 08:06:10 PM PDT 24 |
| Finished | Jul 06 08:14:44 PM PDT 24 |
| Peak memory | 649720 kb |
| Host | smart-e8fccc39-1269-4db0-962f-d1f4f40f36b7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3509702920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.3509702920 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3627147378 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 5013744456 ps |
| CPU time | 788.35 seconds |
| Started | Jul 06 07:32:12 PM PDT 24 |
| Finished | Jul 06 07:45:21 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-a4c09dfc-667b-4208-be67-bf429f2280fb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3627147378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.3627147378 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.2194972569 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 4107642304 ps |
| CPU time | 554.37 seconds |
| Started | Jul 06 08:03:07 PM PDT 24 |
| Finished | Jul 06 08:12:22 PM PDT 24 |
| Peak memory | 649640 kb |
| Host | smart-be64d2a0-9617-4a44-b12d-f07f1831cb40 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2194972569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.2194972569 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.201233498 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 5842899374 ps |
| CPU time | 832.34 seconds |
| Started | Jul 06 08:05:15 PM PDT 24 |
| Finished | Jul 06 08:19:08 PM PDT 24 |
| Peak memory | 650340 kb |
| Host | smart-38b0fa28-85bd-49bc-b77d-530113466f6d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 201233498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.201233498 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2515531627 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 7208722352 ps |
| CPU time | 520.09 seconds |
| Started | Jul 06 08:02:13 PM PDT 24 |
| Finished | Jul 06 08:10:53 PM PDT 24 |
| Peak memory | 662880 kb |
| Host | smart-1ddf1fde-c460-4d17-b2bf-3d36b3d1b5ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515531627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.2515531627 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3059472214 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8866696817 ps |
| CPU time | 1239.68 seconds |
| Started | Jul 06 07:29:31 PM PDT 24 |
| Finished | Jul 06 07:50:13 PM PDT 24 |
| Peak memory | 622904 kb |
| Host | smart-d6b9c96e-a220-4788-8553-fd9429d8b592 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059472214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3059472214 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3512422429 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 5393051550 ps |
| CPU time | 783.28 seconds |
| Started | Jul 06 07:28:35 PM PDT 24 |
| Finished | Jul 06 07:41:40 PM PDT 24 |
| Peak memory | 610412 kb |
| Host | smart-92386937-59a6-4c1d-9286-6233640be3d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35124224 29 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.3512422429 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.3093165153 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 6848911388 ps |
| CPU time | 1435.13 seconds |
| Started | Jul 06 07:30:24 PM PDT 24 |
| Finished | Jul 06 07:54:20 PM PDT 24 |
| Peak memory | 609236 kb |
| Host | smart-70d9bf02-56cf-4c5b-a59b-e32a43be6cc3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093165153 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.3093165153 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3907518855 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 4310293728 ps |
| CPU time | 518.88 seconds |
| Started | Jul 06 08:07:45 PM PDT 24 |
| Finished | Jul 06 08:16:25 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-edc4a205-a2f7-4c02-9ff4-9bd7361e7a8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907518855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.3907518855 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3055475617 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3580128534 ps |
| CPU time | 537.31 seconds |
| Started | Jul 06 07:28:47 PM PDT 24 |
| Finished | Jul 06 07:37:45 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-fd73b607-c058-45f4-95df-daf7556b986d |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305547 5617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3055475617 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3174395275 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3615256244 ps |
| CPU time | 299.62 seconds |
| Started | Jul 06 07:36:28 PM PDT 24 |
| Finished | Jul 06 07:41:28 PM PDT 24 |
| Peak memory | 609088 kb |
| Host | smart-ae7ad791-5a48-4477-bfb2-308fa839483f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174395275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.3174395275 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1576210744 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 9192615594 ps |
| CPU time | 1271.93 seconds |
| Started | Jul 06 07:28:36 PM PDT 24 |
| Finished | Jul 06 07:49:50 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-b912f64c-163d-4af3-9ffd-25d2a7c58f8a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1576210744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.1576210744 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1680619386 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 3626520952 ps |
| CPU time | 694.77 seconds |
| Started | Jul 06 07:29:14 PM PDT 24 |
| Finished | Jul 06 07:40:50 PM PDT 24 |
| Peak memory | 624608 kb |
| Host | smart-fd794d21-afc4-429d-adfd-6c5754c9d91c |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680619386 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.1680619386 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3958275994 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 6486848252 ps |
| CPU time | 590.72 seconds |
| Started | Jul 06 07:44:59 PM PDT 24 |
| Finished | Jul 06 07:54:50 PM PDT 24 |
| Peak memory | 610732 kb |
| Host | smart-89be3339-1429-43ef-a9b0-fe3c698cb1a3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958275994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.3958275994 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.4273355846 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 4233856426 ps |
| CPU time | 517.11 seconds |
| Started | Jul 06 08:08:58 PM PDT 24 |
| Finished | Jul 06 08:17:37 PM PDT 24 |
| Peak memory | 603556 kb |
| Host | smart-59bbf012-cc22-4cb7-a53e-e0eba950cef9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273355846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.4273355846 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3692313414 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1914148435 ps |
| CPU time | 363.19 seconds |
| Started | Jul 06 08:19:15 PM PDT 24 |
| Finished | Jul 06 08:25:20 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-c5780478-c46a-4e1c-aa2a-724a789c1a4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692313414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.3692313414 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4152636741 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5428353960 ps |
| CPU time | 546.69 seconds |
| Started | Jul 06 07:37:52 PM PDT 24 |
| Finished | Jul 06 07:47:00 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-a286be95-1d16-45a8-aa4f-838cc8c98791 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152636741 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4152636741 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.4246761239 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 13977551686 ps |
| CPU time | 524.44 seconds |
| Started | Jul 06 08:21:19 PM PDT 24 |
| Finished | Jul 06 08:30:05 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-d4e3fc4b-e143-4063-af39-9042fdc5d9bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246761239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.4246761239 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.3562058955 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 4663254900 ps |
| CPU time | 508.42 seconds |
| Started | Jul 06 08:04:46 PM PDT 24 |
| Finished | Jul 06 08:13:15 PM PDT 24 |
| Peak memory | 649780 kb |
| Host | smart-7dd0dfe6-7659-4afb-a6f0-36d39c79a5b2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3562058955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.3562058955 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2237931576 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3008978000 ps |
| CPU time | 267.29 seconds |
| Started | Jul 06 07:46:18 PM PDT 24 |
| Finished | Jul 06 07:50:46 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-bca7e9af-4156-47ca-a3e6-faff811b11c9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237931576 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.2237931576 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1960963468 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 2655703052 ps |
| CPU time | 142.79 seconds |
| Started | Jul 06 07:29:49 PM PDT 24 |
| Finished | Jul 06 07:32:13 PM PDT 24 |
| Peak memory | 620464 kb |
| Host | smart-8a0c5e2a-adcf-47a9-84d9-376402a14590 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19609634 68 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.1960963468 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.4229440019 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 6440759808 ps |
| CPU time | 1364.58 seconds |
| Started | Jul 06 07:40:27 PM PDT 24 |
| Finished | Jul 06 08:03:12 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-986f0d5d-d978-4abd-8490-8358de7bb7fb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229440019 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.4229440019 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.2113998668 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 10448981224 ps |
| CPU time | 653.45 seconds |
| Started | Jul 06 08:15:33 PM PDT 24 |
| Finished | Jul 06 08:26:27 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-5eaff66d-960c-4209-9993-3ecffce1981d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113998668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.2113998668 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.2174933391 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 4332153592 ps |
| CPU time | 787.7 seconds |
| Started | Jul 06 07:39:23 PM PDT 24 |
| Finished | Jul 06 07:52:31 PM PDT 24 |
| Peak memory | 609228 kb |
| Host | smart-b3e7e23f-f0c3-49a7-86ed-22b67268e34f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174933391 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.2174933391 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.2129866814 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 8127592324 ps |
| CPU time | 356.48 seconds |
| Started | Jul 06 08:08:25 PM PDT 24 |
| Finished | Jul 06 08:14:22 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-46212f1e-2bc1-42f4-b29d-40c031839196 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129866814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2129866814 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2798059401 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 10331506570 ps |
| CPU time | 1146.37 seconds |
| Started | Jul 06 07:31:21 PM PDT 24 |
| Finished | Jul 06 07:50:29 PM PDT 24 |
| Peak memory | 623300 kb |
| Host | smart-04ab493c-3711-49ba-b6d8-9284b709e134 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798059401 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.2798059401 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.4020942083 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 6345989830 ps |
| CPU time | 718.14 seconds |
| Started | Jul 06 08:11:59 PM PDT 24 |
| Finished | Jul 06 08:23:57 PM PDT 24 |
| Peak memory | 576984 kb |
| Host | smart-95a71d49-476c-4df9-8fcd-f948538829fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020942083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.4020942083 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2106409666 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4560978784 ps |
| CPU time | 478.12 seconds |
| Started | Jul 06 07:42:27 PM PDT 24 |
| Finished | Jul 06 07:50:26 PM PDT 24 |
| Peak memory | 619572 kb |
| Host | smart-ff37e0c9-d2fd-4c0c-93cb-174f4c3f597c |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 106409666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.2106409666 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1889846932 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3895707608 ps |
| CPU time | 432.57 seconds |
| Started | Jul 06 07:39:15 PM PDT 24 |
| Finished | Jul 06 07:46:28 PM PDT 24 |
| Peak memory | 608976 kb |
| Host | smart-99b17492-c85c-424b-a147-8986ee877c34 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18898469 32 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1889846932 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.548307930 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 4715637944 ps |
| CPU time | 522.5 seconds |
| Started | Jul 06 07:50:19 PM PDT 24 |
| Finished | Jul 06 07:59:02 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-ee33602d-7479-446c-97b7-bde3ecd73057 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54830793 0 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.548307930 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2240507541 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 29135743746 ps |
| CPU time | 3550.93 seconds |
| Started | Jul 06 08:04:58 PM PDT 24 |
| Finished | Jul 06 09:04:10 PM PDT 24 |
| Peak memory | 592964 kb |
| Host | smart-91ccd819-88be-4e88-be5c-09738d39c80f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240507541 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.2240507541 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3598600979 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 4286929864 ps |
| CPU time | 784.35 seconds |
| Started | Jul 06 07:52:10 PM PDT 24 |
| Finished | Jul 06 08:05:15 PM PDT 24 |
| Peak memory | 609204 kb |
| Host | smart-c8d0ef29-f5b4-4985-ba9e-40b9cb81a50a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3598600979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3598600979 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.574690393 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5568512954 ps |
| CPU time | 350.22 seconds |
| Started | Jul 06 07:20:35 PM PDT 24 |
| Finished | Jul 06 07:26:26 PM PDT 24 |
| Peak memory | 657160 kb |
| Host | smart-2cfde470-6572-4c11-af2a-2ce6c3be8aca |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574690393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 4.chip_padctrl_attributes.574690393 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2337585293 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 42999233512 ps |
| CPU time | 4994.91 seconds |
| Started | Jul 06 07:46:10 PM PDT 24 |
| Finished | Jul 06 09:09:26 PM PDT 24 |
| Peak memory | 624556 kb |
| Host | smart-8c740e0f-9b43-4008-bb61-99cc1dd035b3 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2337585293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.2337585293 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.3306539831 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 4292783907 ps |
| CPU time | 296.07 seconds |
| Started | Jul 06 08:09:39 PM PDT 24 |
| Finished | Jul 06 08:14:36 PM PDT 24 |
| Peak memory | 597524 kb |
| Host | smart-6558156c-fe5b-4cde-b3f3-55ba5e6325c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306539831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.3306539831 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2787207273 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 3908531267 ps |
| CPU time | 531.59 seconds |
| Started | Jul 06 08:06:17 PM PDT 24 |
| Finished | Jul 06 08:15:09 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-dda0d83f-3e60-422a-9419-6c119c2e6e3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787207273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.2787207273 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2959255075 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 2907895644 ps |
| CPU time | 229.31 seconds |
| Started | Jul 06 07:28:10 PM PDT 24 |
| Finished | Jul 06 07:32:00 PM PDT 24 |
| Peak memory | 619520 kb |
| Host | smart-5866453c-0a46-4aec-a27d-e2574b7fb017 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959255075 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.2959255075 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3745087171 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 10797250889 ps |
| CPU time | 2036.39 seconds |
| Started | Jul 06 07:40:32 PM PDT 24 |
| Finished | Jul 06 08:14:29 PM PDT 24 |
| Peak memory | 617720 kb |
| Host | smart-e608f67f-3b67-4d06-b0ad-1ef3729c3e3b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3745087171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.3745087171 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.1393767172 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 4582499075 ps |
| CPU time | 391.49 seconds |
| Started | Jul 06 08:12:45 PM PDT 24 |
| Finished | Jul 06 08:19:17 PM PDT 24 |
| Peak memory | 576828 kb |
| Host | smart-da19a386-3a9a-43c5-ad8c-a5190cf94f7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393767172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.1393767172 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.326789372 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 6647524932 ps |
| CPU time | 402.58 seconds |
| Started | Jul 06 08:03:10 PM PDT 24 |
| Finished | Jul 06 08:09:53 PM PDT 24 |
| Peak memory | 660524 kb |
| Host | smart-7f292cf7-3874-4f8d-9d4f-ebb101748f7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326789372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_re set.326789372 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2683034517 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 4558954952 ps |
| CPU time | 694.17 seconds |
| Started | Jul 06 07:40:10 PM PDT 24 |
| Finished | Jul 06 07:51:45 PM PDT 24 |
| Peak memory | 613008 kb |
| Host | smart-7ede1d85-5700-4bba-a4c4-71e70535e7ee |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683034517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2683034517 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.3513670555 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3683477146 ps |
| CPU time | 450.25 seconds |
| Started | Jul 06 07:44:39 PM PDT 24 |
| Finished | Jul 06 07:52:10 PM PDT 24 |
| Peak memory | 609216 kb |
| Host | smart-3400aa8e-156c-4764-85d0-de638c0f6af1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513670555 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.3513670555 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2574852888 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 18404610384 ps |
| CPU time | 463.78 seconds |
| Started | Jul 06 07:30:47 PM PDT 24 |
| Finished | Jul 06 07:38:32 PM PDT 24 |
| Peak memory | 617804 kb |
| Host | smart-8b565aff-bc26-45e2-bbd7-edb85682374f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2574852888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2574852888 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.230397882 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 2178786353 ps |
| CPU time | 245.03 seconds |
| Started | Jul 06 08:09:31 PM PDT 24 |
| Finished | Jul 06 08:13:36 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-b276e0eb-cace-423d-8e26-d966533b5d42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230397882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_ with_rand_reset.230397882 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.4277603172 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 20286218638 ps |
| CPU time | 4095.66 seconds |
| Started | Jul 06 07:32:26 PM PDT 24 |
| Finished | Jul 06 08:40:43 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-77ec060e-f7f0-40ab-964c-8c6ef2f484cc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277603172 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.4277603172 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1292381297 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 7543122640 ps |
| CPU time | 1480.22 seconds |
| Started | Jul 06 08:00:05 PM PDT 24 |
| Finished | Jul 06 08:24:46 PM PDT 24 |
| Peak memory | 618608 kb |
| Host | smart-95e5a42c-4f26-4007-9dee-b6e40c8ad7a1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1292381297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.1292381297 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.696720654 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 4936673240 ps |
| CPU time | 868.14 seconds |
| Started | Jul 06 07:28:29 PM PDT 24 |
| Finished | Jul 06 07:42:59 PM PDT 24 |
| Peak memory | 609112 kb |
| Host | smart-104fce34-6c58-4d35-be3a-9d0f7b4d108d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696720654 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_20.696720654 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3748238093 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 44662504091 ps |
| CPU time | 5680.84 seconds |
| Started | Jul 06 07:31:23 PM PDT 24 |
| Finished | Jul 06 09:06:04 PM PDT 24 |
| Peak memory | 624676 kb |
| Host | smart-9b71dd02-8ee4-47dc-9b99-26bf24232b6a |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3748238093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.3748238093 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.3113388635 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 3288314504 ps |
| CPU time | 320.83 seconds |
| Started | Jul 06 07:46:36 PM PDT 24 |
| Finished | Jul 06 07:51:57 PM PDT 24 |
| Peak memory | 608436 kb |
| Host | smart-5be7a75d-174a-42da-ab89-e5ce6728ed7c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113388635 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.3113388635 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.572293953 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2507664436 ps |
| CPU time | 415.95 seconds |
| Started | Jul 06 08:10:39 PM PDT 24 |
| Finished | Jul 06 08:17:35 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-ff4d4bd1-de84-4950-bb9b-6d737b422274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572293953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_ with_rand_reset.572293953 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3429023011 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 2040726921 ps |
| CPU time | 411.33 seconds |
| Started | Jul 06 08:21:29 PM PDT 24 |
| Finished | Jul 06 08:28:21 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-c51645f7-529b-4dea-8dec-a70627c2c58b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429023011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.3429023011 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.2353876148 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 4864283040 ps |
| CPU time | 367.56 seconds |
| Started | Jul 06 08:11:03 PM PDT 24 |
| Finished | Jul 06 08:17:11 PM PDT 24 |
| Peak memory | 597380 kb |
| Host | smart-7806b80c-ad77-46dd-bd4f-6ee880898291 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353876148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.2353876148 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.3860041535 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 3748550550 ps |
| CPU time | 559.09 seconds |
| Started | Jul 06 07:49:57 PM PDT 24 |
| Finished | Jul 06 07:59:17 PM PDT 24 |
| Peak memory | 608860 kb |
| Host | smart-d6384618-9c78-433d-9422-df95901dff75 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860041535 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.3860041535 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.1229125372 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 12693028394 ps |
| CPU time | 1334.7 seconds |
| Started | Jul 06 07:33:18 PM PDT 24 |
| Finished | Jul 06 07:55:34 PM PDT 24 |
| Peak memory | 607816 kb |
| Host | smart-f1615041-580f-423a-8977-4ec6557bc13c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229125372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.1229125372 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1909269962 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 489693299 ps |
| CPU time | 164.1 seconds |
| Started | Jul 06 08:06:35 PM PDT 24 |
| Finished | Jul 06 08:09:20 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-11e99f19-ba3d-45ed-89ca-a12838421d89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909269962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.1909269962 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.635860893 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 12475608316 ps |
| CPU time | 1749.08 seconds |
| Started | Jul 06 07:31:16 PM PDT 24 |
| Finished | Jul 06 08:00:26 PM PDT 24 |
| Peak memory | 611060 kb |
| Host | smart-23b78d99-d94e-47a2-9ab1-8d1f26b26eec |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635860893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.635860893 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.330843013 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 46555969944 ps |
| CPU time | 5932.98 seconds |
| Started | Jul 06 07:28:15 PM PDT 24 |
| Finished | Jul 06 09:07:10 PM PDT 24 |
| Peak memory | 624948 kb |
| Host | smart-c953e861-0684-4a15-94fe-a10dd510d1e1 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330843013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_prod.330843013 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.329270946 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 12572055564 ps |
| CPU time | 759.33 seconds |
| Started | Jul 06 08:19:43 PM PDT 24 |
| Finished | Jul 06 08:32:23 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-78efd769-a964-4e11-a9bc-6189f23dca1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329270946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_ with_rand_reset.329270946 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1251513653 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 4854390852 ps |
| CPU time | 880.87 seconds |
| Started | Jul 06 07:47:05 PM PDT 24 |
| Finished | Jul 06 08:01:48 PM PDT 24 |
| Peak memory | 608960 kb |
| Host | smart-ca9addb5-719d-4297-913a-6c478e7e8e29 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251513653 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.1251513653 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.2363284142 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 4327837544 ps |
| CPU time | 626.85 seconds |
| Started | Jul 06 08:04:52 PM PDT 24 |
| Finished | Jul 06 08:15:19 PM PDT 24 |
| Peak memory | 650108 kb |
| Host | smart-73d9bd27-fdfe-4b5c-8259-95f002fa6936 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2363284142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.2363284142 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.3593748234 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 4240392750 ps |
| CPU time | 607.61 seconds |
| Started | Jul 06 08:05:12 PM PDT 24 |
| Finished | Jul 06 08:15:20 PM PDT 24 |
| Peak memory | 649780 kb |
| Host | smart-a697e22b-c85e-4a79-b77a-99e761bf26c8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3593748234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.3593748234 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3197917052 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2080776709 ps |
| CPU time | 107.51 seconds |
| Started | Jul 06 07:36:10 PM PDT 24 |
| Finished | Jul 06 07:37:58 PM PDT 24 |
| Peak memory | 618512 kb |
| Host | smart-c69b0681-e902-4665-a9af-0da3f5587cca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197917052 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.3197917052 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.2681779025 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 3463037430 ps |
| CPU time | 244.04 seconds |
| Started | Jul 06 08:08:32 PM PDT 24 |
| Finished | Jul 06 08:12:37 PM PDT 24 |
| Peak memory | 597484 kb |
| Host | smart-9d5a4556-85da-4955-82c2-2b494846ae1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681779025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.2681779025 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.4192433459 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 13812833331 ps |
| CPU time | 495.84 seconds |
| Started | Jul 06 08:12:23 PM PDT 24 |
| Finished | Jul 06 08:20:39 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-2552fb79-e959-468c-a204-5fee6d817aa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192433459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.4192433459 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.3798203194 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 5520590248 ps |
| CPU time | 591.15 seconds |
| Started | Jul 06 07:58:51 PM PDT 24 |
| Finished | Jul 06 08:08:43 PM PDT 24 |
| Peak memory | 650140 kb |
| Host | smart-eed96498-1b21-428f-bbbc-96c1800f6222 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3798203194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.3798203194 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.181611109 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 2973376840 ps |
| CPU time | 288.78 seconds |
| Started | Jul 06 07:32:28 PM PDT 24 |
| Finished | Jul 06 07:37:18 PM PDT 24 |
| Peak memory | 611780 kb |
| Host | smart-2d011e19-9736-408e-afdd-5dfc6c21d6ab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181611109 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.181611109 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.218712782 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 14830244312 ps |
| CPU time | 657.44 seconds |
| Started | Jul 06 08:10:37 PM PDT 24 |
| Finished | Jul 06 08:21:35 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-ef5ea0fc-805e-4de3-b368-ec79a350994e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218712782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.218712782 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.756976574 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 3165396462 ps |
| CPU time | 307.18 seconds |
| Started | Jul 06 08:14:11 PM PDT 24 |
| Finished | Jul 06 08:19:18 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-413ac5df-7e74-47d4-8481-e2ee64a55d54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756976574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.756976574 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.3923622023 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 3567324492 ps |
| CPU time | 751.03 seconds |
| Started | Jul 06 07:33:41 PM PDT 24 |
| Finished | Jul 06 07:46:13 PM PDT 24 |
| Peak memory | 608860 kb |
| Host | smart-fb5b9481-d31e-4f99-8583-770b04f037f8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923622023 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.3923622023 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3020012410 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 12651512396 ps |
| CPU time | 2745.37 seconds |
| Started | Jul 06 07:32:23 PM PDT 24 |
| Finished | Jul 06 08:18:10 PM PDT 24 |
| Peak memory | 621644 kb |
| Host | smart-77a6b131-6759-4961-9c71-669dc5fb469e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3020012410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.3020012410 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1857430995 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 11076552734 ps |
| CPU time | 1724.06 seconds |
| Started | Jul 06 07:46:26 PM PDT 24 |
| Finished | Jul 06 08:15:11 PM PDT 24 |
| Peak memory | 611140 kb |
| Host | smart-c7a7b492-79cc-4471-b7e7-cfe346efde53 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1857430995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.1857430995 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.661450440 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4418832554 ps |
| CPU time | 661.2 seconds |
| Started | Jul 06 08:01:54 PM PDT 24 |
| Finished | Jul 06 08:12:56 PM PDT 24 |
| Peak memory | 650056 kb |
| Host | smart-8c08ff28-4802-4ebf-bb5f-3f776761c7f8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 661450440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.661450440 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2733007134 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 5274967736 ps |
| CPU time | 627.37 seconds |
| Started | Jul 06 07:30:49 PM PDT 24 |
| Finished | Jul 06 07:41:17 PM PDT 24 |
| Peak memory | 621288 kb |
| Host | smart-67977fb8-f55d-43e8-bc55-4346e8ac660f |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273300 7134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2733007134 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.3678684050 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 8495419656 ps |
| CPU time | 2201.74 seconds |
| Started | Jul 06 07:31:09 PM PDT 24 |
| Finished | Jul 06 08:07:53 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-3f1a6afa-31dd-46f8-a2a8-7214ccb3b7f6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36786 84050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.3678684050 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.4210711920 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 4146309676 ps |
| CPU time | 593.91 seconds |
| Started | Jul 06 07:44:26 PM PDT 24 |
| Finished | Jul 06 07:54:20 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-c0143761-af5d-4071-b467-de80b4e762b8 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210711920 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.4210711920 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3228597120 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 11703489245 ps |
| CPU time | 684.6 seconds |
| Started | Jul 06 08:09:15 PM PDT 24 |
| Finished | Jul 06 08:20:40 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-f9c34e32-7942-4146-88ec-6f7dd84f197e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228597120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.3228597120 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.4204325041 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 805652012 ps |
| CPU time | 282.54 seconds |
| Started | Jul 06 08:09:55 PM PDT 24 |
| Finished | Jul 06 08:14:38 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-a7cb6459-c8b4-4c3b-8102-028208f65285 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204325041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.4204325041 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.4035928901 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3830855050 ps |
| CPU time | 431.37 seconds |
| Started | Jul 06 07:28:11 PM PDT 24 |
| Finished | Jul 06 07:35:23 PM PDT 24 |
| Peak memory | 648596 kb |
| Host | smart-af54fe0c-3b0e-41de-babd-a1ff502134c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035928901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.4035928901 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.3829586337 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4257929160 ps |
| CPU time | 737.53 seconds |
| Started | Jul 06 07:30:39 PM PDT 24 |
| Finished | Jul 06 07:42:58 PM PDT 24 |
| Peak memory | 649376 kb |
| Host | smart-135b1c01-6b47-4a7e-aff9-35bbf049c1ae |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3829586337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.3829586337 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3211925134 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 3581432784 ps |
| CPU time | 444.75 seconds |
| Started | Jul 06 07:39:04 PM PDT 24 |
| Finished | Jul 06 07:46:29 PM PDT 24 |
| Peak memory | 648556 kb |
| Host | smart-bbd56fe3-cc33-4ec0-9a61-2a3dcc5b94d1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211925134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.3211925134 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.2834571767 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 4920098024 ps |
| CPU time | 613.98 seconds |
| Started | Jul 06 07:57:50 PM PDT 24 |
| Finished | Jul 06 08:08:04 PM PDT 24 |
| Peak memory | 650404 kb |
| Host | smart-99e5df35-c937-473c-bd94-3fbca83c37eb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2834571767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.2834571767 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.3808456782 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 5882882520 ps |
| CPU time | 727.05 seconds |
| Started | Jul 06 07:58:47 PM PDT 24 |
| Finished | Jul 06 08:10:54 PM PDT 24 |
| Peak memory | 650244 kb |
| Host | smart-b7bc46e2-36e0-4f39-a151-5c8a38c4b9c4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3808456782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.3808456782 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2964200002 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 3681450054 ps |
| CPU time | 359.61 seconds |
| Started | Jul 06 07:56:59 PM PDT 24 |
| Finished | Jul 06 08:02:59 PM PDT 24 |
| Peak memory | 648696 kb |
| Host | smart-81681832-4fdd-4c85-a638-ecb52fc6052d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964200002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2964200002 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.3522365128 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 6065698996 ps |
| CPU time | 739.23 seconds |
| Started | Jul 06 07:57:04 PM PDT 24 |
| Finished | Jul 06 08:09:23 PM PDT 24 |
| Peak memory | 649984 kb |
| Host | smart-7127abf4-926d-46ae-8be1-dafd8f33804c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3522365128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.3522365128 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1729371288 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 3977201572 ps |
| CPU time | 410.12 seconds |
| Started | Jul 06 07:59:31 PM PDT 24 |
| Finished | Jul 06 08:06:21 PM PDT 24 |
| Peak memory | 648800 kb |
| Host | smart-e2eba78b-6eb1-4918-aa75-7e5239f71b60 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729371288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1729371288 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.2984870656 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 5106509330 ps |
| CPU time | 586.91 seconds |
| Started | Jul 06 07:57:13 PM PDT 24 |
| Finished | Jul 06 08:07:00 PM PDT 24 |
| Peak memory | 650120 kb |
| Host | smart-1b0c943b-5bc0-453a-baa2-12c4ca39ac44 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2984870656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.2984870656 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2457733687 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 3298445810 ps |
| CPU time | 351.61 seconds |
| Started | Jul 06 07:58:00 PM PDT 24 |
| Finished | Jul 06 08:03:52 PM PDT 24 |
| Peak memory | 648992 kb |
| Host | smart-c9e77919-7c8d-4aee-bb48-80335182cae5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457733687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2457733687 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.269983693 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 6180960000 ps |
| CPU time | 599.75 seconds |
| Started | Jul 06 07:56:27 PM PDT 24 |
| Finished | Jul 06 08:06:27 PM PDT 24 |
| Peak memory | 649888 kb |
| Host | smart-ca5cfbde-e178-4a31-82f5-fda71af297ad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 269983693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.269983693 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.4019627436 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 6619932660 ps |
| CPU time | 810.74 seconds |
| Started | Jul 06 07:57:23 PM PDT 24 |
| Finished | Jul 06 08:10:54 PM PDT 24 |
| Peak memory | 649884 kb |
| Host | smart-321cec9b-0a96-4ee3-8fcc-987625957b01 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4019627436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.4019627436 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.4210448296 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 3314064482 ps |
| CPU time | 399.87 seconds |
| Started | Jul 06 08:00:04 PM PDT 24 |
| Finished | Jul 06 08:06:44 PM PDT 24 |
| Peak memory | 648852 kb |
| Host | smart-256e387b-3363-42c5-92d4-65d4cc97bf3c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210448296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4210448296 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.2225968760 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 5636294486 ps |
| CPU time | 715.35 seconds |
| Started | Jul 06 07:57:53 PM PDT 24 |
| Finished | Jul 06 08:09:48 PM PDT 24 |
| Peak memory | 649820 kb |
| Host | smart-483fe046-0fd1-43eb-a2b5-f04645b8d93d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2225968760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.2225968760 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2858320910 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3766139734 ps |
| CPU time | 519.48 seconds |
| Started | Jul 06 07:58:34 PM PDT 24 |
| Finished | Jul 06 08:07:14 PM PDT 24 |
| Peak memory | 649068 kb |
| Host | smart-d6cc9c36-c220-442f-89ed-acbd840b197b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858320910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2858320910 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2227228092 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3698497750 ps |
| CPU time | 382.87 seconds |
| Started | Jul 06 08:05:16 PM PDT 24 |
| Finished | Jul 06 08:11:39 PM PDT 24 |
| Peak memory | 648772 kb |
| Host | smart-05a802b6-54ed-4475-95a8-4d48f21b9af4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227228092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2227228092 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1875857458 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 3398063732 ps |
| CPU time | 324.04 seconds |
| Started | Jul 06 07:59:02 PM PDT 24 |
| Finished | Jul 06 08:04:27 PM PDT 24 |
| Peak memory | 648588 kb |
| Host | smart-84279531-053c-434f-abd2-6699b4796ddd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875857458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1875857458 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.2572484357 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 5224928800 ps |
| CPU time | 759.4 seconds |
| Started | Jul 06 07:59:10 PM PDT 24 |
| Finished | Jul 06 08:11:50 PM PDT 24 |
| Peak memory | 650176 kb |
| Host | smart-5eef38ce-7f54-48b6-9f53-403f0d915fa6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2572484357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.2572484357 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.2216166119 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 5866386032 ps |
| CPU time | 839.45 seconds |
| Started | Jul 06 07:45:19 PM PDT 24 |
| Finished | Jul 06 07:59:19 PM PDT 24 |
| Peak memory | 649756 kb |
| Host | smart-df8a7275-dffb-4029-bd10-2ee894001d86 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2216166119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.2216166119 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1353482007 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 4120182692 ps |
| CPU time | 358.57 seconds |
| Started | Jul 06 08:06:24 PM PDT 24 |
| Finished | Jul 06 08:12:22 PM PDT 24 |
| Peak memory | 648648 kb |
| Host | smart-f38f086a-1062-4746-854c-d6b621e953d8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353482007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1353482007 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.1916763324 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 4963936400 ps |
| CPU time | 550.77 seconds |
| Started | Jul 06 08:06:04 PM PDT 24 |
| Finished | Jul 06 08:15:15 PM PDT 24 |
| Peak memory | 649792 kb |
| Host | smart-6eb6158a-943a-4565-9072-7e7e11f112f4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1916763324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.1916763324 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.3371615891 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 5651616160 ps |
| CPU time | 624.45 seconds |
| Started | Jul 06 07:58:39 PM PDT 24 |
| Finished | Jul 06 08:09:04 PM PDT 24 |
| Peak memory | 650212 kb |
| Host | smart-11d0c136-3b1f-4021-bbc7-97c20cc404f1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3371615891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.3371615891 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.3314432492 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 5271479708 ps |
| CPU time | 595.39 seconds |
| Started | Jul 06 07:58:19 PM PDT 24 |
| Finished | Jul 06 08:08:15 PM PDT 24 |
| Peak memory | 650056 kb |
| Host | smart-435606ee-453d-45bf-8504-917fd5a7b157 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3314432492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.3314432492 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.543793114 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 5427231160 ps |
| CPU time | 633.2 seconds |
| Started | Jul 06 07:58:03 PM PDT 24 |
| Finished | Jul 06 08:08:37 PM PDT 24 |
| Peak memory | 650344 kb |
| Host | smart-726ebf46-d83c-4092-b337-cec736cdb145 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 543793114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.543793114 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3288593559 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 3612113512 ps |
| CPU time | 346.82 seconds |
| Started | Jul 06 07:58:23 PM PDT 24 |
| Finished | Jul 06 08:04:11 PM PDT 24 |
| Peak memory | 649136 kb |
| Host | smart-e5a9201e-debc-4751-99c0-997c251f570a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288593559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3288593559 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.1169909351 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 5750967406 ps |
| CPU time | 841.82 seconds |
| Started | Jul 06 07:59:44 PM PDT 24 |
| Finished | Jul 06 08:13:47 PM PDT 24 |
| Peak memory | 650292 kb |
| Host | smart-798b425d-7ce0-4ee8-8932-6abd3bbc34b3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1169909351 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.1169909351 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.2193547558 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 5082763452 ps |
| CPU time | 894.77 seconds |
| Started | Jul 06 08:00:34 PM PDT 24 |
| Finished | Jul 06 08:15:30 PM PDT 24 |
| Peak memory | 650156 kb |
| Host | smart-1fc02dff-2257-4883-8a82-1e25991db99b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2193547558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.2193547558 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.822360463 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 6248080806 ps |
| CPU time | 752.53 seconds |
| Started | Jul 06 07:59:55 PM PDT 24 |
| Finished | Jul 06 08:12:28 PM PDT 24 |
| Peak memory | 650028 kb |
| Host | smart-9ab870e5-ab05-4eef-a817-d418a7b21dc6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 822360463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.822360463 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1538977 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 3420727294 ps |
| CPU time | 303.48 seconds |
| Started | Jul 06 07:54:22 PM PDT 24 |
| Finished | Jul 06 07:59:26 PM PDT 24 |
| Peak memory | 649048 kb |
| Host | smart-0e6b0106-0027-4394-9672-9ebfffd92788 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_e scalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_a lert_handler_lpg_sleep_mode_alerts.1538977 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.221119659 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 4008399152 ps |
| CPU time | 361.34 seconds |
| Started | Jul 06 07:59:01 PM PDT 24 |
| Finished | Jul 06 08:05:03 PM PDT 24 |
| Peak memory | 648712 kb |
| Host | smart-5645e4e3-6c88-4e69-a486-1b8810b83b44 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221119659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_s w_alert_handler_lpg_sleep_mode_alerts.221119659 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3632698624 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 4049964476 ps |
| CPU time | 323.67 seconds |
| Started | Jul 06 07:59:48 PM PDT 24 |
| Finished | Jul 06 08:05:12 PM PDT 24 |
| Peak memory | 648956 kb |
| Host | smart-35f8a364-a0eb-4cf7-a38b-6c325d14cee6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632698624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3632698624 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3568502894 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3288152552 ps |
| CPU time | 444.79 seconds |
| Started | Jul 06 07:58:52 PM PDT 24 |
| Finished | Jul 06 08:06:17 PM PDT 24 |
| Peak memory | 648696 kb |
| Host | smart-0e07f4c6-6cc1-4de5-ab32-e1ab781b70f3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568502894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3568502894 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.581471226 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 6445332000 ps |
| CPU time | 937.82 seconds |
| Started | Jul 06 07:58:59 PM PDT 24 |
| Finished | Jul 06 08:14:38 PM PDT 24 |
| Peak memory | 650092 kb |
| Host | smart-51a2483d-a324-4cef-a286-a4f0f2851e3e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 581471226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.581471226 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.754000261 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3924449440 ps |
| CPU time | 358.65 seconds |
| Started | Jul 06 07:59:42 PM PDT 24 |
| Finished | Jul 06 08:05:41 PM PDT 24 |
| Peak memory | 649424 kb |
| Host | smart-be2a5a94-78f4-4755-bebb-2f4651918726 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754000261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_s w_alert_handler_lpg_sleep_mode_alerts.754000261 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.1059741477 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 4857847960 ps |
| CPU time | 784.11 seconds |
| Started | Jul 06 07:58:41 PM PDT 24 |
| Finished | Jul 06 08:11:46 PM PDT 24 |
| Peak memory | 650292 kb |
| Host | smart-87495f06-7188-4cc5-bcd2-ad2d23585628 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1059741477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.1059741477 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.3127694140 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 5859426500 ps |
| CPU time | 654.85 seconds |
| Started | Jul 06 07:59:43 PM PDT 24 |
| Finished | Jul 06 08:10:39 PM PDT 24 |
| Peak memory | 649792 kb |
| Host | smart-ebd1ae9d-8606-49a7-a83b-abef5e8a3a48 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3127694140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.3127694140 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3739899374 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 4559224932 ps |
| CPU time | 455.1 seconds |
| Started | Jul 06 08:00:56 PM PDT 24 |
| Finished | Jul 06 08:08:32 PM PDT 24 |
| Peak memory | 648940 kb |
| Host | smart-6de657a4-9812-4fbc-8583-5bdb071a4372 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739899374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3739899374 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.1057117082 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 6231508056 ps |
| CPU time | 741.78 seconds |
| Started | Jul 06 08:00:28 PM PDT 24 |
| Finished | Jul 06 08:12:50 PM PDT 24 |
| Peak memory | 650084 kb |
| Host | smart-952e90de-5b9b-4bd6-8239-01069aacab67 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1057117082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.1057117082 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.3076102582 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4697006184 ps |
| CPU time | 679.98 seconds |
| Started | Jul 06 07:59:59 PM PDT 24 |
| Finished | Jul 06 08:11:20 PM PDT 24 |
| Peak memory | 650048 kb |
| Host | smart-bdc9df94-56b4-4571-8b48-59e6f1ec0b2c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3076102582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.3076102582 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3838416115 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 3999833808 ps |
| CPU time | 369.82 seconds |
| Started | Jul 06 07:59:21 PM PDT 24 |
| Finished | Jul 06 08:05:31 PM PDT 24 |
| Peak memory | 648972 kb |
| Host | smart-19dd1220-7d77-4ea5-b27e-6576bbf27e99 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838416115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3838416115 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.1694231376 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 5294203888 ps |
| CPU time | 715.89 seconds |
| Started | Jul 06 07:59:44 PM PDT 24 |
| Finished | Jul 06 08:11:40 PM PDT 24 |
| Peak memory | 649888 kb |
| Host | smart-5f301f6e-c42f-40d2-a353-75eb69d34c45 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1694231376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.1694231376 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.679304149 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 4399829896 ps |
| CPU time | 716.56 seconds |
| Started | Jul 06 07:59:26 PM PDT 24 |
| Finished | Jul 06 08:11:23 PM PDT 24 |
| Peak memory | 650144 kb |
| Host | smart-fb4ed8bc-dcfc-46e3-892c-6e0661c10d45 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 679304149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.679304149 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3976500045 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 3753460510 ps |
| CPU time | 398.77 seconds |
| Started | Jul 06 07:55:52 PM PDT 24 |
| Finished | Jul 06 08:02:31 PM PDT 24 |
| Peak memory | 648716 kb |
| Host | smart-fcd1a027-7b23-470f-84db-247ab5d17443 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976500045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.3976500045 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.953992498 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 5738328260 ps |
| CPU time | 544.02 seconds |
| Started | Jul 06 07:56:08 PM PDT 24 |
| Finished | Jul 06 08:05:13 PM PDT 24 |
| Peak memory | 650320 kb |
| Host | smart-a0eb327d-5b42-4707-af6c-8826df45af2d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 953992498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.953992498 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2979985377 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 3352771960 ps |
| CPU time | 511.02 seconds |
| Started | Jul 06 08:00:04 PM PDT 24 |
| Finished | Jul 06 08:08:36 PM PDT 24 |
| Peak memory | 648888 kb |
| Host | smart-c4c75861-6176-4771-9f26-868aff4ee4ed |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979985377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2979985377 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.1993104788 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 5043912960 ps |
| CPU time | 990.32 seconds |
| Started | Jul 06 08:00:00 PM PDT 24 |
| Finished | Jul 06 08:16:30 PM PDT 24 |
| Peak memory | 649868 kb |
| Host | smart-911d6164-9a19-450b-96be-0b9ed215b589 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1993104788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.1993104788 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.555662476 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3436708168 ps |
| CPU time | 337.01 seconds |
| Started | Jul 06 07:59:43 PM PDT 24 |
| Finished | Jul 06 08:05:21 PM PDT 24 |
| Peak memory | 649148 kb |
| Host | smart-596963b8-b945-4670-b974-3709be6b4b45 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555662476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_s w_alert_handler_lpg_sleep_mode_alerts.555662476 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.2010863167 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 5020469676 ps |
| CPU time | 604.34 seconds |
| Started | Jul 06 08:01:25 PM PDT 24 |
| Finished | Jul 06 08:11:30 PM PDT 24 |
| Peak memory | 649984 kb |
| Host | smart-06145ec1-1b9a-4873-ba85-83e725c75a94 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2010863167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.2010863167 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.2414429997 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 5630019724 ps |
| CPU time | 791.82 seconds |
| Started | Jul 06 08:00:25 PM PDT 24 |
| Finished | Jul 06 08:13:37 PM PDT 24 |
| Peak memory | 650200 kb |
| Host | smart-ab899320-6746-48e6-a5c8-343a45db351c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2414429997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.2414429997 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2248458934 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 3969238930 ps |
| CPU time | 431.72 seconds |
| Started | Jul 06 08:01:52 PM PDT 24 |
| Finished | Jul 06 08:09:04 PM PDT 24 |
| Peak memory | 648856 kb |
| Host | smart-8c626847-e9cb-4641-b1b1-1337de211571 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248458934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2248458934 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3177129804 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 4073014840 ps |
| CPU time | 350.52 seconds |
| Started | Jul 06 08:01:14 PM PDT 24 |
| Finished | Jul 06 08:07:07 PM PDT 24 |
| Peak memory | 648908 kb |
| Host | smart-7e497d7f-885c-4e72-924b-d98d119bcd10 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177129804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3177129804 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.131263120 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 6226666040 ps |
| CPU time | 576.72 seconds |
| Started | Jul 06 08:01:27 PM PDT 24 |
| Finished | Jul 06 08:11:04 PM PDT 24 |
| Peak memory | 649964 kb |
| Host | smart-cd3d9e5b-2378-4e3f-b6d9-01de9665a191 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 131263120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.131263120 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.631434760 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 4166290304 ps |
| CPU time | 351.06 seconds |
| Started | Jul 06 07:56:38 PM PDT 24 |
| Finished | Jul 06 08:02:29 PM PDT 24 |
| Peak memory | 648940 kb |
| Host | smart-848f3e2d-174d-479e-835c-3b7af0688f81 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631434760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw _alert_handler_lpg_sleep_mode_alerts.631434760 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2920011996 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 3102710552 ps |
| CPU time | 336.78 seconds |
| Started | Jul 06 08:02:30 PM PDT 24 |
| Finished | Jul 06 08:08:07 PM PDT 24 |
| Peak memory | 648588 kb |
| Host | smart-a115446e-63d1-4dfc-87b0-6b04572a6bbe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920011996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2920011996 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.640781339 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 5256326710 ps |
| CPU time | 512.07 seconds |
| Started | Jul 06 08:02:39 PM PDT 24 |
| Finished | Jul 06 08:11:11 PM PDT 24 |
| Peak memory | 650036 kb |
| Host | smart-518327ba-8dfa-4380-ae3c-8d48267c525f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 640781339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.640781339 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3144509412 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 4190304984 ps |
| CPU time | 497.48 seconds |
| Started | Jul 06 08:01:44 PM PDT 24 |
| Finished | Jul 06 08:10:02 PM PDT 24 |
| Peak memory | 648864 kb |
| Host | smart-57799b4b-4c8c-4114-9cad-fbcc28c6a00b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144509412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3144509412 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3553491408 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 3841377034 ps |
| CPU time | 469.48 seconds |
| Started | Jul 06 08:02:08 PM PDT 24 |
| Finished | Jul 06 08:09:58 PM PDT 24 |
| Peak memory | 648652 kb |
| Host | smart-80b0b319-2940-4829-80ba-13f201742e72 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553491408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3553491408 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3109556885 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3903013684 ps |
| CPU time | 432.3 seconds |
| Started | Jul 06 07:56:44 PM PDT 24 |
| Finished | Jul 06 08:03:57 PM PDT 24 |
| Peak memory | 648860 kb |
| Host | smart-b67dac6d-6f01-4e12-a7fc-2516ba4c4d7b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109556885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.3109556885 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.576407577 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 5475228648 ps |
| CPU time | 776.05 seconds |
| Started | Jul 06 08:01:36 PM PDT 24 |
| Finished | Jul 06 08:14:33 PM PDT 24 |
| Peak memory | 649784 kb |
| Host | smart-e8a74dbb-d0fd-4bce-8af1-f4625b160315 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 576407577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.576407577 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.507981129 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 4103309366 ps |
| CPU time | 635.1 seconds |
| Started | Jul 06 08:02:12 PM PDT 24 |
| Finished | Jul 06 08:12:48 PM PDT 24 |
| Peak memory | 649768 kb |
| Host | smart-0a0de9ba-7037-46e9-a368-b7a597979d4f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 507981129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.507981129 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.645281964 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 4198147150 ps |
| CPU time | 454.58 seconds |
| Started | Jul 06 08:03:42 PM PDT 24 |
| Finished | Jul 06 08:11:17 PM PDT 24 |
| Peak memory | 648604 kb |
| Host | smart-2d7a1fe6-ae62-4499-a1b3-d18a2f6d3a49 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645281964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_s w_alert_handler_lpg_sleep_mode_alerts.645281964 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.771183468 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 4753906690 ps |
| CPU time | 596.68 seconds |
| Started | Jul 06 08:04:43 PM PDT 24 |
| Finished | Jul 06 08:14:40 PM PDT 24 |
| Peak memory | 650108 kb |
| Host | smart-2697eefc-090f-4da9-a337-b28562743187 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 771183468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.771183468 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3990234485 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 3441740456 ps |
| CPU time | 397.84 seconds |
| Started | Jul 06 08:03:30 PM PDT 24 |
| Finished | Jul 06 08:10:09 PM PDT 24 |
| Peak memory | 648896 kb |
| Host | smart-46a519f1-d683-49bb-8bf0-a06f22ef66de |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990234485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3990234485 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.2546884638 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 4468493844 ps |
| CPU time | 530.34 seconds |
| Started | Jul 06 08:03:02 PM PDT 24 |
| Finished | Jul 06 08:11:53 PM PDT 24 |
| Peak memory | 650028 kb |
| Host | smart-474f23d9-f592-4ba5-8957-bba3292f514f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2546884638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.2546884638 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.3410703521 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 4137919200 ps |
| CPU time | 767.95 seconds |
| Started | Jul 06 08:05:15 PM PDT 24 |
| Finished | Jul 06 08:18:04 PM PDT 24 |
| Peak memory | 649684 kb |
| Host | smart-dc1e1b1e-a0ce-4a39-a112-d33c8ba4b4cb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3410703521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.3410703521 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1661303930 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 3328442928 ps |
| CPU time | 366.35 seconds |
| Started | Jul 06 08:04:35 PM PDT 24 |
| Finished | Jul 06 08:10:42 PM PDT 24 |
| Peak memory | 648796 kb |
| Host | smart-1dec273d-37fc-424c-9f5e-dc48cca15262 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661303930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1661303930 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.3337692888 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 5365381240 ps |
| CPU time | 656.64 seconds |
| Started | Jul 06 08:03:52 PM PDT 24 |
| Finished | Jul 06 08:14:49 PM PDT 24 |
| Peak memory | 650020 kb |
| Host | smart-8d923db9-1797-45eb-8a12-cc357a4070d7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3337692888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.3337692888 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2442429574 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3890068880 ps |
| CPU time | 463.35 seconds |
| Started | Jul 06 08:04:00 PM PDT 24 |
| Finished | Jul 06 08:11:43 PM PDT 24 |
| Peak memory | 648932 kb |
| Host | smart-97058a9b-a39e-4113-8eba-3f6f1ce29ff2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442429574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2442429574 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.281438851 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 5337000516 ps |
| CPU time | 482.78 seconds |
| Started | Jul 06 08:05:06 PM PDT 24 |
| Finished | Jul 06 08:13:09 PM PDT 24 |
| Peak memory | 650132 kb |
| Host | smart-74553ddc-a4b5-45ca-9679-90d8022af99e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 281438851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.281438851 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3497003088 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3470523475 ps |
| CPU time | 394.57 seconds |
| Started | Jul 06 07:29:25 PM PDT 24 |
| Finished | Jul 06 07:36:00 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-846a870f-dadb-4989-a7db-14d5618e6498 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497003088 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.3497003088 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3030324453 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 20571900891 ps |
| CPU time | 2059.45 seconds |
| Started | Jul 06 07:41:56 PM PDT 24 |
| Finished | Jul 06 08:16:16 PM PDT 24 |
| Peak memory | 611988 kb |
| Host | smart-52d1a2a4-bbe9-41a8-a639-5ab86df6770d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3030324453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.3030324453 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.4293288877 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 30372572311 ps |
| CPU time | 2940.23 seconds |
| Started | Jul 06 07:59:46 PM PDT 24 |
| Finished | Jul 06 08:48:47 PM PDT 24 |
| Peak memory | 593220 kb |
| Host | smart-59aa8e52-7e7c-4eb3-9206-b19010afbe33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293288877 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.4293288877 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.1020349422 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 4439764543 ps |
| CPU time | 411.99 seconds |
| Started | Jul 06 08:22:22 PM PDT 24 |
| Finished | Jul 06 08:29:14 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-d0c516e8-a371-43bf-94b0-e81f942c8a46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020349422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.1020349422 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2607325852 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 7511976896 ps |
| CPU time | 2081.21 seconds |
| Started | Jul 06 07:33:30 PM PDT 24 |
| Finished | Jul 06 08:08:12 PM PDT 24 |
| Peak memory | 609492 kb |
| Host | smart-1cc0621f-8619-4d93-9afe-53c18a40b1eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2607325852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2607325852 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1367705315 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4311087270 ps |
| CPU time | 400.25 seconds |
| Started | Jul 06 07:33:53 PM PDT 24 |
| Finished | Jul 06 07:40:34 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-8c6762c3-b253-4c80-9ac5-c548483f2887 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367705315 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.1367705315 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.187087127 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 5879823660 ps |
| CPU time | 636.72 seconds |
| Started | Jul 06 07:32:37 PM PDT 24 |
| Finished | Jul 06 07:43:14 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-275cccd9-d59a-4e94-b9ac-8a6b33b2c669 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=187087127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_sl eep_wake_up.187087127 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.869345605 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 5830672018 ps |
| CPU time | 609.85 seconds |
| Started | Jul 06 07:32:15 PM PDT 24 |
| Finished | Jul 06 07:42:26 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-55e49e2d-18e0-45cd-ae82-2aa49659bce8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 869345605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.869345605 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1954899680 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 5315539340 ps |
| CPU time | 760.52 seconds |
| Started | Jul 06 07:28:56 PM PDT 24 |
| Finished | Jul 06 07:41:38 PM PDT 24 |
| Peak memory | 608936 kb |
| Host | smart-d596ddbb-21ba-4523-91f6-c811986b88a3 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954899680 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.1954899680 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2561732275 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 9082436024 ps |
| CPU time | 579.4 seconds |
| Started | Jul 06 07:28:24 PM PDT 24 |
| Finished | Jul 06 07:38:04 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-4efdabe8-2ca9-4e51-bd99-b4c4bbd11657 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561732275 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.2561732275 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2784938260 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 192817354896 ps |
| CPU time | 26054 seconds |
| Started | Jul 06 07:42:57 PM PDT 24 |
| Finished | Jul 07 02:57:14 AM PDT 24 |
| Peak memory | 609572 kb |
| Host | smart-fea7d211-156c-4ed1-bce6-7684f2c7575f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2784938260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.2784938260 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2343415539 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 4478684730 ps |
| CPU time | 498.75 seconds |
| Started | Jul 06 07:29:23 PM PDT 24 |
| Finished | Jul 06 07:37:42 PM PDT 24 |
| Peak memory | 623684 kb |
| Host | smart-f9f23d50-1835-4b04-ad07-149ce6dff018 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343415539 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.2343415539 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.1125196898 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 14311147044 ps |
| CPU time | 1753.58 seconds |
| Started | Jul 06 07:52:28 PM PDT 24 |
| Finished | Jul 06 08:21:42 PM PDT 24 |
| Peak memory | 620948 kb |
| Host | smart-8320d7e5-ae79-4fd7-8522-b0ea27b8db50 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1125196898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.1125196898 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.4198004194 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 359147354 ps |
| CPU time | 19.01 seconds |
| Started | Jul 06 08:06:34 PM PDT 24 |
| Finished | Jul 06 08:06:54 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-af30bed4-4202-492b-a6e8-66efc0099041 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198004194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.4198004194 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.3883556137 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 2991969239 ps |
| CPU time | 309.75 seconds |
| Started | Jul 06 08:01:22 PM PDT 24 |
| Finished | Jul 06 08:06:32 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-79a0b298-19ac-4591-a2ac-0ac98ab3fbca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883556137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3883556137 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1431969866 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 3885481952 ps |
| CPU time | 783.08 seconds |
| Started | Jul 06 07:31:56 PM PDT 24 |
| Finished | Jul 06 07:45:00 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-f53cec85-c90f-4b64-ae30-4413f8295385 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431969866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.1431969866 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.3267519392 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 3535593752 ps |
| CPU time | 621.04 seconds |
| Started | Jul 06 07:34:03 PM PDT 24 |
| Finished | Jul 06 07:44:25 PM PDT 24 |
| Peak memory | 609044 kb |
| Host | smart-162a8cc7-6698-4812-9165-3a323f6810c4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267519392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.3267519392 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3360324311 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1790146598 ps |
| CPU time | 108.95 seconds |
| Started | Jul 06 07:46:52 PM PDT 24 |
| Finished | Jul 06 07:48:42 PM PDT 24 |
| Peak memory | 618560 kb |
| Host | smart-7977016f-225b-4ed5-b058-da6a6069375d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360324311 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.3360324311 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.1597138297 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 2828183230 ps |
| CPU time | 223.96 seconds |
| Started | Jul 06 07:48:45 PM PDT 24 |
| Finished | Jul 06 07:52:30 PM PDT 24 |
| Peak memory | 611936 kb |
| Host | smart-3492473b-de86-4d34-93f0-7de2382453fe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597138297 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.1597138297 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1461657850 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 8225442240 ps |
| CPU time | 2201.25 seconds |
| Started | Jul 06 07:30:45 PM PDT 24 |
| Finished | Jul 06 08:07:27 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-0ff23bb3-a8b4-44ee-b359-d9be03b87bc4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1461657850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.1461657850 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3205794372 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 60051947580 ps |
| CPU time | 10434.6 seconds |
| Started | Jul 06 07:29:53 PM PDT 24 |
| Finished | Jul 06 10:23:49 PM PDT 24 |
| Peak memory | 623764 kb |
| Host | smart-1986ce69-48d8-45c5-beab-919a433d012f |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3205794372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.3205794372 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3620392308 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 4558206026 ps |
| CPU time | 372.91 seconds |
| Started | Jul 06 07:36:24 PM PDT 24 |
| Finished | Jul 06 07:42:37 PM PDT 24 |
| Peak memory | 609616 kb |
| Host | smart-c944602c-73d0-47b5-befb-24e782beb811 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3620392308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.3620392308 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3175472223 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 5617899972 ps |
| CPU time | 472.89 seconds |
| Started | Jul 06 07:29:59 PM PDT 24 |
| Finished | Jul 06 07:37:53 PM PDT 24 |
| Peak memory | 616944 kb |
| Host | smart-5a5e456c-edb2-4e7a-a0cd-87fbf88dbc9a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3175472223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3175472223 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2779614502 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 9949687318 ps |
| CPU time | 995.04 seconds |
| Started | Jul 06 07:31:53 PM PDT 24 |
| Finished | Jul 06 07:48:29 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-77b4824a-4b29-4e71-9397-a439c8675fc7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779614502 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.2779614502 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.1461126736 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 8004562629 ps |
| CPU time | 320.85 seconds |
| Started | Jul 06 08:01:20 PM PDT 24 |
| Finished | Jul 06 08:06:42 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-c7b89f91-8891-470c-9dc7-679a5b61c7fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461126736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1461126736 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.1813648372 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 3217579347 ps |
| CPU time | 134.33 seconds |
| Started | Jul 06 08:10:16 PM PDT 24 |
| Finished | Jul 06 08:12:31 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-6f97f736-3e6a-4502-b077-a1ad4febe398 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813648372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1813648372 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.3515596547 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 3293214509 ps |
| CPU time | 274.07 seconds |
| Started | Jul 06 08:10:25 PM PDT 24 |
| Finished | Jul 06 08:14:59 PM PDT 24 |
| Peak memory | 603544 kb |
| Host | smart-27562a06-0674-42a9-b9fe-3c386f830580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515596547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.3515596547 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.2714001945 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 4323978054 ps |
| CPU time | 397.63 seconds |
| Started | Jul 06 08:11:12 PM PDT 24 |
| Finished | Jul 06 08:17:50 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-f8928810-d518-4ea7-81f7-29a7f15b1cbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714001945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2714001945 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.704643559 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 3844015018 ps |
| CPU time | 404.06 seconds |
| Started | Jul 06 08:15:54 PM PDT 24 |
| Finished | Jul 06 08:22:38 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-c70421a5-de56-4b7a-a9af-f5dd903ac522 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704643559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_reset_error.704643559 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.2137112679 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 11677587753 ps |
| CPU time | 480.94 seconds |
| Started | Jul 06 08:18:39 PM PDT 24 |
| Finished | Jul 06 08:26:41 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-22234b28-ff44-41db-8114-42e6b7264238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137112679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.2137112679 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.2535413449 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 7712332070 ps |
| CPU time | 280.21 seconds |
| Started | Jul 06 08:20:03 PM PDT 24 |
| Finished | Jul 06 08:24:44 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-c11cfbd3-7dbe-49af-befb-15b6e3041356 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535413449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.2535413449 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.3845881953 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 5216188942 ps |
| CPU time | 291.97 seconds |
| Started | Jul 06 08:22:15 PM PDT 24 |
| Finished | Jul 06 08:27:08 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-98c98238-e007-43d9-9e85-fd5f5e23f07f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845881953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.3845881953 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.1206805027 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 10651363799 ps |
| CPU time | 417.29 seconds |
| Started | Jul 06 08:05:47 PM PDT 24 |
| Finished | Jul 06 08:12:45 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-788d3978-8d28-4da5-9274-f7d4a773186b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206805027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1206805027 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.2740169354 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4367160440 ps |
| CPU time | 395.51 seconds |
| Started | Jul 06 07:32:39 PM PDT 24 |
| Finished | Jul 06 07:39:15 PM PDT 24 |
| Peak memory | 608760 kb |
| Host | smart-3ac2517d-2e06-43cc-a4eb-06939c94e72b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740169354 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.2740169354 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.3963929358 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 3411407838 ps |
| CPU time | 274.53 seconds |
| Started | Jul 06 07:30:22 PM PDT 24 |
| Finished | Jul 06 07:34:57 PM PDT 24 |
| Peak memory | 608780 kb |
| Host | smart-8034bd63-a826-4561-9a62-13383ba72c7f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963929358 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.3963929358 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3324879512 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 4808929200 ps |
| CPU time | 894.44 seconds |
| Started | Jul 06 07:29:21 PM PDT 24 |
| Finished | Jul 06 07:44:17 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-12ea169d-07be-4f7f-8c6c-4a27ccd5d650 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33248 79512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.3324879512 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2846694075 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 3895406456 ps |
| CPU time | 621.67 seconds |
| Started | Jul 06 07:38:57 PM PDT 24 |
| Finished | Jul 06 07:49:19 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-80602ef6-b1b6-4b32-ad64-2493f1b6ddca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846694075 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.2846694075 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1873270049 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 5059681384 ps |
| CPU time | 241 seconds |
| Started | Jul 06 08:00:29 PM PDT 24 |
| Finished | Jul 06 08:04:31 PM PDT 24 |
| Peak memory | 663328 kb |
| Host | smart-f3501233-f40a-40ee-96a8-be112cd14228 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873270049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.1873270049 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1077294036 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 4599074812 ps |
| CPU time | 229.65 seconds |
| Started | Jul 06 08:01:29 PM PDT 24 |
| Finished | Jul 06 08:05:19 PM PDT 24 |
| Peak memory | 663056 kb |
| Host | smart-f2083395-4c0d-4c87-a425-4463757f127b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077294036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.1077294036 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.602730997 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 9331351928 ps |
| CPU time | 1656.8 seconds |
| Started | Jul 06 07:31:35 PM PDT 24 |
| Finished | Jul 06 07:59:12 PM PDT 24 |
| Peak memory | 611000 kb |
| Host | smart-122d90d2-1cdb-4a3b-88ff-6a0fb2643ad7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602730 997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.602730997 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.632853321 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 17338746672 ps |
| CPU time | 4056.83 seconds |
| Started | Jul 06 07:29:10 PM PDT 24 |
| Finished | Jul 06 08:36:48 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-de70ea7a-7745-42eb-b8e6-cdb8352ec87f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=632853321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.632853321 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.659288536 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 27217858635 ps |
| CPU time | 2223.31 seconds |
| Started | Jul 06 07:34:50 PM PDT 24 |
| Finished | Jul 06 08:11:54 PM PDT 24 |
| Peak memory | 611108 kb |
| Host | smart-6f835574-1b13-432c-8029-e71c0cd3339f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=659288536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.659288536 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3556446853 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 19902636304 ps |
| CPU time | 873.33 seconds |
| Started | Jul 06 07:58:39 PM PDT 24 |
| Finished | Jul 06 08:13:13 PM PDT 24 |
| Peak memory | 590960 kb |
| Host | smart-5a031783-eae9-4408-945c-0b74ccf1d6bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556446853 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.3556446853 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.640868823 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 2255792930 ps |
| CPU time | 179.32 seconds |
| Started | Jul 06 07:35:48 PM PDT 24 |
| Finished | Jul 06 07:38:48 PM PDT 24 |
| Peak memory | 646348 kb |
| Host | smart-00457dd4-b0cc-4fca-ae6d-04027f3eb27f |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640868823 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.640868823 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.339692350 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 24334899112 ps |
| CPU time | 6222.68 seconds |
| Started | Jul 06 07:38:15 PM PDT 24 |
| Finished | Jul 06 09:21:59 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-aa458a05-b62d-4363-bbaf-919592d6f47b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=339692350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.339692350 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3313930146 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 26190547736 ps |
| CPU time | 3960.93 seconds |
| Started | Jul 06 07:58:28 PM PDT 24 |
| Finished | Jul 06 09:04:29 PM PDT 24 |
| Peak memory | 593500 kb |
| Host | smart-68799635-5044-4b90-b2e4-8eb7b0e85bc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313930146 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.chip_csr_aliasing.3313930146 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2037257988 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 31581873692 ps |
| CPU time | 2999.88 seconds |
| Started | Jul 06 07:58:23 PM PDT 24 |
| Finished | Jul 06 08:48:23 PM PDT 24 |
| Peak memory | 591248 kb |
| Host | smart-7b871218-f494-4ed0-8b35-4a2580d7c41f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037257988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.2037257988 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3300115289 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 5378756960 ps |
| CPU time | 280.86 seconds |
| Started | Jul 06 07:59:29 PM PDT 24 |
| Finished | Jul 06 08:04:10 PM PDT 24 |
| Peak memory | 663208 kb |
| Host | smart-bccf9543-d28c-4c90-9739-a99655346b39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300115289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.3300115289 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.1402986605 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 5706586968 ps |
| CPU time | 792.57 seconds |
| Started | Jul 06 07:59:33 PM PDT 24 |
| Finished | Jul 06 08:12:46 PM PDT 24 |
| Peak memory | 598252 kb |
| Host | smart-15775c69-b24d-4dd9-8b0c-e03a74151b99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402986605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.1402986605 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.351295820 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 7652871283 ps |
| CPU time | 421.99 seconds |
| Started | Jul 06 07:58:36 PM PDT 24 |
| Finished | Jul 06 08:05:38 PM PDT 24 |
| Peak memory | 589048 kb |
| Host | smart-aaca9154-a01d-4143-8957-cbf584d3419f |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351295820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0 .chip_prim_tl_access.351295820 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.213840353 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 15198433707 ps |
| CPU time | 2729.49 seconds |
| Started | Jul 06 07:58:38 PM PDT 24 |
| Finished | Jul 06 08:44:08 PM PDT 24 |
| Peak memory | 592744 kb |
| Host | smart-e4f8021b-c626-4461-8bbe-5f34709c8aeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213840353 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.chip_same_csr_outstanding.213840353 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.3164967640 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 4172825471 ps |
| CPU time | 433.94 seconds |
| Started | Jul 06 07:58:33 PM PDT 24 |
| Finished | Jul 06 08:05:47 PM PDT 24 |
| Peak memory | 597476 kb |
| Host | smart-092d2572-7868-40df-a83a-3041633c49d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164967640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.3164967640 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.326044404 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 1726331071 ps |
| CPU time | 73.49 seconds |
| Started | Jul 06 07:59:04 PM PDT 24 |
| Finished | Jul 06 08:00:18 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-5562d6a7-587e-416b-865f-44947662eb2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326044404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.326044404 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.4074598158 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 126890665935 ps |
| CPU time | 2046.28 seconds |
| Started | Jul 06 07:59:12 PM PDT 24 |
| Finished | Jul 06 08:33:19 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-60283694-faf4-482a-a14a-9b4d6c51004f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074598158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.4074598158 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1946025485 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 88600823 ps |
| CPU time | 14.88 seconds |
| Started | Jul 06 07:59:24 PM PDT 24 |
| Finished | Jul 06 07:59:39 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-bb887a91-763b-4b94-a78a-f1e2be37850f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946025485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .1946025485 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.3052095182 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 1905043156 ps |
| CPU time | 62.87 seconds |
| Started | Jul 06 07:59:07 PM PDT 24 |
| Finished | Jul 06 08:00:10 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-67a974ce-4736-4ceb-849f-19c57fc113a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052095182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3052095182 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.3775886471 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 114966588 ps |
| CPU time | 14.87 seconds |
| Started | Jul 06 07:58:52 PM PDT 24 |
| Finished | Jul 06 07:59:07 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-d38ad1b3-703e-4c79-ae1b-77ff5202f34e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775886471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.3775886471 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2987508223 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 95012373623 ps |
| CPU time | 952.26 seconds |
| Started | Jul 06 07:58:49 PM PDT 24 |
| Finished | Jul 06 08:14:42 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-d6735bcb-6b09-4d4c-992e-2089a8cd3f9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987508223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2987508223 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1216651813 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 59583437066 ps |
| CPU time | 1113.55 seconds |
| Started | Jul 06 07:58:54 PM PDT 24 |
| Finished | Jul 06 08:17:28 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-9c21ac8e-2fc1-4744-ac0d-75d5716f4237 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216651813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1216651813 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1824544253 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 558723458 ps |
| CPU time | 48.68 seconds |
| Started | Jul 06 07:59:29 PM PDT 24 |
| Finished | Jul 06 08:00:18 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-fb2d8754-9863-457d-b4c8-0a5b71cf875d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824544253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.1824544253 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.2247450667 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 1406923539 ps |
| CPU time | 39.85 seconds |
| Started | Jul 06 07:59:08 PM PDT 24 |
| Finished | Jul 06 07:59:48 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-03f0c7b9-34c4-4c40-83dc-4f0bcebd9ab4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247450667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2247450667 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.5836280 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 50862997 ps |
| CPU time | 7.15 seconds |
| Started | Jul 06 07:58:45 PM PDT 24 |
| Finished | Jul 06 07:58:52 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-d46e8d54-e3a5-442a-805e-87b3193f85d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5836280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.5836280 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2603708025 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 6846339070 ps |
| CPU time | 78.87 seconds |
| Started | Jul 06 07:58:47 PM PDT 24 |
| Finished | Jul 06 08:00:06 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-76b75131-d078-4c68-b969-d4c684a2d6bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603708025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2603708025 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.847375364 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 5169045219 ps |
| CPU time | 87.48 seconds |
| Started | Jul 06 07:58:46 PM PDT 24 |
| Finished | Jul 06 08:00:14 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-80b02119-26d4-4f46-93b9-b935a151deb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847375364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.847375364 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1877098838 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 48419285 ps |
| CPU time | 7 seconds |
| Started | Jul 06 07:58:41 PM PDT 24 |
| Finished | Jul 06 07:58:49 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-68716d54-3c94-48b4-abc5-879efc8d4f1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877098838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .1877098838 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.3467156584 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 3066087931 ps |
| CPU time | 102.69 seconds |
| Started | Jul 06 07:59:31 PM PDT 24 |
| Finished | Jul 06 08:01:14 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-8d53809e-12bb-4dc5-9c71-5b88a8ef0a20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467156584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3467156584 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.919453724 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 1110150323 ps |
| CPU time | 104.53 seconds |
| Started | Jul 06 07:59:30 PM PDT 24 |
| Finished | Jul 06 08:01:15 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-2bd95c4e-25bf-45a2-a57c-89306b20b55c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919453724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.919453724 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3713449760 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 24787996 ps |
| CPU time | 44.99 seconds |
| Started | Jul 06 07:59:29 PM PDT 24 |
| Finished | Jul 06 08:00:14 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-19bef773-1afa-439f-8eef-d1372054dcad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713449760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.3713449760 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3829008387 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 5639382715 ps |
| CPU time | 689.94 seconds |
| Started | Jul 06 07:59:30 PM PDT 24 |
| Finished | Jul 06 08:11:00 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-06c36d7c-0162-4e9a-9301-5ecd1b42b6fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829008387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.3829008387 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2034615525 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 1138998291 ps |
| CPU time | 50.81 seconds |
| Started | Jul 06 07:59:11 PM PDT 24 |
| Finished | Jul 06 08:00:02 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-ad0220c5-ac25-475a-9541-1777c9ff01e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034615525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2034615525 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2534351041 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 57538671020 ps |
| CPU time | 9451.45 seconds |
| Started | Jul 06 07:59:33 PM PDT 24 |
| Finished | Jul 06 10:37:06 PM PDT 24 |
| Peak memory | 642260 kb |
| Host | smart-53857b7d-27ef-4fe2-a795-25dc77cc92e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534351041 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.2534351041 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1801976628 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 10735800368 ps |
| CPU time | 1547.1 seconds |
| Started | Jul 06 07:59:39 PM PDT 24 |
| Finished | Jul 06 08:25:26 PM PDT 24 |
| Peak memory | 589160 kb |
| Host | smart-0aac4a91-f6e8-42ec-b7fc-8aec627c2d95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801976628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.1801976628 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.1126564064 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3441426638 ps |
| CPU time | 358.55 seconds |
| Started | Jul 06 08:00:52 PM PDT 24 |
| Finished | Jul 06 08:06:51 PM PDT 24 |
| Peak memory | 597940 kb |
| Host | smart-97a9b736-f43a-4691-b810-ceb8cf49ea62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126564064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.1126564064 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.29221864 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 8585045476 ps |
| CPU time | 346.35 seconds |
| Started | Jul 06 07:59:42 PM PDT 24 |
| Finished | Jul 06 08:05:29 PM PDT 24 |
| Peak memory | 588656 kb |
| Host | smart-c0ecd35e-5c16-433c-9574-f666eba80db6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29221864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. chip_prim_tl_access.29221864 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2154150122 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 10405421135 ps |
| CPU time | 515.19 seconds |
| Started | Jul 06 07:59:53 PM PDT 24 |
| Finished | Jul 06 08:08:29 PM PDT 24 |
| Peak memory | 590912 kb |
| Host | smart-4fd0a2b5-5015-44ef-a531-d91f71a1a4fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154150122 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.2154150122 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.1679850037 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 3728791035 ps |
| CPU time | 348.89 seconds |
| Started | Jul 06 07:59:45 PM PDT 24 |
| Finished | Jul 06 08:05:35 PM PDT 24 |
| Peak memory | 603644 kb |
| Host | smart-f45bda40-4a1f-4f3c-9c85-9770ffb7b7d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679850037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.1679850037 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.3795928405 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 1716067425 ps |
| CPU time | 78.12 seconds |
| Started | Jul 06 08:00:11 PM PDT 24 |
| Finished | Jul 06 08:01:29 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-d22562e5-2d18-4bf1-8d70-c28e84a7ce46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795928405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 3795928405 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3385663373 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 61881075295 ps |
| CPU time | 1110.87 seconds |
| Started | Jul 06 08:00:09 PM PDT 24 |
| Finished | Jul 06 08:18:40 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-b9effffb-aaaf-4ff6-871d-370dfdc4b558 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385663373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.3385663373 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2944411505 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 1190178245 ps |
| CPU time | 53.21 seconds |
| Started | Jul 06 08:00:23 PM PDT 24 |
| Finished | Jul 06 08:01:17 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-6d5d43de-db11-41a5-b233-854cfb533bbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944411505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .2944411505 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.1409227524 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 419077023 ps |
| CPU time | 18.09 seconds |
| Started | Jul 06 08:00:50 PM PDT 24 |
| Finished | Jul 06 08:01:09 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-f713a4ff-99f0-4076-a3bb-afbdcfabded1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409227524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1409227524 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.1427914763 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 239376090 ps |
| CPU time | 25.02 seconds |
| Started | Jul 06 08:00:06 PM PDT 24 |
| Finished | Jul 06 08:00:32 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-53013a15-ec68-4e9c-8cc1-391d08788cec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427914763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.1427914763 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2793403742 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 95708390174 ps |
| CPU time | 952.97 seconds |
| Started | Jul 06 08:00:11 PM PDT 24 |
| Finished | Jul 06 08:16:04 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-5e39349c-cab8-4d55-8059-c7a31981ce91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793403742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2793403742 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2434624676 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 63179498323 ps |
| CPU time | 1180.68 seconds |
| Started | Jul 06 08:00:09 PM PDT 24 |
| Finished | Jul 06 08:19:50 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-b7d8b9ae-cbcc-4318-b5e8-0da6a8b8c55b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434624676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2434624676 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3799405947 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 195262069 ps |
| CPU time | 19.19 seconds |
| Started | Jul 06 08:00:11 PM PDT 24 |
| Finished | Jul 06 08:00:30 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-0cbd39e2-2019-4980-a5b7-ba4e2c9c042f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799405947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.3799405947 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.4162872192 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 2607490133 ps |
| CPU time | 77.92 seconds |
| Started | Jul 06 08:00:08 PM PDT 24 |
| Finished | Jul 06 08:01:26 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-bc475a11-6ddc-45e9-a5e1-0516085bdc4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162872192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.4162872192 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.3445294285 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 39241003 ps |
| CPU time | 7.03 seconds |
| Started | Jul 06 08:00:00 PM PDT 24 |
| Finished | Jul 06 08:00:08 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-042abe1d-efb2-4b2a-b45a-16a3756cd352 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445294285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3445294285 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3729878058 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 6057297705 ps |
| CPU time | 72.13 seconds |
| Started | Jul 06 07:59:58 PM PDT 24 |
| Finished | Jul 06 08:01:11 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-9325032c-52d5-4e3e-ad3d-e16bae89f8c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729878058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3729878058 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3209166330 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 5050871197 ps |
| CPU time | 89.2 seconds |
| Started | Jul 06 07:59:56 PM PDT 24 |
| Finished | Jul 06 08:01:26 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-869406c3-8aad-4220-a335-0a8b358cea9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209166330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3209166330 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.4001789044 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 49432620 ps |
| CPU time | 8.33 seconds |
| Started | Jul 06 07:59:56 PM PDT 24 |
| Finished | Jul 06 08:00:05 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-5725d0f6-b67a-427c-91b7-1c43f7ca898e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001789044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .4001789044 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.4134097858 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 6784591588 ps |
| CPU time | 283.71 seconds |
| Started | Jul 06 08:00:17 PM PDT 24 |
| Finished | Jul 06 08:05:01 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-f4217105-8bdf-4f05-8bc1-c5a4711fbec2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134097858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.4134097858 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.844555539 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 13074327404 ps |
| CPU time | 508.2 seconds |
| Started | Jul 06 08:00:25 PM PDT 24 |
| Finished | Jul 06 08:08:53 PM PDT 24 |
| Peak memory | 576820 kb |
| Host | smart-85f35990-5650-4d9e-b6d0-b3a307c10c2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844555539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.844555539 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.551769222 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 299608703 ps |
| CPU time | 106.94 seconds |
| Started | Jul 06 08:00:30 PM PDT 24 |
| Finished | Jul 06 08:02:17 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-1005d3d6-53d8-432b-848c-7afbe8726e1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551769222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_w ith_rand_reset.551769222 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3362145747 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 73834717 ps |
| CPU time | 13.74 seconds |
| Started | Jul 06 08:00:25 PM PDT 24 |
| Finished | Jul 06 08:00:39 PM PDT 24 |
| Peak memory | 574632 kb |
| Host | smart-b040d5f0-4adb-40e7-aabf-88868f48d156 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362145747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.3362145747 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3056384845 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 43753818 ps |
| CPU time | 8.32 seconds |
| Started | Jul 06 08:00:19 PM PDT 24 |
| Finished | Jul 06 08:00:28 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-ac375425-7cd0-44db-bd68-9dda94cb944d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056384845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3056384845 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.2313964474 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 4064079523 ps |
| CPU time | 340.24 seconds |
| Started | Jul 06 08:06:26 PM PDT 24 |
| Finished | Jul 06 08:12:06 PM PDT 24 |
| Peak memory | 596812 kb |
| Host | smart-6ad6fbc0-96b9-4eb1-bbf0-1df0c739ad47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313964474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.2313964474 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2840827364 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 32440010354 ps |
| CPU time | 4111.4 seconds |
| Started | Jul 06 08:05:57 PM PDT 24 |
| Finished | Jul 06 09:14:29 PM PDT 24 |
| Peak memory | 593236 kb |
| Host | smart-08278caa-3908-4c36-b23b-4107cdfd63a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840827364 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.2840827364 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.2803964124 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 4002865484 ps |
| CPU time | 331.17 seconds |
| Started | Jul 06 08:05:56 PM PDT 24 |
| Finished | Jul 06 08:11:28 PM PDT 24 |
| Peak memory | 598512 kb |
| Host | smart-08c12b41-1835-4e98-84e0-6450ce1c4def |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803964124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.2803964124 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.1479747911 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 3088027028 ps |
| CPU time | 152.49 seconds |
| Started | Jul 06 08:06:05 PM PDT 24 |
| Finished | Jul 06 08:08:38 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-08b5c4f3-3105-4a25-859f-814d1e543c9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479747911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .1479747911 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2048438906 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 29724686913 ps |
| CPU time | 559.85 seconds |
| Started | Jul 06 08:06:09 PM PDT 24 |
| Finished | Jul 06 08:15:29 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-3d1ff2eb-23d3-4246-ae5c-9d009f68810b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048438906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.2048438906 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.613244283 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 176127472 ps |
| CPU time | 22.95 seconds |
| Started | Jul 06 08:06:13 PM PDT 24 |
| Finished | Jul 06 08:06:36 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-eafc3ad7-c55c-4b9e-a337-212a6a02d636 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613244283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr .613244283 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.4029246224 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 565948370 ps |
| CPU time | 50.76 seconds |
| Started | Jul 06 08:06:07 PM PDT 24 |
| Finished | Jul 06 08:06:59 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-279c9ba9-f3df-4b7a-bf67-69ffb44443b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029246224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.4029246224 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.3837297035 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 144897118 ps |
| CPU time | 8.88 seconds |
| Started | Jul 06 08:06:02 PM PDT 24 |
| Finished | Jul 06 08:06:11 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-1b70a526-5dff-43a5-be9b-fdf53596f1a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837297035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.3837297035 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3452588693 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 10746051941 ps |
| CPU time | 122.54 seconds |
| Started | Jul 06 08:06:01 PM PDT 24 |
| Finished | Jul 06 08:08:04 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-e88683e4-9065-40aa-a033-ae5513bb8fc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452588693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3452588693 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1107201747 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 32978946804 ps |
| CPU time | 604.62 seconds |
| Started | Jul 06 08:06:08 PM PDT 24 |
| Finished | Jul 06 08:16:13 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-8eef1d1b-97e5-41ce-92ae-be9610d47e3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107201747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1107201747 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.938335863 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 123909521 ps |
| CPU time | 15.77 seconds |
| Started | Jul 06 08:06:02 PM PDT 24 |
| Finished | Jul 06 08:06:18 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-0fefc18f-203f-47f7-9913-0fa72ee02a42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938335863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_dela ys.938335863 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.3421088139 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 368696988 ps |
| CPU time | 27.78 seconds |
| Started | Jul 06 08:06:06 PM PDT 24 |
| Finished | Jul 06 08:06:34 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-8ee91172-4455-4a61-a404-9b8f14fe07c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421088139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3421088139 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.4174697785 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 58302316 ps |
| CPU time | 7.67 seconds |
| Started | Jul 06 08:05:57 PM PDT 24 |
| Finished | Jul 06 08:06:05 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-5423746a-dfca-4cea-bd0b-244864143525 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174697785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.4174697785 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3254002206 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 9400148179 ps |
| CPU time | 99.6 seconds |
| Started | Jul 06 08:05:56 PM PDT 24 |
| Finished | Jul 06 08:07:36 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-916d9815-ab99-43de-b780-21c2ec629c66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254002206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3254002206 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1896022787 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 4946594306 ps |
| CPU time | 89.82 seconds |
| Started | Jul 06 08:06:03 PM PDT 24 |
| Finished | Jul 06 08:07:33 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-6551f1ce-2169-417f-a410-967bbc84272a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896022787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1896022787 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3676850262 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 50251796 ps |
| CPU time | 7.13 seconds |
| Started | Jul 06 08:05:58 PM PDT 24 |
| Finished | Jul 06 08:06:05 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-7e5d7817-b1d9-4206-839c-20ffff239d99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676850262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.3676850262 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.3230916904 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 7663957657 ps |
| CPU time | 308.81 seconds |
| Started | Jul 06 08:06:14 PM PDT 24 |
| Finished | Jul 06 08:11:23 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-4fc9c378-a10e-4b7f-b744-4a65d1662729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230916904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3230916904 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3145199459 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 1176661708 ps |
| CPU time | 86.74 seconds |
| Started | Jul 06 08:06:17 PM PDT 24 |
| Finished | Jul 06 08:07:44 PM PDT 24 |
| Peak memory | 576868 kb |
| Host | smart-1e0f94ba-9c20-4154-b00e-affe9a9dba13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145199459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3145199459 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3843438855 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 15281596255 ps |
| CPU time | 900.26 seconds |
| Started | Jul 06 08:06:18 PM PDT 24 |
| Finished | Jul 06 08:21:18 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-65b505b7-fe17-4b95-97d9-4c7bf4466143 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843438855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.3843438855 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.2775814089 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 535260861 ps |
| CPU time | 23 seconds |
| Started | Jul 06 08:06:09 PM PDT 24 |
| Finished | Jul 06 08:06:32 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-9ebe1807-8ec3-4e27-8711-152937f26b00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775814089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2775814089 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.2139099421 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 4707074192 ps |
| CPU time | 358.23 seconds |
| Started | Jul 06 08:06:39 PM PDT 24 |
| Finished | Jul 06 08:12:37 PM PDT 24 |
| Peak memory | 596620 kb |
| Host | smart-627a236d-d505-479e-96cd-fcecf48e48f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139099421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.2139099421 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.844331502 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 16535120088 ps |
| CPU time | 2320.12 seconds |
| Started | Jul 06 08:06:18 PM PDT 24 |
| Finished | Jul 06 08:44:58 PM PDT 24 |
| Peak memory | 592872 kb |
| Host | smart-9b5251a6-12d7-4c5c-865c-8389bb40c60e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844331502 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.chip_same_csr_outstanding.844331502 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.1498972899 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 2903569333 ps |
| CPU time | 217.27 seconds |
| Started | Jul 06 08:06:21 PM PDT 24 |
| Finished | Jul 06 08:09:58 PM PDT 24 |
| Peak memory | 603520 kb |
| Host | smart-198097a0-71e7-4cdd-950d-72563e698e56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498972899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.1498972899 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.361131277 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 1236185716 ps |
| CPU time | 88.55 seconds |
| Started | Jul 06 08:06:28 PM PDT 24 |
| Finished | Jul 06 08:07:57 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-d94d1d9f-5118-4788-9922-28d1fe16f8b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361131277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device. 361131277 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1164218377 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 79039212941 ps |
| CPU time | 1366.23 seconds |
| Started | Jul 06 08:06:30 PM PDT 24 |
| Finished | Jul 06 08:29:16 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-da33f332-ae7c-410d-8015-ecdf9f636029 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164218377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.1164218377 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.722150103 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 74665335 ps |
| CPU time | 6.84 seconds |
| Started | Jul 06 08:06:36 PM PDT 24 |
| Finished | Jul 06 08:06:43 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-0c7e9d1c-c285-4735-844a-b79ed823a5f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722150103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr .722150103 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.1088181709 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 141183288 ps |
| CPU time | 16.04 seconds |
| Started | Jul 06 08:06:34 PM PDT 24 |
| Finished | Jul 06 08:06:50 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-a76c2153-2f52-4f99-8715-af9bd39d0d64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088181709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1088181709 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.344078711 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 1713010724 ps |
| CPU time | 77.66 seconds |
| Started | Jul 06 08:06:21 PM PDT 24 |
| Finished | Jul 06 08:07:40 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-906ea6d8-6295-477b-8b76-0d94eeb00cdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344078711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.344078711 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.186671272 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 8807660193 ps |
| CPU time | 88.42 seconds |
| Started | Jul 06 08:06:28 PM PDT 24 |
| Finished | Jul 06 08:07:57 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-79961881-40c7-4037-9421-451ee0b932d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186671272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.186671272 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3517009935 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 2722189767 ps |
| CPU time | 49.63 seconds |
| Started | Jul 06 08:06:27 PM PDT 24 |
| Finished | Jul 06 08:07:17 PM PDT 24 |
| Peak memory | 574792 kb |
| Host | smart-86046d7e-26c2-4202-aac9-857b3966d9a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517009935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3517009935 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1413201217 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 584679941 ps |
| CPU time | 53.65 seconds |
| Started | Jul 06 08:06:24 PM PDT 24 |
| Finished | Jul 06 08:07:18 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-0ddad565-e145-42ca-a8fc-2e48fcdf4023 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413201217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.1413201217 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.4052526976 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 1521801909 ps |
| CPU time | 44.86 seconds |
| Started | Jul 06 08:06:27 PM PDT 24 |
| Finished | Jul 06 08:07:12 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-9af8a146-be85-4e7e-bf30-be08263d4f30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052526976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.4052526976 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.1578021037 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 251953000 ps |
| CPU time | 11.84 seconds |
| Started | Jul 06 08:06:18 PM PDT 24 |
| Finished | Jul 06 08:06:31 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-51eaa88a-108f-43f9-abf6-fbf8ffbebd11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578021037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1578021037 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2732307797 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 7362459573 ps |
| CPU time | 78.26 seconds |
| Started | Jul 06 08:06:23 PM PDT 24 |
| Finished | Jul 06 08:07:42 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-5bd4bcf3-57dc-4b13-9dcd-23bf585f2eab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732307797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2732307797 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2753566228 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 5983904335 ps |
| CPU time | 103.89 seconds |
| Started | Jul 06 08:06:23 PM PDT 24 |
| Finished | Jul 06 08:08:07 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-4ee219ba-fd1f-449b-b15d-0b5b38bfa814 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753566228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2753566228 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3999528572 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 35964655 ps |
| CPU time | 6.49 seconds |
| Started | Jul 06 08:06:23 PM PDT 24 |
| Finished | Jul 06 08:06:30 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-3755b138-4240-40d8-857a-eed8944da1d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999528572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.3999528572 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.4262668124 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 7985696563 ps |
| CPU time | 399.56 seconds |
| Started | Jul 06 08:06:35 PM PDT 24 |
| Finished | Jul 06 08:13:15 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-c4aebbca-6d51-4256-926a-49675a740a85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262668124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.4262668124 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.264673534 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 8834388446 ps |
| CPU time | 365.32 seconds |
| Started | Jul 06 08:06:35 PM PDT 24 |
| Finished | Jul 06 08:12:40 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-15116801-b440-420e-bd19-84e6bda05d8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264673534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.264673534 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3744898729 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 7497605359 ps |
| CPU time | 415.51 seconds |
| Started | Jul 06 08:06:36 PM PDT 24 |
| Finished | Jul 06 08:13:32 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-ddec0135-0691-43a7-bf56-ffbc3aebcb36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744898729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.3744898729 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.100697630 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 5640201950 ps |
| CPU time | 558.23 seconds |
| Started | Jul 06 08:07:07 PM PDT 24 |
| Finished | Jul 06 08:16:25 PM PDT 24 |
| Peak memory | 598832 kb |
| Host | smart-42d4bb51-e734-4450-a451-3f46f555b58b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100697630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.100697630 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.2274260130 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 3966694269 ps |
| CPU time | 342.96 seconds |
| Started | Jul 06 08:06:42 PM PDT 24 |
| Finished | Jul 06 08:12:25 PM PDT 24 |
| Peak memory | 603552 kb |
| Host | smart-1da38f43-1cbc-4322-9f7e-24f18530e8b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274260130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.2274260130 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.2651376510 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2692375493 ps |
| CPU time | 126.8 seconds |
| Started | Jul 06 08:06:45 PM PDT 24 |
| Finished | Jul 06 08:08:52 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-52584ef8-0b1b-412b-bc91-94202c9f37b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651376510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .2651376510 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3493288476 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 122855140435 ps |
| CPU time | 2178.86 seconds |
| Started | Jul 06 08:06:45 PM PDT 24 |
| Finished | Jul 06 08:43:04 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-be2490a8-c68f-4860-aac9-6a5c52f1a8ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493288476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.3493288476 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3941596448 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 339839944 ps |
| CPU time | 36.1 seconds |
| Started | Jul 06 08:06:55 PM PDT 24 |
| Finished | Jul 06 08:07:31 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-62757a66-2838-414c-9468-6737ed647d31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941596448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.3941596448 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.97868552 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 2030860097 ps |
| CPU time | 76.1 seconds |
| Started | Jul 06 08:06:44 PM PDT 24 |
| Finished | Jul 06 08:08:01 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-0f4801e6-9f5a-472b-aaeb-cdc300eb5d88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97868552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.97868552 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.541984361 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1106689938 ps |
| CPU time | 41.49 seconds |
| Started | Jul 06 08:06:40 PM PDT 24 |
| Finished | Jul 06 08:07:22 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-8f4b9122-aba7-42d7-9c09-9d5796307184 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541984361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.541984361 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.4004723715 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 98466910116 ps |
| CPU time | 1100.38 seconds |
| Started | Jul 06 08:06:45 PM PDT 24 |
| Finished | Jul 06 08:25:06 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-0af99068-8eb2-4222-8a65-9f044934b7f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004723715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.4004723715 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2755214985 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 63232017882 ps |
| CPU time | 1040.71 seconds |
| Started | Jul 06 08:06:45 PM PDT 24 |
| Finished | Jul 06 08:24:06 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-4abe35c0-2f29-4276-a0db-9344b36c3399 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755214985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2755214985 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2064420281 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 377428506 ps |
| CPU time | 35.17 seconds |
| Started | Jul 06 08:06:44 PM PDT 24 |
| Finished | Jul 06 08:07:19 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-f172de55-ddc3-4fea-ab60-013b0b05ade5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064420281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.2064420281 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.614188135 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 557110910 ps |
| CPU time | 50.14 seconds |
| Started | Jul 06 08:06:44 PM PDT 24 |
| Finished | Jul 06 08:07:35 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-8628a0ed-20ff-4ff3-a9a1-72ffba8c75d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614188135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.614188135 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.1043796095 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 172794042 ps |
| CPU time | 7.71 seconds |
| Started | Jul 06 08:06:41 PM PDT 24 |
| Finished | Jul 06 08:06:49 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-6c0492b9-0236-4641-9e07-eb25a6bf1250 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043796095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1043796095 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1828714600 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 5470613678 ps |
| CPU time | 58.88 seconds |
| Started | Jul 06 08:06:41 PM PDT 24 |
| Finished | Jul 06 08:07:40 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-3bf41f03-bfbd-4963-a4bd-bc21191c447e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828714600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1828714600 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3979805562 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 6152822347 ps |
| CPU time | 111.79 seconds |
| Started | Jul 06 08:06:42 PM PDT 24 |
| Finished | Jul 06 08:08:34 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-e3909b4c-5299-4023-a4da-22ea22be65ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979805562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3979805562 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.4078072992 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 46037619 ps |
| CPU time | 5.84 seconds |
| Started | Jul 06 08:06:38 PM PDT 24 |
| Finished | Jul 06 08:06:44 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-852c0812-9c63-4bf1-8a20-28a075a3a385 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078072992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.4078072992 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.211985772 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 1964133829 ps |
| CPU time | 82.62 seconds |
| Started | Jul 06 08:07:03 PM PDT 24 |
| Finished | Jul 06 08:08:26 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-9289b2cc-ef90-4ccf-9d1f-7f94df6128d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211985772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.211985772 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1600579039 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1373388687 ps |
| CPU time | 123.16 seconds |
| Started | Jul 06 08:07:03 PM PDT 24 |
| Finished | Jul 06 08:09:06 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-8a241f59-ffc3-4214-8916-8815ea773509 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600579039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1600579039 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.4172112464 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 5800163519 ps |
| CPU time | 685.52 seconds |
| Started | Jul 06 08:06:59 PM PDT 24 |
| Finished | Jul 06 08:18:25 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-37fb687a-db44-475d-b509-fc1bfcbcab85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172112464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.4172112464 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.111695027 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 1545175589 ps |
| CPU time | 231.69 seconds |
| Started | Jul 06 08:06:59 PM PDT 24 |
| Finished | Jul 06 08:10:51 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-6e458f29-ff66-4ea9-9539-e8af73d16e20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111695027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_reset_error.111695027 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2276631851 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 136951864 ps |
| CPU time | 9.88 seconds |
| Started | Jul 06 08:06:49 PM PDT 24 |
| Finished | Jul 06 08:07:00 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-44c4263b-5d93-417e-a2e7-cf35f3f352ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276631851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2276631851 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.4172852845 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 5853993755 ps |
| CPU time | 567.78 seconds |
| Started | Jul 06 08:07:28 PM PDT 24 |
| Finished | Jul 06 08:16:56 PM PDT 24 |
| Peak memory | 598864 kb |
| Host | smart-e6582c0d-cfa4-4450-b99d-577ec9cecc70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172852845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.4172852845 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.707742081 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 14949510680 ps |
| CPU time | 1551.15 seconds |
| Started | Jul 06 08:07:07 PM PDT 24 |
| Finished | Jul 06 08:32:58 PM PDT 24 |
| Peak memory | 592792 kb |
| Host | smart-e3896156-6f21-4dd9-b23f-a12ea227100f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707742081 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 13.chip_same_csr_outstanding.707742081 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.261387819 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 1510606445 ps |
| CPU time | 69.88 seconds |
| Started | Jul 06 08:07:11 PM PDT 24 |
| Finished | Jul 06 08:08:21 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-70d6db37-dc1d-4946-8937-5302f39b2978 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261387819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device. 261387819 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.4147021059 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 81525334582 ps |
| CPU time | 1445.12 seconds |
| Started | Jul 06 08:07:15 PM PDT 24 |
| Finished | Jul 06 08:31:21 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-267cf546-b935-41e4-846c-d45c70939a6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147021059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.4147021059 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2745340543 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 205803420 ps |
| CPU time | 24.23 seconds |
| Started | Jul 06 08:07:21 PM PDT 24 |
| Finished | Jul 06 08:07:45 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-d8cdb8de-1784-4c1a-b4c4-5a8a211d82fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745340543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.2745340543 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.1238363712 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 2460350693 ps |
| CPU time | 105.04 seconds |
| Started | Jul 06 08:07:15 PM PDT 24 |
| Finished | Jul 06 08:09:01 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-e1c507b5-a625-4036-9663-fb6a63a38a05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238363712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1238363712 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.843306922 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 114739660 ps |
| CPU time | 8.31 seconds |
| Started | Jul 06 08:07:11 PM PDT 24 |
| Finished | Jul 06 08:07:19 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-f6ea26b8-6018-46b9-9aa7-233056412950 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843306922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.843306922 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1434406531 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 64777228152 ps |
| CPU time | 655.68 seconds |
| Started | Jul 06 08:07:11 PM PDT 24 |
| Finished | Jul 06 08:18:07 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-0b90f265-484c-4bdb-8b96-edbb692b0ada |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434406531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1434406531 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.795315023 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 20430083657 ps |
| CPU time | 354.77 seconds |
| Started | Jul 06 08:07:13 PM PDT 24 |
| Finished | Jul 06 08:13:08 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-8bb59645-86c5-4098-8902-7ce02fab29b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795315023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.795315023 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3547589538 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 293987492 ps |
| CPU time | 28.08 seconds |
| Started | Jul 06 08:07:15 PM PDT 24 |
| Finished | Jul 06 08:07:43 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-08960934-8569-4c33-b234-e75d823e01ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547589538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.3547589538 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.234861851 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 1805878763 ps |
| CPU time | 63.13 seconds |
| Started | Jul 06 08:07:14 PM PDT 24 |
| Finished | Jul 06 08:08:18 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-85eb8a90-ec73-4464-9767-0a041329c378 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234861851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.234861851 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.608306023 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 209051880 ps |
| CPU time | 9.76 seconds |
| Started | Jul 06 08:07:11 PM PDT 24 |
| Finished | Jul 06 08:07:21 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-6086b445-b86b-423c-9b38-e62ea0f938aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608306023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.608306023 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3161968052 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 6704313444 ps |
| CPU time | 68.97 seconds |
| Started | Jul 06 08:07:10 PM PDT 24 |
| Finished | Jul 06 08:08:19 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-8342ffba-4484-4a04-8a4d-301ecdedabba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161968052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3161968052 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1017109298 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 5589783238 ps |
| CPU time | 102.53 seconds |
| Started | Jul 06 08:07:10 PM PDT 24 |
| Finished | Jul 06 08:08:53 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-52a6658f-b47b-47a8-b57b-539e893515fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017109298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1017109298 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3219683311 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 43792410 ps |
| CPU time | 6.69 seconds |
| Started | Jul 06 08:07:15 PM PDT 24 |
| Finished | Jul 06 08:07:22 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-a0e8211c-a161-44cc-8113-df6e26effdd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219683311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.3219683311 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.2848106111 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 885774720 ps |
| CPU time | 99.02 seconds |
| Started | Jul 06 08:07:21 PM PDT 24 |
| Finished | Jul 06 08:09:01 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-7a611809-6b6d-49c7-953c-4e6f618fb85c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848106111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2848106111 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1149135560 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 1394443591 ps |
| CPU time | 140.88 seconds |
| Started | Jul 06 08:07:22 PM PDT 24 |
| Finished | Jul 06 08:09:43 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-9ea93e34-4bf7-44b3-b79e-95b79c0a8b54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149135560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1149135560 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.291905316 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 3047808264 ps |
| CPU time | 332.08 seconds |
| Started | Jul 06 08:07:22 PM PDT 24 |
| Finished | Jul 06 08:12:54 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-867e989f-74af-4b94-9a7b-751e0917bdfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291905316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_ with_rand_reset.291905316 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.962358755 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 4631237316 ps |
| CPU time | 333.25 seconds |
| Started | Jul 06 08:07:26 PM PDT 24 |
| Finished | Jul 06 08:13:00 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-5644bdd3-5bd1-4d26-839b-9f863ef12aac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962358755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_reset_error.962358755 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.370655742 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 163887539 ps |
| CPU time | 25.86 seconds |
| Started | Jul 06 08:07:17 PM PDT 24 |
| Finished | Jul 06 08:07:43 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-5d5f88c6-4fda-4834-9292-a6550a701a47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370655742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.370655742 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.3655647379 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 6302285406 ps |
| CPU time | 664.35 seconds |
| Started | Jul 06 08:08:00 PM PDT 24 |
| Finished | Jul 06 08:19:04 PM PDT 24 |
| Peak memory | 596848 kb |
| Host | smart-5b3db808-44f8-4e08-b665-8a810ff2107d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655647379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.3655647379 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1097242647 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 15787128363 ps |
| CPU time | 2298.71 seconds |
| Started | Jul 06 08:07:26 PM PDT 24 |
| Finished | Jul 06 08:45:46 PM PDT 24 |
| Peak memory | 592892 kb |
| Host | smart-e418f76d-255c-49dd-89bb-e480ee13c99a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097242647 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.1097242647 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.4244388984 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 3286758496 ps |
| CPU time | 198.97 seconds |
| Started | Jul 06 08:07:26 PM PDT 24 |
| Finished | Jul 06 08:10:45 PM PDT 24 |
| Peak memory | 597404 kb |
| Host | smart-3984b385-0674-467b-9ee1-1dc103f5c767 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244388984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.4244388984 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.1900611606 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 3485399675 ps |
| CPU time | 169.91 seconds |
| Started | Jul 06 08:07:38 PM PDT 24 |
| Finished | Jul 06 08:10:29 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-cccc4331-8da9-42ad-8c91-4cc50e5c5e3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900611606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .1900611606 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.2038242838 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 25049669047 ps |
| CPU time | 435.35 seconds |
| Started | Jul 06 08:07:37 PM PDT 24 |
| Finished | Jul 06 08:14:53 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-2706eef0-452d-4f41-8b8f-32b395318c2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038242838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.2038242838 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1004333047 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 933599869 ps |
| CPU time | 43.09 seconds |
| Started | Jul 06 08:07:44 PM PDT 24 |
| Finished | Jul 06 08:08:27 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-a451b84f-1bd1-4763-8872-1139b86a1e9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004333047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.1004333047 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.3208171113 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 1993785314 ps |
| CPU time | 84.43 seconds |
| Started | Jul 06 08:07:38 PM PDT 24 |
| Finished | Jul 06 08:09:03 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-3d062e52-37d3-4e75-b4e3-afb53328a351 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208171113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3208171113 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.661529124 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 934282821 ps |
| CPU time | 35.2 seconds |
| Started | Jul 06 08:07:34 PM PDT 24 |
| Finished | Jul 06 08:08:10 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-fc878d38-03ab-44ac-9b13-b66ed2ab8fda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661529124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.661529124 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.417777151 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 74096995857 ps |
| CPU time | 754.69 seconds |
| Started | Jul 06 08:07:40 PM PDT 24 |
| Finished | Jul 06 08:20:15 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-570164d4-aad7-4067-ae05-3b77fb92e706 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417777151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.417777151 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1500546460 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 26254877976 ps |
| CPU time | 442.94 seconds |
| Started | Jul 06 08:07:39 PM PDT 24 |
| Finished | Jul 06 08:15:03 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-e0b3ac93-6a70-4911-b4bc-6c7c14295bce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500546460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1500546460 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.64955870 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 333981244 ps |
| CPU time | 34.33 seconds |
| Started | Jul 06 08:07:38 PM PDT 24 |
| Finished | Jul 06 08:08:13 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-e8a0e817-8653-4569-b09e-1942ab0b048b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64955870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delay s.64955870 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.877218108 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 536333050 ps |
| CPU time | 42.49 seconds |
| Started | Jul 06 08:07:38 PM PDT 24 |
| Finished | Jul 06 08:08:21 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-ae297f74-c683-4ac5-aa1f-32585da79937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877218108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.877218108 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.2875453699 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 177004982 ps |
| CPU time | 9.14 seconds |
| Started | Jul 06 08:07:33 PM PDT 24 |
| Finished | Jul 06 08:07:43 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-38ef52ca-69da-4ed8-9b70-d2f400ac688c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875453699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2875453699 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2255320254 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 8309715598 ps |
| CPU time | 86.2 seconds |
| Started | Jul 06 08:07:32 PM PDT 24 |
| Finished | Jul 06 08:08:59 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-b91d5235-eea2-48ee-b4bc-a51caddb635c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255320254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2255320254 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1316608604 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 6295257578 ps |
| CPU time | 116.88 seconds |
| Started | Jul 06 08:07:35 PM PDT 24 |
| Finished | Jul 06 08:09:32 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-a11dd5b4-b2be-4014-a331-8415504a245e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316608604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1316608604 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3759797740 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 45457456 ps |
| CPU time | 6.63 seconds |
| Started | Jul 06 08:07:35 PM PDT 24 |
| Finished | Jul 06 08:07:42 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-72d6bdb4-3f33-4d05-bcad-87d8ff333166 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759797740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.3759797740 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.1685527221 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 10644123816 ps |
| CPU time | 385.3 seconds |
| Started | Jul 06 08:07:45 PM PDT 24 |
| Finished | Jul 06 08:14:11 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-87b56b89-dc92-45d4-8c1a-e1b8a346a7c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685527221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1685527221 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.3109526120 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 8256820219 ps |
| CPU time | 266.46 seconds |
| Started | Jul 06 08:07:51 PM PDT 24 |
| Finished | Jul 06 08:12:18 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-9c84f5b1-afc2-4864-8d6c-20e9147df7a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109526120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3109526120 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.5751939 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 184454978 ps |
| CPU time | 26.38 seconds |
| Started | Jul 06 08:07:51 PM PDT 24 |
| Finished | Jul 06 08:08:18 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-606ad776-e553-406d-8be5-f59da74b4f9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5751939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_w ith_reset_error.5751939 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.1426701894 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 242954264 ps |
| CPU time | 32.78 seconds |
| Started | Jul 06 08:07:40 PM PDT 24 |
| Finished | Jul 06 08:08:13 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-72bdf7ee-c284-4518-a5e3-233a0159200b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426701894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1426701894 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.965776042 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 5629316280 ps |
| CPU time | 676.61 seconds |
| Started | Jul 06 08:08:07 PM PDT 24 |
| Finished | Jul 06 08:19:23 PM PDT 24 |
| Peak memory | 598604 kb |
| Host | smart-24beedff-3ff0-4b7c-8e85-c40df05b539c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965776042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.965776042 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.917882658 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 27582778333 ps |
| CPU time | 3146.47 seconds |
| Started | Jul 06 08:07:55 PM PDT 24 |
| Finished | Jul 06 09:00:23 PM PDT 24 |
| Peak memory | 593012 kb |
| Host | smart-1d13f631-f320-4a42-bae3-8257f0e41c95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917882658 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 15.chip_same_csr_outstanding.917882658 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.909061141 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 4517908350 ps |
| CPU time | 391.8 seconds |
| Started | Jul 06 08:07:52 PM PDT 24 |
| Finished | Jul 06 08:14:24 PM PDT 24 |
| Peak memory | 603604 kb |
| Host | smart-008c1f7a-b0b0-4207-9a00-7a935d6699f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909061141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.909061141 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.3097015105 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 923409598 ps |
| CPU time | 77.3 seconds |
| Started | Jul 06 08:07:55 PM PDT 24 |
| Finished | Jul 06 08:09:13 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-e79ffa4d-44c8-4a80-9c48-83b76281de3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097015105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .3097015105 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.2359422343 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 121587090572 ps |
| CPU time | 2078.53 seconds |
| Started | Jul 06 08:07:58 PM PDT 24 |
| Finished | Jul 06 08:42:37 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-1143095c-e74e-4444-b9f2-e1fa35acb67d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359422343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.2359422343 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2266521688 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 1494150696 ps |
| CPU time | 67.55 seconds |
| Started | Jul 06 08:08:01 PM PDT 24 |
| Finished | Jul 06 08:09:09 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-48c6a1e5-d927-4071-bbeb-94b119ac3175 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266521688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.2266521688 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.2807104948 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 443537078 ps |
| CPU time | 39.55 seconds |
| Started | Jul 06 08:07:55 PM PDT 24 |
| Finished | Jul 06 08:08:35 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-35ce4cf5-573f-4e16-aba2-fb302f23b1ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807104948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2807104948 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.4065274230 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 677832898 ps |
| CPU time | 27.99 seconds |
| Started | Jul 06 08:07:50 PM PDT 24 |
| Finished | Jul 06 08:08:19 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-a2090a4d-1a0a-485d-8088-e9b2e2227208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065274230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.4065274230 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.2444263693 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 60517225901 ps |
| CPU time | 613.47 seconds |
| Started | Jul 06 08:07:49 PM PDT 24 |
| Finished | Jul 06 08:18:03 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-b1acbff7-de8f-47fc-8c87-37bad1328297 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444263693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2444263693 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.1250863504 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 60139183167 ps |
| CPU time | 1069.17 seconds |
| Started | Jul 06 08:07:56 PM PDT 24 |
| Finished | Jul 06 08:25:46 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-1df9f35e-05e5-4ee7-888a-28a89bab88f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250863504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1250863504 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.4105652790 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 74017768 ps |
| CPU time | 8.71 seconds |
| Started | Jul 06 08:07:59 PM PDT 24 |
| Finished | Jul 06 08:08:08 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-c501c6e7-2cc9-4f5d-a3f4-736a8ed30687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105652790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.4105652790 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.2019333223 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 2485191068 ps |
| CPU time | 76.29 seconds |
| Started | Jul 06 08:07:57 PM PDT 24 |
| Finished | Jul 06 08:09:13 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-367ee2ff-8df6-4a77-94d8-f8d3de64c7a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019333223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2019333223 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.1484957470 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 46297094 ps |
| CPU time | 6.64 seconds |
| Started | Jul 06 08:07:52 PM PDT 24 |
| Finished | Jul 06 08:07:59 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-f7361665-2b06-445c-82e4-d3012ede4b98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484957470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1484957470 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.696076214 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 7945643516 ps |
| CPU time | 81.99 seconds |
| Started | Jul 06 08:07:51 PM PDT 24 |
| Finished | Jul 06 08:09:14 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-158d9a29-2b8b-4a3d-b6a9-221017d1d359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696076214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.696076214 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2505951500 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 5309459596 ps |
| CPU time | 96.79 seconds |
| Started | Jul 06 08:07:59 PM PDT 24 |
| Finished | Jul 06 08:09:36 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-d59c8b1c-1f9e-4261-be61-e5aa15febf0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505951500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2505951500 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.4257284231 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 46714571 ps |
| CPU time | 7.07 seconds |
| Started | Jul 06 08:07:55 PM PDT 24 |
| Finished | Jul 06 08:08:02 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-22d6d380-8f30-4270-88b4-80e5381d69fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257284231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.4257284231 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.3784881456 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1553318965 ps |
| CPU time | 154.98 seconds |
| Started | Jul 06 08:08:00 PM PDT 24 |
| Finished | Jul 06 08:10:36 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-21ab9a74-5a58-43fa-b653-2bbef6e9dcf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784881456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3784881456 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.942557846 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 2264107374 ps |
| CPU time | 109.6 seconds |
| Started | Jul 06 08:08:08 PM PDT 24 |
| Finished | Jul 06 08:09:58 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-62f13b22-eac0-447c-9003-a47cfae4536e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942557846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.942557846 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3115833048 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 440676758 ps |
| CPU time | 222.25 seconds |
| Started | Jul 06 08:08:00 PM PDT 24 |
| Finished | Jul 06 08:11:43 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-524ac9ac-7d82-4c5d-b004-b255b656cb87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115833048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.3115833048 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.2753044241 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 345129385 ps |
| CPU time | 31.44 seconds |
| Started | Jul 06 08:08:07 PM PDT 24 |
| Finished | Jul 06 08:08:39 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-be62afa0-ddd0-4507-93cc-30e79731764c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753044241 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.2753044241 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.1742899136 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 82696596 ps |
| CPU time | 7.14 seconds |
| Started | Jul 06 08:07:54 PM PDT 24 |
| Finished | Jul 06 08:08:02 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-5c6bfe97-77f3-434d-921f-60800acace3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742899136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1742899136 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.2889664108 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 4393970138 ps |
| CPU time | 330.35 seconds |
| Started | Jul 06 08:08:30 PM PDT 24 |
| Finished | Jul 06 08:14:00 PM PDT 24 |
| Peak memory | 596844 kb |
| Host | smart-f4d0873e-4d2b-4417-b9b8-1e25152f36a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889664108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.2889664108 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.1182311409 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 15891053723 ps |
| CPU time | 1552.31 seconds |
| Started | Jul 06 08:08:07 PM PDT 24 |
| Finished | Jul 06 08:34:00 PM PDT 24 |
| Peak memory | 592828 kb |
| Host | smart-e4965581-72d3-4ea7-b2e0-a52d9b37300b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182311409 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.1182311409 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.3007805579 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 4807205966 ps |
| CPU time | 486.4 seconds |
| Started | Jul 06 08:08:12 PM PDT 24 |
| Finished | Jul 06 08:16:19 PM PDT 24 |
| Peak memory | 603648 kb |
| Host | smart-126783b1-22d8-46cd-be31-8c4189981286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007805579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.3007805579 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.886526027 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 3377458140 ps |
| CPU time | 157.07 seconds |
| Started | Jul 06 08:08:25 PM PDT 24 |
| Finished | Jul 06 08:11:02 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-4aad9dfb-e089-476c-8f51-c8e2d3435d9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886526027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device. 886526027 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2095767687 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 113508471396 ps |
| CPU time | 1974.71 seconds |
| Started | Jul 06 08:08:25 PM PDT 24 |
| Finished | Jul 06 08:41:20 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-27df7d6d-2fcb-42bc-afa5-3c568322251d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095767687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.2095767687 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.2478553435 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 243956442 ps |
| CPU time | 28.03 seconds |
| Started | Jul 06 08:08:25 PM PDT 24 |
| Finished | Jul 06 08:08:53 PM PDT 24 |
| Peak memory | 576492 kb |
| Host | smart-1cd39fc4-fd45-49ab-813d-507fa21070a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478553435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.2478553435 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.2473405542 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 258695701 ps |
| CPU time | 23.39 seconds |
| Started | Jul 06 08:08:25 PM PDT 24 |
| Finished | Jul 06 08:08:49 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-43f3061a-6d5f-4d11-af4f-6a383c0e7520 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473405542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2473405542 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.2894726573 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 791249896 ps |
| CPU time | 32.49 seconds |
| Started | Jul 06 08:08:20 PM PDT 24 |
| Finished | Jul 06 08:08:53 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-9e2f6a2d-ae5f-48c1-8786-4970916f3560 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894726573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.2894726573 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2384910297 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 74049794936 ps |
| CPU time | 779.54 seconds |
| Started | Jul 06 08:08:20 PM PDT 24 |
| Finished | Jul 06 08:21:20 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-304cb07b-5ee2-41fe-8c95-015d68e9ce06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384910297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2384910297 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.2199536583 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 46428029395 ps |
| CPU time | 839.04 seconds |
| Started | Jul 06 08:08:25 PM PDT 24 |
| Finished | Jul 06 08:22:24 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-753fd602-0ed1-48dd-97a0-daa866ea7e96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199536583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2199536583 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.3669848333 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 479178202 ps |
| CPU time | 49.76 seconds |
| Started | Jul 06 08:08:19 PM PDT 24 |
| Finished | Jul 06 08:09:09 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-c1965208-62a3-4584-b67b-7f1e1bd899ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669848333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.3669848333 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.3427535794 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 2633276465 ps |
| CPU time | 93.19 seconds |
| Started | Jul 06 08:08:26 PM PDT 24 |
| Finished | Jul 06 08:09:59 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-2a0f0b37-3b84-49e0-a3e6-bbdac61951d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427535794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3427535794 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.140810549 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 255686418 ps |
| CPU time | 10.92 seconds |
| Started | Jul 06 08:08:12 PM PDT 24 |
| Finished | Jul 06 08:08:23 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-01856a21-ae85-441d-9399-34dd69fa2300 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140810549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.140810549 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.2632376291 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 8785895936 ps |
| CPU time | 90.72 seconds |
| Started | Jul 06 08:08:18 PM PDT 24 |
| Finished | Jul 06 08:09:50 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-9812818d-301f-4071-8443-edc8e3ab49fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632376291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2632376291 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.4085518830 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 6023758798 ps |
| CPU time | 110.07 seconds |
| Started | Jul 06 08:08:20 PM PDT 24 |
| Finished | Jul 06 08:10:10 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-ff3e8a0a-9981-4c42-9a6f-2750180613e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085518830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.4085518830 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1352178913 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 34389132 ps |
| CPU time | 5.87 seconds |
| Started | Jul 06 08:08:15 PM PDT 24 |
| Finished | Jul 06 08:08:21 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-fb67ddf2-d51c-4f0f-ad8b-54cff731f13f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352178913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.1352178913 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.1091409950 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 3859922449 ps |
| CPU time | 385.32 seconds |
| Started | Jul 06 08:08:27 PM PDT 24 |
| Finished | Jul 06 08:14:52 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-8f2a69e8-8b75-4be2-903d-989082204188 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091409950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1091409950 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.584185057 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 3993467497 ps |
| CPU time | 252.32 seconds |
| Started | Jul 06 08:08:25 PM PDT 24 |
| Finished | Jul 06 08:12:37 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-d06262f4-fd62-4cb1-a8fc-3ccd6505bd47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584185057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_ with_rand_reset.584185057 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.503048712 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 2674733296 ps |
| CPU time | 138.48 seconds |
| Started | Jul 06 08:08:27 PM PDT 24 |
| Finished | Jul 06 08:10:46 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-51083cda-e8b5-4506-9758-df470e9b26f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503048712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_reset_error.503048712 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.326449167 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 280442464 ps |
| CPU time | 37.05 seconds |
| Started | Jul 06 08:08:23 PM PDT 24 |
| Finished | Jul 06 08:09:01 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-5f678100-c392-4c55-8fd0-8347a6b2f49a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326449167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.326449167 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.900611055 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 3674574870 ps |
| CPU time | 420.63 seconds |
| Started | Jul 06 08:08:53 PM PDT 24 |
| Finished | Jul 06 08:15:54 PM PDT 24 |
| Peak memory | 597852 kb |
| Host | smart-79561234-b64a-4ef1-a091-ee78428cb4f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900611055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.900611055 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.76229245 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 15912653874 ps |
| CPU time | 1946.82 seconds |
| Started | Jul 06 08:08:31 PM PDT 24 |
| Finished | Jul 06 08:40:59 PM PDT 24 |
| Peak memory | 592508 kb |
| Host | smart-993afd4d-d7d2-42c2-80e0-85f596bb5948 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76229245 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.chip_same_csr_outstanding.76229245 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.774611664 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3059279720 ps |
| CPU time | 129.06 seconds |
| Started | Jul 06 08:08:49 PM PDT 24 |
| Finished | Jul 06 08:10:59 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-ae5cbf8c-3788-4560-9231-f62b30a55e4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774611664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device. 774611664 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3037345386 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 124591743922 ps |
| CPU time | 2244 seconds |
| Started | Jul 06 08:08:48 PM PDT 24 |
| Finished | Jul 06 08:46:12 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-8d556393-7991-4558-8dc7-addd99d43a8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037345386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.3037345386 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.1973290452 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 209254722 ps |
| CPU time | 27.07 seconds |
| Started | Jul 06 08:08:47 PM PDT 24 |
| Finished | Jul 06 08:09:14 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-02d05c63-4d46-4dcb-b7e5-f638fdcec089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973290452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.1973290452 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.4185708427 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 298375153 ps |
| CPU time | 30.06 seconds |
| Started | Jul 06 08:08:47 PM PDT 24 |
| Finished | Jul 06 08:09:17 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-26d0fab4-3ac6-4f20-8e27-cadae65805a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185708427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.4185708427 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.3850486997 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 90836361 ps |
| CPU time | 12.74 seconds |
| Started | Jul 06 08:08:41 PM PDT 24 |
| Finished | Jul 06 08:08:54 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-676ac91e-f74c-45d7-8e04-a62b24d68b7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850486997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.3850486997 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.3198131983 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 41036045281 ps |
| CPU time | 396.03 seconds |
| Started | Jul 06 08:08:44 PM PDT 24 |
| Finished | Jul 06 08:15:20 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-cd924fc9-30d2-40f5-9829-1f18333b3545 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198131983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3198131983 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.1070985351 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 40220000736 ps |
| CPU time | 717.36 seconds |
| Started | Jul 06 08:08:42 PM PDT 24 |
| Finished | Jul 06 08:20:40 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-390da74c-6a4b-4d21-a1e8-736d8ec6a1b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070985351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1070985351 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.2396422661 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 539008406 ps |
| CPU time | 53.62 seconds |
| Started | Jul 06 08:08:42 PM PDT 24 |
| Finished | Jul 06 08:09:35 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-7653cd4e-9227-40c1-a26e-42738065c953 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396422661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.2396422661 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.171790130 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 569604101 ps |
| CPU time | 37.41 seconds |
| Started | Jul 06 08:08:43 PM PDT 24 |
| Finished | Jul 06 08:09:20 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-bb9d32c9-8798-40f2-b91e-fcbc48c23f74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171790130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.171790130 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.2392109191 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 44585760 ps |
| CPU time | 6.46 seconds |
| Started | Jul 06 08:08:37 PM PDT 24 |
| Finished | Jul 06 08:08:43 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-62e584be-39a9-4286-8c59-3fe45bc66043 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392109191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2392109191 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1358989404 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 6385367232 ps |
| CPU time | 65.61 seconds |
| Started | Jul 06 08:08:36 PM PDT 24 |
| Finished | Jul 06 08:09:42 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-eac8709b-ee9a-4fbf-99b2-84a3c09ffacd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358989404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1358989404 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2488195814 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 4804020307 ps |
| CPU time | 86.26 seconds |
| Started | Jul 06 08:08:37 PM PDT 24 |
| Finished | Jul 06 08:10:04 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-3bbd4110-f32e-4484-a302-99c92af03d9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488195814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2488195814 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.2688465946 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 44859706 ps |
| CPU time | 7.04 seconds |
| Started | Jul 06 08:08:36 PM PDT 24 |
| Finished | Jul 06 08:08:43 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-9a485ffa-1601-4e89-8376-8033149b7ea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688465946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.2688465946 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.3733906295 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 3950242192 ps |
| CPU time | 182.03 seconds |
| Started | Jul 06 08:08:46 PM PDT 24 |
| Finished | Jul 06 08:11:48 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-ce5b2c49-d21e-466f-8882-ddd3dda39828 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733906295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3733906295 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.1339540597 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 732472053 ps |
| CPU time | 63.39 seconds |
| Started | Jul 06 08:08:48 PM PDT 24 |
| Finished | Jul 06 08:09:52 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-92d4f22c-d20a-4757-91f8-9baaedc0efdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339540597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1339540597 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1387607457 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 3449690759 ps |
| CPU time | 469.77 seconds |
| Started | Jul 06 08:08:47 PM PDT 24 |
| Finished | Jul 06 08:16:37 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-d705e56f-b6e3-4284-ac91-53ac12941958 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387607457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.1387607457 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.243052358 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 1022386266 ps |
| CPU time | 200.27 seconds |
| Started | Jul 06 08:08:53 PM PDT 24 |
| Finished | Jul 06 08:12:14 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-c34a0fe9-f6bf-4142-9607-f2c6ddee838e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243052358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_reset_error.243052358 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.4203411560 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 205523812 ps |
| CPU time | 28.75 seconds |
| Started | Jul 06 08:08:47 PM PDT 24 |
| Finished | Jul 06 08:09:16 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-53ca3ca3-1e5b-4ebd-be49-9d44e917d76d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203411560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.4203411560 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.3443067576 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 4929692568 ps |
| CPU time | 517.85 seconds |
| Started | Jul 06 08:09:30 PM PDT 24 |
| Finished | Jul 06 08:18:08 PM PDT 24 |
| Peak memory | 598764 kb |
| Host | smart-331e2c7f-2dc9-4b2b-9b85-b69dd33d6b1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443067576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.3443067576 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.3473995417 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 14394834471 ps |
| CPU time | 1851.64 seconds |
| Started | Jul 06 08:08:58 PM PDT 24 |
| Finished | Jul 06 08:39:52 PM PDT 24 |
| Peak memory | 592932 kb |
| Host | smart-5e3125f3-e888-437c-9895-6f46259e447e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473995417 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.3473995417 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.2887000646 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 2920213097 ps |
| CPU time | 119.15 seconds |
| Started | Jul 06 08:09:12 PM PDT 24 |
| Finished | Jul 06 08:11:11 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-8af5babf-8559-4f76-b91f-453c37bcc386 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887000646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .2887000646 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.504233430 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 31039749291 ps |
| CPU time | 570.27 seconds |
| Started | Jul 06 08:09:08 PM PDT 24 |
| Finished | Jul 06 08:18:39 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-0b0e1d54-27e9-46cb-b855-62f14165968f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504233430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_d evice_slow_rsp.504233430 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2363704777 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 758375816 ps |
| CPU time | 37.43 seconds |
| Started | Jul 06 08:09:14 PM PDT 24 |
| Finished | Jul 06 08:09:51 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-ad930712-a910-427b-bdce-69472bbdef9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363704777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.2363704777 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.34399024 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 70205638 ps |
| CPU time | 9.37 seconds |
| Started | Jul 06 08:09:09 PM PDT 24 |
| Finished | Jul 06 08:09:18 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-0dc0189c-565a-4020-9ce3-b71fabb16d19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34399024 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.34399024 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.2276769619 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 306459371 ps |
| CPU time | 30.35 seconds |
| Started | Jul 06 08:09:13 PM PDT 24 |
| Finished | Jul 06 08:09:43 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-358185cc-128f-424b-bdd2-79d0500265af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276769619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.2276769619 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.628496808 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 28703739872 ps |
| CPU time | 306.54 seconds |
| Started | Jul 06 08:09:08 PM PDT 24 |
| Finished | Jul 06 08:14:15 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-f48e068c-4926-4a93-9174-61a038ef3483 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628496808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.628496808 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1715987227 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 42345882035 ps |
| CPU time | 720.26 seconds |
| Started | Jul 06 08:09:08 PM PDT 24 |
| Finished | Jul 06 08:21:08 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-f4eb36a1-5179-47d5-94c5-3286c157e514 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715987227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1715987227 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.3976200262 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 446858467 ps |
| CPU time | 45.07 seconds |
| Started | Jul 06 08:09:08 PM PDT 24 |
| Finished | Jul 06 08:09:53 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-c79618ec-e09c-42d4-9894-742f21f92b9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976200262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.3976200262 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.109742259 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 124742896 ps |
| CPU time | 13.3 seconds |
| Started | Jul 06 08:09:09 PM PDT 24 |
| Finished | Jul 06 08:09:23 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-6dcc464d-200d-4e91-b377-41b23eba6a86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109742259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.109742259 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.927284640 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 47717289 ps |
| CPU time | 6.5 seconds |
| Started | Jul 06 08:09:03 PM PDT 24 |
| Finished | Jul 06 08:09:11 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-5b40236f-2499-4a9c-af69-c79a87c2f849 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927284640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.927284640 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.1752049991 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 10352963665 ps |
| CPU time | 109.72 seconds |
| Started | Jul 06 08:09:04 PM PDT 24 |
| Finished | Jul 06 08:10:55 PM PDT 24 |
| Peak memory | 574576 kb |
| Host | smart-68b9a18b-601b-4043-a880-b4120ee74d8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752049991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1752049991 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3699557725 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 6177448994 ps |
| CPU time | 112.22 seconds |
| Started | Jul 06 08:09:04 PM PDT 24 |
| Finished | Jul 06 08:10:57 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-a21bf04a-5490-4001-bc97-cc05d5b61428 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699557725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3699557725 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.4251634810 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 47142482 ps |
| CPU time | 6.88 seconds |
| Started | Jul 06 08:09:03 PM PDT 24 |
| Finished | Jul 06 08:09:11 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-e86c2224-a32a-4768-be6a-23b0b88389cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251634810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.4251634810 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.869003206 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 10460187785 ps |
| CPU time | 444.34 seconds |
| Started | Jul 06 08:09:14 PM PDT 24 |
| Finished | Jul 06 08:16:39 PM PDT 24 |
| Peak memory | 576828 kb |
| Host | smart-b1950b4b-8b34-4ec7-a90e-86946cd5f79b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869003206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.869003206 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.2818438080 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 1838996466 ps |
| CPU time | 165.91 seconds |
| Started | Jul 06 08:09:15 PM PDT 24 |
| Finished | Jul 06 08:12:01 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-a369563c-2915-451d-9c35-878c70305ce1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818438080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2818438080 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1141569180 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 14885606705 ps |
| CPU time | 860.12 seconds |
| Started | Jul 06 08:09:20 PM PDT 24 |
| Finished | Jul 06 08:23:40 PM PDT 24 |
| Peak memory | 576828 kb |
| Host | smart-14923538-fdf1-4104-b31b-bf6924f40317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141569180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.1141569180 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.1631854384 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 650901055 ps |
| CPU time | 33.39 seconds |
| Started | Jul 06 08:09:07 PM PDT 24 |
| Finished | Jul 06 08:09:41 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-bd8ad98c-6441-46d8-be53-cef115cd4bf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631854384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1631854384 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.3917981402 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 5344692152 ps |
| CPU time | 560.9 seconds |
| Started | Jul 06 08:09:33 PM PDT 24 |
| Finished | Jul 06 08:18:54 PM PDT 24 |
| Peak memory | 597228 kb |
| Host | smart-d11dbe91-5e7a-4b93-8581-4785590f886e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917981402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.3917981402 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.3537553489 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 16130383117 ps |
| CPU time | 1892.37 seconds |
| Started | Jul 06 08:09:18 PM PDT 24 |
| Finished | Jul 06 08:40:51 PM PDT 24 |
| Peak memory | 592928 kb |
| Host | smart-dedcc57b-585d-4424-bfa2-d93bd97ba1b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537553489 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.3537553489 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.4214410740 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 2813653449 ps |
| CPU time | 189.43 seconds |
| Started | Jul 06 08:09:18 PM PDT 24 |
| Finished | Jul 06 08:12:28 PM PDT 24 |
| Peak memory | 603652 kb |
| Host | smart-9c742ef0-930d-458e-b623-cd00d63e97e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214410740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.4214410740 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.1606708215 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 1240054648 ps |
| CPU time | 59.31 seconds |
| Started | Jul 06 08:09:23 PM PDT 24 |
| Finished | Jul 06 08:10:23 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-0d3d8b59-758c-4ec3-a0b4-9fe9c1bd0362 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606708215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .1606708215 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.1811270966 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 122488082167 ps |
| CPU time | 2156.17 seconds |
| Started | Jul 06 08:09:24 PM PDT 24 |
| Finished | Jul 06 08:45:20 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-58b5667c-d730-48ce-8fa0-032b572fdf2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811270966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.1811270966 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1786227778 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 273264651 ps |
| CPU time | 37.57 seconds |
| Started | Jul 06 08:09:28 PM PDT 24 |
| Finished | Jul 06 08:10:05 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-74ac0d57-5ada-47c3-aa22-efb9ee2a5b6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786227778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.1786227778 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.495536374 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 1853163325 ps |
| CPU time | 76.15 seconds |
| Started | Jul 06 08:09:31 PM PDT 24 |
| Finished | Jul 06 08:10:47 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-ba347977-4312-4afe-baab-e12a349d6ac2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495536374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.495536374 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.1152820964 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 311295238 ps |
| CPU time | 28.49 seconds |
| Started | Jul 06 08:09:30 PM PDT 24 |
| Finished | Jul 06 08:09:59 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-b1981008-cdf9-46dd-a052-84f8561950f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152820964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.1152820964 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.1668092133 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 7446387463 ps |
| CPU time | 79.36 seconds |
| Started | Jul 06 08:09:23 PM PDT 24 |
| Finished | Jul 06 08:10:42 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-71bba0dd-fe35-4130-9bf7-d4867a75f34d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668092133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1668092133 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.1624303158 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 21197879880 ps |
| CPU time | 406.23 seconds |
| Started | Jul 06 08:09:24 PM PDT 24 |
| Finished | Jul 06 08:16:11 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-690e7183-e775-47e9-af2f-17fc48d4bf54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624303158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1624303158 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.2965649889 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 478285922 ps |
| CPU time | 43.9 seconds |
| Started | Jul 06 08:09:23 PM PDT 24 |
| Finished | Jul 06 08:10:08 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-4f1da9de-d731-41c1-a0b6-0ccae3168f93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965649889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.2965649889 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.3078532253 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 504646052 ps |
| CPU time | 42.77 seconds |
| Started | Jul 06 08:09:23 PM PDT 24 |
| Finished | Jul 06 08:10:06 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-6cdd32db-8584-43aa-b82b-4f769d6aa07a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078532253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3078532253 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.2682607625 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 47866000 ps |
| CPU time | 6.61 seconds |
| Started | Jul 06 08:09:29 PM PDT 24 |
| Finished | Jul 06 08:09:36 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-bcbc2e4d-3eaf-4af2-bca5-c29a63068a84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682607625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2682607625 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.3059339513 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 7401257992 ps |
| CPU time | 76.14 seconds |
| Started | Jul 06 08:09:15 PM PDT 24 |
| Finished | Jul 06 08:10:31 PM PDT 24 |
| Peak memory | 574768 kb |
| Host | smart-fb35f298-3b32-4711-8e71-75b67a9119c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059339513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3059339513 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.343021877 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 6433650840 ps |
| CPU time | 112.22 seconds |
| Started | Jul 06 08:09:29 PM PDT 24 |
| Finished | Jul 06 08:11:22 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-b9d26b32-c188-4743-b07d-ec77e38d53fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343021877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.343021877 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.2906904529 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 46635477 ps |
| CPU time | 6.97 seconds |
| Started | Jul 06 08:09:18 PM PDT 24 |
| Finished | Jul 06 08:09:25 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-0039de6a-8d96-4691-82ed-d151eb0d277d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906904529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.2906904529 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.2794996417 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 1669177677 ps |
| CPU time | 68.09 seconds |
| Started | Jul 06 08:09:28 PM PDT 24 |
| Finished | Jul 06 08:10:36 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-13f914c0-0f5e-443e-8bb1-026825ecde65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794996417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2794996417 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.2930371106 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 8795394880 ps |
| CPU time | 356.31 seconds |
| Started | Jul 06 08:09:30 PM PDT 24 |
| Finished | Jul 06 08:15:27 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-d683ae81-8626-470e-a356-cc7c9fd0c8a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930371106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2930371106 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.4275426121 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 233225684 ps |
| CPU time | 179.76 seconds |
| Started | Jul 06 08:09:33 PM PDT 24 |
| Finished | Jul 06 08:12:33 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-e847c2bc-515c-4ab7-bf57-0b9cd9dd60f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275426121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.4275426121 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.1506855179 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1319374037 ps |
| CPU time | 59.21 seconds |
| Started | Jul 06 08:09:28 PM PDT 24 |
| Finished | Jul 06 08:10:28 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-b215f953-a9d5-4f28-aec7-b154b6cb4376 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506855179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1506855179 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.715025041 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 63762342164 ps |
| CPU time | 9516.57 seconds |
| Started | Jul 06 08:00:35 PM PDT 24 |
| Finished | Jul 06 10:39:13 PM PDT 24 |
| Peak memory | 642420 kb |
| Host | smart-d780f47e-b154-4e0e-82c7-77daabc5497c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715025041 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.chip_csr_aliasing.715025041 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.4039331226 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 6423034550 ps |
| CPU time | 817.78 seconds |
| Started | Jul 06 08:00:29 PM PDT 24 |
| Finished | Jul 06 08:14:07 PM PDT 24 |
| Peak memory | 589168 kb |
| Host | smart-8a125ab7-f8ae-4cd4-82a4-5eb72ffb6993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039331226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.4039331226 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.4221708837 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 4456449692 ps |
| CPU time | 349.54 seconds |
| Started | Jul 06 08:01:29 PM PDT 24 |
| Finished | Jul 06 08:07:19 PM PDT 24 |
| Peak memory | 597124 kb |
| Host | smart-fecbc1c2-87b3-4a6b-be0b-6d6524e5fb62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221708837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.4221708837 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.3901879867 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 7017334094 ps |
| CPU time | 306.5 seconds |
| Started | Jul 06 08:00:34 PM PDT 24 |
| Finished | Jul 06 08:05:41 PM PDT 24 |
| Peak memory | 588696 kb |
| Host | smart-6766529f-5455-4c85-b29a-525269eeb815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901879867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.3901879867 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1065758798 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 12839399506 ps |
| CPU time | 569.76 seconds |
| Started | Jul 06 08:00:38 PM PDT 24 |
| Finished | Jul 06 08:10:08 PM PDT 24 |
| Peak memory | 591048 kb |
| Host | smart-0e0998f3-4f40-4411-a427-0ad7d11ebe79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065758798 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.1065758798 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.2913406231 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 16551859457 ps |
| CPU time | 1941.44 seconds |
| Started | Jul 06 08:00:29 PM PDT 24 |
| Finished | Jul 06 08:32:51 PM PDT 24 |
| Peak memory | 591752 kb |
| Host | smart-010272f1-0c88-4c26-ab6c-0b2eba13cfd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913406231 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.2913406231 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.123605436 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 3219627448 ps |
| CPU time | 195.44 seconds |
| Started | Jul 06 08:00:31 PM PDT 24 |
| Finished | Jul 06 08:03:47 PM PDT 24 |
| Peak memory | 597620 kb |
| Host | smart-48d86143-f178-4d72-924c-80bb7b54b7e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123605436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.123605436 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.3949374632 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 523415169 ps |
| CPU time | 29.63 seconds |
| Started | Jul 06 08:01:23 PM PDT 24 |
| Finished | Jul 06 08:01:53 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-c0febee9-5757-48f7-bc35-21eb8924252a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949374632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 3949374632 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2003435506 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 33419537571 ps |
| CPU time | 612.42 seconds |
| Started | Jul 06 08:01:13 PM PDT 24 |
| Finished | Jul 06 08:11:26 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-2ce9bf69-f11b-4f69-bbf2-bbd91f458e70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003435506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.2003435506 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.3051909173 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 95738252 ps |
| CPU time | 11.84 seconds |
| Started | Jul 06 08:01:18 PM PDT 24 |
| Finished | Jul 06 08:01:30 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-7cfab2f1-9882-4b01-a892-1ae1b5ef2d34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051909173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .3051909173 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.2613378915 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 65515624 ps |
| CPU time | 10.03 seconds |
| Started | Jul 06 08:02:35 PM PDT 24 |
| Finished | Jul 06 08:02:45 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-d0c1ab22-9e07-4a82-93ea-7620a4f44d1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613378915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2613378915 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.2220064021 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 2019100479 ps |
| CPU time | 82.82 seconds |
| Started | Jul 06 08:00:56 PM PDT 24 |
| Finished | Jul 06 08:02:19 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-d466dd74-581a-42f6-9435-6573f371f873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220064021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.2220064021 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.904553990 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 60697203231 ps |
| CPU time | 664.43 seconds |
| Started | Jul 06 08:01:23 PM PDT 24 |
| Finished | Jul 06 08:12:28 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-9c7a9ab9-72cf-4aef-8171-1e64ec060941 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904553990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.904553990 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.4270973885 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 35642540142 ps |
| CPU time | 625.72 seconds |
| Started | Jul 06 08:01:14 PM PDT 24 |
| Finished | Jul 06 08:11:40 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-4631f850-1d6e-463a-9b2a-1021b7976c16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270973885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.4270973885 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.69406099 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 350245309 ps |
| CPU time | 35.48 seconds |
| Started | Jul 06 08:00:56 PM PDT 24 |
| Finished | Jul 06 08:01:32 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-43cff6a7-e650-457e-9f55-08ef82f924a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69406099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays .69406099 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.1373342165 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 1792723593 ps |
| CPU time | 60.57 seconds |
| Started | Jul 06 08:01:22 PM PDT 24 |
| Finished | Jul 06 08:02:23 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-0859f7f7-ccf1-47bf-9a62-2c25765b9c08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373342165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1373342165 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.1445566645 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 259941206 ps |
| CPU time | 9.66 seconds |
| Started | Jul 06 08:00:37 PM PDT 24 |
| Finished | Jul 06 08:00:47 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-74108425-eb5f-4c48-806d-ba8a90e34c38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445566645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1445566645 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.2644140850 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 7599596450 ps |
| CPU time | 78.64 seconds |
| Started | Jul 06 08:00:46 PM PDT 24 |
| Finished | Jul 06 08:02:05 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-0a491734-0e80-4ca5-9806-ca4b3e3bf3cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644140850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2644140850 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.1399892991 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 4045567266 ps |
| CPU time | 81.9 seconds |
| Started | Jul 06 08:01:31 PM PDT 24 |
| Finished | Jul 06 08:02:53 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-3f679bd1-6566-4a8e-b263-21062af51da7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399892991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1399892991 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.4287895383 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 41073258 ps |
| CPU time | 6.51 seconds |
| Started | Jul 06 08:00:45 PM PDT 24 |
| Finished | Jul 06 08:00:51 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-a0340330-dcef-4586-b440-db71ba75a18c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287895383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .4287895383 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.104716758 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 200067819 ps |
| CPU time | 64.3 seconds |
| Started | Jul 06 08:01:22 PM PDT 24 |
| Finished | Jul 06 08:02:27 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-9d68cdf9-92de-4ec8-9445-e0e3d674ab91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104716758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_w ith_rand_reset.104716758 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.2628063426 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 241076704 ps |
| CPU time | 103.15 seconds |
| Started | Jul 06 08:01:29 PM PDT 24 |
| Finished | Jul 06 08:03:13 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-5e89b7dd-2036-4dfd-94df-96fabb937465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628063426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.2628063426 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.4091670227 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 887720646 ps |
| CPU time | 43.41 seconds |
| Started | Jul 06 08:01:18 PM PDT 24 |
| Finished | Jul 06 08:02:02 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-c1195cb3-a28c-4ba7-987f-03c5fa500d38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091670227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.4091670227 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.3586049165 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 688866544 ps |
| CPU time | 64.03 seconds |
| Started | Jul 06 08:09:44 PM PDT 24 |
| Finished | Jul 06 08:10:48 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-65528cc6-3878-41bd-97c7-898fc36bdf1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586049165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .3586049165 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.4093357340 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 98618003156 ps |
| CPU time | 1695.88 seconds |
| Started | Jul 06 08:09:43 PM PDT 24 |
| Finished | Jul 06 08:38:00 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-9c07cb38-b043-496d-94e2-c9b71514b489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093357340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.4093357340 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.1750481760 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 201449787 ps |
| CPU time | 27.01 seconds |
| Started | Jul 06 08:09:48 PM PDT 24 |
| Finished | Jul 06 08:10:16 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-0d972ae3-6968-493e-abc2-95588b9c06a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750481760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.1750481760 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.4143037100 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 1690047932 ps |
| CPU time | 59.2 seconds |
| Started | Jul 06 08:09:49 PM PDT 24 |
| Finished | Jul 06 08:10:48 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-bdffeb47-7368-4c32-bc62-eadd0628815e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143037100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.4143037100 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.1539714554 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 542388189 ps |
| CPU time | 53.38 seconds |
| Started | Jul 06 08:09:42 PM PDT 24 |
| Finished | Jul 06 08:10:36 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-63195936-98d0-4e9d-9f8a-effef2b7d603 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539714554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.1539714554 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.2861112938 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 81431845323 ps |
| CPU time | 871.17 seconds |
| Started | Jul 06 08:09:42 PM PDT 24 |
| Finished | Jul 06 08:24:13 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-6235848e-378a-4202-97a5-9ef6e53f4f3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861112938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2861112938 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.1904728893 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 42093386720 ps |
| CPU time | 713.44 seconds |
| Started | Jul 06 08:09:44 PM PDT 24 |
| Finished | Jul 06 08:21:37 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-78b2ee9d-3eb1-4a52-a626-f4da84d5e917 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904728893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1904728893 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.2266764315 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 641246145 ps |
| CPU time | 60.31 seconds |
| Started | Jul 06 08:09:43 PM PDT 24 |
| Finished | Jul 06 08:10:44 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-f2e1b4f6-0c05-46e6-8e5b-5fcb93bb72e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266764315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.2266764315 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.466896280 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 429799904 ps |
| CPU time | 33.9 seconds |
| Started | Jul 06 08:09:49 PM PDT 24 |
| Finished | Jul 06 08:10:23 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-ab94612a-7bea-472e-a640-909969ff50b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466896280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.466896280 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.901767348 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 44526229 ps |
| CPU time | 7.03 seconds |
| Started | Jul 06 08:09:43 PM PDT 24 |
| Finished | Jul 06 08:09:50 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-0a15ab1e-f6c3-4a65-b0ae-7b1d49ac786b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901767348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.901767348 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.555828136 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 7589789748 ps |
| CPU time | 77.93 seconds |
| Started | Jul 06 08:09:39 PM PDT 24 |
| Finished | Jul 06 08:10:58 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-b07ec8a1-4805-4a50-b60c-3122a4dcab0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555828136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.555828136 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.1095285792 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 4819937988 ps |
| CPU time | 83.08 seconds |
| Started | Jul 06 08:09:38 PM PDT 24 |
| Finished | Jul 06 08:11:02 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-8a8d7426-357b-41d5-b85a-c8736b507a08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095285792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1095285792 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.1186588595 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 45749133 ps |
| CPU time | 6.63 seconds |
| Started | Jul 06 08:09:39 PM PDT 24 |
| Finished | Jul 06 08:09:46 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-900b46f3-f5a4-4408-b8b5-249bc3cb8630 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186588595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.1186588595 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.2229145417 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 1969290377 ps |
| CPU time | 206.08 seconds |
| Started | Jul 06 08:09:49 PM PDT 24 |
| Finished | Jul 06 08:13:16 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-7cc16e36-5a5e-49b2-9840-ce60250f92f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229145417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2229145417 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.1297389691 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 11031105890 ps |
| CPU time | 442.17 seconds |
| Started | Jul 06 08:09:53 PM PDT 24 |
| Finished | Jul 06 08:17:16 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-afb7d0da-2ec4-46bc-a463-459b98050525 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297389691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1297389691 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.3466850694 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 234220571 ps |
| CPU time | 100.25 seconds |
| Started | Jul 06 08:09:48 PM PDT 24 |
| Finished | Jul 06 08:11:29 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-d17546b8-70c2-4539-adad-58ab5644e35c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466850694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.3466850694 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.1427311873 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 1263812167 ps |
| CPU time | 56.84 seconds |
| Started | Jul 06 08:09:50 PM PDT 24 |
| Finished | Jul 06 08:10:47 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-15b4058c-a832-41f4-b1dd-a3ccfb454168 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427311873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1427311873 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.2378101033 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 3538785167 ps |
| CPU time | 225.54 seconds |
| Started | Jul 06 08:09:52 PM PDT 24 |
| Finished | Jul 06 08:13:38 PM PDT 24 |
| Peak memory | 603632 kb |
| Host | smart-83159c0f-c78e-4600-967d-5853889b4bd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378101033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.2378101033 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.3267360446 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 3030584744 ps |
| CPU time | 125.23 seconds |
| Started | Jul 06 08:10:03 PM PDT 24 |
| Finished | Jul 06 08:12:08 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-cd1d4978-7142-467c-ae42-970f2ce68be9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267360446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .3267360446 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.302585334 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 45083461863 ps |
| CPU time | 790.39 seconds |
| Started | Jul 06 08:10:03 PM PDT 24 |
| Finished | Jul 06 08:23:14 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-d765f59f-fec0-4db6-9a79-a56a6799ee1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302585334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_d evice_slow_rsp.302585334 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1315294065 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 629196500 ps |
| CPU time | 30.58 seconds |
| Started | Jul 06 08:10:02 PM PDT 24 |
| Finished | Jul 06 08:10:33 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-036f7870-8e58-400e-b82a-dc3a46ad5ecd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315294065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.1315294065 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.1689207700 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 435455608 ps |
| CPU time | 43.19 seconds |
| Started | Jul 06 08:10:03 PM PDT 24 |
| Finished | Jul 06 08:10:47 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-5e013e4a-7802-4ba0-a86d-fbe345d4c16b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689207700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1689207700 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.3864226010 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 438201557 ps |
| CPU time | 41.14 seconds |
| Started | Jul 06 08:10:01 PM PDT 24 |
| Finished | Jul 06 08:10:42 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-e0783883-4bd4-4e38-af95-c30d63eeaf6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864226010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.3864226010 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.2590901554 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 18442873566 ps |
| CPU time | 196.74 seconds |
| Started | Jul 06 08:09:58 PM PDT 24 |
| Finished | Jul 06 08:13:15 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-9f5e7d73-262d-4e9b-a809-16abbd2b7f7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590901554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2590901554 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.2609365311 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 5274291389 ps |
| CPU time | 90.33 seconds |
| Started | Jul 06 08:10:03 PM PDT 24 |
| Finished | Jul 06 08:11:34 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-d29aea5a-9ed6-4618-9ee3-bff085ecc522 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609365311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2609365311 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.3973602801 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 483265674 ps |
| CPU time | 49.38 seconds |
| Started | Jul 06 08:10:56 PM PDT 24 |
| Finished | Jul 06 08:11:45 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-ad0bdc26-8be3-4b87-93f6-789ddc3c01b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973602801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.3973602801 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.2860778147 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 111488141 ps |
| CPU time | 11.32 seconds |
| Started | Jul 06 08:10:03 PM PDT 24 |
| Finished | Jul 06 08:10:15 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-0d833203-6548-43a3-b2a4-a77ac32eb415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860778147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2860778147 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.3259160330 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 224179337 ps |
| CPU time | 9.78 seconds |
| Started | Jul 06 08:09:59 PM PDT 24 |
| Finished | Jul 06 08:10:09 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-7722f54d-9969-4272-aa5f-ce29ab5f0f1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259160330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3259160330 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.3872370600 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 6199607196 ps |
| CPU time | 65.93 seconds |
| Started | Jul 06 08:09:59 PM PDT 24 |
| Finished | Jul 06 08:11:05 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-ce37aa66-899d-40bf-a33e-af994ca3d8cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872370600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3872370600 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.160353370 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 4471078727 ps |
| CPU time | 80.85 seconds |
| Started | Jul 06 08:09:58 PM PDT 24 |
| Finished | Jul 06 08:11:19 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-6b28b9dd-adff-4eee-8102-0a5e88659491 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160353370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.160353370 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.2404829145 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 56353860 ps |
| CPU time | 7.59 seconds |
| Started | Jul 06 08:09:58 PM PDT 24 |
| Finished | Jul 06 08:10:06 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-cc0cc9ca-941c-4b31-b8fc-a58066ebe173 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404829145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.2404829145 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.2196066285 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 7384556893 ps |
| CPU time | 334.44 seconds |
| Started | Jul 06 08:10:07 PM PDT 24 |
| Finished | Jul 06 08:15:42 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-932b7390-19e1-45e8-b18d-46507ef99c07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196066285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.2196066285 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.2815650450 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 11475625846 ps |
| CPU time | 427.07 seconds |
| Started | Jul 06 08:10:14 PM PDT 24 |
| Finished | Jul 06 08:17:22 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-66279c45-c732-4c53-b4e6-282fabbb8bcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815650450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2815650450 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.196511888 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 192296089 ps |
| CPU time | 60.67 seconds |
| Started | Jul 06 08:10:08 PM PDT 24 |
| Finished | Jul 06 08:11:09 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-99fc503b-8fbe-45c4-8004-e1cd2e71468c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196511888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_ with_rand_reset.196511888 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.382889966 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 1479780091 ps |
| CPU time | 298.82 seconds |
| Started | Jul 06 08:10:14 PM PDT 24 |
| Finished | Jul 06 08:15:14 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-5234d8f7-c247-4f53-90e0-c006e257322c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382889966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_reset_error.382889966 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.4092456046 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 1245393216 ps |
| CPU time | 58.94 seconds |
| Started | Jul 06 08:10:04 PM PDT 24 |
| Finished | Jul 06 08:11:03 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-3182b850-3ec4-475b-a3b6-ada34a38d8b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092456046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.4092456046 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.2922192075 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 4276014424 ps |
| CPU time | 306.74 seconds |
| Started | Jul 06 08:10:08 PM PDT 24 |
| Finished | Jul 06 08:15:15 PM PDT 24 |
| Peak memory | 603428 kb |
| Host | smart-dfdde64c-0007-4a0e-ba93-8f79011fea1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922192075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.2922192075 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.2765985284 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 2063695168 ps |
| CPU time | 103.21 seconds |
| Started | Jul 06 08:10:12 PM PDT 24 |
| Finished | Jul 06 08:11:56 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-e3796cc6-3ca3-43d3-90ee-081dd2f4450c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765985284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device .2765985284 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.1829491668 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 9697474366 ps |
| CPU time | 174.49 seconds |
| Started | Jul 06 08:10:17 PM PDT 24 |
| Finished | Jul 06 08:13:12 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-c903b012-303b-4a10-947b-5df0d24e7c80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829491668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.1829491668 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.2873388473 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 1062472170 ps |
| CPU time | 41.81 seconds |
| Started | Jul 06 08:10:20 PM PDT 24 |
| Finished | Jul 06 08:11:03 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-a95f874b-133e-4f8b-ab9c-fab53011b070 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873388473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.2873388473 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.2757321894 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 427309215 ps |
| CPU time | 43.35 seconds |
| Started | Jul 06 08:10:18 PM PDT 24 |
| Finished | Jul 06 08:11:02 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-ecb10087-e36e-4d99-80a1-7ff218dcf841 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757321894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2757321894 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.637173652 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 1847633860 ps |
| CPU time | 78.99 seconds |
| Started | Jul 06 08:10:13 PM PDT 24 |
| Finished | Jul 06 08:11:32 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-1cf63744-04cc-4ab4-9b95-3c0fd1ab6b85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637173652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.637173652 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.3552789117 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 113555337431 ps |
| CPU time | 1152.4 seconds |
| Started | Jul 06 08:10:17 PM PDT 24 |
| Finished | Jul 06 08:29:30 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-47727d50-49b4-4cc7-8422-692612591c00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552789117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3552789117 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.2240851453 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 41438838217 ps |
| CPU time | 749.63 seconds |
| Started | Jul 06 08:10:20 PM PDT 24 |
| Finished | Jul 06 08:22:50 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-2f2a5b23-0cc8-4288-bc74-0cf8e7ffa22c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240851453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2240851453 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.442762666 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 276342342 ps |
| CPU time | 25.56 seconds |
| Started | Jul 06 08:10:19 PM PDT 24 |
| Finished | Jul 06 08:10:45 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-9c02d937-1069-4b2a-86be-e4c56877d1b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442762666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_dela ys.442762666 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.615436702 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 45712891 ps |
| CPU time | 6.51 seconds |
| Started | Jul 06 08:10:19 PM PDT 24 |
| Finished | Jul 06 08:10:25 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-4a53005e-ee01-4432-b8a6-09c813a62081 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615436702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.615436702 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.1759907901 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 174954405 ps |
| CPU time | 8.7 seconds |
| Started | Jul 06 08:10:07 PM PDT 24 |
| Finished | Jul 06 08:10:16 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-6f465577-2114-4e92-8da5-3f5210c7d29c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759907901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1759907901 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.2488020321 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 8403634660 ps |
| CPU time | 87.46 seconds |
| Started | Jul 06 08:10:17 PM PDT 24 |
| Finished | Jul 06 08:11:44 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-5300e423-0abe-4a4b-ab74-e37ee44632c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488020321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2488020321 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.2401369048 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 5749556056 ps |
| CPU time | 100.45 seconds |
| Started | Jul 06 08:10:14 PM PDT 24 |
| Finished | Jul 06 08:11:55 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-73a96d51-f9e7-4bbd-83e6-d06df9a66baf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401369048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2401369048 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.2198482584 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 54320576 ps |
| CPU time | 7.15 seconds |
| Started | Jul 06 08:10:13 PM PDT 24 |
| Finished | Jul 06 08:10:21 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-f4a2a59f-59ab-4b2a-b543-53b298cb7c4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198482584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.2198482584 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.2819899821 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 1901876554 ps |
| CPU time | 165.84 seconds |
| Started | Jul 06 08:10:16 PM PDT 24 |
| Finished | Jul 06 08:13:03 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-0a43012d-e8a7-4b37-b54d-21a19eaa4952 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819899821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2819899821 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.2324006235 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 45894255 ps |
| CPU time | 23.57 seconds |
| Started | Jul 06 08:10:20 PM PDT 24 |
| Finished | Jul 06 08:10:44 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-d47c4cb6-1e6d-4745-8929-58a18a834f32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324006235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.2324006235 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3589881390 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 12242441801 ps |
| CPU time | 608.6 seconds |
| Started | Jul 06 08:10:23 PM PDT 24 |
| Finished | Jul 06 08:20:32 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-57b5f830-2e87-48ce-a059-de5d0bccec97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589881390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.3589881390 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.115097225 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 942769359 ps |
| CPU time | 42.26 seconds |
| Started | Jul 06 08:10:17 PM PDT 24 |
| Finished | Jul 06 08:11:00 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-07bdbffa-53fa-4d76-99a4-7daf7e3cce25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115097225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.115097225 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.363426740 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 1158360307 ps |
| CPU time | 50.13 seconds |
| Started | Jul 06 08:10:29 PM PDT 24 |
| Finished | Jul 06 08:11:20 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-f1c90542-f838-4e64-b618-8c071f05f8d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363426740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device. 363426740 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.3085537167 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 117743591362 ps |
| CPU time | 1984.82 seconds |
| Started | Jul 06 08:10:29 PM PDT 24 |
| Finished | Jul 06 08:43:34 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-a51a965a-5fcc-40f3-aafd-75d5b886a1e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085537167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.3085537167 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3525762633 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 163312253 ps |
| CPU time | 24.9 seconds |
| Started | Jul 06 08:10:29 PM PDT 24 |
| Finished | Jul 06 08:10:54 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-6c060bc7-5d7b-453a-acba-c030927c2db7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525762633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.3525762633 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.1765639748 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 907244464 ps |
| CPU time | 36 seconds |
| Started | Jul 06 08:10:28 PM PDT 24 |
| Finished | Jul 06 08:11:05 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-b48a302c-34b1-4d9a-9754-1aee2a937432 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765639748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1765639748 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.4076129677 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 321209884 ps |
| CPU time | 35.82 seconds |
| Started | Jul 06 08:10:24 PM PDT 24 |
| Finished | Jul 06 08:11:01 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-27d3f71e-80ec-46c8-8fe1-ee61414051e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076129677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.4076129677 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.662873869 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 9392683572 ps |
| CPU time | 96.56 seconds |
| Started | Jul 06 08:10:26 PM PDT 24 |
| Finished | Jul 06 08:12:02 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-df2d8924-f009-427c-921c-45af335a3a6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662873869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.662873869 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.2312427599 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 65660529748 ps |
| CPU time | 1165.1 seconds |
| Started | Jul 06 08:10:24 PM PDT 24 |
| Finished | Jul 06 08:29:50 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-efd2d66f-e3e0-4d62-83a9-12013b293321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312427599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2312427599 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.3975617143 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 67948977 ps |
| CPU time | 9.7 seconds |
| Started | Jul 06 08:10:24 PM PDT 24 |
| Finished | Jul 06 08:10:34 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-85eafd50-2186-4744-9cc3-2402ae36f062 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975617143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.3975617143 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.3157337211 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 2152635554 ps |
| CPU time | 66.96 seconds |
| Started | Jul 06 08:10:29 PM PDT 24 |
| Finished | Jul 06 08:11:36 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-5e3e7acf-afa2-4f94-b122-91e54b9a6ec6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157337211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3157337211 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.1068607625 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 203410030 ps |
| CPU time | 9.38 seconds |
| Started | Jul 06 08:10:26 PM PDT 24 |
| Finished | Jul 06 08:10:36 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-75c471d0-103d-4d5d-ba20-cb8dd0e4d594 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068607625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1068607625 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.2065410534 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 8396849724 ps |
| CPU time | 88.42 seconds |
| Started | Jul 06 08:10:24 PM PDT 24 |
| Finished | Jul 06 08:11:53 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-e70ae651-a70d-4b57-9f62-d971dbb9db2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065410534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2065410534 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.778739036 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 4492885537 ps |
| CPU time | 81.84 seconds |
| Started | Jul 06 08:10:23 PM PDT 24 |
| Finished | Jul 06 08:11:46 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-7c79de26-729c-4b27-b0c1-a5d0b11df64c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778739036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.778739036 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.983969202 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 47221724 ps |
| CPU time | 6.46 seconds |
| Started | Jul 06 08:10:23 PM PDT 24 |
| Finished | Jul 06 08:10:29 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-db80fee1-666b-4221-acea-bfb9dd70f5a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983969202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays .983969202 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.2020649174 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 2510507118 ps |
| CPU time | 88.45 seconds |
| Started | Jul 06 08:10:38 PM PDT 24 |
| Finished | Jul 06 08:12:07 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-0d1f475b-bb22-41d5-b01d-7960976cbac9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020649174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2020649174 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.3572761632 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 427453527 ps |
| CPU time | 109.31 seconds |
| Started | Jul 06 08:10:39 PM PDT 24 |
| Finished | Jul 06 08:12:28 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-61d28197-42be-439a-8c87-ec2e140ca53b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572761632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.3572761632 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.620853441 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 72061883 ps |
| CPU time | 12.15 seconds |
| Started | Jul 06 08:10:29 PM PDT 24 |
| Finished | Jul 06 08:10:41 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-c29de48c-bc99-4f2b-890b-ce7cc5109a31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620853441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.620853441 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.3834147201 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 3216739110 ps |
| CPU time | 149.68 seconds |
| Started | Jul 06 08:10:44 PM PDT 24 |
| Finished | Jul 06 08:13:14 PM PDT 24 |
| Peak memory | 597368 kb |
| Host | smart-7c889360-79e1-4102-b6b5-2b17babcdd0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834147201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.3834147201 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.3011198446 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 659717063 ps |
| CPU time | 64.92 seconds |
| Started | Jul 06 08:10:54 PM PDT 24 |
| Finished | Jul 06 08:11:59 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-027e50bb-5982-4ae0-9ab1-cc1fdacd466b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011198446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .3011198446 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1862537481 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 105914218685 ps |
| CPU time | 1901.55 seconds |
| Started | Jul 06 08:10:55 PM PDT 24 |
| Finished | Jul 06 08:42:37 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-701e66c4-4445-491c-a45b-2e895866ac0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862537481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.1862537481 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.969710581 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 283012432 ps |
| CPU time | 33.83 seconds |
| Started | Jul 06 08:10:57 PM PDT 24 |
| Finished | Jul 06 08:11:31 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-40a55062-53f6-4f21-a449-65ed8c9b2b9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969710581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr .969710581 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.3766145629 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 1478310855 ps |
| CPU time | 55.47 seconds |
| Started | Jul 06 08:10:55 PM PDT 24 |
| Finished | Jul 06 08:11:51 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-566a7efb-c3e1-49b5-b798-c2a6b13cdebe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766145629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3766145629 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.824288251 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 1220679511 ps |
| CPU time | 40.34 seconds |
| Started | Jul 06 08:10:49 PM PDT 24 |
| Finished | Jul 06 08:11:30 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-aa498235-a29e-49d1-92c3-7d9c36b01415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824288251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.824288251 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.661141602 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 34832291203 ps |
| CPU time | 379.5 seconds |
| Started | Jul 06 08:10:56 PM PDT 24 |
| Finished | Jul 06 08:17:16 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-944db1ad-08a9-432d-979d-dab120fd440a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661141602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.661141602 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.783461086 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 46195261510 ps |
| CPU time | 847.03 seconds |
| Started | Jul 06 08:10:53 PM PDT 24 |
| Finished | Jul 06 08:25:00 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-d2210e9d-a753-42ec-a3c3-fd0a7f42fc56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783461086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.783461086 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.265619255 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 194733342 ps |
| CPU time | 22.05 seconds |
| Started | Jul 06 08:10:49 PM PDT 24 |
| Finished | Jul 06 08:11:11 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-29122002-fe73-4b67-a6a8-c17c149a3338 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265619255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_dela ys.265619255 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.2975552163 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 451825420 ps |
| CPU time | 37.61 seconds |
| Started | Jul 06 08:10:53 PM PDT 24 |
| Finished | Jul 06 08:11:30 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-16e6cbb2-4bea-40f1-94d5-d62623034b3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975552163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2975552163 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.295619358 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 183490686 ps |
| CPU time | 9.64 seconds |
| Started | Jul 06 08:10:52 PM PDT 24 |
| Finished | Jul 06 08:11:02 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-44c98e91-42c1-4aa4-b828-48ef435a2762 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295619358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.295619358 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.1338221856 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 7680363598 ps |
| CPU time | 81.33 seconds |
| Started | Jul 06 08:10:48 PM PDT 24 |
| Finished | Jul 06 08:12:10 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-7ff6fcfc-8a9f-4b0f-bfb6-8d41640236e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338221856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1338221856 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.3320738825 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 5731103985 ps |
| CPU time | 101.81 seconds |
| Started | Jul 06 08:10:53 PM PDT 24 |
| Finished | Jul 06 08:12:35 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-9574a345-186c-4ce4-9bef-786864ef0a6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320738825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3320738825 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.775072873 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 51135074 ps |
| CPU time | 7.18 seconds |
| Started | Jul 06 08:10:47 PM PDT 24 |
| Finished | Jul 06 08:10:55 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-b571f918-86f5-4aae-83c0-424aeb6a8203 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775072873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays .775072873 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.3582796768 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 13431248430 ps |
| CPU time | 554.96 seconds |
| Started | Jul 06 08:10:58 PM PDT 24 |
| Finished | Jul 06 08:20:13 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-c445907f-851c-4594-b72b-fe695211063b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582796768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3582796768 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.656868355 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 2197422362 ps |
| CPU time | 87.62 seconds |
| Started | Jul 06 08:10:58 PM PDT 24 |
| Finished | Jul 06 08:12:26 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-144c6ef7-616b-461b-bd82-bac1c107f693 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656868355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.656868355 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.2749144278 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 6693892322 ps |
| CPU time | 378.6 seconds |
| Started | Jul 06 08:10:58 PM PDT 24 |
| Finished | Jul 06 08:17:17 PM PDT 24 |
| Peak memory | 576828 kb |
| Host | smart-a97e15a4-e623-4863-b152-0c2ae00ad318 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749144278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.2749144278 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.2809724472 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 498249633 ps |
| CPU time | 195.9 seconds |
| Started | Jul 06 08:11:04 PM PDT 24 |
| Finished | Jul 06 08:14:21 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-046e16ed-8562-48a0-8f02-ada9c0a84734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809724472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.2809724472 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.3244613614 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 993831471 ps |
| CPU time | 47.42 seconds |
| Started | Jul 06 08:10:59 PM PDT 24 |
| Finished | Jul 06 08:11:47 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-18e504e9-950d-4181-88d4-522d33384477 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244613614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3244613614 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.1250567990 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 600409634 ps |
| CPU time | 67.34 seconds |
| Started | Jul 06 08:11:10 PM PDT 24 |
| Finished | Jul 06 08:12:18 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-037a5c2c-069e-46f2-9bca-2d6f2117d7f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250567990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .1250567990 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1240370034 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 39506646544 ps |
| CPU time | 683.56 seconds |
| Started | Jul 06 08:11:08 PM PDT 24 |
| Finished | Jul 06 08:22:32 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-efdf528d-fa55-41d8-b28e-c5ef2b51524d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240370034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_ device_slow_rsp.1240370034 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2436789644 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 1230726163 ps |
| CPU time | 55.71 seconds |
| Started | Jul 06 08:11:15 PM PDT 24 |
| Finished | Jul 06 08:12:11 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-48f9b588-1749-44e9-b177-599b1ae378bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436789644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.2436789644 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.2739948615 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 619603087 ps |
| CPU time | 24.99 seconds |
| Started | Jul 06 08:11:11 PM PDT 24 |
| Finished | Jul 06 08:11:36 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-df98f702-1d79-40bc-8fd8-4ac04e62a59f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739948615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2739948615 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.2657802712 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 59970086 ps |
| CPU time | 9.58 seconds |
| Started | Jul 06 08:11:09 PM PDT 24 |
| Finished | Jul 06 08:11:19 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-872fd5b4-9896-468b-b760-06f205ab12fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657802712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.2657802712 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.2058904291 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 32694303855 ps |
| CPU time | 341.69 seconds |
| Started | Jul 06 08:11:09 PM PDT 24 |
| Finished | Jul 06 08:16:51 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-4a9194b2-b030-4b62-b9e4-b085763fb43c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058904291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2058904291 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.3127119972 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 54822278186 ps |
| CPU time | 993.34 seconds |
| Started | Jul 06 08:11:08 PM PDT 24 |
| Finished | Jul 06 08:27:42 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-f84967f4-62fb-4b72-b0ed-6637e382cbe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127119972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3127119972 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.1967174781 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 254282683 ps |
| CPU time | 24.73 seconds |
| Started | Jul 06 08:11:08 PM PDT 24 |
| Finished | Jul 06 08:11:33 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-f2a59f0a-febe-4c3d-b46d-1ec4b35ec649 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967174781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.1967174781 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.694704468 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 389865573 ps |
| CPU time | 15.63 seconds |
| Started | Jul 06 08:11:10 PM PDT 24 |
| Finished | Jul 06 08:11:25 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-b6574168-7aef-4946-92df-3478e2280863 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694704468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.694704468 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.2816921629 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 222708697 ps |
| CPU time | 9.55 seconds |
| Started | Jul 06 08:11:06 PM PDT 24 |
| Finished | Jul 06 08:11:16 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-b46e958d-02c1-48c9-9afc-7eaa2f9c212b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816921629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2816921629 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.3060155070 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 8985116838 ps |
| CPU time | 96.72 seconds |
| Started | Jul 06 08:11:06 PM PDT 24 |
| Finished | Jul 06 08:12:43 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-baf2c873-3de7-41cb-a194-9ee14708751a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060155070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3060155070 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.797481015 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 5492356768 ps |
| CPU time | 96.37 seconds |
| Started | Jul 06 08:11:04 PM PDT 24 |
| Finished | Jul 06 08:12:41 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-69228f00-0044-420e-ab1f-12eac0b0a0d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797481015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.797481015 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.2482029330 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 50109976 ps |
| CPU time | 7 seconds |
| Started | Jul 06 08:11:04 PM PDT 24 |
| Finished | Jul 06 08:11:11 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-4ac1b7e7-a2bf-4ed4-9a71-74e30ca92c6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482029330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.2482029330 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.1637197853 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 7479972473 ps |
| CPU time | 292.33 seconds |
| Started | Jul 06 08:11:14 PM PDT 24 |
| Finished | Jul 06 08:16:06 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-d662f991-3c99-42cb-9025-e5ad49875574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637197853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1637197853 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1722896989 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 67234634 ps |
| CPU time | 23.72 seconds |
| Started | Jul 06 08:11:13 PM PDT 24 |
| Finished | Jul 06 08:11:36 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-d1f534c3-71f9-4598-90f9-ba9f784570e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722896989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.1722896989 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.849864740 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 241666087 ps |
| CPU time | 54.26 seconds |
| Started | Jul 06 08:11:13 PM PDT 24 |
| Finished | Jul 06 08:12:08 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-b2b2c12b-285d-4176-a0b1-7aea69f6e082 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849864740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_reset_error.849864740 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.1636731927 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 264419152 ps |
| CPU time | 32.19 seconds |
| Started | Jul 06 08:11:13 PM PDT 24 |
| Finished | Jul 06 08:11:46 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-bcf5208b-8b7f-48b4-a93f-7af55d03f095 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636731927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1636731927 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.4056136149 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 2898819503 ps |
| CPU time | 204.8 seconds |
| Started | Jul 06 08:11:17 PM PDT 24 |
| Finished | Jul 06 08:14:42 PM PDT 24 |
| Peak memory | 598508 kb |
| Host | smart-0dffd6c3-ea6a-47d1-b2e4-be14dca0afd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056136149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.4056136149 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.4251635574 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 476277060 ps |
| CPU time | 40.15 seconds |
| Started | Jul 06 08:11:29 PM PDT 24 |
| Finished | Jul 06 08:12:09 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-5dbb68c3-2eb7-4246-a5ff-0282ff0321f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251635574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .4251635574 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.1652675909 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 93732939317 ps |
| CPU time | 1579.64 seconds |
| Started | Jul 06 08:11:28 PM PDT 24 |
| Finished | Jul 06 08:37:48 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-6429c11c-156e-47fc-bafb-2a8d9577ad27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652675909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.1652675909 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.4021031715 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 74257036 ps |
| CPU time | 12.42 seconds |
| Started | Jul 06 08:11:27 PM PDT 24 |
| Finished | Jul 06 08:11:40 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-a91be878-aa79-41e6-8ac1-8acdb480444d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021031715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.4021031715 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.3505014961 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 1784942905 ps |
| CPU time | 57.95 seconds |
| Started | Jul 06 08:11:27 PM PDT 24 |
| Finished | Jul 06 08:12:25 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-f85578d5-7187-44e7-8dca-5e5e9042a656 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505014961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3505014961 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.2316029650 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 388199484 ps |
| CPU time | 39.59 seconds |
| Started | Jul 06 08:11:19 PM PDT 24 |
| Finished | Jul 06 08:11:59 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-f2e7868b-4f40-4f67-80a3-cb5ca5abeca7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316029650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.2316029650 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.4265113131 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 97268948109 ps |
| CPU time | 1001.81 seconds |
| Started | Jul 06 08:11:22 PM PDT 24 |
| Finished | Jul 06 08:28:04 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-6d1675f0-1913-48f7-b14f-4a4e73284006 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265113131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.4265113131 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.1811630616 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 38932223197 ps |
| CPU time | 666.63 seconds |
| Started | Jul 06 08:11:20 PM PDT 24 |
| Finished | Jul 06 08:22:27 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-f25e294a-7321-4f35-9a06-bf5ea566dd6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811630616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1811630616 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.925289983 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 280436096 ps |
| CPU time | 29.95 seconds |
| Started | Jul 06 08:11:18 PM PDT 24 |
| Finished | Jul 06 08:11:48 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-89a17c1d-4398-4e79-b6e4-d61b3326ae20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925289983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_dela ys.925289983 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.15226713 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 405626943 ps |
| CPU time | 35.8 seconds |
| Started | Jul 06 08:11:28 PM PDT 24 |
| Finished | Jul 06 08:12:04 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-00e270ba-0a3d-48f2-b53e-833189b35c7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15226713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.15226713 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.1393630516 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 51109174 ps |
| CPU time | 6.88 seconds |
| Started | Jul 06 08:11:13 PM PDT 24 |
| Finished | Jul 06 08:11:20 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-7d2d8bf1-3515-4a72-a1fc-43288bb1f648 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393630516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1393630516 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.2130402114 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 7863674748 ps |
| CPU time | 81.22 seconds |
| Started | Jul 06 08:11:19 PM PDT 24 |
| Finished | Jul 06 08:12:41 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-dd66466e-d0a9-47aa-9495-2f7f3e88cfa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130402114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2130402114 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.2318375097 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 5731592778 ps |
| CPU time | 97.9 seconds |
| Started | Jul 06 08:11:20 PM PDT 24 |
| Finished | Jul 06 08:12:58 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-1b7a200d-f322-4eb5-8aaa-fd9ce0aad595 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318375097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2318375097 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.2766976617 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 32833333 ps |
| CPU time | 5.99 seconds |
| Started | Jul 06 08:11:15 PM PDT 24 |
| Finished | Jul 06 08:11:21 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-341f41ef-6071-415e-8b21-0bcc42154050 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766976617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.2766976617 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.2011223691 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 236194609 ps |
| CPU time | 34.51 seconds |
| Started | Jul 06 08:11:28 PM PDT 24 |
| Finished | Jul 06 08:12:02 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-0709ac54-4352-4859-b8b7-bca3a4a36b83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011223691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2011223691 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.550409390 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 13827431973 ps |
| CPU time | 468.94 seconds |
| Started | Jul 06 08:11:34 PM PDT 24 |
| Finished | Jul 06 08:19:23 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-b68c3ae9-b9b9-4031-b79b-81fcbf2e889d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550409390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.550409390 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.274388201 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 9694719767 ps |
| CPU time | 430.28 seconds |
| Started | Jul 06 08:11:27 PM PDT 24 |
| Finished | Jul 06 08:18:38 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-285b1ded-1746-48c3-ba60-c3d9ed5658b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274388201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_ with_rand_reset.274388201 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2020214114 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 54959450 ps |
| CPU time | 27.25 seconds |
| Started | Jul 06 08:11:33 PM PDT 24 |
| Finished | Jul 06 08:12:01 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-be40e423-eb3c-46c4-b397-a684bb9bf561 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020214114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.2020214114 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.2412536886 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 129678637 ps |
| CPU time | 9.53 seconds |
| Started | Jul 06 08:11:28 PM PDT 24 |
| Finished | Jul 06 08:11:38 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-09f6e3e1-34d7-4f2c-8897-f41ef1349ff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412536886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2412536886 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.2811263693 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 3410173304 ps |
| CPU time | 255.75 seconds |
| Started | Jul 06 08:11:34 PM PDT 24 |
| Finished | Jul 06 08:15:50 PM PDT 24 |
| Peak memory | 597476 kb |
| Host | smart-0745f07b-7afa-4ca9-a36f-914b36c61799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811263693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.2811263693 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.2381898856 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 148239256 ps |
| CPU time | 32.09 seconds |
| Started | Jul 06 08:11:39 PM PDT 24 |
| Finished | Jul 06 08:12:12 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-f1d15315-f231-4d1e-8975-7a17c5e744a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381898856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .2381898856 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.4110069946 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 160873642992 ps |
| CPU time | 2757.34 seconds |
| Started | Jul 06 08:11:44 PM PDT 24 |
| Finished | Jul 06 08:57:41 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-8dbc8b71-5151-462c-bb34-05b61703986a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110069946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.4110069946 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.2211493619 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 1036489280 ps |
| CPU time | 45.23 seconds |
| Started | Jul 06 08:11:44 PM PDT 24 |
| Finished | Jul 06 08:12:30 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-69d6dbc2-cfba-4b20-8fb5-c4cd9e6410fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211493619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.2211493619 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.2238700857 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 251625095 ps |
| CPU time | 24.66 seconds |
| Started | Jul 06 08:11:43 PM PDT 24 |
| Finished | Jul 06 08:12:08 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-c41cd6bf-8c8b-4f52-aa2d-4ae7aba28789 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238700857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2238700857 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.812314474 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 1702575433 ps |
| CPU time | 64.37 seconds |
| Started | Jul 06 08:11:39 PM PDT 24 |
| Finished | Jul 06 08:12:44 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-2f6b62ae-38e1-4b2f-bd42-ffb3815c1814 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812314474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.812314474 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.2749045978 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 65676714384 ps |
| CPU time | 765.29 seconds |
| Started | Jul 06 08:11:41 PM PDT 24 |
| Finished | Jul 06 08:24:27 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-65c41749-c375-4b2d-905e-217cdc5df162 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749045978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2749045978 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.1221229483 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 56562939450 ps |
| CPU time | 1080.6 seconds |
| Started | Jul 06 08:11:37 PM PDT 24 |
| Finished | Jul 06 08:29:38 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-5ac47863-7701-4062-b065-c580134e5ad0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221229483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1221229483 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.4223280602 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 400734171 ps |
| CPU time | 31.36 seconds |
| Started | Jul 06 08:11:38 PM PDT 24 |
| Finished | Jul 06 08:12:10 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-7adf003c-4a29-4aab-a5ba-c4364304923b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223280602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.4223280602 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.3435353109 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 528206098 ps |
| CPU time | 46.64 seconds |
| Started | Jul 06 08:11:44 PM PDT 24 |
| Finished | Jul 06 08:12:31 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-b369fe5a-6bad-4792-95b6-f88fb726424e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435353109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3435353109 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.3219897956 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 50353877 ps |
| CPU time | 7.32 seconds |
| Started | Jul 06 08:11:33 PM PDT 24 |
| Finished | Jul 06 08:11:41 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-385981ed-413e-4123-88a6-130a96301d5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219897956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3219897956 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.3035968734 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 6599341608 ps |
| CPU time | 71.65 seconds |
| Started | Jul 06 08:11:35 PM PDT 24 |
| Finished | Jul 06 08:12:47 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-3531455d-d7f4-48cb-ac41-2386b2e2957d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035968734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3035968734 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.2440693986 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 3577083323 ps |
| CPU time | 61.37 seconds |
| Started | Jul 06 08:11:32 PM PDT 24 |
| Finished | Jul 06 08:12:34 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-697f0ea9-818d-48a3-8cfb-df4baae213a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440693986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2440693986 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.2682983400 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 42593596 ps |
| CPU time | 6.11 seconds |
| Started | Jul 06 08:11:35 PM PDT 24 |
| Finished | Jul 06 08:11:42 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-f2f16cd9-1080-4366-b0bc-efc6a25d36da |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682983400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.2682983400 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.1619318228 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 13422823166 ps |
| CPU time | 561.9 seconds |
| Started | Jul 06 08:11:44 PM PDT 24 |
| Finished | Jul 06 08:21:06 PM PDT 24 |
| Peak memory | 576820 kb |
| Host | smart-016d249c-ad47-4f81-bdf4-dc5c908de35d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619318228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1619318228 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.4484101 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 10585879715 ps |
| CPU time | 446.99 seconds |
| Started | Jul 06 08:11:51 PM PDT 24 |
| Finished | Jul 06 08:19:18 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-f95fb32a-e3a9-49d1-a6a3-df74ccea20a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4484101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.4484101 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.220972275 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 7908399289 ps |
| CPU time | 771.15 seconds |
| Started | Jul 06 08:11:48 PM PDT 24 |
| Finished | Jul 06 08:24:39 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-28da670c-8b06-47fb-8600-9151d40b62f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220972275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_ with_rand_reset.220972275 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3186377726 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 3338675783 ps |
| CPU time | 390.51 seconds |
| Started | Jul 06 08:11:49 PM PDT 24 |
| Finished | Jul 06 08:18:20 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-0f59bb5c-10a5-47fc-833f-47ac1f112c6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186377726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.3186377726 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.3320842095 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 961755492 ps |
| CPU time | 42.88 seconds |
| Started | Jul 06 08:11:44 PM PDT 24 |
| Finished | Jul 06 08:12:27 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-6e3be614-76dc-485f-8774-1dd5976c4835 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320842095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3320842095 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.2034327154 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 3058185600 ps |
| CPU time | 193.26 seconds |
| Started | Jul 06 08:11:51 PM PDT 24 |
| Finished | Jul 06 08:15:04 PM PDT 24 |
| Peak memory | 597400 kb |
| Host | smart-01f79395-5062-406f-826f-5a774706bd33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034327154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.2034327154 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.2015522589 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 1463420877 ps |
| CPU time | 62.37 seconds |
| Started | Jul 06 08:11:56 PM PDT 24 |
| Finished | Jul 06 08:12:59 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-12373888-cc81-4d43-aa14-6625701e0ba9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015522589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .2015522589 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.793744123 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 12619843364 ps |
| CPU time | 229.8 seconds |
| Started | Jul 06 08:11:59 PM PDT 24 |
| Finished | Jul 06 08:15:49 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-e5788836-9373-4eef-b845-a82d65484b88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793744123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_d evice_slow_rsp.793744123 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2048491340 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 136124040 ps |
| CPU time | 8.94 seconds |
| Started | Jul 06 08:11:54 PM PDT 24 |
| Finished | Jul 06 08:12:03 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-d195931a-8585-4b9d-bf21-5093fdfd4fc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048491340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.2048491340 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.1101153808 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 2506029404 ps |
| CPU time | 78.85 seconds |
| Started | Jul 06 08:11:58 PM PDT 24 |
| Finished | Jul 06 08:13:17 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-62714350-c3b4-4ce5-b329-2b6b3feff580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101153808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1101153808 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.1602960792 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 2009169999 ps |
| CPU time | 80.81 seconds |
| Started | Jul 06 08:11:49 PM PDT 24 |
| Finished | Jul 06 08:13:10 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-79a7f737-fccd-4c69-9368-5930795d88b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602960792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.1602960792 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.3575565619 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 22307986116 ps |
| CPU time | 241.8 seconds |
| Started | Jul 06 08:11:56 PM PDT 24 |
| Finished | Jul 06 08:15:58 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-b4065680-e66c-493c-a39a-24fcb74c7f66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575565619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3575565619 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.3821948235 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 54247136469 ps |
| CPU time | 1003.37 seconds |
| Started | Jul 06 08:11:54 PM PDT 24 |
| Finished | Jul 06 08:28:38 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-2026af1f-4505-413d-ab1f-b0e412026654 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821948235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3821948235 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.572818311 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 559866308 ps |
| CPU time | 54.1 seconds |
| Started | Jul 06 08:11:54 PM PDT 24 |
| Finished | Jul 06 08:12:49 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-b1c9585b-cbb9-4745-8714-756af29a45cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572818311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_dela ys.572818311 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.1029955842 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 403305971 ps |
| CPU time | 34.13 seconds |
| Started | Jul 06 08:11:56 PM PDT 24 |
| Finished | Jul 06 08:12:30 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-4e1a2bf9-a0e4-438a-8dc6-8dd7129ac670 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029955842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1029955842 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.49813124 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 41159086 ps |
| CPU time | 6.12 seconds |
| Started | Jul 06 08:11:50 PM PDT 24 |
| Finished | Jul 06 08:11:56 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-1c374817-4695-45ab-bb6e-8d7e499b14fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49813124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.49813124 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.1332869017 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 6944497955 ps |
| CPU time | 70.97 seconds |
| Started | Jul 06 08:11:48 PM PDT 24 |
| Finished | Jul 06 08:12:59 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-a0f6896b-9848-4e95-9a1f-56599f971e99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332869017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1332869017 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.322218765 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 5146282644 ps |
| CPU time | 95.11 seconds |
| Started | Jul 06 08:11:49 PM PDT 24 |
| Finished | Jul 06 08:13:24 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-a4551385-e119-4e42-ba10-8fd75ea19894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322218765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.322218765 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1332299022 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 39767166 ps |
| CPU time | 6.25 seconds |
| Started | Jul 06 08:11:49 PM PDT 24 |
| Finished | Jul 06 08:11:56 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-324fe90e-ae3e-4c09-9caa-6b3af9bf636b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332299022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.1332299022 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.2183751883 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 1273263812 ps |
| CPU time | 123.99 seconds |
| Started | Jul 06 08:12:02 PM PDT 24 |
| Finished | Jul 06 08:14:06 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-aebf389d-a2c4-47da-9669-221dd620b40c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183751883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2183751883 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.153669590 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 14029099371 ps |
| CPU time | 613.6 seconds |
| Started | Jul 06 08:12:03 PM PDT 24 |
| Finished | Jul 06 08:22:17 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-16c23939-2efb-4a83-8d43-ce983547e859 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153669590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.153669590 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.2957926812 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 7147440332 ps |
| CPU time | 698.5 seconds |
| Started | Jul 06 08:12:04 PM PDT 24 |
| Finished | Jul 06 08:23:43 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-91516d68-03f2-4f7a-a296-6eba917264b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957926812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.2957926812 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.3941299912 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 1367878111 ps |
| CPU time | 66.94 seconds |
| Started | Jul 06 08:11:55 PM PDT 24 |
| Finished | Jul 06 08:13:02 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-43fc659b-56b8-48cb-bc98-5e2acd9ad516 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941299912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3941299912 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.3515180938 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 3502408774 ps |
| CPU time | 195.35 seconds |
| Started | Jul 06 08:12:01 PM PDT 24 |
| Finished | Jul 06 08:15:16 PM PDT 24 |
| Peak memory | 598468 kb |
| Host | smart-58736f1f-a772-4164-8356-bdffee0f4c0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515180938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.3515180938 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.2913849588 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 3578679176 ps |
| CPU time | 168.23 seconds |
| Started | Jul 06 08:12:05 PM PDT 24 |
| Finished | Jul 06 08:14:53 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-f7ffecab-8cdb-4731-b579-3af8704e0bcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913849588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .2913849588 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.697431229 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 69867560074 ps |
| CPU time | 1184.15 seconds |
| Started | Jul 06 08:12:05 PM PDT 24 |
| Finished | Jul 06 08:31:50 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-dc6849a7-ecd3-423a-a715-f0ea84b652e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697431229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_d evice_slow_rsp.697431229 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.976144597 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 980622593 ps |
| CPU time | 43 seconds |
| Started | Jul 06 08:12:09 PM PDT 24 |
| Finished | Jul 06 08:12:52 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-c0656752-d0fe-4285-b232-4f54336460e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976144597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr .976144597 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.836169907 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 1971859272 ps |
| CPU time | 78.43 seconds |
| Started | Jul 06 08:12:07 PM PDT 24 |
| Finished | Jul 06 08:13:25 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-77acf9f5-42e4-4e5c-b07a-c38d4ba9a619 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836169907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.836169907 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.2592383994 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 497588076 ps |
| CPU time | 48.86 seconds |
| Started | Jul 06 08:12:04 PM PDT 24 |
| Finished | Jul 06 08:12:53 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-7913befc-650d-4997-b85b-e85bbe2a4051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592383994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.2592383994 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.2789066309 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 91621184129 ps |
| CPU time | 925.5 seconds |
| Started | Jul 06 08:11:59 PM PDT 24 |
| Finished | Jul 06 08:27:25 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-992aa7f7-de5f-431e-849f-20708a533b74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789066309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2789066309 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.440051794 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 14215650089 ps |
| CPU time | 241.68 seconds |
| Started | Jul 06 08:12:00 PM PDT 24 |
| Finished | Jul 06 08:16:02 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-7a05d935-cf20-4864-bc99-7170f423d788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440051794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.440051794 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.678510303 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 109325364 ps |
| CPU time | 13.23 seconds |
| Started | Jul 06 08:11:59 PM PDT 24 |
| Finished | Jul 06 08:12:13 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-1f9b750b-371d-4edf-9f9d-a4c920c3a9ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678510303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_dela ys.678510303 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.4014599825 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 360652772 ps |
| CPU time | 28.98 seconds |
| Started | Jul 06 08:12:05 PM PDT 24 |
| Finished | Jul 06 08:12:35 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-1d41f2ec-1c45-4318-95db-3e2b71df788f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014599825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.4014599825 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.144722005 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 189102902 ps |
| CPU time | 7.94 seconds |
| Started | Jul 06 08:12:01 PM PDT 24 |
| Finished | Jul 06 08:12:09 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-eff2787c-d1bb-4e7d-bdf9-15e0ed729438 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144722005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.144722005 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.2473911672 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 7086323276 ps |
| CPU time | 73.92 seconds |
| Started | Jul 06 08:12:00 PM PDT 24 |
| Finished | Jul 06 08:13:14 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-abb539b9-d38d-40e8-9936-2caee0c7a972 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473911672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2473911672 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.2251786715 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 5247179857 ps |
| CPU time | 95.84 seconds |
| Started | Jul 06 08:11:59 PM PDT 24 |
| Finished | Jul 06 08:13:36 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-40a02a8a-8571-4b6a-94f1-fe5472f90753 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251786715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2251786715 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.190115263 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 47125195 ps |
| CPU time | 6.83 seconds |
| Started | Jul 06 08:11:58 PM PDT 24 |
| Finished | Jul 06 08:12:05 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-fb42ea1e-d16f-4878-a75c-dd31d5ae0757 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190115263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays .190115263 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.2686471052 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 3791403776 ps |
| CPU time | 358.49 seconds |
| Started | Jul 06 08:12:06 PM PDT 24 |
| Finished | Jul 06 08:18:05 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-721c55ee-0034-4c80-9d25-758570fcfb6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686471052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2686471052 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.2708656576 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 4416883646 ps |
| CPU time | 177.13 seconds |
| Started | Jul 06 08:12:05 PM PDT 24 |
| Finished | Jul 06 08:15:02 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-311246cf-0771-4f21-a9aa-3877e0e811ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708656576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2708656576 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1971434486 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 7928988268 ps |
| CPU time | 814.41 seconds |
| Started | Jul 06 08:12:07 PM PDT 24 |
| Finished | Jul 06 08:25:42 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-53c68e0f-c9cd-4f4f-922b-9f4b4ef0f8cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971434486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.1971434486 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2125140508 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 349289056 ps |
| CPU time | 123.07 seconds |
| Started | Jul 06 08:12:05 PM PDT 24 |
| Finished | Jul 06 08:14:09 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-0dadeebb-809f-4ca4-82fb-a2676f6185f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125140508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.2125140508 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.2755053823 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 261088171 ps |
| CPU time | 30.81 seconds |
| Started | Jul 06 08:12:06 PM PDT 24 |
| Finished | Jul 06 08:12:37 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-db40071e-cf1e-41b5-aee1-b2a43188e2c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755053823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2755053823 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.998309524 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 35423948120 ps |
| CPU time | 6060.71 seconds |
| Started | Jul 06 08:01:36 PM PDT 24 |
| Finished | Jul 06 09:42:38 PM PDT 24 |
| Peak memory | 593524 kb |
| Host | smart-392c1d58-7a50-48dc-8c73-f7145d4d93b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998309524 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 3.chip_csr_aliasing.998309524 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.496502233 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 3985356356 ps |
| CPU time | 235.5 seconds |
| Started | Jul 06 08:01:39 PM PDT 24 |
| Finished | Jul 06 08:05:35 PM PDT 24 |
| Peak memory | 589032 kb |
| Host | smart-a015b27b-c96f-4d40-aecc-33b0226ca493 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496502233 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.496502233 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.39794611 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 6243820710 ps |
| CPU time | 743.69 seconds |
| Started | Jul 06 08:02:27 PM PDT 24 |
| Finished | Jul 06 08:14:51 PM PDT 24 |
| Peak memory | 599136 kb |
| Host | smart-c9d0bcd9-a79e-4f2b-86ec-725a3f48d980 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39794611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.39794611 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.3970887347 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 16476468290 ps |
| CPU time | 1674.75 seconds |
| Started | Jul 06 08:01:33 PM PDT 24 |
| Finished | Jul 06 08:29:28 PM PDT 24 |
| Peak memory | 592772 kb |
| Host | smart-3376c816-3da6-4521-89cd-eaf23c7d95ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970887347 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.3970887347 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.2795127005 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 5734492498 ps |
| CPU time | 562.82 seconds |
| Started | Jul 06 08:01:42 PM PDT 24 |
| Finished | Jul 06 08:11:06 PM PDT 24 |
| Peak memory | 603548 kb |
| Host | smart-754774c6-a097-4459-ac33-c42d7966d2b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795127005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.2795127005 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.800155443 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 726962678 ps |
| CPU time | 56.24 seconds |
| Started | Jul 06 08:01:49 PM PDT 24 |
| Finished | Jul 06 08:02:45 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-8edc5dba-5471-4fc4-b310-b8fcc2afb409 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800155443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.800155443 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.2234086688 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 160224302 ps |
| CPU time | 19.84 seconds |
| Started | Jul 06 08:01:57 PM PDT 24 |
| Finished | Jul 06 08:02:17 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-d2e25bd7-9d0b-46c1-8491-e23bfae9e784 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234086688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .2234086688 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.3334628815 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 258765467 ps |
| CPU time | 25.99 seconds |
| Started | Jul 06 08:01:57 PM PDT 24 |
| Finished | Jul 06 08:02:24 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-fa11e78b-6d5d-41ad-a741-5a26ed2ee3f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334628815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3334628815 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.3085457877 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 572062425 ps |
| CPU time | 50.56 seconds |
| Started | Jul 06 08:01:42 PM PDT 24 |
| Finished | Jul 06 08:02:33 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-0d1e8dc5-32e1-4ae8-ab8f-12d30b1aa86f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085457877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.3085457877 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.928148219 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 25318798239 ps |
| CPU time | 271.89 seconds |
| Started | Jul 06 08:01:47 PM PDT 24 |
| Finished | Jul 06 08:06:19 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-e4918263-3db3-4d68-95a6-8d50ea7e4b48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928148219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.928148219 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.2744810232 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 36301853199 ps |
| CPU time | 634.97 seconds |
| Started | Jul 06 08:01:50 PM PDT 24 |
| Finished | Jul 06 08:12:25 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-2181e517-46d4-4d29-817a-95b2091ebff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744810232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2744810232 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.3953702979 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 107672051 ps |
| CPU time | 13.99 seconds |
| Started | Jul 06 08:01:48 PM PDT 24 |
| Finished | Jul 06 08:02:02 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-c60e7d0e-68f0-42f6-9540-9d833dce5398 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953702979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.3953702979 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.4274410152 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 599509280 ps |
| CPU time | 49.74 seconds |
| Started | Jul 06 08:01:54 PM PDT 24 |
| Finished | Jul 06 08:02:44 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-13f6101f-4f52-475e-8f30-2b0dc159501e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274410152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.4274410152 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.3395109043 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 58410674 ps |
| CPU time | 7.72 seconds |
| Started | Jul 06 08:01:32 PM PDT 24 |
| Finished | Jul 06 08:01:40 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-24e398b2-3cdf-48c4-967a-04f2a0d5caca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395109043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3395109043 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.172053360 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 8895197625 ps |
| CPU time | 99.31 seconds |
| Started | Jul 06 08:01:38 PM PDT 24 |
| Finished | Jul 06 08:03:18 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-3e3de514-9659-4e9d-a7f0-78a9fb75728c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172053360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.172053360 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.3140338534 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 5943538315 ps |
| CPU time | 110.62 seconds |
| Started | Jul 06 08:01:42 PM PDT 24 |
| Finished | Jul 06 08:03:32 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-c9f71e94-e4f1-4b79-a953-0e8a33fcd6bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140338534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3140338534 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.209030612 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 40557112 ps |
| CPU time | 6.47 seconds |
| Started | Jul 06 08:01:43 PM PDT 24 |
| Finished | Jul 06 08:01:50 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-7371480d-85f1-4ef5-804e-c526fce1bf98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209030612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays. 209030612 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.1436844648 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 3773416415 ps |
| CPU time | 168.23 seconds |
| Started | Jul 06 08:02:02 PM PDT 24 |
| Finished | Jul 06 08:04:51 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-7ab3c206-51fe-4efd-bb56-7cf26f7dbf4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436844648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1436844648 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.1155013640 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 6500779 ps |
| CPU time | 4.1 seconds |
| Started | Jul 06 08:02:10 PM PDT 24 |
| Finished | Jul 06 08:02:14 PM PDT 24 |
| Peak memory | 565420 kb |
| Host | smart-9cc3de94-a295-4bc0-a765-868dc6ca8809 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155013640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1155013640 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.1700953134 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 2795841444 ps |
| CPU time | 449.8 seconds |
| Started | Jul 06 08:02:12 PM PDT 24 |
| Finished | Jul 06 08:09:42 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-9dede080-4e60-4e36-87c1-aa1c293bd2de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700953134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.1700953134 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2805822491 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 262968819 ps |
| CPU time | 87.06 seconds |
| Started | Jul 06 08:02:11 PM PDT 24 |
| Finished | Jul 06 08:03:38 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-8e6c4d60-9e70-4f3a-b5b5-b40c695252b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805822491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.2805822491 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.3540590808 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 251544063 ps |
| CPU time | 14.37 seconds |
| Started | Jul 06 08:01:57 PM PDT 24 |
| Finished | Jul 06 08:02:11 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-11a66734-1a26-4e5a-ac91-c8fdd950b2fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540590808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3540590808 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.65239858 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 1050611558 ps |
| CPU time | 48.15 seconds |
| Started | Jul 06 08:12:09 PM PDT 24 |
| Finished | Jul 06 08:12:58 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-8a765a5f-58cf-4c76-9729-fbcd45ba1125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65239858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.65239858 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.3362566085 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 133545108844 ps |
| CPU time | 2400.98 seconds |
| Started | Jul 06 08:12:12 PM PDT 24 |
| Finished | Jul 06 08:52:13 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-2c421483-cc6c-44a6-9966-14bfcc67f07d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362566085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.3362566085 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.1402092531 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 878038943 ps |
| CPU time | 38.89 seconds |
| Started | Jul 06 08:12:17 PM PDT 24 |
| Finished | Jul 06 08:12:56 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-d3e1ab7b-c256-4d88-8f2c-a10806a60bf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402092531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.1402092531 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.2853718603 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 273222488 ps |
| CPU time | 12.59 seconds |
| Started | Jul 06 08:12:17 PM PDT 24 |
| Finished | Jul 06 08:12:30 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-57c7f8d5-e3b5-48bd-b263-4e0bafc51723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853718603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2853718603 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.1145105151 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 323949982 ps |
| CPU time | 33.32 seconds |
| Started | Jul 06 08:12:11 PM PDT 24 |
| Finished | Jul 06 08:12:45 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-5445009d-4aeb-4b62-bcef-d2dbc8cc5a6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145105151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.1145105151 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.3801656481 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 35336109432 ps |
| CPU time | 384.23 seconds |
| Started | Jul 06 08:12:11 PM PDT 24 |
| Finished | Jul 06 08:18:35 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-1723af7e-30e9-454c-8ba5-46f9e43cf60c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801656481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3801656481 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.4056039070 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 36571578266 ps |
| CPU time | 623.92 seconds |
| Started | Jul 06 08:12:13 PM PDT 24 |
| Finished | Jul 06 08:22:37 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-4252daa5-d1a5-492b-8ab4-c3b092195932 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056039070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.4056039070 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.2435105005 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 410910211 ps |
| CPU time | 39.7 seconds |
| Started | Jul 06 08:12:11 PM PDT 24 |
| Finished | Jul 06 08:12:51 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-ad905be8-d87a-4a50-8c09-927e04d6157a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435105005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.2435105005 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.1761051737 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 2505738692 ps |
| CPU time | 87.7 seconds |
| Started | Jul 06 08:12:11 PM PDT 24 |
| Finished | Jul 06 08:13:40 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-15e2cb1c-40eb-499e-aaeb-1a2ef67b256f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761051737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1761051737 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.1706797250 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 207681176 ps |
| CPU time | 9.01 seconds |
| Started | Jul 06 08:12:05 PM PDT 24 |
| Finished | Jul 06 08:12:14 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-1aa9be69-5468-4123-804d-509c6d2bf6d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706797250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1706797250 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.3315194969 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 9891122526 ps |
| CPU time | 107.75 seconds |
| Started | Jul 06 08:12:09 PM PDT 24 |
| Finished | Jul 06 08:13:57 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-1536e352-7bcf-4e63-abc1-8a703a59b22c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315194969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3315194969 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.1520423570 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 4883380106 ps |
| CPU time | 91.51 seconds |
| Started | Jul 06 08:12:10 PM PDT 24 |
| Finished | Jul 06 08:13:42 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-708323ef-885d-4f07-a2fd-86eb12fed1df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520423570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1520423570 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2285554006 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 38725317 ps |
| CPU time | 5.86 seconds |
| Started | Jul 06 08:12:05 PM PDT 24 |
| Finished | Jul 06 08:12:11 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-11cd2bd4-d389-479d-92ee-742e9702e1ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285554006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.2285554006 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.2411756905 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 4383803836 ps |
| CPU time | 391.67 seconds |
| Started | Jul 06 08:12:18 PM PDT 24 |
| Finished | Jul 06 08:18:50 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-58d0a04c-5189-4c8a-83f0-0a5f4c993cd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411756905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2411756905 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1027961386 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 12266609004 ps |
| CPU time | 664.54 seconds |
| Started | Jul 06 08:12:16 PM PDT 24 |
| Finished | Jul 06 08:23:21 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-849f7f0f-1273-49c5-a415-24df36687954 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027961386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.1027961386 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2344143201 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 1382931561 ps |
| CPU time | 243.26 seconds |
| Started | Jul 06 08:12:23 PM PDT 24 |
| Finished | Jul 06 08:16:27 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-ab75f7c0-e931-47ea-8d31-30355dafc39f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344143201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.2344143201 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.2674722154 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 1083029056 ps |
| CPU time | 47.4 seconds |
| Started | Jul 06 08:12:17 PM PDT 24 |
| Finished | Jul 06 08:13:05 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-ec8dac01-ca21-4403-b002-65d15d474cd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674722154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2674722154 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.527889292 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 494303208 ps |
| CPU time | 47.58 seconds |
| Started | Jul 06 08:12:27 PM PDT 24 |
| Finished | Jul 06 08:13:15 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-69503acb-49b9-4935-bbea-cfafd75595f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527889292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device. 527889292 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.1175207238 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 113879735609 ps |
| CPU time | 2176.19 seconds |
| Started | Jul 06 08:12:27 PM PDT 24 |
| Finished | Jul 06 08:48:44 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-b648fcac-b817-443e-91c6-7d582d400ca4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175207238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_ device_slow_rsp.1175207238 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3704227514 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 675854085 ps |
| CPU time | 30.55 seconds |
| Started | Jul 06 08:12:28 PM PDT 24 |
| Finished | Jul 06 08:13:00 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-1da6cf0e-42d0-4f12-895c-484c92cc138f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704227514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.3704227514 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.327819234 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 2175954631 ps |
| CPU time | 71.47 seconds |
| Started | Jul 06 08:12:28 PM PDT 24 |
| Finished | Jul 06 08:13:40 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-e00e3d88-6d08-4cf1-af6d-33dd3aaf06be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327819234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.327819234 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.301518381 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 1221959504 ps |
| CPU time | 41.5 seconds |
| Started | Jul 06 08:12:21 PM PDT 24 |
| Finished | Jul 06 08:13:03 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-f3a3a9c6-3c7d-475e-9e57-588f0f537f84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301518381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.301518381 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.2512095497 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 58978887614 ps |
| CPU time | 610.95 seconds |
| Started | Jul 06 08:12:27 PM PDT 24 |
| Finished | Jul 06 08:22:38 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-3c7fcb56-2758-4c96-b97b-7815390333d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512095497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2512095497 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.3904049718 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 45881104788 ps |
| CPU time | 787.7 seconds |
| Started | Jul 06 08:12:28 PM PDT 24 |
| Finished | Jul 06 08:25:37 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-f5aef63f-a20b-4345-95b5-46b09e1527ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904049718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3904049718 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.1696543354 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 307158460 ps |
| CPU time | 30.69 seconds |
| Started | Jul 06 08:12:29 PM PDT 24 |
| Finished | Jul 06 08:13:00 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-669f2f6e-4582-41f9-9d57-f180594958e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696543354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.1696543354 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.226178644 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 2272499632 ps |
| CPU time | 80.53 seconds |
| Started | Jul 06 08:12:28 PM PDT 24 |
| Finished | Jul 06 08:13:49 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-ba8ae212-c16a-4a42-bb8f-f5b1d1f4c07a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226178644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.226178644 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.4227555771 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 215820031 ps |
| CPU time | 10.21 seconds |
| Started | Jul 06 08:12:22 PM PDT 24 |
| Finished | Jul 06 08:12:33 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-d7e9e3b1-7e99-489a-b92b-3ede3121a3bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227555771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.4227555771 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.2186614578 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 9620166734 ps |
| CPU time | 101.36 seconds |
| Started | Jul 06 08:12:25 PM PDT 24 |
| Finished | Jul 06 08:14:06 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-ca85cd90-b97b-4988-b6ea-030f597aaa9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186614578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2186614578 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.4091746225 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 4606929009 ps |
| CPU time | 84.78 seconds |
| Started | Jul 06 08:12:24 PM PDT 24 |
| Finished | Jul 06 08:13:49 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-9489b9d9-3a54-4ca5-a1de-b76c2310718e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091746225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.4091746225 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3582332848 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 41614037 ps |
| CPU time | 6.46 seconds |
| Started | Jul 06 08:12:23 PM PDT 24 |
| Finished | Jul 06 08:12:29 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-c770eff2-fee3-44d7-a764-c96ce4102aef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582332848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.3582332848 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.1103199287 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 3718466610 ps |
| CPU time | 132.59 seconds |
| Started | Jul 06 08:12:31 PM PDT 24 |
| Finished | Jul 06 08:14:45 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-040d3f9b-6135-4c06-8e79-b5a1e128db2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103199287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1103199287 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.1391070863 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 21179559504 ps |
| CPU time | 703.73 seconds |
| Started | Jul 06 08:12:26 PM PDT 24 |
| Finished | Jul 06 08:24:10 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-4e0d11dc-4f6b-49d8-9237-55d728a6bdba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391070863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1391070863 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.443285078 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 516531591 ps |
| CPU time | 53.99 seconds |
| Started | Jul 06 08:12:30 PM PDT 24 |
| Finished | Jul 06 08:13:24 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-e0f9e51e-7df5-445c-ada6-229204ef2359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443285078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_ with_rand_reset.443285078 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1620431736 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 92368693 ps |
| CPU time | 28.67 seconds |
| Started | Jul 06 08:12:27 PM PDT 24 |
| Finished | Jul 06 08:12:56 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-ad259195-1f38-4232-a6ed-74d50e42d4e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620431736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.1620431736 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.2796928664 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 199297521 ps |
| CPU time | 27.37 seconds |
| Started | Jul 06 08:12:31 PM PDT 24 |
| Finished | Jul 06 08:12:59 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-09877c45-6455-4112-aa97-1cb66c0eb54c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796928664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.2796928664 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.2178045599 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 714626906 ps |
| CPU time | 64.19 seconds |
| Started | Jul 06 08:12:40 PM PDT 24 |
| Finished | Jul 06 08:13:45 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-7d999456-02ce-439d-b5b5-67f59a3568c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178045599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .2178045599 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.1823843931 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 65188902702 ps |
| CPU time | 1166.06 seconds |
| Started | Jul 06 08:12:40 PM PDT 24 |
| Finished | Jul 06 08:32:06 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-90e63325-ea77-4f9c-95b1-eb7b8cff5367 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823843931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.1823843931 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1535474598 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 1124509063 ps |
| CPU time | 50.96 seconds |
| Started | Jul 06 08:12:44 PM PDT 24 |
| Finished | Jul 06 08:13:35 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-68c1d419-741a-4ca7-b0e5-63dd23c46259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535474598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.1535474598 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.2424701270 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 290594974 ps |
| CPU time | 27.82 seconds |
| Started | Jul 06 08:12:39 PM PDT 24 |
| Finished | Jul 06 08:13:07 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-afd26e7e-7b3a-4fc3-b2ab-a9ed3e19d78c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424701270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2424701270 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.3607105929 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 1981137983 ps |
| CPU time | 79.48 seconds |
| Started | Jul 06 08:12:36 PM PDT 24 |
| Finished | Jul 06 08:13:56 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-23fb697b-4a14-4771-9c5c-0aa93f2016c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607105929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.3607105929 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.167004377 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 10569835900 ps |
| CPU time | 120.34 seconds |
| Started | Jul 06 08:12:41 PM PDT 24 |
| Finished | Jul 06 08:14:42 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-ffc27f90-2375-49f5-9a1f-2daea9d9a098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167004377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.167004377 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.1176747257 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 27659125506 ps |
| CPU time | 476.21 seconds |
| Started | Jul 06 08:12:43 PM PDT 24 |
| Finished | Jul 06 08:20:40 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-3567fc80-d110-44ff-8295-0f59a94ae4a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176747257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1176747257 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.973078706 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 584575995 ps |
| CPU time | 61.22 seconds |
| Started | Jul 06 08:12:40 PM PDT 24 |
| Finished | Jul 06 08:13:42 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-2b6606f0-df76-46f9-aaa9-5483707c5444 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973078706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_dela ys.973078706 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.2483840555 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 2705604592 ps |
| CPU time | 87.56 seconds |
| Started | Jul 06 08:12:40 PM PDT 24 |
| Finished | Jul 06 08:14:08 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-25c01aa0-13bf-4f5d-8731-79384813aaa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483840555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2483840555 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.2555055039 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 53655627 ps |
| CPU time | 7.27 seconds |
| Started | Jul 06 08:12:36 PM PDT 24 |
| Finished | Jul 06 08:12:44 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-d6ff05b0-ffaa-4913-9566-f79e1fc7130b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555055039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2555055039 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.594164132 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 10450849082 ps |
| CPU time | 116.5 seconds |
| Started | Jul 06 08:12:34 PM PDT 24 |
| Finished | Jul 06 08:14:31 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-e2408f9f-18e7-4ef7-af51-d8999d99e272 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594164132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.594164132 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.3332930078 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 3289289993 ps |
| CPU time | 60.21 seconds |
| Started | Jul 06 08:12:32 PM PDT 24 |
| Finished | Jul 06 08:13:33 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-f41fc3f8-61e8-4d37-a527-d40ce15dbba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332930078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3332930078 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.2385151180 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 50748903 ps |
| CPU time | 6.44 seconds |
| Started | Jul 06 08:12:35 PM PDT 24 |
| Finished | Jul 06 08:12:42 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-30ff4b7f-1e00-484b-aa40-9231c8697cb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385151180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.2385151180 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.2363211525 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 10235164422 ps |
| CPU time | 439.33 seconds |
| Started | Jul 06 08:12:41 PM PDT 24 |
| Finished | Jul 06 08:20:00 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-c0e85496-14cd-46bb-a4c7-019da9b48ab9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363211525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2363211525 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.3750145208 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 3522030090 ps |
| CPU time | 263.62 seconds |
| Started | Jul 06 08:12:47 PM PDT 24 |
| Finished | Jul 06 08:17:11 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-f8b1e911-637e-4e37-b23a-088f4542a7ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750145208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3750145208 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.1841881960 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 1502176192 ps |
| CPU time | 271.81 seconds |
| Started | Jul 06 08:12:45 PM PDT 24 |
| Finished | Jul 06 08:17:17 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-84289c7d-f7c6-4f54-ae45-d1fbc2eb37ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841881960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.1841881960 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.816750959 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 205900964 ps |
| CPU time | 12.34 seconds |
| Started | Jul 06 08:12:44 PM PDT 24 |
| Finished | Jul 06 08:12:56 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-bbc9c9ac-7665-4a96-a5b3-b743bd4c7cb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816750959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.816750959 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.3384895303 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 2655836552 ps |
| CPU time | 116.1 seconds |
| Started | Jul 06 08:12:48 PM PDT 24 |
| Finished | Jul 06 08:14:44 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-a221b0c6-bb5e-4d76-a7f1-9b0b4d99ad54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384895303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .3384895303 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1646996541 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 127572827003 ps |
| CPU time | 2203.1 seconds |
| Started | Jul 06 08:12:48 PM PDT 24 |
| Finished | Jul 06 08:49:31 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-0dea4f6c-bd60-43b1-8c0f-34cccf540c63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646996541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.1646996541 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.2891844746 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 704578178 ps |
| CPU time | 32.39 seconds |
| Started | Jul 06 08:12:52 PM PDT 24 |
| Finished | Jul 06 08:13:25 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-e2b9a63d-430d-4f9a-b052-b07ab121bc5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891844746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.2891844746 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.613053739 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 1961467903 ps |
| CPU time | 73.45 seconds |
| Started | Jul 06 08:12:51 PM PDT 24 |
| Finished | Jul 06 08:14:05 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-505146bb-2228-41ff-9bbe-10d53aff7f08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613053739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.613053739 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.2978899971 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 111037152 ps |
| CPU time | 11.47 seconds |
| Started | Jul 06 08:12:55 PM PDT 24 |
| Finished | Jul 06 08:13:06 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-42dfc042-d297-4724-b8d7-5889ec454e9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978899971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.2978899971 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.1167641341 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 62946249402 ps |
| CPU time | 659.38 seconds |
| Started | Jul 06 08:12:45 PM PDT 24 |
| Finished | Jul 06 08:23:45 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-ce598d1e-4ece-4dec-9a8d-d0f6d38ba99d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167641341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1167641341 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.119365320 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 51707620932 ps |
| CPU time | 992.87 seconds |
| Started | Jul 06 08:12:50 PM PDT 24 |
| Finished | Jul 06 08:29:23 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-85d4e6d6-e5f3-4df9-9fcd-4b86b4694a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119365320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.119365320 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.3836148783 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 473077892 ps |
| CPU time | 46.95 seconds |
| Started | Jul 06 08:12:51 PM PDT 24 |
| Finished | Jul 06 08:13:39 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-0bd7afa8-062e-4da5-a6ac-45eaf6dd385b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836148783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.3836148783 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.3914190235 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 2666241388 ps |
| CPU time | 88.02 seconds |
| Started | Jul 06 08:12:46 PM PDT 24 |
| Finished | Jul 06 08:14:14 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-3088b1fe-7b59-41c9-9858-b43013d82207 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914190235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3914190235 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.663412352 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 211090366 ps |
| CPU time | 10.16 seconds |
| Started | Jul 06 08:12:54 PM PDT 24 |
| Finished | Jul 06 08:13:05 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-e5b53537-98f1-4a49-a540-108d59e60c54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663412352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.663412352 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.1489638264 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 8981058192 ps |
| CPU time | 101.85 seconds |
| Started | Jul 06 08:12:46 PM PDT 24 |
| Finished | Jul 06 08:14:28 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-2bd46e29-2041-428e-8256-d88defa949a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489638264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1489638264 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.39373266 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 4954496505 ps |
| CPU time | 83.83 seconds |
| Started | Jul 06 08:12:54 PM PDT 24 |
| Finished | Jul 06 08:14:19 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-5786d31c-97a1-41f5-ae48-c999d77bb2cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39373266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.39373266 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3793630972 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 35679316 ps |
| CPU time | 6.14 seconds |
| Started | Jul 06 08:12:47 PM PDT 24 |
| Finished | Jul 06 08:12:53 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-a7f25c7d-3b6f-4aa8-a635-b87081568dbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793630972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.3793630972 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.3872968969 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 7327576919 ps |
| CPU time | 283.81 seconds |
| Started | Jul 06 08:12:53 PM PDT 24 |
| Finished | Jul 06 08:17:37 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-5b2d82d0-c5a7-408e-8a5f-86992b6b05a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872968969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3872968969 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.4195270515 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 7885938632 ps |
| CPU time | 280.15 seconds |
| Started | Jul 06 08:12:52 PM PDT 24 |
| Finished | Jul 06 08:17:33 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-daddfc4a-6ab7-499b-983e-c835a4ea6af9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195270515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.4195270515 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2858314947 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 7538499357 ps |
| CPU time | 451.2 seconds |
| Started | Jul 06 08:12:51 PM PDT 24 |
| Finished | Jul 06 08:20:23 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-d332810f-9c54-464e-b45d-9d0284e67e25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858314947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.2858314947 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1798458326 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 9628939788 ps |
| CPU time | 478.05 seconds |
| Started | Jul 06 08:12:53 PM PDT 24 |
| Finished | Jul 06 08:20:52 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-a4b4e1ce-28e8-45ac-a3c7-9e8e2805a326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798458326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.1798458326 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.424416220 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 109052459 ps |
| CPU time | 15.58 seconds |
| Started | Jul 06 08:12:51 PM PDT 24 |
| Finished | Jul 06 08:13:07 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-503bd223-6961-4d4e-9ddd-a90a34227477 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424416220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.424416220 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.3785710479 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 2576084446 ps |
| CPU time | 115.81 seconds |
| Started | Jul 06 08:12:59 PM PDT 24 |
| Finished | Jul 06 08:14:56 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-48156623-df5e-442e-bd9a-550b7c9ec509 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785710479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .3785710479 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.2114336446 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 98373176861 ps |
| CPU time | 1638.01 seconds |
| Started | Jul 06 08:12:58 PM PDT 24 |
| Finished | Jul 06 08:40:16 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-95816ca2-8dc8-4297-a327-7509b4bfbb9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114336446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.2114336446 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3325896277 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 1423711526 ps |
| CPU time | 64.27 seconds |
| Started | Jul 06 08:13:02 PM PDT 24 |
| Finished | Jul 06 08:14:07 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-49ee87aa-0753-4c3d-a286-7596aea4068c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325896277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.3325896277 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.3703416337 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 450898965 ps |
| CPU time | 20.81 seconds |
| Started | Jul 06 08:12:59 PM PDT 24 |
| Finished | Jul 06 08:13:20 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-51562a7a-74b5-473f-9503-91a6a1cb197f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703416337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3703416337 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.2145788148 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 1822695656 ps |
| CPU time | 73.61 seconds |
| Started | Jul 06 08:12:51 PM PDT 24 |
| Finished | Jul 06 08:14:06 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-a4db28e3-400a-47b8-a767-30524ac95744 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145788148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.2145788148 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.3492755970 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 92623230049 ps |
| CPU time | 987.73 seconds |
| Started | Jul 06 08:13:00 PM PDT 24 |
| Finished | Jul 06 08:29:28 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-c23feeaf-ed3e-44f4-996d-c115b7970bb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492755970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3492755970 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.3408134639 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 42902229253 ps |
| CPU time | 763.28 seconds |
| Started | Jul 06 08:13:00 PM PDT 24 |
| Finished | Jul 06 08:25:43 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-59b3e0b9-7d38-451a-9302-0521524b157a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408134639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3408134639 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.3669560792 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 557576431 ps |
| CPU time | 54.3 seconds |
| Started | Jul 06 08:12:52 PM PDT 24 |
| Finished | Jul 06 08:13:47 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-83092e1f-5e2b-4f7e-8e86-d06cddd91e22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669560792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.3669560792 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.3232883655 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 569665287 ps |
| CPU time | 44.54 seconds |
| Started | Jul 06 08:12:57 PM PDT 24 |
| Finished | Jul 06 08:13:42 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-43d2457b-c97d-4049-82d7-39763fd8e2fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232883655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3232883655 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.2240069436 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 206083196 ps |
| CPU time | 9.26 seconds |
| Started | Jul 06 08:12:55 PM PDT 24 |
| Finished | Jul 06 08:13:04 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-692ab2c6-a10f-4d34-b92f-f460a518d9a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240069436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2240069436 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.4292410656 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 8228113419 ps |
| CPU time | 85.33 seconds |
| Started | Jul 06 08:12:53 PM PDT 24 |
| Finished | Jul 06 08:14:19 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-a2989852-ac64-4cc7-bf15-9f8142aea959 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292410656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.4292410656 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1264494900 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 4010079591 ps |
| CPU time | 68.55 seconds |
| Started | Jul 06 08:12:53 PM PDT 24 |
| Finished | Jul 06 08:14:02 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-df1f2901-c16f-48db-9278-a6aa5c162894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264494900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1264494900 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.1763315062 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 44255866 ps |
| CPU time | 6.22 seconds |
| Started | Jul 06 08:12:52 PM PDT 24 |
| Finished | Jul 06 08:12:59 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-c9dc8f34-60a4-49b9-81ac-e842a023d44b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763315062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.1763315062 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.1433763498 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 411212182 ps |
| CPU time | 38.34 seconds |
| Started | Jul 06 08:13:06 PM PDT 24 |
| Finished | Jul 06 08:13:45 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-2437f230-7e02-44cc-80c1-7e2ccf3285a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433763498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1433763498 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1030444310 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 6565549 ps |
| CPU time | 3.94 seconds |
| Started | Jul 06 08:13:04 PM PDT 24 |
| Finished | Jul 06 08:13:08 PM PDT 24 |
| Peak memory | 565400 kb |
| Host | smart-acf3e1ab-586a-41fe-b193-00244a068550 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030444310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1030444310 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2786006101 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 179232109 ps |
| CPU time | 25.33 seconds |
| Started | Jul 06 08:13:06 PM PDT 24 |
| Finished | Jul 06 08:13:32 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-40eb9f92-cc65-4419-8a05-6c4b96d58e7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786006101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.2786006101 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.1774180170 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 29781023 ps |
| CPU time | 20.51 seconds |
| Started | Jul 06 08:13:02 PM PDT 24 |
| Finished | Jul 06 08:13:23 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-f1736021-1e8b-419c-af31-779f34c447af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774180170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.1774180170 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.1420636675 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 182948146 ps |
| CPU time | 27.61 seconds |
| Started | Jul 06 08:13:04 PM PDT 24 |
| Finished | Jul 06 08:13:32 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-d4ab48e5-1972-4771-ba1b-c384ba39037e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420636675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1420636675 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.3917915407 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 392824843 ps |
| CPU time | 33.1 seconds |
| Started | Jul 06 08:13:09 PM PDT 24 |
| Finished | Jul 06 08:13:42 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-5a746447-d64a-4750-8408-24b5e94b021e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917915407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .3917915407 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3584660097 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 32415239066 ps |
| CPU time | 557.48 seconds |
| Started | Jul 06 08:13:10 PM PDT 24 |
| Finished | Jul 06 08:22:27 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-48a54566-9233-4ac2-9132-032d158e2524 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584660097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.3584660097 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3886550083 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 39686590 ps |
| CPU time | 8.06 seconds |
| Started | Jul 06 08:13:14 PM PDT 24 |
| Finished | Jul 06 08:13:23 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-d7ee17a8-5e61-48c4-9ef9-a781f47bf24b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886550083 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.3886550083 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.3811740676 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 1675153911 ps |
| CPU time | 56.55 seconds |
| Started | Jul 06 08:13:16 PM PDT 24 |
| Finished | Jul 06 08:14:13 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-c07b11f5-e2f1-459d-8a3a-d5e1adef77ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811740676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3811740676 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.3895480096 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 258981100 ps |
| CPU time | 21.44 seconds |
| Started | Jul 06 08:13:11 PM PDT 24 |
| Finished | Jul 06 08:13:33 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-08c5c2aa-adb5-46da-b992-403655caf197 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895480096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.3895480096 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.401631056 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 4358402292 ps |
| CPU time | 47.46 seconds |
| Started | Jul 06 08:13:10 PM PDT 24 |
| Finished | Jul 06 08:13:57 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-98c368ee-129a-449f-9558-81ea9d7cc404 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401631056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.401631056 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.1479703657 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 48179931113 ps |
| CPU time | 893.52 seconds |
| Started | Jul 06 08:13:09 PM PDT 24 |
| Finished | Jul 06 08:28:03 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-5751b170-0466-424f-a49e-3527f081e9e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479703657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1479703657 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.3994651836 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 553447991 ps |
| CPU time | 52.18 seconds |
| Started | Jul 06 08:13:10 PM PDT 24 |
| Finished | Jul 06 08:14:03 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-a6f77173-6dad-4eff-b743-ca3dbad59b96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994651836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del ays.3994651836 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.2655078446 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 2408279607 ps |
| CPU time | 74.43 seconds |
| Started | Jul 06 08:13:25 PM PDT 24 |
| Finished | Jul 06 08:14:40 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-4c22b96a-b6de-4644-8880-3f5f1e16adad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655078446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2655078446 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.3437287506 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 212703686 ps |
| CPU time | 10 seconds |
| Started | Jul 06 08:13:03 PM PDT 24 |
| Finished | Jul 06 08:13:14 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-07155b2e-eced-4453-9476-58b3aa8c217c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437287506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3437287506 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.1115694919 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 8535380224 ps |
| CPU time | 92.2 seconds |
| Started | Jul 06 08:13:10 PM PDT 24 |
| Finished | Jul 06 08:14:43 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-61ebc880-7c83-47a3-a6cd-c090c157005a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115694919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1115694919 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.4028149566 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 6021099284 ps |
| CPU time | 107.12 seconds |
| Started | Jul 06 08:13:11 PM PDT 24 |
| Finished | Jul 06 08:14:58 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-25844bf1-3098-4e75-a783-1cc1695a3c93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028149566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.4028149566 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.4115733853 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 38952095 ps |
| CPU time | 5.77 seconds |
| Started | Jul 06 08:13:10 PM PDT 24 |
| Finished | Jul 06 08:13:16 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-2c20e525-a3d3-4989-9237-6891faf6d782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115733853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.4115733853 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.2561897644 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 1301444184 ps |
| CPU time | 61.79 seconds |
| Started | Jul 06 08:13:25 PM PDT 24 |
| Finished | Jul 06 08:14:27 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-eeec2e15-e8c6-4ee3-9d0b-8515531d7b20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561897644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2561897644 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.1447111136 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 12172529845 ps |
| CPU time | 428.88 seconds |
| Started | Jul 06 08:13:14 PM PDT 24 |
| Finished | Jul 06 08:20:24 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-8e8a0f75-0cb5-417a-b74a-bafbed49de6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447111136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1447111136 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.221317130 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 59526306 ps |
| CPU time | 71.42 seconds |
| Started | Jul 06 08:13:19 PM PDT 24 |
| Finished | Jul 06 08:14:30 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-fab6d80b-0d70-4d95-9dfc-e6706de48404 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221317130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_ with_rand_reset.221317130 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.438888354 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 7626519 ps |
| CPU time | 13.2 seconds |
| Started | Jul 06 08:13:16 PM PDT 24 |
| Finished | Jul 06 08:13:30 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-cf03ac48-4f46-4ef0-91d1-7ea56c5f2cba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438888354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_reset_error.438888354 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.1926785117 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 109802304 ps |
| CPU time | 16.63 seconds |
| Started | Jul 06 08:13:15 PM PDT 24 |
| Finished | Jul 06 08:13:32 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-4104c4ae-8673-4714-a366-ca2b980df82a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926785117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1926785117 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.4086664506 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 807433926 ps |
| CPU time | 80.02 seconds |
| Started | Jul 06 08:13:21 PM PDT 24 |
| Finished | Jul 06 08:14:41 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-99ecdc85-ce2b-4d90-bb0a-71b09686ebb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086664506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .4086664506 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1966706167 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 54939870928 ps |
| CPU time | 968.86 seconds |
| Started | Jul 06 08:13:22 PM PDT 24 |
| Finished | Jul 06 08:29:32 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-04741086-22f1-418c-9a92-0d78616cef1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966706167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.1966706167 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.2301604754 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1272420142 ps |
| CPU time | 56.69 seconds |
| Started | Jul 06 08:13:26 PM PDT 24 |
| Finished | Jul 06 08:14:23 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-83786bec-261e-40a8-bd4a-f488af2ec40f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301604754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.2301604754 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.1205751019 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 615438221 ps |
| CPU time | 23.53 seconds |
| Started | Jul 06 08:13:30 PM PDT 24 |
| Finished | Jul 06 08:13:54 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-2c9c9838-bb44-4ea6-970e-e2ea3d80324c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205751019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1205751019 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.389846383 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 571595466 ps |
| CPU time | 24.26 seconds |
| Started | Jul 06 08:13:20 PM PDT 24 |
| Finished | Jul 06 08:13:44 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-e27eb11e-97d6-440f-97f2-dbdcbe352396 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389846383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.389846383 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.2323367225 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 67240533233 ps |
| CPU time | 721.37 seconds |
| Started | Jul 06 08:13:14 PM PDT 24 |
| Finished | Jul 06 08:25:15 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-d3554340-a0af-4fe9-885a-8d9c325397c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323367225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2323367225 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.1182218015 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 65430110514 ps |
| CPU time | 1095.29 seconds |
| Started | Jul 06 08:13:21 PM PDT 24 |
| Finished | Jul 06 08:31:36 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-cec24fa2-6012-4ec4-8b75-901356daec4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182218015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1182218015 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.2320796542 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 276889524 ps |
| CPU time | 27.4 seconds |
| Started | Jul 06 08:13:25 PM PDT 24 |
| Finished | Jul 06 08:13:53 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-dff671d3-b5e9-4317-98cc-a0633cc55b41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320796542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.2320796542 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.3850042836 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 826644737 ps |
| CPU time | 27.46 seconds |
| Started | Jul 06 08:13:20 PM PDT 24 |
| Finished | Jul 06 08:13:48 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-fdd474f6-b263-438b-9e0e-52a6e1a4950e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850042836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3850042836 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.2997994041 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 47942758 ps |
| CPU time | 6.55 seconds |
| Started | Jul 06 08:13:20 PM PDT 24 |
| Finished | Jul 06 08:13:26 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-1cbeec5a-1feb-4387-b939-92a8f97f9ecd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997994041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2997994041 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.4097057103 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 9070655270 ps |
| CPU time | 92.77 seconds |
| Started | Jul 06 08:13:17 PM PDT 24 |
| Finished | Jul 06 08:14:50 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-ad163dc6-1110-48f5-8a2b-a914ef5a9bfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097057103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.4097057103 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.3837906759 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 5348073869 ps |
| CPU time | 94.37 seconds |
| Started | Jul 06 08:13:15 PM PDT 24 |
| Finished | Jul 06 08:14:49 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-6f56a56b-6777-44e4-ac73-d7e9182d1c30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837906759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3837906759 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.2981891887 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 54355949 ps |
| CPU time | 7.05 seconds |
| Started | Jul 06 08:13:25 PM PDT 24 |
| Finished | Jul 06 08:13:32 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-5dad694e-87f9-44a0-87aa-2fd9dda939a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981891887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.2981891887 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.1267040473 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 14101359564 ps |
| CPU time | 563.17 seconds |
| Started | Jul 06 08:13:24 PM PDT 24 |
| Finished | Jul 06 08:22:48 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-d06856c5-4740-466e-a59e-0b5ca76e986d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267040473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1267040473 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.2198311303 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 3591848669 ps |
| CPU time | 296.63 seconds |
| Started | Jul 06 08:13:37 PM PDT 24 |
| Finished | Jul 06 08:18:34 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-d1bb06ef-9299-4155-b86b-503ba169f682 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198311303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2198311303 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.3361999960 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 2684420790 ps |
| CPU time | 499.63 seconds |
| Started | Jul 06 08:13:37 PM PDT 24 |
| Finished | Jul 06 08:21:57 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-a27d293e-fdbe-49db-8a17-26c2f1208c58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361999960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.3361999960 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.3204434692 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 7043254 ps |
| CPU time | 8.6 seconds |
| Started | Jul 06 08:13:32 PM PDT 24 |
| Finished | Jul 06 08:13:41 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-6a57b621-9c4e-414e-abc0-9735cf7b2d07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204434692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.3204434692 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.2522580508 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 314153578 ps |
| CPU time | 40.42 seconds |
| Started | Jul 06 08:13:31 PM PDT 24 |
| Finished | Jul 06 08:14:11 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-522c23e6-54a7-48cf-b2fc-0e918961052c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522580508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2522580508 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.2922655538 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 785809864 ps |
| CPU time | 63.23 seconds |
| Started | Jul 06 08:13:35 PM PDT 24 |
| Finished | Jul 06 08:14:39 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-4e315b59-5355-4cf9-b444-9c616637f4e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922655538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .2922655538 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.2450940122 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 61505842152 ps |
| CPU time | 1161.26 seconds |
| Started | Jul 06 08:13:35 PM PDT 24 |
| Finished | Jul 06 08:32:57 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-09da4de2-c5db-463d-8e90-9b70dec12d3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450940122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.2450940122 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.3940460420 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 416769732 ps |
| CPU time | 19.92 seconds |
| Started | Jul 06 08:13:37 PM PDT 24 |
| Finished | Jul 06 08:13:57 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-4534a61c-e96e-400f-899b-c1bd1198812e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940460420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.3940460420 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.1985724374 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 193858334 ps |
| CPU time | 10.31 seconds |
| Started | Jul 06 08:13:36 PM PDT 24 |
| Finished | Jul 06 08:13:47 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-b1a1c856-46f3-4ed4-a528-87f02e6ced54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985724374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1985724374 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.683296222 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 2226099981 ps |
| CPU time | 81.38 seconds |
| Started | Jul 06 08:13:33 PM PDT 24 |
| Finished | Jul 06 08:14:55 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-2ab7e185-19d3-498c-bddd-4ac95c76fd9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683296222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.683296222 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.4255513394 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 57560094730 ps |
| CPU time | 619.95 seconds |
| Started | Jul 06 08:13:35 PM PDT 24 |
| Finished | Jul 06 08:23:56 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-7f21d300-79de-429b-a3fa-ec4dfef3c421 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255513394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.4255513394 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.1429660842 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 46654324469 ps |
| CPU time | 870.22 seconds |
| Started | Jul 06 08:13:36 PM PDT 24 |
| Finished | Jul 06 08:28:07 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-4e8e79d3-0199-4016-a082-21af3aba0e51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429660842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1429660842 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.1323069373 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 289016796 ps |
| CPU time | 28.29 seconds |
| Started | Jul 06 08:13:36 PM PDT 24 |
| Finished | Jul 06 08:14:05 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-5cda2e8d-7d18-498f-b013-ca8848d4d9cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323069373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.1323069373 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.870317660 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 163509879 ps |
| CPU time | 13.86 seconds |
| Started | Jul 06 08:13:41 PM PDT 24 |
| Finished | Jul 06 08:13:55 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-ea09307f-8d63-4ebd-aa7a-5780a2f80055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870317660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.870317660 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.2587636338 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 45988981 ps |
| CPU time | 6.95 seconds |
| Started | Jul 06 08:13:31 PM PDT 24 |
| Finished | Jul 06 08:13:39 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-a43e5b08-1fb2-457f-9712-2241a918880d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587636338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2587636338 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.391374965 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 7883590733 ps |
| CPU time | 80.92 seconds |
| Started | Jul 06 08:13:32 PM PDT 24 |
| Finished | Jul 06 08:14:54 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-e317c213-7665-446d-a48b-494e2bce399e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391374965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.391374965 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.2518494503 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 5894047264 ps |
| CPU time | 104.07 seconds |
| Started | Jul 06 08:13:31 PM PDT 24 |
| Finished | Jul 06 08:15:15 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-505ae566-419b-450e-92d2-9c4ac86e8f31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518494503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2518494503 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.595866138 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 43283675 ps |
| CPU time | 6.72 seconds |
| Started | Jul 06 08:13:37 PM PDT 24 |
| Finished | Jul 06 08:13:44 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-8d858d23-d732-41e7-ad9e-6e69a18afc9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595866138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays .595866138 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.1588376699 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 7222131739 ps |
| CPU time | 282.85 seconds |
| Started | Jul 06 08:13:36 PM PDT 24 |
| Finished | Jul 06 08:18:20 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-c8cba2db-7ac4-4a74-8b5d-f4e10392cb67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588376699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1588376699 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.2008951739 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 3931607827 ps |
| CPU time | 150.79 seconds |
| Started | Jul 06 08:13:35 PM PDT 24 |
| Finished | Jul 06 08:16:07 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-9a8f584d-23b4-488c-ba85-4b6e614db4eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008951739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2008951739 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.1246028866 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 6698561297 ps |
| CPU time | 515.18 seconds |
| Started | Jul 06 08:13:35 PM PDT 24 |
| Finished | Jul 06 08:22:11 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-c3b6afa2-06e4-4c42-aad1-9f484294306b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246028866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.1246028866 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2373684473 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 19956856099 ps |
| CPU time | 853.78 seconds |
| Started | Jul 06 08:13:37 PM PDT 24 |
| Finished | Jul 06 08:27:51 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-1402eb38-95a0-479a-9a6f-36bfdd53f69c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373684473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.2373684473 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.930952982 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 322045741 ps |
| CPU time | 43.96 seconds |
| Started | Jul 06 08:13:37 PM PDT 24 |
| Finished | Jul 06 08:14:22 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-3d997d52-2ef5-4ec1-8155-a798d6c998d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930952982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.930952982 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.2422436793 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 1804656495 ps |
| CPU time | 76.36 seconds |
| Started | Jul 06 08:13:44 PM PDT 24 |
| Finished | Jul 06 08:15:01 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-e579608f-3f41-4a75-a0aa-cd29a33bf494 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422436793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .2422436793 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.2885221410 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 25886717 ps |
| CPU time | 5.95 seconds |
| Started | Jul 06 08:13:49 PM PDT 24 |
| Finished | Jul 06 08:13:55 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-e79bcc71-3e62-499f-9004-509a5778897e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885221410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.2885221410 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.3668500194 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 94786264 ps |
| CPU time | 11.12 seconds |
| Started | Jul 06 08:13:48 PM PDT 24 |
| Finished | Jul 06 08:14:00 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-71a8f588-b73a-48db-83e9-998f2bea602b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668500194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3668500194 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.3870211527 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 505951366 ps |
| CPU time | 22.61 seconds |
| Started | Jul 06 08:13:43 PM PDT 24 |
| Finished | Jul 06 08:14:06 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-dc756083-612f-4f13-b6e1-4681e5a2726a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870211527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.3870211527 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.297369801 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 34012108291 ps |
| CPU time | 378.78 seconds |
| Started | Jul 06 08:13:43 PM PDT 24 |
| Finished | Jul 06 08:20:02 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-0bb8d44d-6cfe-42af-afc0-e5bc3b8abb19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297369801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.297369801 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.3842716401 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 58933282307 ps |
| CPU time | 1074.59 seconds |
| Started | Jul 06 08:13:42 PM PDT 24 |
| Finished | Jul 06 08:31:37 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-73c9de5d-fb4b-48f0-ba79-0aeb3fc12519 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842716401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3842716401 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.628267397 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 285564207 ps |
| CPU time | 27.2 seconds |
| Started | Jul 06 08:13:45 PM PDT 24 |
| Finished | Jul 06 08:14:12 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-ff21ce16-e9e1-4eb3-b77d-5f09039a7147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628267397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_dela ys.628267397 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.1284362119 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 52268012 ps |
| CPU time | 7.12 seconds |
| Started | Jul 06 08:13:49 PM PDT 24 |
| Finished | Jul 06 08:13:56 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-b76a31f4-37ff-4020-a9f4-16d490b7f3ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284362119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1284362119 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.3224645309 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 240584064 ps |
| CPU time | 10.95 seconds |
| Started | Jul 06 08:13:36 PM PDT 24 |
| Finished | Jul 06 08:13:48 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-f1d94570-e2f8-426e-8b58-c72d4b3cbd51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224645309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3224645309 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.590364287 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 8565193519 ps |
| CPU time | 88.45 seconds |
| Started | Jul 06 08:13:41 PM PDT 24 |
| Finished | Jul 06 08:15:09 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-94d2a6b2-1699-4ad4-80e1-134de3937376 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590364287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.590364287 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.423806594 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 3380838305 ps |
| CPU time | 63.7 seconds |
| Started | Jul 06 08:13:42 PM PDT 24 |
| Finished | Jul 06 08:14:46 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-db5f8f89-148d-498e-ac96-2374532913c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423806594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.423806594 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1569683429 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 55750186 ps |
| CPU time | 6.78 seconds |
| Started | Jul 06 08:13:45 PM PDT 24 |
| Finished | Jul 06 08:13:52 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-c31d7841-cbc7-4ff9-8692-2dcce7d1f546 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569683429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.1569683429 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.1582846007 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 4448352746 ps |
| CPU time | 390.34 seconds |
| Started | Jul 06 08:13:47 PM PDT 24 |
| Finished | Jul 06 08:20:18 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-3fb100cf-89ac-4ba0-8862-e986de18b69c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582846007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1582846007 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2972381506 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 317506041 ps |
| CPU time | 174.49 seconds |
| Started | Jul 06 08:13:48 PM PDT 24 |
| Finished | Jul 06 08:16:43 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-37c5c225-a592-4cfc-8864-55b38aae9871 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972381506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.2972381506 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2807384957 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 488215721 ps |
| CPU time | 156.36 seconds |
| Started | Jul 06 08:13:53 PM PDT 24 |
| Finished | Jul 06 08:16:30 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-aa7aa87c-f277-492d-ad4c-2a1e66c91eb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807384957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.2807384957 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.1556156783 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 251572354 ps |
| CPU time | 31.79 seconds |
| Started | Jul 06 08:13:48 PM PDT 24 |
| Finished | Jul 06 08:14:21 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-56d8ce66-eebe-4e31-b324-430976dc9602 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556156783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1556156783 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.1792940291 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 396588644 ps |
| CPU time | 44.65 seconds |
| Started | Jul 06 08:13:59 PM PDT 24 |
| Finished | Jul 06 08:14:44 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-2680b10b-ae59-4ec8-aeb0-9d94ea6fe1a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792940291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .1792940291 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.4226326713 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 110283013333 ps |
| CPU time | 2010.6 seconds |
| Started | Jul 06 08:14:04 PM PDT 24 |
| Finished | Jul 06 08:47:35 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-8b2c3225-1081-40f7-996d-02e744e5e75e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226326713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.4226326713 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.3954639590 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 152263034 ps |
| CPU time | 18.99 seconds |
| Started | Jul 06 08:14:09 PM PDT 24 |
| Finished | Jul 06 08:14:29 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-6f7db400-e871-471d-a079-c08d7099be4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954639590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.3954639590 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.1655132276 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 2522413354 ps |
| CPU time | 96.07 seconds |
| Started | Jul 06 08:14:05 PM PDT 24 |
| Finished | Jul 06 08:15:42 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-7ab33cd3-7686-442e-a5c0-2a105f599f87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655132276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1655132276 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.462097761 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 320880522 ps |
| CPU time | 34.92 seconds |
| Started | Jul 06 08:13:54 PM PDT 24 |
| Finished | Jul 06 08:14:29 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-a2647ce1-2877-4e03-a7a0-6af8802befee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462097761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.462097761 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.2893476226 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 39265228950 ps |
| CPU time | 410.97 seconds |
| Started | Jul 06 08:13:58 PM PDT 24 |
| Finished | Jul 06 08:20:50 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-1fe77ee7-90bb-4048-a46e-5a3efed0b3e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893476226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2893476226 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.3701746144 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 72129031899 ps |
| CPU time | 1298.17 seconds |
| Started | Jul 06 08:13:59 PM PDT 24 |
| Finished | Jul 06 08:35:38 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-e603b7ad-c171-4cd1-9fd1-8514c03c098e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701746144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3701746144 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.454422979 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 425504231 ps |
| CPU time | 33.08 seconds |
| Started | Jul 06 08:14:02 PM PDT 24 |
| Finished | Jul 06 08:14:35 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-2dcd7ec5-f470-4371-99cc-98748b33e33c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454422979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_dela ys.454422979 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.3054751830 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 247408278 ps |
| CPU time | 11.34 seconds |
| Started | Jul 06 08:13:59 PM PDT 24 |
| Finished | Jul 06 08:14:10 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-dc52ee00-91b8-4719-905b-5339d4321414 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054751830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3054751830 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.1987853554 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 175784270 ps |
| CPU time | 8.44 seconds |
| Started | Jul 06 08:13:51 PM PDT 24 |
| Finished | Jul 06 08:14:00 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-b2704661-2e7a-4cbd-960c-daec84d6e7b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987853554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1987853554 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.2295037340 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 10847134149 ps |
| CPU time | 111.29 seconds |
| Started | Jul 06 08:13:55 PM PDT 24 |
| Finished | Jul 06 08:15:46 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-7b70baf5-1a42-4be3-8f60-c2cca8834c99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295037340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2295037340 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1650412380 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 4547393455 ps |
| CPU time | 80.36 seconds |
| Started | Jul 06 08:13:53 PM PDT 24 |
| Finished | Jul 06 08:15:13 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-e572f20f-f08d-42ed-9f58-04158ade5ff5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650412380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1650412380 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3720985917 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 51113005 ps |
| CPU time | 6.87 seconds |
| Started | Jul 06 08:13:53 PM PDT 24 |
| Finished | Jul 06 08:14:00 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-f5a226e1-e888-498e-9f0d-8fe04abf6847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720985917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.3720985917 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.767822181 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 1992144349 ps |
| CPU time | 188.49 seconds |
| Started | Jul 06 08:14:05 PM PDT 24 |
| Finished | Jul 06 08:17:14 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-c8cbc8b0-7d4e-40cc-88e0-5b8fe4909cb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767822181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.767822181 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.2078084436 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 6826250760 ps |
| CPU time | 304.86 seconds |
| Started | Jul 06 08:14:05 PM PDT 24 |
| Finished | Jul 06 08:19:10 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-0878433c-ddf5-4d95-b025-733d433405db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078084436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2078084436 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.2296776204 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 1996821679 ps |
| CPU time | 358.93 seconds |
| Started | Jul 06 08:14:09 PM PDT 24 |
| Finished | Jul 06 08:20:08 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-14520b96-a881-48a5-a779-68aeb3eb97c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296776204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.2296776204 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3225907458 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 7311292424 ps |
| CPU time | 748.32 seconds |
| Started | Jul 06 08:14:04 PM PDT 24 |
| Finished | Jul 06 08:26:32 PM PDT 24 |
| Peak memory | 582872 kb |
| Host | smart-242be981-eee9-4026-9658-89cf011d269c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225907458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.3225907458 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.217319469 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 25060932 ps |
| CPU time | 5.95 seconds |
| Started | Jul 06 08:14:05 PM PDT 24 |
| Finished | Jul 06 08:14:11 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-d1f70352-2532-4dde-b0fc-adafd6f367f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217319469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.217319469 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.2105717269 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 55250118596 ps |
| CPU time | 7831.03 seconds |
| Started | Jul 06 08:03:05 PM PDT 24 |
| Finished | Jul 06 10:13:37 PM PDT 24 |
| Peak memory | 633116 kb |
| Host | smart-118a75e5-58c2-4fb3-9b50-23f7bf2e9d73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105717269 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.2105717269 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.737036754 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 59505443709 ps |
| CPU time | 5581.92 seconds |
| Started | Jul 06 08:02:16 PM PDT 24 |
| Finished | Jul 06 09:35:19 PM PDT 24 |
| Peak memory | 590764 kb |
| Host | smart-f93b922e-dd58-432e-9f9d-28606c0a7f3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737036754 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.737036754 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.210279819 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 4481490100 ps |
| CPU time | 362.46 seconds |
| Started | Jul 06 08:03:13 PM PDT 24 |
| Finished | Jul 06 08:09:16 PM PDT 24 |
| Peak memory | 598512 kb |
| Host | smart-1d2eae81-4536-4cc3-ae77-65917aeeae77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210279819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.210279819 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.931034373 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 14848684160 ps |
| CPU time | 1660.78 seconds |
| Started | Jul 06 08:03:05 PM PDT 24 |
| Finished | Jul 06 08:30:47 PM PDT 24 |
| Peak memory | 592740 kb |
| Host | smart-c08e3bcd-91d9-43d6-95af-af4e53ef1573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931034373 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.chip_same_csr_outstanding.931034373 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.2121580631 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 3866260396 ps |
| CPU time | 248.78 seconds |
| Started | Jul 06 08:02:20 PM PDT 24 |
| Finished | Jul 06 08:06:29 PM PDT 24 |
| Peak memory | 597532 kb |
| Host | smart-9421fbc5-92d2-46e0-b68e-272dadbcbfab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121580631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.2121580631 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.3795929432 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 1596461872 ps |
| CPU time | 74.61 seconds |
| Started | Jul 06 08:02:35 PM PDT 24 |
| Finished | Jul 06 08:03:50 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-cff9c418-7782-4010-abdd-e986cbf57102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795929432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 3795929432 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.2511151239 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 98246091347 ps |
| CPU time | 1689.01 seconds |
| Started | Jul 06 08:02:42 PM PDT 24 |
| Finished | Jul 06 08:30:51 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-ce46cdac-5bc7-44a4-a825-85d986f0dde7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511151239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.2511151239 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.1204464552 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 741865736 ps |
| CPU time | 32.24 seconds |
| Started | Jul 06 08:02:57 PM PDT 24 |
| Finished | Jul 06 08:03:30 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-a45e5e60-34a8-4828-8218-d8184437b1c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204464552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .1204464552 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.54668467 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 1025090367 ps |
| CPU time | 37 seconds |
| Started | Jul 06 08:02:40 PM PDT 24 |
| Finished | Jul 06 08:03:17 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-6128aefd-ae95-4f6b-b0d8-3ad3d4adcc64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54668467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.54668467 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.1846733675 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 2027636083 ps |
| CPU time | 88.74 seconds |
| Started | Jul 06 08:02:32 PM PDT 24 |
| Finished | Jul 06 08:04:01 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-1ae878d8-e813-41b3-aef8-916743c832bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846733675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.1846733675 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.1817862936 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 91441476207 ps |
| CPU time | 1004.69 seconds |
| Started | Jul 06 08:02:41 PM PDT 24 |
| Finished | Jul 06 08:19:26 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-c8037e8f-1e70-4e37-9f8e-6cd822421f98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817862936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1817862936 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.3223428890 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 55850046684 ps |
| CPU time | 996.07 seconds |
| Started | Jul 06 08:02:40 PM PDT 24 |
| Finished | Jul 06 08:19:17 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-d368303d-3926-4506-9d90-ec379fc5b2eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223428890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3223428890 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.3817076124 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 289913388 ps |
| CPU time | 31.16 seconds |
| Started | Jul 06 08:02:38 PM PDT 24 |
| Finished | Jul 06 08:03:09 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-4ad5bf9e-91b0-43a5-948e-c8c981fb0882 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817076124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.3817076124 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.4098451782 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 1087173775 ps |
| CPU time | 30.93 seconds |
| Started | Jul 06 08:02:40 PM PDT 24 |
| Finished | Jul 06 08:03:11 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-71878192-8209-45a2-90a4-25abca628c8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098451782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.4098451782 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.2107801422 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 50273545 ps |
| CPU time | 7.32 seconds |
| Started | Jul 06 08:02:20 PM PDT 24 |
| Finished | Jul 06 08:02:28 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-b00c8875-0af1-4c18-bf5c-c847ac8b402a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107801422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2107801422 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.3478402271 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 9086674925 ps |
| CPU time | 95.92 seconds |
| Started | Jul 06 08:02:32 PM PDT 24 |
| Finished | Jul 06 08:04:08 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-7fa586a4-53a5-45c4-aacc-2a4c54caeed5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478402271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3478402271 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.1596915426 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 4881736000 ps |
| CPU time | 80.89 seconds |
| Started | Jul 06 08:02:30 PM PDT 24 |
| Finished | Jul 06 08:03:51 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-cf5887cb-1054-40d6-ac5e-f4071960d652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596915426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1596915426 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.1530228376 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 36122117 ps |
| CPU time | 6.54 seconds |
| Started | Jul 06 08:02:27 PM PDT 24 |
| Finished | Jul 06 08:02:34 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-b5be6080-450e-4df4-aa9e-88a1b10e741a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530228376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .1530228376 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.1472448118 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 3845997506 ps |
| CPU time | 155.61 seconds |
| Started | Jul 06 08:02:58 PM PDT 24 |
| Finished | Jul 06 08:05:33 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-13ec73b2-63ad-47fc-924d-a7c3c0f28e72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472448118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1472448118 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.1721484946 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 9473999375 ps |
| CPU time | 419.98 seconds |
| Started | Jul 06 08:03:13 PM PDT 24 |
| Finished | Jul 06 08:10:13 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-819ef7b8-abc1-4c38-8360-0599eee575f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721484946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1721484946 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.3540081448 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 3578542287 ps |
| CPU time | 447.94 seconds |
| Started | Jul 06 08:02:56 PM PDT 24 |
| Finished | Jul 06 08:10:24 PM PDT 24 |
| Peak memory | 576852 kb |
| Host | smart-791f4b4b-2155-4a08-9762-8d14d2a2def7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540081448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.3540081448 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1046321686 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 494370422 ps |
| CPU time | 150.42 seconds |
| Started | Jul 06 08:03:09 PM PDT 24 |
| Finished | Jul 06 08:05:40 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-4001a903-0913-419d-99d5-b525f1fee112 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046321686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.1046321686 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.479208015 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 846535086 ps |
| CPU time | 42.45 seconds |
| Started | Jul 06 08:02:44 PM PDT 24 |
| Finished | Jul 06 08:03:27 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-17317fcf-f5c9-48bc-8878-55ffbed66338 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479208015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.479208015 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.1437968815 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 652248118 ps |
| CPU time | 34.56 seconds |
| Started | Jul 06 08:14:11 PM PDT 24 |
| Finished | Jul 06 08:14:46 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-5cce5a45-0d1c-4ba2-81e5-d2f31dc68f6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437968815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .1437968815 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.1816939349 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 34411087947 ps |
| CPU time | 648.65 seconds |
| Started | Jul 06 08:14:08 PM PDT 24 |
| Finished | Jul 06 08:24:57 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-5ff3a2f1-e102-45ba-801e-4337c3c8e52d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816939349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.1816939349 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.1107363280 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 829685371 ps |
| CPU time | 37.83 seconds |
| Started | Jul 06 08:14:07 PM PDT 24 |
| Finished | Jul 06 08:14:45 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-7fcb4634-a6f5-4386-97d3-2045ac2d8e10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107363280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.1107363280 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.1514905021 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 2115841323 ps |
| CPU time | 80.06 seconds |
| Started | Jul 06 08:14:11 PM PDT 24 |
| Finished | Jul 06 08:15:31 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-76687e10-6737-452a-b813-1be2cf4e688c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514905021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1514905021 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.2000362653 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 1762393230 ps |
| CPU time | 61.79 seconds |
| Started | Jul 06 08:14:02 PM PDT 24 |
| Finished | Jul 06 08:15:04 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-459724a4-7d11-4d81-b0b9-6dbaa82b53c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000362653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.2000362653 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.1548431957 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 59113825853 ps |
| CPU time | 640.39 seconds |
| Started | Jul 06 08:14:04 PM PDT 24 |
| Finished | Jul 06 08:24:45 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-aa4581e1-de10-4e03-9796-1bb091979803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548431957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1548431957 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.4269556844 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 61764605649 ps |
| CPU time | 1058.92 seconds |
| Started | Jul 06 08:14:03 PM PDT 24 |
| Finished | Jul 06 08:31:42 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-aa116722-2dd9-4e16-a6af-7008ef5a55cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269556844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.4269556844 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1725871503 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 626266802 ps |
| CPU time | 59.76 seconds |
| Started | Jul 06 08:14:04 PM PDT 24 |
| Finished | Jul 06 08:15:04 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-dadd92de-3b7f-4bd4-be4d-c0851593712d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725871503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.1725871503 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.3498887901 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 1430896959 ps |
| CPU time | 43.92 seconds |
| Started | Jul 06 08:14:10 PM PDT 24 |
| Finished | Jul 06 08:14:54 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-f0b70735-d543-4da8-a91d-b45a5e87c8fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498887901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3498887901 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.3764462008 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 235400462 ps |
| CPU time | 10.17 seconds |
| Started | Jul 06 08:14:09 PM PDT 24 |
| Finished | Jul 06 08:14:20 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-35bc06e9-9ab4-49e2-8d86-3fd80fe52365 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764462008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3764462008 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.2465508584 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 7665709793 ps |
| CPU time | 84.93 seconds |
| Started | Jul 06 08:14:06 PM PDT 24 |
| Finished | Jul 06 08:15:31 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-ac297a26-d8a1-47d3-953c-4772c3ace72b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465508584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2465508584 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.4169342935 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 4272115028 ps |
| CPU time | 75.1 seconds |
| Started | Jul 06 08:14:02 PM PDT 24 |
| Finished | Jul 06 08:15:18 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-243e21d2-765a-4d93-9031-1df788e83e78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169342935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.4169342935 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.3766483163 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 55012541 ps |
| CPU time | 7.81 seconds |
| Started | Jul 06 08:14:06 PM PDT 24 |
| Finished | Jul 06 08:14:14 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-8a4a5926-9357-4bd3-a4ff-c25a0ab3a4bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766483163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.3766483163 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.994553640 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 12258910383 ps |
| CPU time | 499.92 seconds |
| Started | Jul 06 08:14:14 PM PDT 24 |
| Finished | Jul 06 08:22:35 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-5e8c2868-feed-4a52-bbf7-354b68b781df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994553640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.994553640 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.680408334 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1869046468 ps |
| CPU time | 402.91 seconds |
| Started | Jul 06 08:14:15 PM PDT 24 |
| Finished | Jul 06 08:20:58 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-a4a74a99-3619-402d-9395-3598ab244553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680408334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_ with_rand_reset.680408334 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2935556385 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 3473569029 ps |
| CPU time | 393.74 seconds |
| Started | Jul 06 08:14:12 PM PDT 24 |
| Finished | Jul 06 08:20:46 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-fb457865-98bb-47ed-b97f-9e2ea0a24ad1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935556385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.2935556385 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.3203463401 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 25482525 ps |
| CPU time | 6.06 seconds |
| Started | Jul 06 08:14:08 PM PDT 24 |
| Finished | Jul 06 08:14:15 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-3aca30c8-58ad-4493-b59a-3aca9be0711c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203463401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3203463401 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.78891626 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1189257747 ps |
| CPU time | 64.11 seconds |
| Started | Jul 06 08:14:19 PM PDT 24 |
| Finished | Jul 06 08:15:23 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-31c48666-4d3d-4478-baed-2894dbf6a8f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78891626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.78891626 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.995179539 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 74554276480 ps |
| CPU time | 1359.72 seconds |
| Started | Jul 06 08:14:21 PM PDT 24 |
| Finished | Jul 06 08:37:02 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-72b06a52-9d85-4110-8387-a4f69def05ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995179539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_d evice_slow_rsp.995179539 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.3733279751 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 1261930727 ps |
| CPU time | 56.45 seconds |
| Started | Jul 06 08:14:25 PM PDT 24 |
| Finished | Jul 06 08:15:22 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-5fb18088-88ed-4830-a074-f49e420f8d7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733279751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.3733279751 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.2948225898 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 1257079316 ps |
| CPU time | 48.91 seconds |
| Started | Jul 06 08:14:21 PM PDT 24 |
| Finished | Jul 06 08:15:10 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-7c7beee5-6a0c-416b-9ce0-319c07bff114 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948225898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2948225898 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.865036225 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 355989967 ps |
| CPU time | 33.59 seconds |
| Started | Jul 06 08:14:13 PM PDT 24 |
| Finished | Jul 06 08:14:47 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-29951c56-e950-422f-863b-3061f343949b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865036225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.865036225 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.2844303503 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 93534227434 ps |
| CPU time | 1031.08 seconds |
| Started | Jul 06 08:14:18 PM PDT 24 |
| Finished | Jul 06 08:31:29 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-f9388564-20fd-4837-8803-35d608a2e9d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844303503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2844303503 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.296844382 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 13965813439 ps |
| CPU time | 253.48 seconds |
| Started | Jul 06 08:14:18 PM PDT 24 |
| Finished | Jul 06 08:18:32 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-f280423c-a873-4f87-8c78-73461fe168e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296844382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.296844382 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.3669383857 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 80586681 ps |
| CPU time | 10.77 seconds |
| Started | Jul 06 08:14:13 PM PDT 24 |
| Finished | Jul 06 08:14:24 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-7da1edc6-31ec-4e3e-9f89-72aa83cd47be |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669383857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.3669383857 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.2468328304 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 160300654 ps |
| CPU time | 14.88 seconds |
| Started | Jul 06 08:14:18 PM PDT 24 |
| Finished | Jul 06 08:14:33 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-627b278c-9569-40c1-b28b-761d3871cde1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468328304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2468328304 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.1172986099 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 227354188 ps |
| CPU time | 9.81 seconds |
| Started | Jul 06 08:14:13 PM PDT 24 |
| Finished | Jul 06 08:14:24 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-6095b172-a194-47a6-9180-945cf564e030 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172986099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1172986099 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.1567379308 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 8441437530 ps |
| CPU time | 98.02 seconds |
| Started | Jul 06 08:14:15 PM PDT 24 |
| Finished | Jul 06 08:15:53 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-9716615f-1e35-46df-963b-fa649fa714b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567379308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1567379308 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.4091728272 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 3290536960 ps |
| CPU time | 56.92 seconds |
| Started | Jul 06 08:14:13 PM PDT 24 |
| Finished | Jul 06 08:15:11 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-0ca07e93-e535-4442-a72d-967c9c7fec9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091728272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.4091728272 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2121773946 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 49964047 ps |
| CPU time | 6.96 seconds |
| Started | Jul 06 08:14:13 PM PDT 24 |
| Finished | Jul 06 08:14:20 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-a1e65252-1ac5-4b51-9b75-dfa45bfea199 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121773946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.2121773946 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.780471753 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 7521630145 ps |
| CPU time | 317.88 seconds |
| Started | Jul 06 08:14:25 PM PDT 24 |
| Finished | Jul 06 08:19:43 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-f8a1a80c-6de4-4116-9ff5-3aa5e9c773b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780471753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.780471753 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.1924387348 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 7268764494 ps |
| CPU time | 234.85 seconds |
| Started | Jul 06 08:14:24 PM PDT 24 |
| Finished | Jul 06 08:18:20 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-b5f2661f-8f33-4984-b286-4039b94e4dd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924387348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1924387348 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3942576025 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 117102047 ps |
| CPU time | 33.44 seconds |
| Started | Jul 06 08:14:24 PM PDT 24 |
| Finished | Jul 06 08:14:58 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-56b679c6-b240-4189-a7c6-9edcf3acce67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942576025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.3942576025 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2622683873 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 1311877321 ps |
| CPU time | 79.83 seconds |
| Started | Jul 06 08:14:19 PM PDT 24 |
| Finished | Jul 06 08:15:39 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-92996aaa-eae1-414a-b967-a1a2019c754a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622683873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.2622683873 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.726345192 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 1085137432 ps |
| CPU time | 49.89 seconds |
| Started | Jul 06 08:14:21 PM PDT 24 |
| Finished | Jul 06 08:15:11 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-1f371c72-4f8f-488d-a8eb-4273d7b0ab67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726345192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.726345192 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.3226615053 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 548918125 ps |
| CPU time | 69.13 seconds |
| Started | Jul 06 08:14:30 PM PDT 24 |
| Finished | Jul 06 08:15:40 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-51894363-f5a8-48e8-8f72-81561e4f51e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226615053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .3226615053 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.2146796782 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 36270118511 ps |
| CPU time | 657.85 seconds |
| Started | Jul 06 08:14:32 PM PDT 24 |
| Finished | Jul 06 08:25:30 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-75fbae66-d20e-4cbb-ab8c-914584c93218 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146796782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_ device_slow_rsp.2146796782 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.3547593069 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 789730865 ps |
| CPU time | 33.39 seconds |
| Started | Jul 06 08:14:32 PM PDT 24 |
| Finished | Jul 06 08:15:06 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-9dcfd894-5c7a-4147-a51a-776f89972875 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547593069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.3547593069 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.867290084 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 1497609488 ps |
| CPU time | 52.63 seconds |
| Started | Jul 06 08:14:31 PM PDT 24 |
| Finished | Jul 06 08:15:24 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-4b0bae61-b097-4b40-9aa4-f3f27c973254 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867290084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.867290084 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.398828510 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 287834603 ps |
| CPU time | 32.34 seconds |
| Started | Jul 06 08:14:25 PM PDT 24 |
| Finished | Jul 06 08:14:58 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-fc972763-83a8-4c19-80ea-a560bf4c6e8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398828510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.398828510 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.4149360362 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 88433039592 ps |
| CPU time | 901.4 seconds |
| Started | Jul 06 08:14:24 PM PDT 24 |
| Finished | Jul 06 08:29:25 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-5bcaee38-5edc-45ea-ba4b-ce60e2aad55f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149360362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.4149360362 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.1477801391 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 31458950648 ps |
| CPU time | 593.45 seconds |
| Started | Jul 06 08:14:34 PM PDT 24 |
| Finished | Jul 06 08:24:28 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-f157e252-cf73-4ecf-ab79-28f16adf5b62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477801391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1477801391 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.247721050 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 451093572 ps |
| CPU time | 45.02 seconds |
| Started | Jul 06 08:14:26 PM PDT 24 |
| Finished | Jul 06 08:15:11 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-6ae0cf82-1a00-4f36-9118-b33ea2f70eb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247721050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_dela ys.247721050 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.1348450487 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 439787856 ps |
| CPU time | 38.05 seconds |
| Started | Jul 06 08:14:34 PM PDT 24 |
| Finished | Jul 06 08:15:12 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-9ea34727-0bb7-4ec0-9525-e1745625314b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348450487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1348450487 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.1827514821 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 162454869 ps |
| CPU time | 8.18 seconds |
| Started | Jul 06 08:14:24 PM PDT 24 |
| Finished | Jul 06 08:14:33 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-a6986906-7c8e-4170-af4a-40efb25f7cba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827514821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1827514821 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.134582695 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 7437892823 ps |
| CPU time | 78.54 seconds |
| Started | Jul 06 08:14:29 PM PDT 24 |
| Finished | Jul 06 08:15:48 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-2ef8cc80-0a70-41e5-a66a-ace32eda15a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134582695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.134582695 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.2412207624 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 5692723786 ps |
| CPU time | 99.38 seconds |
| Started | Jul 06 08:14:26 PM PDT 24 |
| Finished | Jul 06 08:16:06 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-feec4002-3e1c-436c-bbf4-59dbe8c04ebe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412207624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2412207624 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.974454872 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 42639517 ps |
| CPU time | 6.54 seconds |
| Started | Jul 06 08:14:26 PM PDT 24 |
| Finished | Jul 06 08:14:33 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-53e35c7e-1219-433a-89d4-3b18919fc08b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974454872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays .974454872 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.2200104964 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 335263106 ps |
| CPU time | 38.88 seconds |
| Started | Jul 06 08:14:31 PM PDT 24 |
| Finished | Jul 06 08:15:10 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-db7e486b-8315-49ec-ba63-1b8596880c98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200104964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2200104964 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.3073465059 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 15434970753 ps |
| CPU time | 741.59 seconds |
| Started | Jul 06 08:14:32 PM PDT 24 |
| Finished | Jul 06 08:26:54 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-1b0576db-f888-4429-846b-a9af184bb9ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073465059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3073465059 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.425156789 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 5192623330 ps |
| CPU time | 222.37 seconds |
| Started | Jul 06 08:14:34 PM PDT 24 |
| Finished | Jul 06 08:18:17 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-6343bb2b-a82b-42ac-92ba-7b9be9433012 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425156789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_ with_rand_reset.425156789 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.713750390 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 1102867425 ps |
| CPU time | 136.78 seconds |
| Started | Jul 06 08:14:38 PM PDT 24 |
| Finished | Jul 06 08:16:55 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-ad33859f-ec19-4b83-a027-cc49a44bbac4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713750390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_reset_error.713750390 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.3365420250 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 261823226 ps |
| CPU time | 36.64 seconds |
| Started | Jul 06 08:14:32 PM PDT 24 |
| Finished | Jul 06 08:15:09 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-fc08d9e0-2997-41ab-8232-1b2f4047294d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365420250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3365420250 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.619922679 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 208521867 ps |
| CPU time | 13.57 seconds |
| Started | Jul 06 08:14:36 PM PDT 24 |
| Finished | Jul 06 08:14:50 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-657fa013-d581-4ee7-9fce-88ffb7b8eab9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619922679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device. 619922679 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.2825671866 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 53581661294 ps |
| CPU time | 959.29 seconds |
| Started | Jul 06 08:14:39 PM PDT 24 |
| Finished | Jul 06 08:30:38 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-411eac7b-836a-4d20-8281-f99698f2e952 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825671866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.2825671866 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.3872881989 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 1286670140 ps |
| CPU time | 54.2 seconds |
| Started | Jul 06 08:14:48 PM PDT 24 |
| Finished | Jul 06 08:15:42 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-658e6d0e-9254-43b1-b84c-e36d9c411cba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872881989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.3872881989 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.2120735155 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 2434823039 ps |
| CPU time | 84.88 seconds |
| Started | Jul 06 08:14:49 PM PDT 24 |
| Finished | Jul 06 08:16:14 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-1dc658ea-cbaf-403d-b4e8-8ef786fb14f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120735155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2120735155 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.352843968 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 1060811917 ps |
| CPU time | 41.21 seconds |
| Started | Jul 06 08:14:36 PM PDT 24 |
| Finished | Jul 06 08:15:18 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-82f1c8f9-dbb0-4dd1-99d6-db516dadffef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352843968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.352843968 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.2681291914 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 78844735513 ps |
| CPU time | 887.77 seconds |
| Started | Jul 06 08:14:38 PM PDT 24 |
| Finished | Jul 06 08:29:26 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-ba24c2ac-225c-43cc-978d-d6bc5cb4f0bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681291914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2681291914 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.2375541318 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 47032635356 ps |
| CPU time | 782.81 seconds |
| Started | Jul 06 08:14:36 PM PDT 24 |
| Finished | Jul 06 08:27:39 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-0474f9d4-8eab-442a-8aad-adbc7d305dce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375541318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2375541318 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.3360926172 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 364413022 ps |
| CPU time | 36.81 seconds |
| Started | Jul 06 08:14:36 PM PDT 24 |
| Finished | Jul 06 08:15:13 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-80dafc41-5c11-4a52-b744-42964d1fd7a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360926172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.3360926172 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.2238022480 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 90012064 ps |
| CPU time | 9.7 seconds |
| Started | Jul 06 08:14:36 PM PDT 24 |
| Finished | Jul 06 08:14:46 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-ef8884d4-8e63-4f7f-9a25-27dcd11ca605 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238022480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2238022480 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.2466573276 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 179630654 ps |
| CPU time | 9.07 seconds |
| Started | Jul 06 08:14:38 PM PDT 24 |
| Finished | Jul 06 08:14:48 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-300a3e4e-683c-4a37-b597-6e6d1a07966b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466573276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2466573276 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.2863898746 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 8932428314 ps |
| CPU time | 99.75 seconds |
| Started | Jul 06 08:14:36 PM PDT 24 |
| Finished | Jul 06 08:16:17 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-7b0f4048-2cf0-4455-b7e6-18d0add006be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863898746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2863898746 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.1761400699 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 5927053042 ps |
| CPU time | 104.98 seconds |
| Started | Jul 06 08:14:38 PM PDT 24 |
| Finished | Jul 06 08:16:24 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-6bdd85c0-15c3-4111-b0aa-c97260b31636 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761400699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1761400699 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.3549329734 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 54514377 ps |
| CPU time | 7.01 seconds |
| Started | Jul 06 08:14:38 PM PDT 24 |
| Finished | Jul 06 08:14:45 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-60fe54d6-4111-48cd-9e22-652a1c0896db |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549329734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.3549329734 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.634713472 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 18154661114 ps |
| CPU time | 707.53 seconds |
| Started | Jul 06 08:14:49 PM PDT 24 |
| Finished | Jul 06 08:26:37 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-0a88d9c8-4a03-496e-a081-56096a88d066 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634713472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.634713472 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.851561303 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 4906706658 ps |
| CPU time | 182.36 seconds |
| Started | Jul 06 08:14:47 PM PDT 24 |
| Finished | Jul 06 08:17:50 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-14ecad9e-fb6f-43a7-8ecc-47310c03ed4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851561303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.851561303 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2403379593 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 460519826 ps |
| CPU time | 126.95 seconds |
| Started | Jul 06 08:14:47 PM PDT 24 |
| Finished | Jul 06 08:16:54 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-99487766-277b-4619-89fb-cafe7c571947 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403379593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.2403379593 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.2026717937 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 629171610 ps |
| CPU time | 107 seconds |
| Started | Jul 06 08:14:47 PM PDT 24 |
| Finished | Jul 06 08:16:34 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-366c102a-bffb-4cd2-ac7f-2ca2474efc88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026717937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.2026717937 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.1575101796 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 156870987 ps |
| CPU time | 22.07 seconds |
| Started | Jul 06 08:14:47 PM PDT 24 |
| Finished | Jul 06 08:15:10 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-4a21d368-9208-41ff-a3ba-ccd824e353bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575101796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1575101796 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.1593492751 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 20039021 ps |
| CPU time | 7.45 seconds |
| Started | Jul 06 08:15:18 PM PDT 24 |
| Finished | Jul 06 08:15:26 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-3a173e69-63bf-48be-b8d1-9ad38dd275b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593492751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .1593492751 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3123379935 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 129679435716 ps |
| CPU time | 2529.43 seconds |
| Started | Jul 06 08:14:47 PM PDT 24 |
| Finished | Jul 06 08:56:58 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-550ea492-03f1-4a07-9c75-c43b24736e83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123379935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.3123379935 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3514701711 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 190329772 ps |
| CPU time | 9.6 seconds |
| Started | Jul 06 08:14:48 PM PDT 24 |
| Finished | Jul 06 08:14:58 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-7b70117d-2e65-458d-aba1-76feb90906ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514701711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.3514701711 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.1823544909 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 1062983012 ps |
| CPU time | 34.16 seconds |
| Started | Jul 06 08:14:48 PM PDT 24 |
| Finished | Jul 06 08:15:22 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-14a1005d-951f-4a78-9ffd-ae1730884a22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823544909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1823544909 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.3225153950 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 280115194 ps |
| CPU time | 27.64 seconds |
| Started | Jul 06 08:14:45 PM PDT 24 |
| Finished | Jul 06 08:15:13 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-dfd077f1-26ab-4696-b4aa-4d2859a7a184 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225153950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.3225153950 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.2855036878 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 71238082878 ps |
| CPU time | 744.62 seconds |
| Started | Jul 06 08:14:52 PM PDT 24 |
| Finished | Jul 06 08:27:17 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-8fdeb67e-545d-4d14-8710-a5a6fd3b1740 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855036878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2855036878 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.2821043629 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 48513778515 ps |
| CPU time | 791.06 seconds |
| Started | Jul 06 08:14:52 PM PDT 24 |
| Finished | Jul 06 08:28:04 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-05bc46f5-78e0-45de-b162-5bda586121d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821043629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2821043629 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.3695788758 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 190564071 ps |
| CPU time | 21.52 seconds |
| Started | Jul 06 08:14:49 PM PDT 24 |
| Finished | Jul 06 08:15:11 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-085f452b-7f89-4f05-a578-83f252dae588 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695788758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.3695788758 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.1106117534 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 1306407922 ps |
| CPU time | 36.94 seconds |
| Started | Jul 06 08:14:47 PM PDT 24 |
| Finished | Jul 06 08:15:24 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-5535af6e-9c73-436a-8a11-7ddca57d0be9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106117534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1106117534 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.3422716347 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 199796205 ps |
| CPU time | 9.3 seconds |
| Started | Jul 06 08:14:46 PM PDT 24 |
| Finished | Jul 06 08:14:55 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-595ba45f-ead6-40b6-a44b-5ca07e6da684 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422716347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3422716347 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.3661957600 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 8220387200 ps |
| CPU time | 86.51 seconds |
| Started | Jul 06 08:14:46 PM PDT 24 |
| Finished | Jul 06 08:16:13 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-6897368c-4e9e-4fd6-9d12-3ec10c6df707 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661957600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3661957600 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.2887387881 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 5473120084 ps |
| CPU time | 93.93 seconds |
| Started | Jul 06 08:14:48 PM PDT 24 |
| Finished | Jul 06 08:16:23 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-0f3f802f-57ee-4eac-b81d-698f6c402818 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887387881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2887387881 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.546122944 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 46556971 ps |
| CPU time | 6.87 seconds |
| Started | Jul 06 08:14:49 PM PDT 24 |
| Finished | Jul 06 08:14:56 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-4b342ccc-5cb8-4922-a244-728d7827aa37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546122944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays .546122944 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.2638379294 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 19018579328 ps |
| CPU time | 935.6 seconds |
| Started | Jul 06 08:14:51 PM PDT 24 |
| Finished | Jul 06 08:30:27 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-7bb15e4f-e04c-427e-8b40-18b3bf71c10e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638379294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2638379294 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.3410888332 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 11706277386 ps |
| CPU time | 473.75 seconds |
| Started | Jul 06 08:14:52 PM PDT 24 |
| Finished | Jul 06 08:22:46 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-7cda70d6-7e25-4844-bf2f-a9cd87ccdc14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410888332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3410888332 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.3430394803 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 562316575 ps |
| CPU time | 263.84 seconds |
| Started | Jul 06 08:14:49 PM PDT 24 |
| Finished | Jul 06 08:19:13 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-ddb8519f-8be5-4e38-a792-35188d362aa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430394803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.3430394803 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.1031630656 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 9338416125 ps |
| CPU time | 438.88 seconds |
| Started | Jul 06 08:14:54 PM PDT 24 |
| Finished | Jul 06 08:22:14 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-b0764bef-dd3f-4907-8722-dd7a01982943 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031630656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.1031630656 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.1226896637 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 1048821159 ps |
| CPU time | 50.78 seconds |
| Started | Jul 06 08:14:51 PM PDT 24 |
| Finished | Jul 06 08:15:42 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-b507ff83-9e09-4c26-a105-f13c058d8891 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226896637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1226896637 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.1438961089 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 3463222951 ps |
| CPU time | 159.83 seconds |
| Started | Jul 06 08:14:54 PM PDT 24 |
| Finished | Jul 06 08:17:35 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-a13cb9bc-41f5-4184-9c9b-211225efa36f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438961089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .1438961089 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.3025933578 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 107840649487 ps |
| CPU time | 1788.25 seconds |
| Started | Jul 06 08:14:51 PM PDT 24 |
| Finished | Jul 06 08:44:40 PM PDT 24 |
| Peak memory | 576936 kb |
| Host | smart-2a008871-4d1f-4613-a8b6-6be38dbf1558 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025933578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.3025933578 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2174435033 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 89710042 ps |
| CPU time | 7.07 seconds |
| Started | Jul 06 08:14:57 PM PDT 24 |
| Finished | Jul 06 08:15:04 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-d7eb908b-c65d-4154-9b8e-4d1f1d9fbc34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174435033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.2174435033 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.2332884346 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 955810059 ps |
| CPU time | 32.7 seconds |
| Started | Jul 06 08:14:57 PM PDT 24 |
| Finished | Jul 06 08:15:30 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-a6b6794d-8b5b-4ca0-8c61-fb51194bde79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332884346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2332884346 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.4059370489 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 41985269 ps |
| CPU time | 7.9 seconds |
| Started | Jul 06 08:14:53 PM PDT 24 |
| Finished | Jul 06 08:15:01 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-2f7770a8-2fd8-4efd-a61c-f3abb444b66d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059370489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.4059370489 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.3742697674 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 100741917666 ps |
| CPU time | 1095.98 seconds |
| Started | Jul 06 08:14:54 PM PDT 24 |
| Finished | Jul 06 08:33:11 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-ad4e0690-a622-4b7c-864e-f00d0a761728 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742697674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3742697674 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.3471325898 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 40565555734 ps |
| CPU time | 712.89 seconds |
| Started | Jul 06 08:14:55 PM PDT 24 |
| Finished | Jul 06 08:26:48 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-b4434ec4-7a2c-4ef6-8cd3-119e10283859 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471325898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3471325898 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.1069469046 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 216238353 ps |
| CPU time | 22.36 seconds |
| Started | Jul 06 08:14:58 PM PDT 24 |
| Finished | Jul 06 08:15:20 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-c0bab4ea-ba77-477e-a96d-d47261dd4e9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069469046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.1069469046 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.3228579398 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 2278797043 ps |
| CPU time | 74.09 seconds |
| Started | Jul 06 08:14:58 PM PDT 24 |
| Finished | Jul 06 08:16:13 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-87354502-2111-442d-bd66-46d033ab9f9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228579398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3228579398 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.2606166756 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 38936412 ps |
| CPU time | 6.5 seconds |
| Started | Jul 06 08:14:54 PM PDT 24 |
| Finished | Jul 06 08:15:01 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-1ef7af04-8a42-4e42-b3f7-34eeb6e5102d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606166756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2606166756 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.1168970698 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 7842731963 ps |
| CPU time | 82.08 seconds |
| Started | Jul 06 08:14:52 PM PDT 24 |
| Finished | Jul 06 08:16:14 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-3d0e95f7-b33c-4b14-aa91-e325106e9643 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168970698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1168970698 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.2746771739 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 5049411632 ps |
| CPU time | 93.56 seconds |
| Started | Jul 06 08:14:54 PM PDT 24 |
| Finished | Jul 06 08:16:28 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-a4f81001-f046-46cf-a21c-fcfce33084df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746771739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2746771739 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.2714187187 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 43618435 ps |
| CPU time | 6.85 seconds |
| Started | Jul 06 08:14:55 PM PDT 24 |
| Finished | Jul 06 08:15:02 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-6c22029d-fefd-4038-b84e-fc00bc572134 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714187187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.2714187187 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.2009852442 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 13661910880 ps |
| CPU time | 557.06 seconds |
| Started | Jul 06 08:14:56 PM PDT 24 |
| Finished | Jul 06 08:24:14 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-1193c8cf-10e1-4c18-acd5-acc595807ae2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009852442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2009852442 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.1730456139 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 16404711301 ps |
| CPU time | 712 seconds |
| Started | Jul 06 08:14:57 PM PDT 24 |
| Finished | Jul 06 08:26:50 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-93c054c5-aa5b-4ba1-bf07-99acd24a2177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730456139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1730456139 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.943132861 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 107292521 ps |
| CPU time | 54.04 seconds |
| Started | Jul 06 08:14:57 PM PDT 24 |
| Finished | Jul 06 08:15:52 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-c2811dd0-a26e-4d0a-b549-34b02a167f69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943132861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_ with_rand_reset.943132861 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.66550916 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 4110663862 ps |
| CPU time | 529.63 seconds |
| Started | Jul 06 08:15:03 PM PDT 24 |
| Finished | Jul 06 08:23:53 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-1517194f-f19c-492a-897d-bed1994411b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66550916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_ with_reset_error.66550916 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.2454836158 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 147151477 ps |
| CPU time | 21.47 seconds |
| Started | Jul 06 08:14:58 PM PDT 24 |
| Finished | Jul 06 08:15:20 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-ef6bc8b0-9999-42b8-b8e6-a8ddf4e5833e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454836158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2454836158 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.3427941074 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 810036394 ps |
| CPU time | 62.33 seconds |
| Started | Jul 06 08:15:06 PM PDT 24 |
| Finished | Jul 06 08:16:09 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-b70341ea-5784-4592-bbd9-d11f965a3a6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427941074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .3427941074 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.1332934914 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 30884547195 ps |
| CPU time | 578.63 seconds |
| Started | Jul 06 08:15:03 PM PDT 24 |
| Finished | Jul 06 08:24:42 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-23e09b53-c42d-4809-943f-51863990860f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332934914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.1332934914 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.569482738 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 492347290 ps |
| CPU time | 23.15 seconds |
| Started | Jul 06 08:15:18 PM PDT 24 |
| Finished | Jul 06 08:15:42 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-a615e722-df53-4d51-8af8-2cd2325dedf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569482738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr .569482738 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.1683903205 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 922445816 ps |
| CPU time | 34 seconds |
| Started | Jul 06 08:15:08 PM PDT 24 |
| Finished | Jul 06 08:15:43 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-44dca5c8-928b-410f-9077-85c513a3de11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683903205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1683903205 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.1055246708 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 2302752280 ps |
| CPU time | 92.03 seconds |
| Started | Jul 06 08:15:05 PM PDT 24 |
| Finished | Jul 06 08:16:37 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-4e859d17-3b66-4ab6-aeda-dfa603e1ba2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055246708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.1055246708 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.1509915410 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 8830862212 ps |
| CPU time | 93.38 seconds |
| Started | Jul 06 08:15:02 PM PDT 24 |
| Finished | Jul 06 08:16:35 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-8da3aace-dc37-4168-93a5-69a644c8a211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509915410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1509915410 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.1901493128 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 64392354410 ps |
| CPU time | 1156.12 seconds |
| Started | Jul 06 08:15:08 PM PDT 24 |
| Finished | Jul 06 08:34:25 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-b01d2926-596e-432b-9a68-de8e99a90455 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901493128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1901493128 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.1813277353 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 233743403 ps |
| CPU time | 20.19 seconds |
| Started | Jul 06 08:15:03 PM PDT 24 |
| Finished | Jul 06 08:15:24 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-f8e348ff-c0de-477e-81f6-226c12e71671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813277353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.1813277353 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.3482422243 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 1127591132 ps |
| CPU time | 38.47 seconds |
| Started | Jul 06 08:15:08 PM PDT 24 |
| Finished | Jul 06 08:15:47 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-fb66fad9-ecce-49bf-8bd9-5462c4f21a53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482422243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3482422243 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.1437541383 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 142355663 ps |
| CPU time | 7.88 seconds |
| Started | Jul 06 08:15:02 PM PDT 24 |
| Finished | Jul 06 08:15:10 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-ddae96f0-691c-46ea-b6d1-bea80e2cb1d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437541383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1437541383 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.2388458035 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 9162526698 ps |
| CPU time | 95.15 seconds |
| Started | Jul 06 08:15:05 PM PDT 24 |
| Finished | Jul 06 08:16:40 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-8453dfbd-262f-45d8-886d-b33c499d1b4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388458035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2388458035 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.1850564500 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 3564312322 ps |
| CPU time | 61.45 seconds |
| Started | Jul 06 08:15:05 PM PDT 24 |
| Finished | Jul 06 08:16:07 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-be153463-3f3f-4f51-abc8-f21206bd25dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850564500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1850564500 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.3437261508 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 46261443 ps |
| CPU time | 6.89 seconds |
| Started | Jul 06 08:15:06 PM PDT 24 |
| Finished | Jul 06 08:15:13 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-b83eb488-772b-42e5-8929-ec3fc7fa5e5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437261508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.3437261508 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.3975397672 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 2650266999 ps |
| CPU time | 250.38 seconds |
| Started | Jul 06 08:15:11 PM PDT 24 |
| Finished | Jul 06 08:19:22 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-afb63a84-2f88-4d9b-b3e8-d4c573f8eb96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975397672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3975397672 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.2524475635 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 6810178412 ps |
| CPU time | 294.87 seconds |
| Started | Jul 06 08:15:15 PM PDT 24 |
| Finished | Jul 06 08:20:10 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-addc2cef-a254-4408-bf31-f133b9f7d751 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524475635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2524475635 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3760207315 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 996385861 ps |
| CPU time | 201.08 seconds |
| Started | Jul 06 08:15:12 PM PDT 24 |
| Finished | Jul 06 08:18:34 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-b1644e1e-dcbe-4c79-acae-28e05de57b71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760207315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.3760207315 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.3834578257 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 618472543 ps |
| CPU time | 175.09 seconds |
| Started | Jul 06 08:15:15 PM PDT 24 |
| Finished | Jul 06 08:18:11 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-76653b37-83e9-4c59-9398-5616cb2cee1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834578257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.3834578257 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.1079464376 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 1033167079 ps |
| CPU time | 53.37 seconds |
| Started | Jul 06 08:15:11 PM PDT 24 |
| Finished | Jul 06 08:16:05 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-c7ee4da5-eb25-4254-a85c-436129d6eca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079464376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1079464376 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.994225721 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 2091833651 ps |
| CPU time | 93.32 seconds |
| Started | Jul 06 08:15:22 PM PDT 24 |
| Finished | Jul 06 08:16:55 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-1a8cf243-5fd1-4f2b-8182-9f5b295764c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994225721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device. 994225721 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2307964667 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 92005469332 ps |
| CPU time | 1543.82 seconds |
| Started | Jul 06 08:15:20 PM PDT 24 |
| Finished | Jul 06 08:41:04 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-d6db5703-9007-456d-8bf1-be2c0156a2b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307964667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.2307964667 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.4164869881 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 351595616 ps |
| CPU time | 41.71 seconds |
| Started | Jul 06 08:15:22 PM PDT 24 |
| Finished | Jul 06 08:16:04 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-c14ad947-2eac-45fa-9cea-4fe34520a815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164869881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.4164869881 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.1116161645 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 1863926607 ps |
| CPU time | 70.03 seconds |
| Started | Jul 06 08:15:17 PM PDT 24 |
| Finished | Jul 06 08:16:28 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-e78c87ea-cb2c-4ea0-98b6-0e1d54010322 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116161645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1116161645 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.265975210 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 35292941 ps |
| CPU time | 6.33 seconds |
| Started | Jul 06 08:15:12 PM PDT 24 |
| Finished | Jul 06 08:15:19 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-be089868-55c9-4c41-8717-422bd9b803f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265975210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.265975210 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.3697193146 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 78726547351 ps |
| CPU time | 766.27 seconds |
| Started | Jul 06 08:15:20 PM PDT 24 |
| Finished | Jul 06 08:28:07 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-68dd825b-f50d-4648-bed9-e33885f2a203 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697193146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3697193146 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.2865564124 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 14564950098 ps |
| CPU time | 264.91 seconds |
| Started | Jul 06 08:15:17 PM PDT 24 |
| Finished | Jul 06 08:19:42 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-e84e6932-f1e4-478e-ab5e-3780773b5762 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865564124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2865564124 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.3370451404 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 498393494 ps |
| CPU time | 51.57 seconds |
| Started | Jul 06 08:15:18 PM PDT 24 |
| Finished | Jul 06 08:16:10 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-bcc61680-129d-4a88-bb68-aa3252220c0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370451404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.3370451404 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.1094087719 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 1760743661 ps |
| CPU time | 60.24 seconds |
| Started | Jul 06 08:15:17 PM PDT 24 |
| Finished | Jul 06 08:16:17 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-2364dcec-a298-487b-9da8-129872c36111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094087719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1094087719 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.661247994 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 48927531 ps |
| CPU time | 7.57 seconds |
| Started | Jul 06 08:15:12 PM PDT 24 |
| Finished | Jul 06 08:15:20 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-bb91cb0c-e538-4c86-b5c9-390c7943ce79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661247994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.661247994 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.1789425014 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 7317017911 ps |
| CPU time | 82.71 seconds |
| Started | Jul 06 08:15:15 PM PDT 24 |
| Finished | Jul 06 08:16:38 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-84d148a7-4369-44e5-a0d6-f03d416aa2a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789425014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1789425014 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1617101164 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 3419549048 ps |
| CPU time | 62.59 seconds |
| Started | Jul 06 08:15:18 PM PDT 24 |
| Finished | Jul 06 08:16:21 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-86af06d2-5cb1-41aa-ace0-9b2644fa0174 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617101164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1617101164 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.4248295176 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 47527479 ps |
| CPU time | 6.81 seconds |
| Started | Jul 06 08:15:15 PM PDT 24 |
| Finished | Jul 06 08:15:22 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-6ddae910-c5c9-4fd4-9514-2166ca757e9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248295176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.4248295176 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.1849837973 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 1502476323 ps |
| CPU time | 142.5 seconds |
| Started | Jul 06 08:15:18 PM PDT 24 |
| Finished | Jul 06 08:17:41 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-de37dc78-049e-4df8-af90-054ccdb26ea0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849837973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1849837973 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.263999186 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 3038021521 ps |
| CPU time | 239.53 seconds |
| Started | Jul 06 08:15:21 PM PDT 24 |
| Finished | Jul 06 08:19:21 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-576ee550-c275-4254-85bf-028ce991af92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263999186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.263999186 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.1651333594 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 1891264337 ps |
| CPU time | 439.32 seconds |
| Started | Jul 06 08:15:17 PM PDT 24 |
| Finished | Jul 06 08:22:37 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-ad9be35e-d602-4f16-aec0-d52841d9a9b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651333594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.1651333594 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.2409152384 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 12850616593 ps |
| CPU time | 579.89 seconds |
| Started | Jul 06 08:15:23 PM PDT 24 |
| Finished | Jul 06 08:25:03 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-37a1667c-5d83-447d-8e20-4f2c35d8e445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409152384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.2409152384 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.845962292 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 1201528245 ps |
| CPU time | 59.13 seconds |
| Started | Jul 06 08:15:17 PM PDT 24 |
| Finished | Jul 06 08:16:17 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-9ae9f18d-8237-4418-85e5-6b1ab4adf095 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845962292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.845962292 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.3749770482 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 3345410879 ps |
| CPU time | 127.61 seconds |
| Started | Jul 06 08:15:32 PM PDT 24 |
| Finished | Jul 06 08:17:40 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-e2b90d48-07ae-40b9-ae77-48726c4f9b70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749770482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .3749770482 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.2904507311 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 2934532012 ps |
| CPU time | 52.87 seconds |
| Started | Jul 06 08:15:28 PM PDT 24 |
| Finished | Jul 06 08:16:21 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-72b087b1-d1c8-4bbb-abe1-dd065b8c43fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904507311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.2904507311 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.4185330169 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 224254429 ps |
| CPU time | 23.93 seconds |
| Started | Jul 06 08:15:33 PM PDT 24 |
| Finished | Jul 06 08:15:58 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-147c24eb-29fb-474d-bc1f-d6362730e1a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185330169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.4185330169 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.1290686091 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 1817710911 ps |
| CPU time | 75.23 seconds |
| Started | Jul 06 08:15:27 PM PDT 24 |
| Finished | Jul 06 08:16:43 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-20c283c2-df94-4410-acf6-e3d24c8e0e06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290686091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1290686091 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.1519984245 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 72881561 ps |
| CPU time | 10.38 seconds |
| Started | Jul 06 08:15:23 PM PDT 24 |
| Finished | Jul 06 08:15:34 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-db1ace97-ccca-4482-90cd-d95b5ef7e19f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519984245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.1519984245 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.3654052131 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 96013118392 ps |
| CPU time | 920.14 seconds |
| Started | Jul 06 08:15:25 PM PDT 24 |
| Finished | Jul 06 08:30:46 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-fd60fe87-c84d-40b7-a306-c5536076f29c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654052131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3654052131 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.2456671507 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 20280568403 ps |
| CPU time | 359.25 seconds |
| Started | Jul 06 08:15:28 PM PDT 24 |
| Finished | Jul 06 08:21:27 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-b4f593fa-a276-4a10-a077-2a5f2be11a4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456671507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2456671507 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.1292545601 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 493025506 ps |
| CPU time | 45.85 seconds |
| Started | Jul 06 08:15:27 PM PDT 24 |
| Finished | Jul 06 08:16:13 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-c98ae68d-9a29-4b51-a08d-10fc5c7c97ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292545601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.1292545601 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.1739861587 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 44557735 ps |
| CPU time | 7.08 seconds |
| Started | Jul 06 08:15:28 PM PDT 24 |
| Finished | Jul 06 08:15:35 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-79dc8cd3-e28d-435c-83e7-8dccb09ab1ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739861587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1739861587 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.3806312202 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 57275267 ps |
| CPU time | 6.86 seconds |
| Started | Jul 06 08:15:22 PM PDT 24 |
| Finished | Jul 06 08:15:29 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-cd865623-d100-433b-afbb-3646271ca7ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806312202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3806312202 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.2852231847 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 5690429942 ps |
| CPU time | 58 seconds |
| Started | Jul 06 08:15:20 PM PDT 24 |
| Finished | Jul 06 08:16:19 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-1b59eccc-8fad-4cd0-9063-bc3acc054ffe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852231847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2852231847 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1984347063 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 4898677438 ps |
| CPU time | 86.03 seconds |
| Started | Jul 06 08:15:20 PM PDT 24 |
| Finished | Jul 06 08:16:47 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-81bd0535-c17a-4fd7-bde1-9f3cddbe6379 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984347063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1984347063 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.1339205210 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 53619631 ps |
| CPU time | 6.91 seconds |
| Started | Jul 06 08:15:23 PM PDT 24 |
| Finished | Jul 06 08:15:31 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-0e7c29cb-4884-4dce-ac27-a215f6eeae4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339205210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay s.1339205210 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.73564272 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 2043557613 ps |
| CPU time | 66.82 seconds |
| Started | Jul 06 08:15:34 PM PDT 24 |
| Finished | Jul 06 08:16:41 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-6fb308f0-3511-4901-bc7d-84ed7f8fe977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73564272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.73564272 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.1228988853 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 3719719443 ps |
| CPU time | 273.51 seconds |
| Started | Jul 06 08:15:34 PM PDT 24 |
| Finished | Jul 06 08:20:08 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-bffccec1-6f29-46e8-a015-6a8136e27e1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228988853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1228988853 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.3441284831 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 481465139 ps |
| CPU time | 168.26 seconds |
| Started | Jul 06 08:15:35 PM PDT 24 |
| Finished | Jul 06 08:18:23 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-d8df4918-3ba7-4acc-b3ad-5568f919f08e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441284831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.3441284831 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.213751860 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 1005768894 ps |
| CPU time | 54.97 seconds |
| Started | Jul 06 08:15:28 PM PDT 24 |
| Finished | Jul 06 08:16:23 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-1173d690-8231-46df-b1ce-9fe47c6e2144 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213751860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.213751860 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.1077092361 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 1406250823 ps |
| CPU time | 62.23 seconds |
| Started | Jul 06 08:15:38 PM PDT 24 |
| Finished | Jul 06 08:16:41 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-287b9292-884e-42d6-8532-c4d8c2cbb17f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077092361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .1077092361 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.493464286 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 34748937813 ps |
| CPU time | 663.27 seconds |
| Started | Jul 06 08:15:37 PM PDT 24 |
| Finished | Jul 06 08:26:41 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-e97f2225-142b-43a1-8e00-0062e9595e5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493464286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_d evice_slow_rsp.493464286 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.2261501361 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 95786196 ps |
| CPU time | 7.72 seconds |
| Started | Jul 06 08:15:44 PM PDT 24 |
| Finished | Jul 06 08:15:52 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-26a35482-e700-4d48-961c-42777a712ac4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261501361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.2261501361 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.500963137 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 292156842 ps |
| CPU time | 27.97 seconds |
| Started | Jul 06 08:15:45 PM PDT 24 |
| Finished | Jul 06 08:16:13 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-ef458af8-0bea-448a-9479-5f69ec9dfb3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500963137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.500963137 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.1813684886 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 364787622 ps |
| CPU time | 18.26 seconds |
| Started | Jul 06 08:15:37 PM PDT 24 |
| Finished | Jul 06 08:15:56 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-7cf34d0a-9def-45ad-b6a8-b85ddf21c391 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813684886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.1813684886 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.2713133372 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 103640126535 ps |
| CPU time | 1107.04 seconds |
| Started | Jul 06 08:15:39 PM PDT 24 |
| Finished | Jul 06 08:34:06 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-84c38755-c591-4552-9cbe-95e7030a96c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713133372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2713133372 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.2202817047 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 23813178975 ps |
| CPU time | 422.34 seconds |
| Started | Jul 06 08:15:41 PM PDT 24 |
| Finished | Jul 06 08:22:44 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-efcd2357-c8fa-4d20-9236-ca2742e16a9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202817047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2202817047 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.3362749423 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 173914678 ps |
| CPU time | 18.51 seconds |
| Started | Jul 06 08:15:37 PM PDT 24 |
| Finished | Jul 06 08:15:55 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-10c0fad9-f592-4a26-ab5b-7e1d9e558fe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362749423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.3362749423 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.3135213536 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 455904901 ps |
| CPU time | 33.49 seconds |
| Started | Jul 06 08:15:39 PM PDT 24 |
| Finished | Jul 06 08:16:13 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-e69c7a2c-13c2-4d78-bf3a-6ce26dafb21b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135213536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3135213536 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.569434035 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 199279868 ps |
| CPU time | 9.85 seconds |
| Started | Jul 06 08:15:35 PM PDT 24 |
| Finished | Jul 06 08:15:46 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-a60aebad-38c5-4e66-8c96-f3d5dd302292 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569434035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.569434035 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.882043490 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 8341664580 ps |
| CPU time | 84.49 seconds |
| Started | Jul 06 08:16:40 PM PDT 24 |
| Finished | Jul 06 08:18:05 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-eeb6321a-a587-4a4b-a566-b1d1636e50b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882043490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.882043490 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.2309843675 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 6174708759 ps |
| CPU time | 104.96 seconds |
| Started | Jul 06 08:15:37 PM PDT 24 |
| Finished | Jul 06 08:17:22 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-9ffb8887-7f07-498c-9668-e84dea5441bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309843675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2309843675 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.40323759 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 49788729 ps |
| CPU time | 7.16 seconds |
| Started | Jul 06 08:15:33 PM PDT 24 |
| Finished | Jul 06 08:15:40 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-6a511d03-5349-4abc-85b9-33d462aa088d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40323759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.40323759 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.199483787 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 1209251302 ps |
| CPU time | 97.57 seconds |
| Started | Jul 06 08:15:47 PM PDT 24 |
| Finished | Jul 06 08:17:25 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-e78a1f8e-92f3-4df2-a75a-b0cb9ef6c807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199483787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.199483787 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.1781618271 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 779199652 ps |
| CPU time | 76.5 seconds |
| Started | Jul 06 08:15:46 PM PDT 24 |
| Finished | Jul 06 08:17:03 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-ccac3ca7-b5e7-41fe-b68a-58b59498d47d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781618271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1781618271 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.1919332772 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 10929220944 ps |
| CPU time | 544.97 seconds |
| Started | Jul 06 08:15:46 PM PDT 24 |
| Finished | Jul 06 08:24:52 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-536b65fb-c07c-49f7-a25f-e3ec9431e7b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919332772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.1919332772 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2097261939 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 3343911877 ps |
| CPU time | 437.99 seconds |
| Started | Jul 06 08:15:44 PM PDT 24 |
| Finished | Jul 06 08:23:02 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-f5c4e111-262f-4179-93b6-f5d89b98849d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097261939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.2097261939 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.104731070 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 79937457 ps |
| CPU time | 12.65 seconds |
| Started | Jul 06 08:15:43 PM PDT 24 |
| Finished | Jul 06 08:15:56 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-eaab712f-2d02-4540-94d0-7afae51724b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104731070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.104731070 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.3828486107 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 5858377812 ps |
| CPU time | 645.11 seconds |
| Started | Jul 06 08:03:41 PM PDT 24 |
| Finished | Jul 06 08:14:27 PM PDT 24 |
| Peak memory | 598508 kb |
| Host | smart-5f542dee-2e10-4c94-b16c-8d0fdcf38d33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828486107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.3828486107 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.614256021 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 13489807744 ps |
| CPU time | 1768.72 seconds |
| Started | Jul 06 08:03:24 PM PDT 24 |
| Finished | Jul 06 08:32:53 PM PDT 24 |
| Peak memory | 591856 kb |
| Host | smart-b1849fa7-1b3f-41a7-ac61-12a4afe2f404 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614256021 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.chip_same_csr_outstanding.614256021 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.481691055 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 2930131431 ps |
| CPU time | 99.37 seconds |
| Started | Jul 06 08:03:21 PM PDT 24 |
| Finished | Jul 06 08:05:01 PM PDT 24 |
| Peak memory | 597392 kb |
| Host | smart-8c350a1f-10ed-490a-8404-a2bd31f380b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481691055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.481691055 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.2342492094 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 704622260 ps |
| CPU time | 74.59 seconds |
| Started | Jul 06 08:03:25 PM PDT 24 |
| Finished | Jul 06 08:04:40 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-f160198c-20f2-417c-9789-259723d9cc87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342492094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 2342492094 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1608366797 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 22725161938 ps |
| CPU time | 415.11 seconds |
| Started | Jul 06 08:03:27 PM PDT 24 |
| Finished | Jul 06 08:10:23 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-e1d3ef75-e379-4a94-beb6-868ac43be1cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608366797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.1608366797 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.3069619178 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 216763621 ps |
| CPU time | 25.94 seconds |
| Started | Jul 06 08:06:27 PM PDT 24 |
| Finished | Jul 06 08:06:53 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-ca41d651-2475-4bc2-a365-a4767845dbe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069619178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .3069619178 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.1688050666 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 302910408 ps |
| CPU time | 24.67 seconds |
| Started | Jul 06 08:03:34 PM PDT 24 |
| Finished | Jul 06 08:03:59 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-da5692d2-df6e-4598-9aab-fb5697787dab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688050666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1688050666 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.2307299737 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 127690223 ps |
| CPU time | 15.49 seconds |
| Started | Jul 06 08:03:25 PM PDT 24 |
| Finished | Jul 06 08:03:41 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-3a38ac86-ad0a-4143-9eef-b81eb1029abb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307299737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.2307299737 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.4084395309 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 101200261598 ps |
| CPU time | 1184.53 seconds |
| Started | Jul 06 08:03:26 PM PDT 24 |
| Finished | Jul 06 08:23:11 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-3fe49eb3-0c75-4b7e-833e-4180268a6927 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084395309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.4084395309 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.2935697892 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 41270705177 ps |
| CPU time | 744.99 seconds |
| Started | Jul 06 08:03:29 PM PDT 24 |
| Finished | Jul 06 08:15:55 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-88fad681-2849-4566-900b-59077babda61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935697892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2935697892 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.51793801 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 79806091 ps |
| CPU time | 11.3 seconds |
| Started | Jul 06 08:03:24 PM PDT 24 |
| Finished | Jul 06 08:03:36 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-6a2b3a41-e22d-48a6-b62b-ceed4bb68ae8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51793801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays .51793801 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.4110345565 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 240679476 ps |
| CPU time | 24.91 seconds |
| Started | Jul 06 08:03:44 PM PDT 24 |
| Finished | Jul 06 08:04:10 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-73244a7d-ecc4-4573-9be0-9e5b9cfe068e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110345565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.4110345565 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.1010137599 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 37311351 ps |
| CPU time | 5.92 seconds |
| Started | Jul 06 08:03:23 PM PDT 24 |
| Finished | Jul 06 08:03:29 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-05cca50e-933a-4cf9-ab22-52a7c5847253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010137599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1010137599 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.4244693304 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 6249597355 ps |
| CPU time | 62.97 seconds |
| Started | Jul 06 08:03:20 PM PDT 24 |
| Finished | Jul 06 08:04:24 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-97f62d4c-17d9-4af1-befa-bed9657d9cc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244693304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.4244693304 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.2541328891 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 3444480291 ps |
| CPU time | 62.9 seconds |
| Started | Jul 06 08:03:22 PM PDT 24 |
| Finished | Jul 06 08:04:26 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-a526af72-d7be-4997-9912-c50d9e84b64e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541328891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2541328891 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.369447301 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 45300352 ps |
| CPU time | 6.31 seconds |
| Started | Jul 06 08:03:22 PM PDT 24 |
| Finished | Jul 06 08:03:29 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-37007be6-8b33-4ffd-9af8-d7ba2905dc1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369447301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays. 369447301 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.2127600766 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 548125691 ps |
| CPU time | 67.23 seconds |
| Started | Jul 06 08:03:36 PM PDT 24 |
| Finished | Jul 06 08:04:43 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-512733b1-c9fd-4c15-9fce-8e41a2b279e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127600766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2127600766 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.2414999772 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 6549859950 ps |
| CPU time | 298.95 seconds |
| Started | Jul 06 08:03:35 PM PDT 24 |
| Finished | Jul 06 08:08:34 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-a2f2a2f4-794e-4ad7-9ac9-1bad520c2b63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414999772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2414999772 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3356023472 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 6113341029 ps |
| CPU time | 677.18 seconds |
| Started | Jul 06 08:03:35 PM PDT 24 |
| Finished | Jul 06 08:14:53 PM PDT 24 |
| Peak memory | 576820 kb |
| Host | smart-ad722875-b175-4b5c-9ac6-387a3b6851b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356023472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.3356023472 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1304063660 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 8583181888 ps |
| CPU time | 817.18 seconds |
| Started | Jul 06 08:03:41 PM PDT 24 |
| Finished | Jul 06 08:17:19 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-a0d5c229-e449-4b55-a598-8d208c68423a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304063660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.1304063660 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.2380071734 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 52246383 ps |
| CPU time | 9.69 seconds |
| Started | Jul 06 08:03:34 PM PDT 24 |
| Finished | Jul 06 08:03:44 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-84d30417-1410-4077-8781-b834f06f28e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380071734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2380071734 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.496133604 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 1463420639 ps |
| CPU time | 85.2 seconds |
| Started | Jul 06 08:15:48 PM PDT 24 |
| Finished | Jul 06 08:17:14 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-c733c524-bd42-4b15-a0ba-fb9515ccbb29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496133604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device. 496133604 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1883670018 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 95764886865 ps |
| CPU time | 1616.04 seconds |
| Started | Jul 06 08:15:50 PM PDT 24 |
| Finished | Jul 06 08:42:46 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-6b4584fd-5a8f-4e95-8a36-82768dcde75c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883670018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.1883670018 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.991688500 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 1371992528 ps |
| CPU time | 50.97 seconds |
| Started | Jul 06 08:15:55 PM PDT 24 |
| Finished | Jul 06 08:16:46 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-42aeb78d-be43-4918-95c5-5568d3fae5f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991688500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_addr .991688500 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.926939215 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 853949266 ps |
| CPU time | 26.14 seconds |
| Started | Jul 06 08:15:46 PM PDT 24 |
| Finished | Jul 06 08:16:12 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-040032b8-aad2-4c15-be22-73e1f6fdb951 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926939215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.926939215 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.4062432914 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 266495937 ps |
| CPU time | 29.41 seconds |
| Started | Jul 06 08:15:48 PM PDT 24 |
| Finished | Jul 06 08:16:18 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-43c95b00-1dc0-4481-9d23-db1235873108 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062432914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.4062432914 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.513355485 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 25922796696 ps |
| CPU time | 296.3 seconds |
| Started | Jul 06 08:15:47 PM PDT 24 |
| Finished | Jul 06 08:20:44 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-31791a27-6687-4ad2-873d-64f7d96c0232 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513355485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.513355485 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.4122053435 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 36072385002 ps |
| CPU time | 663.74 seconds |
| Started | Jul 06 08:15:49 PM PDT 24 |
| Finished | Jul 06 08:26:54 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-26de085d-832e-42c2-bc89-16d769819ac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122053435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.4122053435 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.3665907895 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 122009941 ps |
| CPU time | 12.82 seconds |
| Started | Jul 06 08:15:51 PM PDT 24 |
| Finished | Jul 06 08:16:04 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-a84b71e2-40fb-44dd-98bc-b7c85945e8f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665907895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.3665907895 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.1190533532 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 270589473 ps |
| CPU time | 24.97 seconds |
| Started | Jul 06 08:15:48 PM PDT 24 |
| Finished | Jul 06 08:16:13 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-9f9f62c5-d023-45a4-a7ec-3eb9cc505e83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190533532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.1190533532 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.4018973153 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 213721602 ps |
| CPU time | 9.1 seconds |
| Started | Jul 06 08:15:43 PM PDT 24 |
| Finished | Jul 06 08:15:52 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-9430003b-89e4-4bac-b38a-826f996f25a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018973153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.4018973153 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.3347418415 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 10014719482 ps |
| CPU time | 115.98 seconds |
| Started | Jul 06 08:15:48 PM PDT 24 |
| Finished | Jul 06 08:17:44 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-c0c27c5e-e0b4-41a6-b5da-bc348da162ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347418415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.3347418415 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.2717380204 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 4015291629 ps |
| CPU time | 71.09 seconds |
| Started | Jul 06 08:15:49 PM PDT 24 |
| Finished | Jul 06 08:17:01 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-b0a10d27-6256-4934-81b1-cfd595d7f752 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717380204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.2717380204 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.1887777260 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 44184989 ps |
| CPU time | 6.86 seconds |
| Started | Jul 06 08:15:47 PM PDT 24 |
| Finished | Jul 06 08:15:54 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-cd4e99e3-d452-4101-a113-d02dd0361fc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887777260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.1887777260 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.3430978176 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 872210740 ps |
| CPU time | 75.29 seconds |
| Started | Jul 06 08:15:52 PM PDT 24 |
| Finished | Jul 06 08:17:08 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-97e8de8f-a7e9-4df0-9c16-9d7e049a3edd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430978176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.3430978176 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.2799483439 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 4309971124 ps |
| CPU time | 138.94 seconds |
| Started | Jul 06 08:15:52 PM PDT 24 |
| Finished | Jul 06 08:18:11 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-58f9334e-1564-471c-93d7-e21460d5edbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799483439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.2799483439 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.1943092251 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1310971726 ps |
| CPU time | 260.06 seconds |
| Started | Jul 06 08:15:53 PM PDT 24 |
| Finished | Jul 06 08:20:13 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-2b106b38-1206-41bf-9cfd-2e03a02dbc51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943092251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.1943092251 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.166795349 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 228199072 ps |
| CPU time | 12.7 seconds |
| Started | Jul 06 08:15:52 PM PDT 24 |
| Finished | Jul 06 08:16:05 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-6687d68f-d515-4ce6-9fc2-3e50d77e508a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166795349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.166795349 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.3184107095 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 3198734647 ps |
| CPU time | 140.49 seconds |
| Started | Jul 06 08:15:58 PM PDT 24 |
| Finished | Jul 06 08:18:19 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-87b5c831-7d45-44d1-a4f7-b2fe857fa4b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184107095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .3184107095 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.237117565 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 47481068860 ps |
| CPU time | 786.02 seconds |
| Started | Jul 06 08:15:59 PM PDT 24 |
| Finished | Jul 06 08:29:05 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-3c2bd9e9-2fe9-4dbc-8e53-f7603f970f87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237117565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_d evice_slow_rsp.237117565 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.703708237 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 19051535 ps |
| CPU time | 5.43 seconds |
| Started | Jul 06 08:16:02 PM PDT 24 |
| Finished | Jul 06 08:16:07 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-e6e7c925-35e3-4ba3-afa8-f82dc97b34ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703708237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_addr .703708237 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.534386977 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 430952805 ps |
| CPU time | 17.03 seconds |
| Started | Jul 06 08:15:59 PM PDT 24 |
| Finished | Jul 06 08:16:16 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-88785dfd-60b8-4f48-a778-4de01e7e6b73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534386977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.534386977 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.1185983552 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 1772413310 ps |
| CPU time | 65.49 seconds |
| Started | Jul 06 08:15:51 PM PDT 24 |
| Finished | Jul 06 08:16:57 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-340e2297-e2c7-413b-9d20-ab334fd824e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185983552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.1185983552 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.3439507764 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 75990659894 ps |
| CPU time | 876.28 seconds |
| Started | Jul 06 08:15:56 PM PDT 24 |
| Finished | Jul 06 08:30:33 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-5ccc14bf-2704-4fd1-967a-f2d25fc50518 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439507764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.3439507764 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.2093709535 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 51094513164 ps |
| CPU time | 884.11 seconds |
| Started | Jul 06 08:15:57 PM PDT 24 |
| Finished | Jul 06 08:30:42 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-cc68ed10-f742-4204-8580-bf59f68f422a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093709535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.2093709535 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.121261916 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 568057019 ps |
| CPU time | 55.47 seconds |
| Started | Jul 06 08:15:57 PM PDT 24 |
| Finished | Jul 06 08:16:53 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-cfc016f3-32e8-4228-a65a-c64d95f23828 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121261916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_dela ys.121261916 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.1903696160 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 2077206900 ps |
| CPU time | 71.03 seconds |
| Started | Jul 06 08:15:59 PM PDT 24 |
| Finished | Jul 06 08:17:10 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-311dcb3d-f0cd-4046-a8e1-1b98a92f3834 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903696160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.1903696160 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.556887133 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 234801734 ps |
| CPU time | 9.81 seconds |
| Started | Jul 06 08:15:51 PM PDT 24 |
| Finished | Jul 06 08:16:01 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-dff566eb-af1e-4ba2-9d1e-9387f445852b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556887133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.556887133 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.3808067777 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 6633357893 ps |
| CPU time | 71.08 seconds |
| Started | Jul 06 08:15:52 PM PDT 24 |
| Finished | Jul 06 08:17:04 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-1f58ff73-e1f2-47e5-9dce-c9e0d388645a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808067777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.3808067777 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3868306833 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 5048420443 ps |
| CPU time | 87.63 seconds |
| Started | Jul 06 08:15:53 PM PDT 24 |
| Finished | Jul 06 08:17:21 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-57d17d22-96d4-4b4f-b487-6b1a27120bd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868306833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.3868306833 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.3739827293 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 50952786 ps |
| CPU time | 6.4 seconds |
| Started | Jul 06 08:15:55 PM PDT 24 |
| Finished | Jul 06 08:16:02 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-c8d6aa12-159e-403e-9f10-d9f6c9823e86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739827293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.3739827293 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.2515105463 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 11177196030 ps |
| CPU time | 395.86 seconds |
| Started | Jul 06 08:16:09 PM PDT 24 |
| Finished | Jul 06 08:22:45 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-0e3a862d-8e5d-4a76-b827-b482935faf39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515105463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.2515105463 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.1266800257 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 3750918186 ps |
| CPU time | 120.7 seconds |
| Started | Jul 06 08:16:04 PM PDT 24 |
| Finished | Jul 06 08:18:05 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-dac8ac4b-3527-452f-88ea-d17c1e726627 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266800257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.1266800257 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1564694390 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 4188619607 ps |
| CPU time | 432.7 seconds |
| Started | Jul 06 08:16:03 PM PDT 24 |
| Finished | Jul 06 08:23:16 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-dfec4ed0-c708-4954-884f-4c5a01d29d77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564694390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.1564694390 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.524863565 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 4233995016 ps |
| CPU time | 388.27 seconds |
| Started | Jul 06 08:16:04 PM PDT 24 |
| Finished | Jul 06 08:22:33 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-3fa65c98-b70f-4fc5-89d7-dc324dd97da5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524863565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_reset_error.524863565 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.3542400472 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 1509081133 ps |
| CPU time | 66.01 seconds |
| Started | Jul 06 08:16:00 PM PDT 24 |
| Finished | Jul 06 08:17:06 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-bfaa5aeb-2607-4162-a869-9446e3acba85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542400472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.3542400472 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.3745649116 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 1464213888 ps |
| CPU time | 56.89 seconds |
| Started | Jul 06 08:16:07 PM PDT 24 |
| Finished | Jul 06 08:17:04 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-f4f795ae-77f4-4917-b496-4dc203e75ec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745649116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .3745649116 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.1871563665 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 117467591899 ps |
| CPU time | 1966.28 seconds |
| Started | Jul 06 08:16:14 PM PDT 24 |
| Finished | Jul 06 08:49:01 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-3806488a-3e11-4040-9b89-deb03c3afeda |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871563665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.1871563665 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.483303315 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 919067867 ps |
| CPU time | 40.37 seconds |
| Started | Jul 06 08:16:08 PM PDT 24 |
| Finished | Jul 06 08:16:48 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-1bf8ff16-63bb-485c-abdc-8070545372b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483303315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_addr .483303315 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.909968775 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 131151811 ps |
| CPU time | 14.04 seconds |
| Started | Jul 06 08:16:07 PM PDT 24 |
| Finished | Jul 06 08:16:21 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-3e5d37d6-c8be-4ec5-a174-881cc8188abc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909968775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.909968775 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.986955277 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 406405153 ps |
| CPU time | 38.59 seconds |
| Started | Jul 06 08:16:09 PM PDT 24 |
| Finished | Jul 06 08:16:48 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-11cd59e2-bd0b-4bbb-b5bd-c0f49f0e906f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986955277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.986955277 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.2934593717 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 114890446358 ps |
| CPU time | 1197.21 seconds |
| Started | Jul 06 08:16:10 PM PDT 24 |
| Finished | Jul 06 08:36:08 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-8a383b47-9d5c-4e7f-8adf-490fd3434ac0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934593717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.2934593717 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.2602319198 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 42887217630 ps |
| CPU time | 736.6 seconds |
| Started | Jul 06 08:16:08 PM PDT 24 |
| Finished | Jul 06 08:28:25 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-7ab54e0b-953e-4f42-8593-2787926a2591 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602319198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.2602319198 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.941572811 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 478727568 ps |
| CPU time | 46 seconds |
| Started | Jul 06 08:16:09 PM PDT 24 |
| Finished | Jul 06 08:16:55 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-eb70bc90-c221-45bc-b27f-4cb8bb9512b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941572811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_dela ys.941572811 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.1041169572 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 829476892 ps |
| CPU time | 25.98 seconds |
| Started | Jul 06 08:16:09 PM PDT 24 |
| Finished | Jul 06 08:16:35 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-329fd017-9c3a-4023-bc14-4afee3d352a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041169572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.1041169572 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.3529349814 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 43219656 ps |
| CPU time | 6.46 seconds |
| Started | Jul 06 08:16:03 PM PDT 24 |
| Finished | Jul 06 08:16:10 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-641ebedd-4f34-43da-8b17-59b55e42a1df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529349814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.3529349814 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.3281177391 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 7045722019 ps |
| CPU time | 76.29 seconds |
| Started | Jul 06 08:16:03 PM PDT 24 |
| Finished | Jul 06 08:17:19 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-36261f77-3ec2-4fe3-abe8-b7e2a3be3397 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281177391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.3281177391 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1080622040 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 7215205014 ps |
| CPU time | 124.3 seconds |
| Started | Jul 06 08:16:02 PM PDT 24 |
| Finished | Jul 06 08:18:07 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-9d8d2e07-0e4e-4795-9759-5d8990f97ed0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080622040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.1080622040 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2394693396 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 54945942 ps |
| CPU time | 7.16 seconds |
| Started | Jul 06 08:16:03 PM PDT 24 |
| Finished | Jul 06 08:16:10 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-7647a277-7662-4d43-8974-b0588bff1e4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394693396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.2394693396 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.1084597568 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 2135749504 ps |
| CPU time | 220.71 seconds |
| Started | Jul 06 08:16:07 PM PDT 24 |
| Finished | Jul 06 08:19:48 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-6fc81b23-0283-4bca-a23b-10c539e9195d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084597568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.1084597568 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.609970331 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 3456740392 ps |
| CPU time | 285.74 seconds |
| Started | Jul 06 08:16:13 PM PDT 24 |
| Finished | Jul 06 08:20:59 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-5a4abe0e-24ef-4f60-a714-a726f91f6fc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609970331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.609970331 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2522784793 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 71250139 ps |
| CPU time | 91.06 seconds |
| Started | Jul 06 08:16:07 PM PDT 24 |
| Finished | Jul 06 08:17:38 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-4a9f218f-caa5-4d46-899f-d0458d18962f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522784793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.2522784793 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.2665405389 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 2987765867 ps |
| CPU time | 237.63 seconds |
| Started | Jul 06 08:16:05 PM PDT 24 |
| Finished | Jul 06 08:20:03 PM PDT 24 |
| Peak memory | 576992 kb |
| Host | smart-aa04993b-ea1a-4847-97b9-5e3aa97284cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665405389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.2665405389 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.2632905915 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 1056863705 ps |
| CPU time | 38.93 seconds |
| Started | Jul 06 08:16:11 PM PDT 24 |
| Finished | Jul 06 08:16:50 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-788d3532-7aee-4605-9fe7-f27b1c7e2280 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632905915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.2632905915 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3823505791 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 58902813336 ps |
| CPU time | 1014.52 seconds |
| Started | Jul 06 08:16:20 PM PDT 24 |
| Finished | Jul 06 08:33:15 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-39c2c61a-cd21-4587-95bc-590137e68c7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823505791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.3823505791 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2210738693 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 673888513 ps |
| CPU time | 33.15 seconds |
| Started | Jul 06 08:16:20 PM PDT 24 |
| Finished | Jul 06 08:16:53 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-460ec604-d7c6-428f-8fa0-cdf1ca8c85b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210738693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.2210738693 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.1899745866 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 2187082712 ps |
| CPU time | 82.71 seconds |
| Started | Jul 06 08:16:18 PM PDT 24 |
| Finished | Jul 06 08:17:41 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-3dc8b6c1-11d3-4a10-b9f3-441a735db917 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899745866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.1899745866 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.1909248591 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 615686707 ps |
| CPU time | 26.24 seconds |
| Started | Jul 06 08:16:12 PM PDT 24 |
| Finished | Jul 06 08:16:38 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-d762e08c-d4f3-4bca-8279-a58ecfdffe34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909248591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.1909248591 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.2383733538 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 36808315729 ps |
| CPU time | 419.02 seconds |
| Started | Jul 06 08:16:14 PM PDT 24 |
| Finished | Jul 06 08:23:13 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-07d91f80-2060-4ba5-82d5-b4af3b4e3c11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383733538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.2383733538 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.1197567962 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 39288061524 ps |
| CPU time | 683.24 seconds |
| Started | Jul 06 08:16:15 PM PDT 24 |
| Finished | Jul 06 08:27:39 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-5f27b070-ce3d-4c6c-9203-9bf199a95f2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197567962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.1197567962 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.1439135591 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 520043451 ps |
| CPU time | 48.08 seconds |
| Started | Jul 06 08:16:16 PM PDT 24 |
| Finished | Jul 06 08:17:04 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-cc091a69-bc71-4c85-bcb5-b7259a033f68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439135591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.1439135591 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.2897962816 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 384173883 ps |
| CPU time | 30.49 seconds |
| Started | Jul 06 08:16:17 PM PDT 24 |
| Finished | Jul 06 08:16:48 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-234ae994-b782-4731-b2b4-4625701b9ed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897962816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.2897962816 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.3442839865 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 173797141 ps |
| CPU time | 9.09 seconds |
| Started | Jul 06 08:16:15 PM PDT 24 |
| Finished | Jul 06 08:16:25 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-7d5edd70-e85f-467d-88e2-865eb0ac4ea2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442839865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.3442839865 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.1337997950 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 9231111584 ps |
| CPU time | 103.65 seconds |
| Started | Jul 06 08:16:15 PM PDT 24 |
| Finished | Jul 06 08:17:59 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-ca0a4ffe-84b4-4f4e-abb2-8beb625e5802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337997950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.1337997950 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1191280757 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 5397076405 ps |
| CPU time | 98.3 seconds |
| Started | Jul 06 08:16:14 PM PDT 24 |
| Finished | Jul 06 08:17:53 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-77891848-a6d6-4fd4-9d89-4abb3be406a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191280757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.1191280757 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.1927847199 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 39071207 ps |
| CPU time | 6.54 seconds |
| Started | Jul 06 08:16:31 PM PDT 24 |
| Finished | Jul 06 08:16:37 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-b34a62ec-54d3-45d9-ad1d-c890b5aef5e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927847199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.1927847199 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.2169750531 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 5496939027 ps |
| CPU time | 238.93 seconds |
| Started | Jul 06 08:16:19 PM PDT 24 |
| Finished | Jul 06 08:20:18 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-bf9aa32f-ccca-447d-ba60-036b733c9fe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169750531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.2169750531 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1818683036 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 3315035997 ps |
| CPU time | 116.66 seconds |
| Started | Jul 06 08:16:19 PM PDT 24 |
| Finished | Jul 06 08:18:16 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-9875db4c-df30-4ff4-ab61-e8aad79e8991 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818683036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.1818683036 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.3126341099 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 312370704 ps |
| CPU time | 120.48 seconds |
| Started | Jul 06 08:16:16 PM PDT 24 |
| Finished | Jul 06 08:18:18 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-bbaee1be-0afd-46da-ae7e-133ae18bf9e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126341099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.3126341099 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.3880218960 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 134201712 ps |
| CPU time | 60.81 seconds |
| Started | Jul 06 08:16:19 PM PDT 24 |
| Finished | Jul 06 08:17:20 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-d631bdb3-84cc-42fa-a6c1-92d3cb2208f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880218960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.3880218960 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.1598241163 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 71243374 ps |
| CPU time | 12.72 seconds |
| Started | Jul 06 08:16:17 PM PDT 24 |
| Finished | Jul 06 08:16:31 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-c2f0029c-5029-4914-b4d4-a3bc3351daea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598241163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.1598241163 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.1171032990 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 195291742 ps |
| CPU time | 20.3 seconds |
| Started | Jul 06 08:16:24 PM PDT 24 |
| Finished | Jul 06 08:16:44 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-b6856409-394e-48af-8be9-514a5ffd2860 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171032990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .1171032990 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.3412948344 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 10960443461 ps |
| CPU time | 203.63 seconds |
| Started | Jul 06 08:16:23 PM PDT 24 |
| Finished | Jul 06 08:19:47 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-5b3952e4-6137-4dec-86c3-aacbcd905470 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412948344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.3412948344 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.3194987823 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 1224719161 ps |
| CPU time | 57.62 seconds |
| Started | Jul 06 08:16:32 PM PDT 24 |
| Finished | Jul 06 08:17:30 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-f42a6ab8-ad38-484d-9500-17d1b7780163 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194987823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.3194987823 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.2172799136 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 1446867056 ps |
| CPU time | 49.2 seconds |
| Started | Jul 06 08:16:23 PM PDT 24 |
| Finished | Jul 06 08:17:13 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-74864f89-d1c4-476b-b253-9bd53ee0f979 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172799136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.2172799136 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.3997503568 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 531048100 ps |
| CPU time | 25.66 seconds |
| Started | Jul 06 08:16:23 PM PDT 24 |
| Finished | Jul 06 08:16:48 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-5670b36f-24dd-4834-a568-00e04eff724c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997503568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.3997503568 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.1208289432 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 67203406394 ps |
| CPU time | 716.67 seconds |
| Started | Jul 06 08:16:23 PM PDT 24 |
| Finished | Jul 06 08:28:20 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-e051502c-f949-4d72-b801-d8bd99ad062c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208289432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.1208289432 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.2475319639 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 52647033615 ps |
| CPU time | 970.11 seconds |
| Started | Jul 06 08:16:24 PM PDT 24 |
| Finished | Jul 06 08:32:34 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-2b7d6cb3-41e1-4f1a-8a5d-33fd014fcc67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475319639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.2475319639 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.1087706160 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 36992124 ps |
| CPU time | 6.6 seconds |
| Started | Jul 06 08:16:26 PM PDT 24 |
| Finished | Jul 06 08:16:33 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-b7e2f3e9-a68b-4a47-9aa2-8b2169560c7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087706160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.1087706160 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.296074759 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 453762323 ps |
| CPU time | 34.16 seconds |
| Started | Jul 06 08:16:21 PM PDT 24 |
| Finished | Jul 06 08:16:56 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-c3f26bad-c827-44a1-a67c-5f9ae215bc60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296074759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.296074759 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.1957823366 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 243650084 ps |
| CPU time | 10.98 seconds |
| Started | Jul 06 08:16:18 PM PDT 24 |
| Finished | Jul 06 08:16:29 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-691deed2-6787-4a42-b18c-93ef1f23f171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957823366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.1957823366 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.2881299388 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 6890063272 ps |
| CPU time | 72.1 seconds |
| Started | Jul 06 08:16:17 PM PDT 24 |
| Finished | Jul 06 08:17:30 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-91257f41-b0a7-4e9b-9c70-5a101d0590e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881299388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.2881299388 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.506066933 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 3659983955 ps |
| CPU time | 64.26 seconds |
| Started | Jul 06 08:16:24 PM PDT 24 |
| Finished | Jul 06 08:17:28 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-ee0773a7-d00f-427c-b71e-4afeb9e15f32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506066933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.506066933 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.3710830455 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 50872008 ps |
| CPU time | 7 seconds |
| Started | Jul 06 08:16:16 PM PDT 24 |
| Finished | Jul 06 08:16:24 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-685de719-2921-4dae-80c8-e7018493c113 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710830455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.3710830455 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.3983219888 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 4738274141 ps |
| CPU time | 195 seconds |
| Started | Jul 06 08:16:29 PM PDT 24 |
| Finished | Jul 06 08:19:44 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-2819b9f2-c562-4998-9b1a-71722028d226 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983219888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.3983219888 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.1576586666 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 1924635723 ps |
| CPU time | 186.35 seconds |
| Started | Jul 06 08:16:30 PM PDT 24 |
| Finished | Jul 06 08:19:36 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-c098c1ea-14cc-4977-8727-60afec7a0eb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576586666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.1576586666 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.1134386199 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 4480516642 ps |
| CPU time | 379.67 seconds |
| Started | Jul 06 08:16:30 PM PDT 24 |
| Finished | Jul 06 08:22:50 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-8a413e6a-23b1-4e78-bf54-a4d8b6ea7653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134386199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.1134386199 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.2727115298 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 935218845 ps |
| CPU time | 239.58 seconds |
| Started | Jul 06 08:16:28 PM PDT 24 |
| Finished | Jul 06 08:20:28 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-cffde03e-344a-4461-adf5-2fc18cdb8e39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727115298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.2727115298 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.56209090 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 795479951 ps |
| CPU time | 36.68 seconds |
| Started | Jul 06 08:16:23 PM PDT 24 |
| Finished | Jul 06 08:17:00 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-fe05ae62-bae6-46d6-a65b-1ae20a9b4ea2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56209090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.56209090 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.3664733274 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 283983312 ps |
| CPU time | 24 seconds |
| Started | Jul 06 08:16:36 PM PDT 24 |
| Finished | Jul 06 08:17:00 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-616a2049-6339-424a-86c9-7e5456b1d69c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664733274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .3664733274 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3516044646 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 2794524061 ps |
| CPU time | 52.22 seconds |
| Started | Jul 06 08:16:37 PM PDT 24 |
| Finished | Jul 06 08:17:29 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-43f2a97c-54b5-4316-92ff-477661d9825d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516044646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.3516044646 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.3268699358 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 288683511 ps |
| CPU time | 33.29 seconds |
| Started | Jul 06 08:16:38 PM PDT 24 |
| Finished | Jul 06 08:17:12 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-c359ac1e-25b9-4b4a-849f-43b3df8bcb4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268699358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add r.3268699358 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.2342971563 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 2213011697 ps |
| CPU time | 89.24 seconds |
| Started | Jul 06 08:16:34 PM PDT 24 |
| Finished | Jul 06 08:18:04 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-b81cf89a-3e2a-4696-a5d9-408e26245d17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342971563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.2342971563 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.3374041118 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 1125441659 ps |
| CPU time | 46.53 seconds |
| Started | Jul 06 08:16:32 PM PDT 24 |
| Finished | Jul 06 08:17:19 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-bc047849-36f3-4f35-96a4-f5b4cbc4e91b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374041118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.3374041118 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.4255798107 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 101459854345 ps |
| CPU time | 1134.45 seconds |
| Started | Jul 06 08:16:27 PM PDT 24 |
| Finished | Jul 06 08:35:22 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-8bf833c0-d468-4ada-9edf-9ba78f1abc40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255798107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.4255798107 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.2422222076 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 20423541680 ps |
| CPU time | 380.19 seconds |
| Started | Jul 06 08:16:38 PM PDT 24 |
| Finished | Jul 06 08:22:58 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-ad386ae7-3597-4bfd-82dd-99d90327bd73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422222076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.2422222076 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.1724925488 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 231331442 ps |
| CPU time | 22.49 seconds |
| Started | Jul 06 08:16:30 PM PDT 24 |
| Finished | Jul 06 08:16:52 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-4a185e6d-7fa2-4d49-8cb7-9fddf49bb03b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724925488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.1724925488 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.304270619 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 205183477 ps |
| CPU time | 20.87 seconds |
| Started | Jul 06 08:16:34 PM PDT 24 |
| Finished | Jul 06 08:16:55 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-895cdf8b-3ca6-4c6d-8448-14e3f6f02f76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304270619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.304270619 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.769390889 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 196869791 ps |
| CPU time | 9.12 seconds |
| Started | Jul 06 08:16:29 PM PDT 24 |
| Finished | Jul 06 08:16:38 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-84216ff5-ef19-4287-b4b2-c6588a98ab3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769390889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.769390889 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.575436858 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 8791547350 ps |
| CPU time | 101.71 seconds |
| Started | Jul 06 08:16:28 PM PDT 24 |
| Finished | Jul 06 08:18:10 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-03ddda3c-812c-425e-be0a-0cc554b70be5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575436858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.575436858 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.2755278702 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 6164298554 ps |
| CPU time | 110.15 seconds |
| Started | Jul 06 08:16:29 PM PDT 24 |
| Finished | Jul 06 08:18:20 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-b43e5286-3b4d-46f6-a5a5-f733c8d9fc3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755278702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.2755278702 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.160526702 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 47823222 ps |
| CPU time | 6.12 seconds |
| Started | Jul 06 08:16:30 PM PDT 24 |
| Finished | Jul 06 08:16:36 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-2e5eb8e7-7a8b-4a2b-804b-a7da63234ba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160526702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delays .160526702 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.1592026295 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 2600714429 ps |
| CPU time | 280.2 seconds |
| Started | Jul 06 08:16:35 PM PDT 24 |
| Finished | Jul 06 08:21:15 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-da242e0a-760a-437b-ac96-f29e802ecbc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592026295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.1592026295 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.717286560 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 11715934641 ps |
| CPU time | 421.44 seconds |
| Started | Jul 06 08:16:38 PM PDT 24 |
| Finished | Jul 06 08:23:40 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-bd2688a1-b611-4b6e-90b6-9122e0995a1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717286560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.717286560 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.1109823145 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 3609055115 ps |
| CPU time | 473.04 seconds |
| Started | Jul 06 08:16:34 PM PDT 24 |
| Finished | Jul 06 08:24:27 PM PDT 24 |
| Peak memory | 576828 kb |
| Host | smart-4574d32d-0d04-4487-9aaf-1142c37ecb53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109823145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.1109823145 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.1378386991 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 8732656992 ps |
| CPU time | 503.37 seconds |
| Started | Jul 06 08:16:38 PM PDT 24 |
| Finished | Jul 06 08:25:02 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-1e52289a-fce2-498f-93f3-28c0f34b42c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378386991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.1378386991 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.273632071 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 935594402 ps |
| CPU time | 44.08 seconds |
| Started | Jul 06 08:16:34 PM PDT 24 |
| Finished | Jul 06 08:17:18 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-7dfeadf8-34e3-4cee-9ca1-30a70206bf83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273632071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.273632071 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.2195521623 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 2889856983 ps |
| CPU time | 127.86 seconds |
| Started | Jul 06 08:16:44 PM PDT 24 |
| Finished | Jul 06 08:18:52 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-24184145-0220-4347-beee-e186f5481c6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195521623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .2195521623 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2852720357 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 86384360794 ps |
| CPU time | 1465.08 seconds |
| Started | Jul 06 08:16:43 PM PDT 24 |
| Finished | Jul 06 08:41:09 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-623ded79-a8ae-415c-9e47-7f50efa2723e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852720357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.2852720357 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.1287078565 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 617661965 ps |
| CPU time | 28.8 seconds |
| Started | Jul 06 08:16:58 PM PDT 24 |
| Finished | Jul 06 08:17:27 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-5567979c-2581-45e1-b9cb-e7fe98839343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287078565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.1287078565 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.3381324071 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 949117108 ps |
| CPU time | 31.85 seconds |
| Started | Jul 06 08:16:45 PM PDT 24 |
| Finished | Jul 06 08:17:17 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-e07ed160-d09c-4c19-aa20-440060f55393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381324071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.3381324071 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.1110005919 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 98471254 ps |
| CPU time | 12.06 seconds |
| Started | Jul 06 08:16:38 PM PDT 24 |
| Finished | Jul 06 08:16:51 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-1ffdcf92-c04e-432c-95e2-b087cc41d766 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110005919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.1110005919 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.2835121522 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 91473441537 ps |
| CPU time | 983.77 seconds |
| Started | Jul 06 08:16:40 PM PDT 24 |
| Finished | Jul 06 08:33:04 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-d7c9b345-36e5-4fb4-a798-263560058a5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835121522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.2835121522 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.4014761902 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 46028377718 ps |
| CPU time | 768.87 seconds |
| Started | Jul 06 08:16:39 PM PDT 24 |
| Finished | Jul 06 08:29:29 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-0619af37-b33d-4b10-99da-cc6283d390c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014761902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.4014761902 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.1405375874 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 637261478 ps |
| CPU time | 59.82 seconds |
| Started | Jul 06 08:16:39 PM PDT 24 |
| Finished | Jul 06 08:17:39 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-ee28e192-aeb5-4948-9af6-f99c05ba068c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405375874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.1405375874 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.3225187355 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 206205297 ps |
| CPU time | 18.32 seconds |
| Started | Jul 06 08:16:44 PM PDT 24 |
| Finished | Jul 06 08:17:03 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-b7186033-746d-42b0-8a62-cd0e6a7cbff8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225187355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.3225187355 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.1884931004 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 151007948 ps |
| CPU time | 7.72 seconds |
| Started | Jul 06 08:16:38 PM PDT 24 |
| Finished | Jul 06 08:16:46 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-1f1677a8-176e-4055-8cd8-2d2164365ab4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884931004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.1884931004 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.3788865847 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 7859661322 ps |
| CPU time | 89.2 seconds |
| Started | Jul 06 08:16:38 PM PDT 24 |
| Finished | Jul 06 08:18:08 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-d3311e25-0ac5-438d-85ce-cedcd1e66db8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788865847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.3788865847 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.503825972 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 6270877776 ps |
| CPU time | 105.11 seconds |
| Started | Jul 06 08:16:40 PM PDT 24 |
| Finished | Jul 06 08:18:25 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-ee1200ea-c6e7-4811-af94-603b4c25e0e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503825972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.503825972 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.806961020 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 56346153 ps |
| CPU time | 7.71 seconds |
| Started | Jul 06 08:16:36 PM PDT 24 |
| Finished | Jul 06 08:16:44 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-2d22d1db-13d4-48e8-bdef-a73fd7ce6a53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806961020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delays .806961020 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.3667051648 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 4916826189 ps |
| CPU time | 186.79 seconds |
| Started | Jul 06 08:16:50 PM PDT 24 |
| Finished | Jul 06 08:19:58 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-fe8d96b4-d5fd-4663-a4fc-36c70d87fbeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667051648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.3667051648 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.2222829699 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 16958846742 ps |
| CPU time | 655.1 seconds |
| Started | Jul 06 08:16:49 PM PDT 24 |
| Finished | Jul 06 08:27:44 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-469db988-e74f-48cc-bca7-c7bf48eb75e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222829699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.2222829699 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.1132505834 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 1642086054 ps |
| CPU time | 244.73 seconds |
| Started | Jul 06 08:16:52 PM PDT 24 |
| Finished | Jul 06 08:20:57 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-b9b79204-9401-4ef0-b7c8-9956a4671439 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132505834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.1132505834 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.3747961605 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 1324173215 ps |
| CPU time | 170.35 seconds |
| Started | Jul 06 08:16:50 PM PDT 24 |
| Finished | Jul 06 08:19:41 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-c694878e-bb38-40aa-8a68-9c40c62f1cb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747961605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.3747961605 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.3282942099 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 1255101553 ps |
| CPU time | 57.87 seconds |
| Started | Jul 06 08:16:45 PM PDT 24 |
| Finished | Jul 06 08:17:43 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-419a3527-787c-437e-a042-673bc8dcb646 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282942099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.3282942099 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.181526386 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 400052183 ps |
| CPU time | 21.71 seconds |
| Started | Jul 06 08:16:56 PM PDT 24 |
| Finished | Jul 06 08:17:18 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-df1cf025-d399-4bd2-b2d5-878b07d1a20c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181526386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device. 181526386 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.1563799782 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 9641751919 ps |
| CPU time | 168.25 seconds |
| Started | Jul 06 08:16:55 PM PDT 24 |
| Finished | Jul 06 08:19:44 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-680063d6-9d10-471f-a887-1657744b7852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563799782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.1563799782 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.4250459858 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 1087396525 ps |
| CPU time | 45.06 seconds |
| Started | Jul 06 08:17:02 PM PDT 24 |
| Finished | Jul 06 08:17:48 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-1a676dc3-8830-4fd6-8d61-3e5fee6dec54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250459858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.4250459858 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.781082597 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 1802241617 ps |
| CPU time | 68.84 seconds |
| Started | Jul 06 08:17:02 PM PDT 24 |
| Finished | Jul 06 08:18:11 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-603c751e-e0e1-4f52-bd33-ac4f6c448aef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781082597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.781082597 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.1513701435 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 583928813 ps |
| CPU time | 54.91 seconds |
| Started | Jul 06 08:17:45 PM PDT 24 |
| Finished | Jul 06 08:18:40 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-2357f687-d4c3-4ec3-93cf-85ea5e95950e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513701435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.1513701435 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.618451541 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 26842629570 ps |
| CPU time | 282.88 seconds |
| Started | Jul 06 08:17:03 PM PDT 24 |
| Finished | Jul 06 08:21:46 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-5f6c885c-4baa-4892-9eaa-18bfb9f5bead |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618451541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.618451541 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.1746465782 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 5656001786 ps |
| CPU time | 95.96 seconds |
| Started | Jul 06 08:17:39 PM PDT 24 |
| Finished | Jul 06 08:19:15 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-cdd0dbf5-6f8b-4bb5-a8bd-4e7f523bca97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746465782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.1746465782 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.3369671170 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 296862059 ps |
| CPU time | 29.28 seconds |
| Started | Jul 06 08:16:56 PM PDT 24 |
| Finished | Jul 06 08:17:25 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-01007a9b-a24d-4a50-8ded-03062b4aa1d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369671170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.3369671170 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.2914484977 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 160835097 ps |
| CPU time | 13.3 seconds |
| Started | Jul 06 08:17:00 PM PDT 24 |
| Finished | Jul 06 08:17:14 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-2e149697-1935-4d18-928c-d5ef80737e11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914484977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.2914484977 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.2250194742 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 49561910 ps |
| CPU time | 6.86 seconds |
| Started | Jul 06 08:16:49 PM PDT 24 |
| Finished | Jul 06 08:16:56 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-b07909f4-196e-4af2-a65c-297180c70e3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250194742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.2250194742 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.1325979129 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 11139313098 ps |
| CPU time | 123.25 seconds |
| Started | Jul 06 08:16:48 PM PDT 24 |
| Finished | Jul 06 08:18:52 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-55ec84de-66fc-4d79-8a3c-b39abeca7047 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325979129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.1325979129 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.3619731697 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 5104522080 ps |
| CPU time | 88.71 seconds |
| Started | Jul 06 08:16:50 PM PDT 24 |
| Finished | Jul 06 08:18:20 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-cd19a3a3-dabb-48c1-8294-1de5a7e93f32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619731697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.3619731697 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.210883519 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 40883763 ps |
| CPU time | 6.52 seconds |
| Started | Jul 06 08:16:50 PM PDT 24 |
| Finished | Jul 06 08:16:57 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-febde1e8-4027-49e8-859e-2e49dc856384 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210883519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delays .210883519 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.3534315742 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 448607042 ps |
| CPU time | 50.47 seconds |
| Started | Jul 06 08:17:09 PM PDT 24 |
| Finished | Jul 06 08:17:59 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-f1e3900e-7d0b-47fe-93b1-8b50dfb7bd19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534315742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.3534315742 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.3675456750 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 2545371791 ps |
| CPU time | 191.47 seconds |
| Started | Jul 06 08:17:08 PM PDT 24 |
| Finished | Jul 06 08:20:20 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-6bb5f9e4-ba54-4af5-af13-ec93841d616c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675456750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.3675456750 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2899116343 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 4688944536 ps |
| CPU time | 686.22 seconds |
| Started | Jul 06 08:17:04 PM PDT 24 |
| Finished | Jul 06 08:28:30 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-1ffe2ef7-7ff8-4a1e-a6a6-dc120337a40b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899116343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.2899116343 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1876714517 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 5265907777 ps |
| CPU time | 388.75 seconds |
| Started | Jul 06 08:17:02 PM PDT 24 |
| Finished | Jul 06 08:23:31 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-89562731-2598-4d00-885c-f79f9979003d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876714517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.1876714517 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.1776121962 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 59567311 ps |
| CPU time | 10.35 seconds |
| Started | Jul 06 08:17:00 PM PDT 24 |
| Finished | Jul 06 08:17:11 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-947aa245-3528-4e2e-924a-efb99811bf7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776121962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.1776121962 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.1769997730 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 966346477 ps |
| CPU time | 73.67 seconds |
| Started | Jul 06 08:17:11 PM PDT 24 |
| Finished | Jul 06 08:18:25 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-263074e1-f4f5-48fa-81b1-89e42f0fb83a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769997730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .1769997730 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.982029432 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 104797618658 ps |
| CPU time | 2035.38 seconds |
| Started | Jul 06 08:17:10 PM PDT 24 |
| Finished | Jul 06 08:51:06 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-742db57b-4791-4278-bf75-afaa2dbc9e69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982029432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_d evice_slow_rsp.982029432 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.2418349521 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 175259263 ps |
| CPU time | 18.47 seconds |
| Started | Jul 06 08:17:24 PM PDT 24 |
| Finished | Jul 06 08:17:43 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-d87ef775-ab61-47b1-a459-2b3f1b9c3942 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418349521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.2418349521 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.551198435 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 354437337 ps |
| CPU time | 32.6 seconds |
| Started | Jul 06 08:17:11 PM PDT 24 |
| Finished | Jul 06 08:17:43 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-1bceb374-55e6-46cc-a5cc-124917853344 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551198435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.551198435 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.625121401 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 1714116385 ps |
| CPU time | 63.3 seconds |
| Started | Jul 06 08:17:06 PM PDT 24 |
| Finished | Jul 06 08:18:09 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-e6644a6d-2450-4722-8bab-3455c01949b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625121401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.625121401 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.347773926 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 91524513372 ps |
| CPU time | 904.72 seconds |
| Started | Jul 06 08:17:05 PM PDT 24 |
| Finished | Jul 06 08:32:10 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-f8115ab6-0355-44e1-b0b3-1bff7c5d83cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347773926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.347773926 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.2655018059 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 30353647320 ps |
| CPU time | 550.58 seconds |
| Started | Jul 06 08:17:05 PM PDT 24 |
| Finished | Jul 06 08:26:16 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-b8fd9872-14bb-48c7-b55e-40a3c5b5dc3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655018059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.2655018059 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.357187856 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 548512561 ps |
| CPU time | 50.69 seconds |
| Started | Jul 06 08:17:05 PM PDT 24 |
| Finished | Jul 06 08:17:56 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-1fb18776-42c2-46e3-8f6d-b5ddf03d54ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357187856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_dela ys.357187856 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.2253035251 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 1121887198 ps |
| CPU time | 34.57 seconds |
| Started | Jul 06 08:17:23 PM PDT 24 |
| Finished | Jul 06 08:17:58 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-63dcbabc-dc2d-4a8d-b469-4063f8f78a26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253035251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.2253035251 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.2777041765 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 155754436 ps |
| CPU time | 8.6 seconds |
| Started | Jul 06 08:17:04 PM PDT 24 |
| Finished | Jul 06 08:17:13 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-9741cde3-2de4-4fc0-9725-7c2748dd9b4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777041765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.2777041765 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.1285947584 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 8814062660 ps |
| CPU time | 92.74 seconds |
| Started | Jul 06 08:17:02 PM PDT 24 |
| Finished | Jul 06 08:18:35 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-22624452-c007-4291-b740-b658836ca261 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285947584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.1285947584 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.3190482966 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 4440311825 ps |
| CPU time | 76.55 seconds |
| Started | Jul 06 08:17:08 PM PDT 24 |
| Finished | Jul 06 08:18:25 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-cfb5c9c0-0da1-4e6d-b11c-273eead20a9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190482966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.3190482966 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2482054513 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 46087199 ps |
| CPU time | 6.64 seconds |
| Started | Jul 06 08:17:04 PM PDT 24 |
| Finished | Jul 06 08:17:11 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-0dd69fb4-27d9-4488-9a88-309e8e29977a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482054513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.2482054513 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.3883284680 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 10374242767 ps |
| CPU time | 398.36 seconds |
| Started | Jul 06 08:17:12 PM PDT 24 |
| Finished | Jul 06 08:23:50 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-ded35837-46f6-43e1-8b76-e571178224d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883284680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.3883284680 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.1726173173 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 3807569586 ps |
| CPU time | 302.26 seconds |
| Started | Jul 06 08:17:09 PM PDT 24 |
| Finished | Jul 06 08:22:12 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-e53b04f8-19d4-4cf8-8c0a-ea733767d3d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726173173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.1726173173 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.213133536 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 35830951 ps |
| CPU time | 12.06 seconds |
| Started | Jul 06 08:17:12 PM PDT 24 |
| Finished | Jul 06 08:17:24 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-a2b74864-68e7-44c9-a6d6-79e2a9de9614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213133536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_ with_rand_reset.213133536 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.540011628 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 1365217780 ps |
| CPU time | 118.36 seconds |
| Started | Jul 06 08:17:23 PM PDT 24 |
| Finished | Jul 06 08:19:22 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-2174d752-3926-41a2-bd76-4185eb665588 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540011628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_reset_error.540011628 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.2678088096 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 621349976 ps |
| CPU time | 26.96 seconds |
| Started | Jul 06 08:17:23 PM PDT 24 |
| Finished | Jul 06 08:17:51 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-bc0233de-7ce1-465c-b22a-e75df7d98aed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678088096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.2678088096 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.4263279413 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 942582257 ps |
| CPU time | 75.86 seconds |
| Started | Jul 06 08:17:15 PM PDT 24 |
| Finished | Jul 06 08:18:31 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-fb38fa20-97d8-4a9a-8b42-4e91579dd017 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263279413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .4263279413 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.4186706439 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 151360769798 ps |
| CPU time | 2595.59 seconds |
| Started | Jul 06 08:17:16 PM PDT 24 |
| Finished | Jul 06 09:00:33 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-c16e6e9c-9539-4697-8443-b07c49540168 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186706439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.4186706439 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.239837650 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 553414959 ps |
| CPU time | 26.63 seconds |
| Started | Jul 06 08:17:20 PM PDT 24 |
| Finished | Jul 06 08:17:47 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-d25681d6-99f7-43f1-996d-1ef4f744429d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239837650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_addr .239837650 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.2669658279 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 1348057310 ps |
| CPU time | 48.47 seconds |
| Started | Jul 06 08:17:15 PM PDT 24 |
| Finished | Jul 06 08:18:04 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-085b1435-eb44-41e8-9a73-c62e33d01105 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669658279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.2669658279 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.2904143366 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 40389438 ps |
| CPU time | 5.99 seconds |
| Started | Jul 06 08:17:15 PM PDT 24 |
| Finished | Jul 06 08:17:21 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-a31b0d1a-44fc-483f-b0d2-60993c48944c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904143366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.2904143366 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.1668370910 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 33178937141 ps |
| CPU time | 390.45 seconds |
| Started | Jul 06 08:17:15 PM PDT 24 |
| Finished | Jul 06 08:23:46 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-8fe03a2d-fa8d-4df8-a776-2789933db7f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668370910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.1668370910 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.671321843 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 37367987011 ps |
| CPU time | 632.28 seconds |
| Started | Jul 06 08:17:17 PM PDT 24 |
| Finished | Jul 06 08:27:50 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-06b23a09-e81a-43b4-ac0a-57d4213fcb60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671321843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.671321843 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.1075135281 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 139768197 ps |
| CPU time | 16.34 seconds |
| Started | Jul 06 08:17:20 PM PDT 24 |
| Finished | Jul 06 08:17:37 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-febe79a6-d492-465b-87f9-8e5fa64fa761 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075135281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.1075135281 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.2050159429 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 417542015 ps |
| CPU time | 15.81 seconds |
| Started | Jul 06 08:17:15 PM PDT 24 |
| Finished | Jul 06 08:17:31 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-08edf563-1e89-43a5-99e3-72b10c34fd53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050159429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.2050159429 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.2792522222 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 154672953 ps |
| CPU time | 8.43 seconds |
| Started | Jul 06 08:17:12 PM PDT 24 |
| Finished | Jul 06 08:17:21 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-8a50d011-70d6-4cba-8b03-44b451eb1600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792522222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.2792522222 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.1992482779 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 7977518686 ps |
| CPU time | 80.86 seconds |
| Started | Jul 06 08:17:17 PM PDT 24 |
| Finished | Jul 06 08:18:38 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-ed65bef7-8500-49c2-a4bf-807c2c814e5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992482779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.1992482779 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.1474799391 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 4696349830 ps |
| CPU time | 83.42 seconds |
| Started | Jul 06 08:17:15 PM PDT 24 |
| Finished | Jul 06 08:18:39 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-d5858ee0-69d0-4fbf-b2d1-e05672a0868c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474799391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.1474799391 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.3691465280 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 45201051 ps |
| CPU time | 7.09 seconds |
| Started | Jul 06 08:17:14 PM PDT 24 |
| Finished | Jul 06 08:17:22 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-74fd4f84-4e23-442d-8dc6-d69e088d1637 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691465280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.3691465280 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.375301981 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 1467011594 ps |
| CPU time | 120.27 seconds |
| Started | Jul 06 08:17:21 PM PDT 24 |
| Finished | Jul 06 08:19:22 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-57ca70f1-8015-47e9-baf5-fc7b685c8075 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375301981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.375301981 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.4089307393 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 4418737269 ps |
| CPU time | 184.29 seconds |
| Started | Jul 06 08:17:22 PM PDT 24 |
| Finished | Jul 06 08:20:27 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-e4c1719f-70ff-43fb-9f21-ba18aa13e2d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089307393 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.4089307393 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.2435422910 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 3289522244 ps |
| CPU time | 169.4 seconds |
| Started | Jul 06 08:17:21 PM PDT 24 |
| Finished | Jul 06 08:20:10 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-466e7d2e-b9aa-4c8c-8458-2bb7cef04f32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435422910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.2435422910 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2108742091 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 889344964 ps |
| CPU time | 159.74 seconds |
| Started | Jul 06 08:17:22 PM PDT 24 |
| Finished | Jul 06 08:20:02 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-d9b1c399-d735-48a9-9e68-7665a416a70d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108742091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.2108742091 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.396229775 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 1339955669 ps |
| CPU time | 65.33 seconds |
| Started | Jul 06 08:17:24 PM PDT 24 |
| Finished | Jul 06 08:18:29 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-46952252-7dea-4fab-bbc3-d6895342be6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396229775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.396229775 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3575230512 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 16369433041 ps |
| CPU time | 2007.36 seconds |
| Started | Jul 06 08:03:53 PM PDT 24 |
| Finished | Jul 06 08:37:22 PM PDT 24 |
| Peak memory | 592760 kb |
| Host | smart-85d04c9e-87d0-48e5-b4e1-83a84377dccd |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575230512 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.3575230512 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.2896950644 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 2925681867 ps |
| CPU time | 204.82 seconds |
| Started | Jul 06 08:03:51 PM PDT 24 |
| Finished | Jul 06 08:07:17 PM PDT 24 |
| Peak memory | 603644 kb |
| Host | smart-f434cda6-c394-45c3-b258-a842d7d7e49d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896950644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.2896950644 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.3213163271 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 2748400628 ps |
| CPU time | 157.07 seconds |
| Started | Jul 06 08:04:12 PM PDT 24 |
| Finished | Jul 06 08:06:49 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-d3163b93-b896-45aa-9393-463ebce6473d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213163271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 3213163271 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.194684446 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 116689980781 ps |
| CPU time | 2142.61 seconds |
| Started | Jul 06 08:04:12 PM PDT 24 |
| Finished | Jul 06 08:39:55 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-adb50645-6413-468d-ad54-53b57efc26c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194684446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_de vice_slow_rsp.194684446 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3988455695 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 717158301 ps |
| CPU time | 36.5 seconds |
| Started | Jul 06 08:04:20 PM PDT 24 |
| Finished | Jul 06 08:04:56 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-74b57a56-d3dd-48ba-90a7-b40ec64c2fe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988455695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .3988455695 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.1129413995 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 1151566725 ps |
| CPU time | 41.73 seconds |
| Started | Jul 06 08:04:15 PM PDT 24 |
| Finished | Jul 06 08:04:57 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-22b7a19f-4aff-475b-a737-da0fdc73cf2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129413995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1129413995 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.4057455975 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 624898657 ps |
| CPU time | 23.32 seconds |
| Started | Jul 06 08:04:00 PM PDT 24 |
| Finished | Jul 06 08:04:23 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-c25fdf4f-5ce9-4a41-9b96-df0ff89db4f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057455975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.4057455975 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.596070666 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 80797660894 ps |
| CPU time | 859.63 seconds |
| Started | Jul 06 08:04:11 PM PDT 24 |
| Finished | Jul 06 08:18:31 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-1ec75b99-7372-4ab3-a17d-b7328be2e8e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596070666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.596070666 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.1100144343 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 12784215207 ps |
| CPU time | 241.38 seconds |
| Started | Jul 06 08:04:06 PM PDT 24 |
| Finished | Jul 06 08:08:07 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-dedf5f0b-b83a-4c56-b463-6081c450ab06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100144343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1100144343 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.4059629011 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 461110213 ps |
| CPU time | 42.59 seconds |
| Started | Jul 06 08:04:05 PM PDT 24 |
| Finished | Jul 06 08:04:48 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-f3cdca15-b043-467f-ad4d-4fe88d31f1f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059629011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.4059629011 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.363944485 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 404930573 ps |
| CPU time | 36.8 seconds |
| Started | Jul 06 08:04:13 PM PDT 24 |
| Finished | Jul 06 08:04:50 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-1a1579ac-ff24-4944-bcd6-ba399438b4e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363944485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.363944485 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.3201680148 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 186585944 ps |
| CPU time | 8.66 seconds |
| Started | Jul 06 08:03:54 PM PDT 24 |
| Finished | Jul 06 08:04:03 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-efd72e8c-bf86-41a8-95b7-29a73e28f146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201680148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3201680148 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.3130715320 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 7342308573 ps |
| CPU time | 79.83 seconds |
| Started | Jul 06 08:03:54 PM PDT 24 |
| Finished | Jul 06 08:05:14 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-9a66c756-cc0e-462e-b59d-7e308938595d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130715320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3130715320 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.3225740566 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 5398476363 ps |
| CPU time | 94.49 seconds |
| Started | Jul 06 08:04:02 PM PDT 24 |
| Finished | Jul 06 08:05:37 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-09cf6f85-a289-4892-9911-96b98e590ab6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225740566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3225740566 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.1801105617 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 43400142 ps |
| CPU time | 6.44 seconds |
| Started | Jul 06 08:03:52 PM PDT 24 |
| Finished | Jul 06 08:03:59 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-47b5e230-800c-48e4-b358-ac8b5ce81233 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801105617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .1801105617 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.910764804 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 724457014 ps |
| CPU time | 65.8 seconds |
| Started | Jul 06 08:04:18 PM PDT 24 |
| Finished | Jul 06 08:05:24 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-82ff9062-a0eb-4999-bb71-3edfd55c2b1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910764804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.910764804 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.109609138 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 1906763393 ps |
| CPU time | 170.21 seconds |
| Started | Jul 06 08:04:18 PM PDT 24 |
| Finished | Jul 06 08:07:09 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-f12e543d-96a6-4e02-b34d-5858b5a492e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109609138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.109609138 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.3543643932 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 28716840 ps |
| CPU time | 40.84 seconds |
| Started | Jul 06 08:04:28 PM PDT 24 |
| Finished | Jul 06 08:05:09 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-3fa47f38-1728-4ece-91ac-e847d648bdd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543643932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.3543643932 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.483502014 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 25696969 ps |
| CPU time | 16.84 seconds |
| Started | Jul 06 08:04:18 PM PDT 24 |
| Finished | Jul 06 08:04:35 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-8c7a28bb-db4c-4aa5-ac77-b8cf0d5fe6e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483502014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_reset_error.483502014 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.2773679043 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 779314037 ps |
| CPU time | 31.27 seconds |
| Started | Jul 06 08:04:19 PM PDT 24 |
| Finished | Jul 06 08:04:50 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-d036e0eb-c413-4d99-9bb3-602ac64f25c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773679043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2773679043 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.3511192504 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 484684364 ps |
| CPU time | 26.04 seconds |
| Started | Jul 06 08:17:26 PM PDT 24 |
| Finished | Jul 06 08:17:52 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-76ac0903-e967-4ce5-8a6d-72e1815cc98e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511192504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .3511192504 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.733763687 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 14202450831 ps |
| CPU time | 258.84 seconds |
| Started | Jul 06 08:17:27 PM PDT 24 |
| Finished | Jul 06 08:21:46 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-043a4693-a75d-4906-9489-c388a769cdb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733763687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_d evice_slow_rsp.733763687 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1266546708 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 142047133 ps |
| CPU time | 20.56 seconds |
| Started | Jul 06 08:17:28 PM PDT 24 |
| Finished | Jul 06 08:17:49 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-d59a1d57-f736-4c87-8fb2-60ebfa3d4b4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266546708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.1266546708 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.598518669 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 1071989685 ps |
| CPU time | 39.65 seconds |
| Started | Jul 06 08:17:26 PM PDT 24 |
| Finished | Jul 06 08:18:06 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-f4482638-be63-4c42-9f69-cf69cdcca370 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598518669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.598518669 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.2624107602 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 1621575615 ps |
| CPU time | 59.46 seconds |
| Started | Jul 06 08:17:25 PM PDT 24 |
| Finished | Jul 06 08:18:25 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-b4ef4910-6b62-43d0-b234-aed91b7f4d19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624107602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.2624107602 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.2013002297 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 107050697679 ps |
| CPU time | 1105.75 seconds |
| Started | Jul 06 08:17:25 PM PDT 24 |
| Finished | Jul 06 08:35:52 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-ba681caf-7bf0-4f0e-a94a-8fb6e9dabe0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013002297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.2013002297 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1507322594 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 34028431695 ps |
| CPU time | 571.27 seconds |
| Started | Jul 06 08:17:20 PM PDT 24 |
| Finished | Jul 06 08:26:52 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-9333a232-6d7d-41c8-b21f-2d3c22919e52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507322594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.1507322594 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.584458914 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 308310062 ps |
| CPU time | 27.29 seconds |
| Started | Jul 06 08:17:22 PM PDT 24 |
| Finished | Jul 06 08:17:50 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-36498e78-8843-4fa1-9b23-359c58e8c74b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584458914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_dela ys.584458914 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.4011910654 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 1089593649 ps |
| CPU time | 33.9 seconds |
| Started | Jul 06 08:17:27 PM PDT 24 |
| Finished | Jul 06 08:18:01 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-959d735c-a4f5-4c32-bc3d-5bff059871af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011910654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.4011910654 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.4160023015 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 56006355 ps |
| CPU time | 7.51 seconds |
| Started | Jul 06 08:17:22 PM PDT 24 |
| Finished | Jul 06 08:17:30 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-a968ba8d-f1b8-468d-baac-a1665d9ca05a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160023015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.4160023015 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.1852195996 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 8165600886 ps |
| CPU time | 94.83 seconds |
| Started | Jul 06 08:17:20 PM PDT 24 |
| Finished | Jul 06 08:18:55 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-e48fcfa4-276e-443c-8d0b-e0dfc63c0ae1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852195996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.1852195996 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1747602040 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 5316174986 ps |
| CPU time | 93.48 seconds |
| Started | Jul 06 08:17:22 PM PDT 24 |
| Finished | Jul 06 08:18:56 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-d13231c9-a92b-417e-962c-766159b5eb39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747602040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.1747602040 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2652167304 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 54903198 ps |
| CPU time | 7.7 seconds |
| Started | Jul 06 08:17:22 PM PDT 24 |
| Finished | Jul 06 08:17:30 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-048d718c-5297-4d75-8686-47bd495b53ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652167304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.2652167304 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.2083659808 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1505953498 ps |
| CPU time | 110.99 seconds |
| Started | Jul 06 08:17:25 PM PDT 24 |
| Finished | Jul 06 08:19:17 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-5dccffee-d60c-4eb9-afe8-3bfb33dcb0cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083659808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.2083659808 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.3066436448 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 9469554168 ps |
| CPU time | 337.17 seconds |
| Started | Jul 06 08:17:32 PM PDT 24 |
| Finished | Jul 06 08:23:10 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-e4006cff-e5be-46e3-bde4-5b408588bcad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066436448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.3066436448 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.2468852156 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 747168476 ps |
| CPU time | 201.38 seconds |
| Started | Jul 06 08:17:25 PM PDT 24 |
| Finished | Jul 06 08:20:47 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-8de4e98d-f75e-4a96-9acd-2ebec3d23afb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468852156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.2468852156 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.3840820046 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 293524794 ps |
| CPU time | 40.76 seconds |
| Started | Jul 06 08:17:34 PM PDT 24 |
| Finished | Jul 06 08:18:15 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-dc003a82-a588-4acb-9039-a20e0887f00b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840820046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.3840820046 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.3344453074 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 66042587 ps |
| CPU time | 7.82 seconds |
| Started | Jul 06 08:17:35 PM PDT 24 |
| Finished | Jul 06 08:17:43 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-d5883563-dc0a-432f-a658-039b22332346 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344453074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .3344453074 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.2231276194 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 140923481943 ps |
| CPU time | 2381.57 seconds |
| Started | Jul 06 08:17:39 PM PDT 24 |
| Finished | Jul 06 08:57:21 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-da0d22a0-012a-4d5e-8820-567070cd250b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231276194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.2231276194 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.131565860 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 287574025 ps |
| CPU time | 14.25 seconds |
| Started | Jul 06 08:17:35 PM PDT 24 |
| Finished | Jul 06 08:17:49 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-33347e5b-bc21-49ab-8b00-20a57792fc68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131565860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_addr .131565860 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.932277447 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 603530739 ps |
| CPU time | 51.93 seconds |
| Started | Jul 06 08:17:37 PM PDT 24 |
| Finished | Jul 06 08:18:29 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-af5f259a-d69f-4220-b38c-b86f35c1e2f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932277447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.932277447 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.1005510314 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 536318165 ps |
| CPU time | 49.58 seconds |
| Started | Jul 06 08:17:31 PM PDT 24 |
| Finished | Jul 06 08:18:21 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-0bd76f25-5fae-47e8-a1f1-4dc4536efa1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005510314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.1005510314 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.1653161900 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 80285492489 ps |
| CPU time | 868.73 seconds |
| Started | Jul 06 08:17:34 PM PDT 24 |
| Finished | Jul 06 08:32:03 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-aad20d54-f359-4447-a393-2802fa403a95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653161900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.1653161900 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.3911193322 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 21723064748 ps |
| CPU time | 388.9 seconds |
| Started | Jul 06 08:17:35 PM PDT 24 |
| Finished | Jul 06 08:24:04 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-adf876f7-318f-427d-928f-a5a2cbe1e2ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911193322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.3911193322 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.3111643028 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 378407321 ps |
| CPU time | 33.75 seconds |
| Started | Jul 06 08:17:30 PM PDT 24 |
| Finished | Jul 06 08:18:04 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-c3c67a2b-f22f-4935-9b96-de86c964bef3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111643028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.3111643028 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.4196428308 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 806699388 ps |
| CPU time | 27.25 seconds |
| Started | Jul 06 08:17:35 PM PDT 24 |
| Finished | Jul 06 08:18:02 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-0fc0d70d-7cd5-471a-9af3-e5c1b7e4e7b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196428308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.4196428308 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.3280269158 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 156864102 ps |
| CPU time | 8.62 seconds |
| Started | Jul 06 08:17:31 PM PDT 24 |
| Finished | Jul 06 08:17:40 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-725f9708-0162-4b56-9d94-88788b7795bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280269158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.3280269158 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.2508796703 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 6658842491 ps |
| CPU time | 72.39 seconds |
| Started | Jul 06 08:17:30 PM PDT 24 |
| Finished | Jul 06 08:18:43 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-adb1f49b-9302-4002-96df-4e6df3386d34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508796703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.2508796703 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.897625255 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 5453628168 ps |
| CPU time | 96.88 seconds |
| Started | Jul 06 08:17:30 PM PDT 24 |
| Finished | Jul 06 08:19:07 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-5fa5e3ad-000a-409b-94cb-41bbb0285e77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897625255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.897625255 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3132523713 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 51159985 ps |
| CPU time | 7.37 seconds |
| Started | Jul 06 08:17:32 PM PDT 24 |
| Finished | Jul 06 08:17:40 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-5561854a-8291-4337-b669-92932fac0678 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132523713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.3132523713 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.191425898 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 10278462906 ps |
| CPU time | 421.74 seconds |
| Started | Jul 06 08:17:44 PM PDT 24 |
| Finished | Jul 06 08:24:46 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-89e11d35-43a0-4899-9982-93b23d8fe39a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191425898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.191425898 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.2687036283 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 10645934782 ps |
| CPU time | 440.11 seconds |
| Started | Jul 06 08:17:44 PM PDT 24 |
| Finished | Jul 06 08:25:04 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-6f924a12-c540-4436-af4f-e3008a74a94e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687036283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.2687036283 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.1773270694 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 8932707159 ps |
| CPU time | 1007.81 seconds |
| Started | Jul 06 08:17:41 PM PDT 24 |
| Finished | Jul 06 08:34:29 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-4fbde9b6-a757-44df-a406-8eaf5e2b8412 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773270694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.1773270694 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.847468601 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 48960335 ps |
| CPU time | 25.27 seconds |
| Started | Jul 06 08:17:40 PM PDT 24 |
| Finished | Jul 06 08:18:05 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-a0d89570-8aa7-47a6-b0be-b0501107b986 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847468601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_reset_error.847468601 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.1337556308 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 632652075 ps |
| CPU time | 26.51 seconds |
| Started | Jul 06 08:17:36 PM PDT 24 |
| Finished | Jul 06 08:18:03 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-8f9313d1-1506-46d0-b23a-b4f2816d4b81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337556308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.1337556308 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.2646153931 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 76522621 ps |
| CPU time | 10.92 seconds |
| Started | Jul 06 08:17:45 PM PDT 24 |
| Finished | Jul 06 08:17:57 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-6e2d028e-8ebd-4e7e-b4e8-bb2589499b83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646153931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .2646153931 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.346846343 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 107060566720 ps |
| CPU time | 1761.91 seconds |
| Started | Jul 06 08:17:46 PM PDT 24 |
| Finished | Jul 06 08:47:09 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-26a66519-dd1a-403f-b379-1b6ba407dffb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346846343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_d evice_slow_rsp.346846343 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.2327122498 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 140350987 ps |
| CPU time | 18.01 seconds |
| Started | Jul 06 08:17:51 PM PDT 24 |
| Finished | Jul 06 08:18:10 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-48eae588-ac93-4e74-8c73-e06add72d550 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327122498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.2327122498 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.3672231100 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 208522425 ps |
| CPU time | 11.81 seconds |
| Started | Jul 06 08:17:47 PM PDT 24 |
| Finished | Jul 06 08:17:59 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-7f1b6fc7-6861-4168-b539-c32c8256a940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672231100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.3672231100 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.1713104242 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 124004452 ps |
| CPU time | 7.5 seconds |
| Started | Jul 06 08:17:46 PM PDT 24 |
| Finished | Jul 06 08:17:53 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-6ca455ef-9eb3-4887-ad1f-ac755bd4def3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713104242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.1713104242 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.3694609287 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 57503234379 ps |
| CPU time | 591.87 seconds |
| Started | Jul 06 08:17:44 PM PDT 24 |
| Finished | Jul 06 08:27:36 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-3a534b69-9f73-4a52-9040-383d69a6eb39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694609287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.3694609287 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.2516032322 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 55443984587 ps |
| CPU time | 976.38 seconds |
| Started | Jul 06 08:17:46 PM PDT 24 |
| Finished | Jul 06 08:34:03 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-d5752bd5-5aab-45b1-b405-434077f2ace0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516032322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.2516032322 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.2642607319 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 238831567 ps |
| CPU time | 27.71 seconds |
| Started | Jul 06 08:17:44 PM PDT 24 |
| Finished | Jul 06 08:18:12 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-d207216c-614e-445e-9b72-03b5c4640e2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642607319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.2642607319 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.1418414649 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 1727429949 ps |
| CPU time | 59.57 seconds |
| Started | Jul 06 08:17:47 PM PDT 24 |
| Finished | Jul 06 08:18:47 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-bbc02843-62b5-425a-a527-d1ea7eb843eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418414649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.1418414649 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.3897750948 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 186492306 ps |
| CPU time | 8.87 seconds |
| Started | Jul 06 08:17:40 PM PDT 24 |
| Finished | Jul 06 08:17:49 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-24a9ee18-1f8e-4ba9-b17a-64ff39bdcadd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897750948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.3897750948 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.3336601586 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 9384193510 ps |
| CPU time | 103.08 seconds |
| Started | Jul 06 08:17:44 PM PDT 24 |
| Finished | Jul 06 08:19:27 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-ad38f427-7981-4e1e-a62f-b07ff3bd184e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336601586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.3336601586 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.2692655374 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 4901778688 ps |
| CPU time | 86.04 seconds |
| Started | Jul 06 08:17:39 PM PDT 24 |
| Finished | Jul 06 08:19:05 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-b98788a5-9ecf-41a9-aff2-a677bdf4d4b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692655374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.2692655374 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.1151732855 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 45148686 ps |
| CPU time | 6.57 seconds |
| Started | Jul 06 08:17:41 PM PDT 24 |
| Finished | Jul 06 08:17:48 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-64c25956-8020-48e7-ba7a-ec9e96bb077c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151732855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.1151732855 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.3694949004 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 4955754321 ps |
| CPU time | 196.12 seconds |
| Started | Jul 06 08:17:51 PM PDT 24 |
| Finished | Jul 06 08:21:08 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-7758531f-5a2d-4ebc-8af8-a4233774e9e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694949004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.3694949004 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.3817571247 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 9124169607 ps |
| CPU time | 379.33 seconds |
| Started | Jul 06 08:17:50 PM PDT 24 |
| Finished | Jul 06 08:24:10 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-0cb7ee19-61e0-49fa-8eac-b44982694a24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817571247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.3817571247 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.540840212 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 225916633 ps |
| CPU time | 116.57 seconds |
| Started | Jul 06 08:17:51 PM PDT 24 |
| Finished | Jul 06 08:19:48 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-62686a68-2efa-4cc8-a5c7-17acfe7730d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540840212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_ with_rand_reset.540840212 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.3688719418 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 91192503 ps |
| CPU time | 39.59 seconds |
| Started | Jul 06 08:17:50 PM PDT 24 |
| Finished | Jul 06 08:18:30 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-abe014f1-65db-4a2e-94dc-cb82665a0b2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688719418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.3688719418 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.1457478081 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 1213642683 ps |
| CPU time | 51.11 seconds |
| Started | Jul 06 08:17:50 PM PDT 24 |
| Finished | Jul 06 08:18:41 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-067117ee-0c61-459e-b6de-1d4b74fa3305 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457478081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.1457478081 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.1210742622 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 141932290 ps |
| CPU time | 16.93 seconds |
| Started | Jul 06 08:17:57 PM PDT 24 |
| Finished | Jul 06 08:18:14 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-41477453-19bc-4e3d-8472-e47e77af6e05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210742622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .1210742622 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1406373914 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 34689159598 ps |
| CPU time | 599.95 seconds |
| Started | Jul 06 08:17:55 PM PDT 24 |
| Finished | Jul 06 08:27:55 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-bec54054-4837-4e77-9e8a-eb64c044bd17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406373914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.1406373914 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.1130705198 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 1281238295 ps |
| CPU time | 58.28 seconds |
| Started | Jul 06 08:18:00 PM PDT 24 |
| Finished | Jul 06 08:18:59 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-705ba190-aacd-4b31-86dc-eb1a58020fcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130705198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.1130705198 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.2505675103 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 289265445 ps |
| CPU time | 26.94 seconds |
| Started | Jul 06 08:17:55 PM PDT 24 |
| Finished | Jul 06 08:18:23 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-221391ce-aade-4f7e-a219-a1f27c8a6ede |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505675103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.2505675103 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.2454792909 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 253066451 ps |
| CPU time | 13.72 seconds |
| Started | Jul 06 08:17:51 PM PDT 24 |
| Finished | Jul 06 08:18:05 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-f61a5e39-8ac1-4cf2-8198-1ec08e06afe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454792909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.2454792909 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.3765828421 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 105631278570 ps |
| CPU time | 1104.73 seconds |
| Started | Jul 06 08:17:56 PM PDT 24 |
| Finished | Jul 06 08:36:21 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-c44c73bf-6116-4413-8615-d5540f7f8149 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765828421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.3765828421 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.3693020924 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 61602683982 ps |
| CPU time | 1068.15 seconds |
| Started | Jul 06 08:17:55 PM PDT 24 |
| Finished | Jul 06 08:35:43 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-b4f544c8-d93d-47b6-9c15-ace7ced9d897 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693020924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.3693020924 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.95083779 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 546898795 ps |
| CPU time | 52.95 seconds |
| Started | Jul 06 08:17:54 PM PDT 24 |
| Finished | Jul 06 08:18:48 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-9468d973-48ac-440b-aa26-da151a567cff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95083779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_delay s.95083779 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.1264985121 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 1901360044 ps |
| CPU time | 58.33 seconds |
| Started | Jul 06 08:17:55 PM PDT 24 |
| Finished | Jul 06 08:18:54 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-2e2f1174-2da9-4cff-890e-0af81baa4f06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264985121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.1264985121 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.2466485152 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 46842476 ps |
| CPU time | 7.16 seconds |
| Started | Jul 06 08:17:51 PM PDT 24 |
| Finished | Jul 06 08:17:58 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-591d9add-b8f7-41ed-8182-2b97080aac56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466485152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.2466485152 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.2013570304 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 6672503569 ps |
| CPU time | 71.24 seconds |
| Started | Jul 06 08:17:52 PM PDT 24 |
| Finished | Jul 06 08:19:04 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-185e9a2f-613e-4b2f-9226-1f375bd5beab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013570304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.2013570304 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.1916680748 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 6004870712 ps |
| CPU time | 112.58 seconds |
| Started | Jul 06 08:17:53 PM PDT 24 |
| Finished | Jul 06 08:19:46 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-20fa762c-6a72-4d37-9870-1abfa8352143 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916680748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.1916680748 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.275899085 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 44391004 ps |
| CPU time | 6.58 seconds |
| Started | Jul 06 08:17:51 PM PDT 24 |
| Finished | Jul 06 08:17:58 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-37dc0673-e9a0-40e9-a96c-cd64fdde4d56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275899085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delays .275899085 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.379646209 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 1175261148 ps |
| CPU time | 102.73 seconds |
| Started | Jul 06 08:18:01 PM PDT 24 |
| Finished | Jul 06 08:19:44 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-b733124f-989b-4cfc-99c6-ac6f8869798d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379646209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.379646209 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.2627237202 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 10221206926 ps |
| CPU time | 409.74 seconds |
| Started | Jul 06 08:18:00 PM PDT 24 |
| Finished | Jul 06 08:24:51 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-040d529e-065f-4a66-a3df-4c849224434a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627237202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.2627237202 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3210336343 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 164276652 ps |
| CPU time | 36.05 seconds |
| Started | Jul 06 08:18:01 PM PDT 24 |
| Finished | Jul 06 08:18:38 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-7bfe8dd6-4119-4f4b-948d-0deaacbb81bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210336343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.3210336343 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.2670370348 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 327632217 ps |
| CPU time | 133.82 seconds |
| Started | Jul 06 08:17:59 PM PDT 24 |
| Finished | Jul 06 08:20:13 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-a75c7650-a5cc-460b-a25e-c5b396d2d724 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670370348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.2670370348 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.3703026340 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 41438944 ps |
| CPU time | 8.76 seconds |
| Started | Jul 06 08:17:59 PM PDT 24 |
| Finished | Jul 06 08:18:08 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-1ce458d6-bb20-41c8-b158-d2a763ca9214 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703026340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.3703026340 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.942482035 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 3186625547 ps |
| CPU time | 116.12 seconds |
| Started | Jul 06 08:18:05 PM PDT 24 |
| Finished | Jul 06 08:20:01 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-19550448-8729-4e9d-a96c-4f116803998b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942482035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device. 942482035 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.1987745634 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 73467431180 ps |
| CPU time | 1273.3 seconds |
| Started | Jul 06 08:18:04 PM PDT 24 |
| Finished | Jul 06 08:39:18 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-d0c6297e-d017-467d-801f-4f5d49be1d9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987745634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.1987745634 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.3866766654 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 1307012760 ps |
| CPU time | 61.48 seconds |
| Started | Jul 06 08:18:08 PM PDT 24 |
| Finished | Jul 06 08:19:10 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-f07fa983-b3a8-45f3-9bf6-aad88046cc59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866766654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.3866766654 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.205343255 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 554006133 ps |
| CPU time | 49.47 seconds |
| Started | Jul 06 08:18:11 PM PDT 24 |
| Finished | Jul 06 08:19:01 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-850e2c41-5103-432f-b030-1d76f375bd24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205343255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.205343255 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.565852085 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 1868223732 ps |
| CPU time | 72.87 seconds |
| Started | Jul 06 08:18:04 PM PDT 24 |
| Finished | Jul 06 08:19:17 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-4b44b982-7d76-4e86-ab7f-a845d85f5579 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565852085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.565852085 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.1591667877 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 92901442831 ps |
| CPU time | 951.49 seconds |
| Started | Jul 06 08:18:00 PM PDT 24 |
| Finished | Jul 06 08:33:52 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-2af24549-9873-461b-a263-44a60e2884e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591667877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.1591667877 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.1727521005 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 35776711472 ps |
| CPU time | 641.02 seconds |
| Started | Jul 06 08:18:04 PM PDT 24 |
| Finished | Jul 06 08:28:46 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-b3252f8c-de09-4b47-951c-8c2c7e878ed5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727521005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.1727521005 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.500763235 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 77049611 ps |
| CPU time | 11.77 seconds |
| Started | Jul 06 08:18:00 PM PDT 24 |
| Finished | Jul 06 08:18:13 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-dfb137d3-18ab-4de6-bea6-36bec1de6984 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500763235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_dela ys.500763235 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.288467950 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 176194893 ps |
| CPU time | 16.1 seconds |
| Started | Jul 06 08:18:09 PM PDT 24 |
| Finished | Jul 06 08:18:25 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-8ce74c33-e94b-4c70-92e1-dfe5e1479ca3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288467950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.288467950 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.1647339767 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 262056224 ps |
| CPU time | 11.31 seconds |
| Started | Jul 06 08:17:59 PM PDT 24 |
| Finished | Jul 06 08:18:10 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-4ffd88a3-ad89-4516-98f3-fa96ec334da8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647339767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.1647339767 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.2167956297 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 6748285515 ps |
| CPU time | 70.56 seconds |
| Started | Jul 06 08:17:59 PM PDT 24 |
| Finished | Jul 06 08:19:10 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-16df8261-6d1f-4b4d-8935-8f6a28ad2256 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167956297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.2167956297 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.514611497 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 4398371997 ps |
| CPU time | 77.77 seconds |
| Started | Jul 06 08:18:04 PM PDT 24 |
| Finished | Jul 06 08:19:23 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-77e9da7d-7654-4210-acf1-4e17823a9993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514611497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.514611497 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.508244388 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 40942886 ps |
| CPU time | 5.85 seconds |
| Started | Jul 06 08:18:03 PM PDT 24 |
| Finished | Jul 06 08:18:10 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-0ab33d76-f3e7-49a5-98c0-d43bcaa3faaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508244388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delays .508244388 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.3124273997 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 4655496195 ps |
| CPU time | 407.01 seconds |
| Started | Jul 06 08:19:37 PM PDT 24 |
| Finished | Jul 06 08:26:24 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-2c458a0a-905f-4ffb-b180-81e133d526ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124273997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.3124273997 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.3064728771 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 2778927900 ps |
| CPU time | 244.18 seconds |
| Started | Jul 06 08:18:22 PM PDT 24 |
| Finished | Jul 06 08:22:27 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-20111ab2-608d-4a2f-acec-0cb1e65c9da9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064728771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.3064728771 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.728979783 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 1121018162 ps |
| CPU time | 256.08 seconds |
| Started | Jul 06 08:18:12 PM PDT 24 |
| Finished | Jul 06 08:22:28 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-f9e7a581-ad19-4b57-a5d5-cef26c0905d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728979783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_ with_rand_reset.728979783 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3672443734 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 2025715428 ps |
| CPU time | 148.62 seconds |
| Started | Jul 06 08:18:15 PM PDT 24 |
| Finished | Jul 06 08:20:44 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-8ef4a84e-3b5d-42e0-8850-71eef4fdc859 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672443734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.3672443734 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.3425335377 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 103608687 ps |
| CPU time | 14.41 seconds |
| Started | Jul 06 08:18:10 PM PDT 24 |
| Finished | Jul 06 08:18:24 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-6a1712d4-98f8-4b13-bf32-74bb800d3c29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425335377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.3425335377 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.4197671446 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 855785755 ps |
| CPU time | 78.6 seconds |
| Started | Jul 06 08:18:23 PM PDT 24 |
| Finished | Jul 06 08:19:42 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-2ea6bd16-f5ea-4fcf-972e-d902541f679b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197671446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .4197671446 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.77484425 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 9608747096 ps |
| CPU time | 171.64 seconds |
| Started | Jul 06 08:18:23 PM PDT 24 |
| Finished | Jul 06 08:21:15 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-45e87af2-8a34-4f56-8d83-bb66ebec4326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77484425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_de vice_slow_rsp.77484425 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.924219513 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 1071206681 ps |
| CPU time | 40.52 seconds |
| Started | Jul 06 08:18:20 PM PDT 24 |
| Finished | Jul 06 08:19:01 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-87669393-52e8-45cc-818c-b83067c0d98d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924219513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr .924219513 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.3029866993 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 186111754 ps |
| CPU time | 18.47 seconds |
| Started | Jul 06 08:18:23 PM PDT 24 |
| Finished | Jul 06 08:18:42 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-cfc041ba-2682-4578-a70b-310fbfb7715e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029866993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.3029866993 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.657448882 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 2486199197 ps |
| CPU time | 90.8 seconds |
| Started | Jul 06 08:18:16 PM PDT 24 |
| Finished | Jul 06 08:19:47 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-5685f5d7-22af-49de-ad85-4400a041c6e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657448882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.657448882 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.3880186969 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 19739351294 ps |
| CPU time | 219.08 seconds |
| Started | Jul 06 08:18:15 PM PDT 24 |
| Finished | Jul 06 08:21:54 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-f19fa848-2038-497e-b7c0-af4614ba65fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880186969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.3880186969 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.358836741 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 43766225618 ps |
| CPU time | 713.18 seconds |
| Started | Jul 06 08:18:22 PM PDT 24 |
| Finished | Jul 06 08:30:16 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-67ca6414-d8c4-44e9-bfb7-8410654076be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358836741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.358836741 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.3907704543 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 171442670 ps |
| CPU time | 17.83 seconds |
| Started | Jul 06 08:18:22 PM PDT 24 |
| Finished | Jul 06 08:18:40 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-0728b052-3510-4eba-ac9e-f5bf0c4d55e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907704543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.3907704543 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.1991130951 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 110006194 ps |
| CPU time | 10.24 seconds |
| Started | Jul 06 08:18:21 PM PDT 24 |
| Finished | Jul 06 08:18:32 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-9ed7e6bf-f4c4-477d-9b32-80667f7dd3d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991130951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.1991130951 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.1701738909 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 41184982 ps |
| CPU time | 5.78 seconds |
| Started | Jul 06 08:18:17 PM PDT 24 |
| Finished | Jul 06 08:18:23 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-d2ccdc28-8dad-4fe2-8d14-667c8ed11e6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701738909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.1701738909 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.1573058241 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 7843381778 ps |
| CPU time | 78.69 seconds |
| Started | Jul 06 08:18:14 PM PDT 24 |
| Finished | Jul 06 08:19:33 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-ee8b2aa4-8d5e-417d-a92a-06fecd4ab305 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573058241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.1573058241 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.3127847684 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 5341264344 ps |
| CPU time | 94.42 seconds |
| Started | Jul 06 08:18:17 PM PDT 24 |
| Finished | Jul 06 08:19:51 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-d50e9f83-8c15-4079-a24a-d4c467a361c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127847684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.3127847684 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.782065406 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 48785190 ps |
| CPU time | 7.07 seconds |
| Started | Jul 06 08:18:15 PM PDT 24 |
| Finished | Jul 06 08:18:23 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-006db25c-01f2-40f5-98a6-b3fbed277148 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782065406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delays .782065406 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.1997191228 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 9524459767 ps |
| CPU time | 365.34 seconds |
| Started | Jul 06 08:18:22 PM PDT 24 |
| Finished | Jul 06 08:24:28 PM PDT 24 |
| Peak memory | 576856 kb |
| Host | smart-5d938fd9-01c1-409f-b88e-bcdbd0c6085d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997191228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.1997191228 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.3464251184 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 11011728064 ps |
| CPU time | 473.39 seconds |
| Started | Jul 06 08:18:20 PM PDT 24 |
| Finished | Jul 06 08:26:14 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-b6f1a9c2-f1be-4685-9bb6-fa162dc58cb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464251184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.3464251184 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.741112938 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 569148432 ps |
| CPU time | 176.33 seconds |
| Started | Jul 06 08:18:26 PM PDT 24 |
| Finished | Jul 06 08:21:23 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-77669694-42b1-46cb-ac88-957cfdb82083 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741112938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_ with_rand_reset.741112938 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.2971458595 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 1464289264 ps |
| CPU time | 183.79 seconds |
| Started | Jul 06 08:18:22 PM PDT 24 |
| Finished | Jul 06 08:21:27 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-d244a22d-93cc-4221-bd57-e61e3ce1d7c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971458595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.2971458595 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1249021139 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 931281100 ps |
| CPU time | 40.15 seconds |
| Started | Jul 06 08:18:21 PM PDT 24 |
| Finished | Jul 06 08:19:02 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-87a0fc92-0db5-4ffe-b083-7ec27dde0adf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249021139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.1249021139 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.865292554 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 2239474924 ps |
| CPU time | 109.13 seconds |
| Started | Jul 06 08:18:30 PM PDT 24 |
| Finished | Jul 06 08:20:20 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-cd13b0a9-71cc-4252-baa3-19eb0adf913b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865292554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device. 865292554 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.738876239 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 110755830654 ps |
| CPU time | 2188.89 seconds |
| Started | Jul 06 08:18:29 PM PDT 24 |
| Finished | Jul 06 08:54:59 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-a43180fc-d117-4593-802d-e1f839d28602 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738876239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_d evice_slow_rsp.738876239 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.221617454 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 53960121 ps |
| CPU time | 8.89 seconds |
| Started | Jul 06 08:18:41 PM PDT 24 |
| Finished | Jul 06 08:18:51 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-2c99ad65-4779-4d39-b1f4-74a2eaa0e4bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221617454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_addr .221617454 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.1655472664 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 123952396 ps |
| CPU time | 8.02 seconds |
| Started | Jul 06 08:18:29 PM PDT 24 |
| Finished | Jul 06 08:18:38 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-d8cf1089-1aea-444e-897d-df6477b118d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655472664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.1655472664 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.2422315543 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1695144485 ps |
| CPU time | 61 seconds |
| Started | Jul 06 08:18:29 PM PDT 24 |
| Finished | Jul 06 08:19:31 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-c7f83a2d-5e7a-486c-a311-d7db95cf95cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422315543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.2422315543 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.3089324709 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 26114408828 ps |
| CPU time | 285.4 seconds |
| Started | Jul 06 08:18:29 PM PDT 24 |
| Finished | Jul 06 08:23:15 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-f38d40e3-55f4-4b1c-bb2a-42c3bc3f518f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089324709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.3089324709 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.2295529948 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 59801680343 ps |
| CPU time | 1009.48 seconds |
| Started | Jul 06 08:18:30 PM PDT 24 |
| Finished | Jul 06 08:35:20 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-17533f80-9419-42f9-a0f0-e133ec91476e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295529948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.2295529948 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.539760423 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 196429181 ps |
| CPU time | 17.84 seconds |
| Started | Jul 06 08:18:29 PM PDT 24 |
| Finished | Jul 06 08:18:48 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-b78089ff-ded0-4cb7-86fe-97db69db09b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539760423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_dela ys.539760423 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.804371395 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 485304522 ps |
| CPU time | 36.08 seconds |
| Started | Jul 06 08:18:28 PM PDT 24 |
| Finished | Jul 06 08:19:05 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-daa952f4-7a0c-4397-ad70-b83e3229d21d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804371395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.804371395 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.2346684246 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 254546148 ps |
| CPU time | 11.4 seconds |
| Started | Jul 06 08:18:23 PM PDT 24 |
| Finished | Jul 06 08:18:35 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-f2bbf596-11f8-47f6-b814-6582ba48939d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346684246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.2346684246 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.436937609 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 7389171982 ps |
| CPU time | 76.56 seconds |
| Started | Jul 06 08:18:30 PM PDT 24 |
| Finished | Jul 06 08:19:47 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-d21b1504-0055-42bf-afa9-ac26f67d9af9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436937609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.436937609 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.1211342562 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 5877006790 ps |
| CPU time | 109.22 seconds |
| Started | Jul 06 08:18:30 PM PDT 24 |
| Finished | Jul 06 08:20:20 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-ac817913-8572-426a-85c3-bf3249ab0e5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211342562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.1211342562 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.2951178906 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 43399776 ps |
| CPU time | 6.22 seconds |
| Started | Jul 06 08:18:21 PM PDT 24 |
| Finished | Jul 06 08:18:28 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-d02c2919-5ee8-4ccb-9349-c4a5516bee56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951178906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.2951178906 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.1492112853 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 10777227028 ps |
| CPU time | 391.11 seconds |
| Started | Jul 06 08:18:38 PM PDT 24 |
| Finished | Jul 06 08:25:10 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-824875d7-cbd3-4c07-aaa2-8f9c52ca269c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492112853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.1492112853 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.773792628 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 5232537309 ps |
| CPU time | 860.94 seconds |
| Started | Jul 06 08:18:37 PM PDT 24 |
| Finished | Jul 06 08:32:59 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-4935f402-2d42-45f2-82a9-70942e548b43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773792628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_ with_rand_reset.773792628 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3266118289 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 2363207666 ps |
| CPU time | 235.46 seconds |
| Started | Jul 06 08:18:35 PM PDT 24 |
| Finished | Jul 06 08:22:31 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-8290c59d-e75e-4632-9634-1ec68b1a4d1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266118289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.3266118289 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.2743601081 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 194516312 ps |
| CPU time | 25.59 seconds |
| Started | Jul 06 08:18:31 PM PDT 24 |
| Finished | Jul 06 08:18:57 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-b3540980-3cb1-4b1a-b187-b09d1a5576fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743601081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.2743601081 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.3218517148 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 2121900962 ps |
| CPU time | 93.31 seconds |
| Started | Jul 06 08:18:42 PM PDT 24 |
| Finished | Jul 06 08:20:16 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-8902c760-e5c3-4da8-bb97-e6a15c8044bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218517148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .3218517148 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.3473885138 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 62964978240 ps |
| CPU time | 1058.97 seconds |
| Started | Jul 06 08:18:42 PM PDT 24 |
| Finished | Jul 06 08:36:22 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-428a2f66-7508-4a7a-b739-60624f4ee484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473885138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.3473885138 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.469594530 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 103953754 ps |
| CPU time | 13.05 seconds |
| Started | Jul 06 08:18:49 PM PDT 24 |
| Finished | Jul 06 08:19:03 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-91dccc10-5dfc-4267-9d25-e1bae4cbe700 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469594530 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_addr .469594530 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.744768815 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 2174727190 ps |
| CPU time | 83.75 seconds |
| Started | Jul 06 08:18:42 PM PDT 24 |
| Finished | Jul 06 08:20:06 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-48264632-b7d2-4f30-931f-7873841382c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744768815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.744768815 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.1099350164 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 425251806 ps |
| CPU time | 42.53 seconds |
| Started | Jul 06 08:18:37 PM PDT 24 |
| Finished | Jul 06 08:19:20 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-966e71ec-6f74-4f2d-a8e9-3f29b8eaa33b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099350164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.1099350164 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.2789344747 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 48078128873 ps |
| CPU time | 520.86 seconds |
| Started | Jul 06 08:18:41 PM PDT 24 |
| Finished | Jul 06 08:27:23 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-a13e91f2-7dd7-4477-8503-9ad57f7dc974 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789344747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.2789344747 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.4216984896 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 16642119459 ps |
| CPU time | 282.73 seconds |
| Started | Jul 06 08:18:37 PM PDT 24 |
| Finished | Jul 06 08:23:20 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-67114c95-df0e-4508-9180-8ab27748bc55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216984896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.4216984896 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.1294546643 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 412192486 ps |
| CPU time | 40.64 seconds |
| Started | Jul 06 08:18:35 PM PDT 24 |
| Finished | Jul 06 08:19:16 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-4f6c2713-013c-41ef-99a8-957feb44dffe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294546643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.1294546643 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.825396822 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 82788465 ps |
| CPU time | 9.99 seconds |
| Started | Jul 06 08:18:41 PM PDT 24 |
| Finished | Jul 06 08:18:51 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-13bb9521-af2f-47f0-bde0-099caa35aef2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825396822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.825396822 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.29754305 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 206829620 ps |
| CPU time | 9.2 seconds |
| Started | Jul 06 08:18:40 PM PDT 24 |
| Finished | Jul 06 08:18:49 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-7d175a2b-4405-4c9c-8194-2d74cf66a4a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29754305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.29754305 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.3318453184 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 10780657931 ps |
| CPU time | 116.95 seconds |
| Started | Jul 06 08:18:38 PM PDT 24 |
| Finished | Jul 06 08:20:36 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-ce388fd7-adbe-47e7-965e-a79aa988a5e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318453184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.3318453184 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.453515708 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 5347369735 ps |
| CPU time | 91.85 seconds |
| Started | Jul 06 08:18:34 PM PDT 24 |
| Finished | Jul 06 08:20:06 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-99cba9cc-ae0b-4f1c-b2b8-ac3dd3f6b491 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453515708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.453515708 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2658279163 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 47040458 ps |
| CPU time | 7.2 seconds |
| Started | Jul 06 08:18:35 PM PDT 24 |
| Finished | Jul 06 08:18:43 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-e21bc402-871b-4088-aa6e-7e81fff276b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658279163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.2658279163 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.356298513 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 3020585215 ps |
| CPU time | 124.22 seconds |
| Started | Jul 06 08:18:48 PM PDT 24 |
| Finished | Jul 06 08:20:52 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-e74e5e12-c898-40dc-ad8b-fe0001573615 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356298513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.356298513 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.2058572100 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 3754813184 ps |
| CPU time | 140.05 seconds |
| Started | Jul 06 08:18:51 PM PDT 24 |
| Finished | Jul 06 08:21:12 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-e957db07-3a27-4228-9933-98235fd83489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058572100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.2058572100 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3810576729 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 9866862913 ps |
| CPU time | 622.79 seconds |
| Started | Jul 06 08:19:02 PM PDT 24 |
| Finished | Jul 06 08:29:26 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-548b75b8-2e1d-4741-b10c-945df02ead33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810576729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.3810576729 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3237564385 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 395550139 ps |
| CPU time | 164.03 seconds |
| Started | Jul 06 08:18:46 PM PDT 24 |
| Finished | Jul 06 08:21:30 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-cb1fa2ce-e791-4b18-b05a-5830a1cea8ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237564385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.3237564385 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.2022382369 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 780833356 ps |
| CPU time | 32.75 seconds |
| Started | Jul 06 08:18:42 PM PDT 24 |
| Finished | Jul 06 08:19:16 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-6f8628fe-41f3-45c6-a424-298a6ea4c119 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022382369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.2022382369 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.4139543167 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 455567605 ps |
| CPU time | 41.07 seconds |
| Started | Jul 06 08:18:59 PM PDT 24 |
| Finished | Jul 06 08:19:41 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-2a3a89f6-3a97-4cd2-8556-c28a7d207c67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139543167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .4139543167 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3715373541 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 38427617949 ps |
| CPU time | 690.37 seconds |
| Started | Jul 06 08:18:56 PM PDT 24 |
| Finished | Jul 06 08:30:27 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-ddc2fa54-4c37-4c7e-8d5d-59eaadbdf8b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715373541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.3715373541 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.1356642573 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 409778908 ps |
| CPU time | 16.81 seconds |
| Started | Jul 06 08:19:00 PM PDT 24 |
| Finished | Jul 06 08:19:18 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-cbe49b87-61e4-46a6-8db0-7a6c6b634b00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356642573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.1356642573 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.2795310225 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 283041239 ps |
| CPU time | 14.9 seconds |
| Started | Jul 06 08:18:57 PM PDT 24 |
| Finished | Jul 06 08:19:13 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-a53ff461-5984-4680-b3be-0cf057906005 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795310225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.2795310225 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.2741052808 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 470890095 ps |
| CPU time | 47.5 seconds |
| Started | Jul 06 08:18:49 PM PDT 24 |
| Finished | Jul 06 08:19:36 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-cbbab9eb-3cb7-4f95-be6c-122598f30948 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741052808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.2741052808 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.117447471 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 44799904742 ps |
| CPU time | 486.13 seconds |
| Started | Jul 06 08:19:01 PM PDT 24 |
| Finished | Jul 06 08:27:08 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-cc1913bb-252e-45d3-a1c8-c4b96bf79c35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117447471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.117447471 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.847250252 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 6393189575 ps |
| CPU time | 110.03 seconds |
| Started | Jul 06 08:19:02 PM PDT 24 |
| Finished | Jul 06 08:20:53 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-4d10e481-f7db-428c-98cb-dceed59ae4e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847250252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.847250252 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.3012652915 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 540380314 ps |
| CPU time | 52.89 seconds |
| Started | Jul 06 08:18:49 PM PDT 24 |
| Finished | Jul 06 08:19:42 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-b14ec163-da1f-4f47-9fef-b03f21700dba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012652915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.3012652915 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.982267601 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 206439352 ps |
| CPU time | 16.94 seconds |
| Started | Jul 06 08:18:59 PM PDT 24 |
| Finished | Jul 06 08:19:17 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-f4d5a085-a4e6-4541-8843-fc7b9185b1ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982267601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.982267601 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.1101206198 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 198583297 ps |
| CPU time | 9 seconds |
| Started | Jul 06 08:18:50 PM PDT 24 |
| Finished | Jul 06 08:19:00 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-539ea18d-9b26-4dcc-8729-f24225512f9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101206198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.1101206198 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.3825529018 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 8247227111 ps |
| CPU time | 84.97 seconds |
| Started | Jul 06 08:19:02 PM PDT 24 |
| Finished | Jul 06 08:20:28 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-afc632bd-2c5d-40fc-b110-91ecf536f50e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825529018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.3825529018 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3191487229 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 5146756352 ps |
| CPU time | 92.46 seconds |
| Started | Jul 06 08:19:02 PM PDT 24 |
| Finished | Jul 06 08:20:35 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-0e4968f5-c13a-4888-98f3-4e59f5683c65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191487229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.3191487229 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.1720775710 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 43677016 ps |
| CPU time | 6.23 seconds |
| Started | Jul 06 08:19:02 PM PDT 24 |
| Finished | Jul 06 08:19:09 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-3516d391-e510-460e-a1e1-fd631b9cbbaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720775710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.1720775710 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.729160144 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 4158095462 ps |
| CPU time | 377.69 seconds |
| Started | Jul 06 08:18:58 PM PDT 24 |
| Finished | Jul 06 08:25:16 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-1b66a267-b27c-4514-900b-4a06436b1a7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729160144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.729160144 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2975408186 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 9099507934 ps |
| CPU time | 357.57 seconds |
| Started | Jul 06 08:18:58 PM PDT 24 |
| Finished | Jul 06 08:24:56 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-eea84ac2-7aee-42d5-b566-60ffee26e5de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975408186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.2975408186 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.139489009 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 918965713 ps |
| CPU time | 414.15 seconds |
| Started | Jul 06 08:18:54 PM PDT 24 |
| Finished | Jul 06 08:25:49 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-48b1bf59-f62d-44e3-b996-751fc64b22f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139489009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_ with_rand_reset.139489009 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3352985376 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 1508592029 ps |
| CPU time | 110.97 seconds |
| Started | Jul 06 08:18:57 PM PDT 24 |
| Finished | Jul 06 08:20:49 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-e8fead58-ab7b-4d57-a14b-25a843874c35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352985376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.3352985376 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.3913633259 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 85105619 ps |
| CPU time | 14.07 seconds |
| Started | Jul 06 08:18:54 PM PDT 24 |
| Finished | Jul 06 08:19:09 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-ff9ba24b-f0d9-414b-801c-f323fcd4b3ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913633259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.3913633259 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.2512135378 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 438091299 ps |
| CPU time | 44.78 seconds |
| Started | Jul 06 08:19:00 PM PDT 24 |
| Finished | Jul 06 08:19:45 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-828c9da0-cd8d-41af-9002-0085e10c48b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512135378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .2512135378 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.899387239 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 133943395637 ps |
| CPU time | 2226.52 seconds |
| Started | Jul 06 08:19:10 PM PDT 24 |
| Finished | Jul 06 08:56:17 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-3b69bf60-5e3e-4229-91f3-94382793a16f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899387239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_d evice_slow_rsp.899387239 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1639921491 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 1362260996 ps |
| CPU time | 57.53 seconds |
| Started | Jul 06 08:19:10 PM PDT 24 |
| Finished | Jul 06 08:20:09 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-18df2466-5e3a-4510-adf2-bc5aff2baf9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639921491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.1639921491 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.3864224952 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 350106428 ps |
| CPU time | 31.24 seconds |
| Started | Jul 06 08:19:06 PM PDT 24 |
| Finished | Jul 06 08:19:39 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-40d6b6f2-6966-45f3-b294-d7db7e6bc773 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864224952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.3864224952 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.1596569752 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 2215249213 ps |
| CPU time | 82.03 seconds |
| Started | Jul 06 08:19:00 PM PDT 24 |
| Finished | Jul 06 08:20:24 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-3b5e0ac9-dc5b-4ae5-a1fc-1d8d9f0bf91a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596569752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.1596569752 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.3915119314 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 93464587800 ps |
| CPU time | 1027.26 seconds |
| Started | Jul 06 08:19:04 PM PDT 24 |
| Finished | Jul 06 08:36:12 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-ca02428a-a3d0-42ef-a289-940babf08cff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915119314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.3915119314 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.3539498313 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 63573971443 ps |
| CPU time | 1096.2 seconds |
| Started | Jul 06 08:19:03 PM PDT 24 |
| Finished | Jul 06 08:37:20 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-b730e9b5-3ff0-4016-8800-e0b40745cabc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539498313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.3539498313 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.2460230776 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 36940712 ps |
| CPU time | 6.29 seconds |
| Started | Jul 06 08:19:01 PM PDT 24 |
| Finished | Jul 06 08:19:09 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-e1d3e24e-7c39-469d-bd09-251d324a5428 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460230776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.2460230776 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.1084286542 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 2628438610 ps |
| CPU time | 77.32 seconds |
| Started | Jul 06 08:19:08 PM PDT 24 |
| Finished | Jul 06 08:20:26 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-9fc7d78e-cc2a-4a19-b594-d28c02980a29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084286542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.1084286542 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.3150800471 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 159790369 ps |
| CPU time | 7.89 seconds |
| Started | Jul 06 08:18:57 PM PDT 24 |
| Finished | Jul 06 08:19:06 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-ad6116d3-6e6f-4aeb-bd25-20241ac68b2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150800471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.3150800471 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.584528027 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 8479455342 ps |
| CPU time | 88.12 seconds |
| Started | Jul 06 08:19:01 PM PDT 24 |
| Finished | Jul 06 08:20:30 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-4ee6e0d3-2bfe-4f91-85d7-c21f320c9c12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584528027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.584528027 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.3232854265 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 3390207224 ps |
| CPU time | 55.99 seconds |
| Started | Jul 06 08:19:04 PM PDT 24 |
| Finished | Jul 06 08:20:00 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-e6b1064f-8cfc-4a99-9d8c-1c27a9152ac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232854265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.3232854265 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.8634667 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 45876604 ps |
| CPU time | 6.93 seconds |
| Started | Jul 06 08:18:54 PM PDT 24 |
| Finished | Jul 06 08:19:02 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-1e2fecb5-15b6-495a-9274-2701c4205c64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8634667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delays.8634667 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.1853823007 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 7663559392 ps |
| CPU time | 303.66 seconds |
| Started | Jul 06 08:19:07 PM PDT 24 |
| Finished | Jul 06 08:24:12 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-2d487168-1b23-42e6-b284-0a141c78df71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853823007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.1853823007 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.3487779790 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 1535709402 ps |
| CPU time | 52.52 seconds |
| Started | Jul 06 08:19:09 PM PDT 24 |
| Finished | Jul 06 08:20:02 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-f46ebef0-552c-4492-977d-554d3c2b80f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487779790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.3487779790 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3307948247 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 580951538 ps |
| CPU time | 193.05 seconds |
| Started | Jul 06 08:19:07 PM PDT 24 |
| Finished | Jul 06 08:22:21 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-d8da029d-8c20-4d3b-bacd-a39567390266 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307948247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.3307948247 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.205846120 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 353557567 ps |
| CPU time | 167.35 seconds |
| Started | Jul 06 08:19:07 PM PDT 24 |
| Finished | Jul 06 08:21:55 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-7a00038b-d18e-4b1b-ac15-11b43d7ab8d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205846120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_reset_error.205846120 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.1535935685 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 388080986 ps |
| CPU time | 19.67 seconds |
| Started | Jul 06 08:19:11 PM PDT 24 |
| Finished | Jul 06 08:19:31 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-18175cf5-618e-4e4e-aae8-cd6a103f5306 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535935685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.1535935685 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.170140977 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 3844497541 ps |
| CPU time | 361.59 seconds |
| Started | Jul 06 08:04:54 PM PDT 24 |
| Finished | Jul 06 08:10:56 PM PDT 24 |
| Peak memory | 597056 kb |
| Host | smart-7a0edb29-1c32-4604-9356-c725b574c77f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170140977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.170140977 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.3468155203 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 4938715911 ps |
| CPU time | 514.38 seconds |
| Started | Jul 06 08:04:32 PM PDT 24 |
| Finished | Jul 06 08:13:07 PM PDT 24 |
| Peak memory | 603648 kb |
| Host | smart-758d45b5-1e4a-4ace-9569-0bae686be374 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468155203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.3468155203 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.3948777849 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 256768938 ps |
| CPU time | 19.94 seconds |
| Started | Jul 06 08:04:41 PM PDT 24 |
| Finished | Jul 06 08:05:01 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-8958e11e-4a3a-47aa-a1eb-7119e1dc1c46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948777849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 3948777849 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.533249899 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 145667220142 ps |
| CPU time | 2617.29 seconds |
| Started | Jul 06 08:04:46 PM PDT 24 |
| Finished | Jul 06 08:48:24 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-ba56dbf3-f249-490f-a496-1639ea5f7f04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533249899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_de vice_slow_rsp.533249899 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.1924257259 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 175219699 ps |
| CPU time | 24.14 seconds |
| Started | Jul 06 08:04:51 PM PDT 24 |
| Finished | Jul 06 08:05:15 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-315446ab-2f72-4917-9107-5973aceba31f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924257259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .1924257259 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.2653208715 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 589897518 ps |
| CPU time | 53.53 seconds |
| Started | Jul 06 08:04:45 PM PDT 24 |
| Finished | Jul 06 08:05:38 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-a42969ad-ed5e-4f56-883b-21d22d550739 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653208715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2653208715 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.362503108 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 378279930 ps |
| CPU time | 40.78 seconds |
| Started | Jul 06 08:04:38 PM PDT 24 |
| Finished | Jul 06 08:05:19 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-3f9bbb14-914a-4fbf-9b8a-49a3529284cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362503108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.362503108 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.1634408168 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 17040641080 ps |
| CPU time | 171.69 seconds |
| Started | Jul 06 08:04:37 PM PDT 24 |
| Finished | Jul 06 08:07:29 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-3d7d2178-18e1-4134-8630-94d749941d48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634408168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1634408168 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.1149131974 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 6802455150 ps |
| CPU time | 126.03 seconds |
| Started | Jul 06 08:04:40 PM PDT 24 |
| Finished | Jul 06 08:06:46 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-bcf13aa0-93cb-4e19-b2f2-94989d08e0cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149131974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1149131974 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.2226750355 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 114858736 ps |
| CPU time | 13.31 seconds |
| Started | Jul 06 08:04:39 PM PDT 24 |
| Finished | Jul 06 08:04:53 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-c5d67545-24df-4bf8-a093-015ee0381f7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226750355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.2226750355 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.3328364671 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 1244301539 ps |
| CPU time | 39.93 seconds |
| Started | Jul 06 08:04:46 PM PDT 24 |
| Finished | Jul 06 08:05:26 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-b4537272-0fc3-4188-9e87-8789a2049ff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328364671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3328364671 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.3303841835 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 49583308 ps |
| CPU time | 6.64 seconds |
| Started | Jul 06 08:04:32 PM PDT 24 |
| Finished | Jul 06 08:04:39 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-563c873d-d929-420a-83e8-6f08245cdb11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303841835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3303841835 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.233882800 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 8684423340 ps |
| CPU time | 94.14 seconds |
| Started | Jul 06 08:04:38 PM PDT 24 |
| Finished | Jul 06 08:06:12 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-030878ff-e61c-441a-b867-bb73e66b47be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233882800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.233882800 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.50054127 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 5691755076 ps |
| CPU time | 105.28 seconds |
| Started | Jul 06 08:04:39 PM PDT 24 |
| Finished | Jul 06 08:06:25 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-811dea93-8b47-4b26-bca3-85ff0efff429 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50054127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.50054127 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.262433032 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 35196405 ps |
| CPU time | 5.55 seconds |
| Started | Jul 06 08:04:32 PM PDT 24 |
| Finished | Jul 06 08:04:38 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-468f5286-ae99-449c-9ca9-8a09acd6bef3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262433032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays. 262433032 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.717396469 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 2504019928 ps |
| CPU time | 99.14 seconds |
| Started | Jul 06 08:04:50 PM PDT 24 |
| Finished | Jul 06 08:06:30 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-19e4f1b6-0b88-4b4c-8a89-e41f03e22acb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717396469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.717396469 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.2939341465 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 1040276098 ps |
| CPU time | 102.35 seconds |
| Started | Jul 06 08:05:03 PM PDT 24 |
| Finished | Jul 06 08:06:45 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-209980c8-81dc-4631-ab13-b8632201efbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939341465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2939341465 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.105230659 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 8519120257 ps |
| CPU time | 562.88 seconds |
| Started | Jul 06 08:05:03 PM PDT 24 |
| Finished | Jul 06 08:14:26 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-bb7a2d50-732e-4a5b-ad2b-31b1a533d2b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105230659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_w ith_rand_reset.105230659 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3827601237 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 682377935 ps |
| CPU time | 294.4 seconds |
| Started | Jul 06 08:04:53 PM PDT 24 |
| Finished | Jul 06 08:09:48 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-5c788b0b-ab52-4335-942c-c3b771fc18cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827601237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.3827601237 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.2962094664 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 196995295 ps |
| CPU time | 12.41 seconds |
| Started | Jul 06 08:04:48 PM PDT 24 |
| Finished | Jul 06 08:05:01 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-b9d24f09-0828-48d3-be96-ebadcc418b68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962094664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2962094664 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.232382909 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 1105270267 ps |
| CPU time | 88.58 seconds |
| Started | Jul 06 08:19:16 PM PDT 24 |
| Finished | Jul 06 08:20:46 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-23b27be1-9f3b-41f4-943a-4dd710e797b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232382909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device. 232382909 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2894521229 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 77216527742 ps |
| CPU time | 1435.93 seconds |
| Started | Jul 06 08:19:13 PM PDT 24 |
| Finished | Jul 06 08:43:10 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-20ed4f46-a7e4-49c2-879b-2f08b39ab49a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894521229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.2894521229 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.230472750 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 1267625200 ps |
| CPU time | 54.85 seconds |
| Started | Jul 06 08:19:14 PM PDT 24 |
| Finished | Jul 06 08:20:10 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-96c1eb14-e8d4-4f99-aa09-8e436c1cb2f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230472750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_addr .230472750 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.2359862149 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 390372113 ps |
| CPU time | 32.45 seconds |
| Started | Jul 06 08:19:14 PM PDT 24 |
| Finished | Jul 06 08:19:48 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-5b18af80-52e5-469a-bd6d-ec357f490c01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359862149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.2359862149 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.2549274746 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 2449914413 ps |
| CPU time | 102.28 seconds |
| Started | Jul 06 08:19:14 PM PDT 24 |
| Finished | Jul 06 08:20:58 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-0cf8d873-777b-40d8-99ff-41bca8d0bac1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549274746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.2549274746 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.3871825284 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 79542152398 ps |
| CPU time | 831.21 seconds |
| Started | Jul 06 08:19:14 PM PDT 24 |
| Finished | Jul 06 08:33:06 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-7728bd30-4a5f-43cb-b4f6-f404238c6922 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871825284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.3871825284 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.2355727955 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 13270309046 ps |
| CPU time | 239.12 seconds |
| Started | Jul 06 08:19:13 PM PDT 24 |
| Finished | Jul 06 08:23:12 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-4e317e65-4e09-4db7-a165-bcfe932f0b69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355727955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.2355727955 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.2838934190 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 429974764 ps |
| CPU time | 42.51 seconds |
| Started | Jul 06 08:19:16 PM PDT 24 |
| Finished | Jul 06 08:20:00 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-2c1037c9-ad45-40fd-97fb-9f87294ef4ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838934190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.2838934190 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.955811987 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 302649499 ps |
| CPU time | 25.25 seconds |
| Started | Jul 06 08:19:14 PM PDT 24 |
| Finished | Jul 06 08:19:40 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-9be8587a-734e-49ff-8380-ba00412cdf03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955811987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.955811987 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.1687985001 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 45946601 ps |
| CPU time | 7.02 seconds |
| Started | Jul 06 08:19:07 PM PDT 24 |
| Finished | Jul 06 08:19:15 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-62a9a1d0-ef0a-4f63-a833-a3a695c4e860 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687985001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.1687985001 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.529909415 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 7102467394 ps |
| CPU time | 81.52 seconds |
| Started | Jul 06 08:19:14 PM PDT 24 |
| Finished | Jul 06 08:20:38 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-a8ab236e-899a-4787-86b2-64cf8e823650 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529909415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.529909415 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.4020707520 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 5538854804 ps |
| CPU time | 97.57 seconds |
| Started | Jul 06 08:19:13 PM PDT 24 |
| Finished | Jul 06 08:20:52 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-ea8987fe-5812-4267-8478-e8cf0ccb8f4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020707520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.4020707520 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1836215302 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 44096119 ps |
| CPU time | 6.61 seconds |
| Started | Jul 06 08:19:07 PM PDT 24 |
| Finished | Jul 06 08:19:14 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-841eb9af-2ea2-4876-9440-5ad95cc30e04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836215302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.1836215302 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.1427284819 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 14846125318 ps |
| CPU time | 659.32 seconds |
| Started | Jul 06 08:19:12 PM PDT 24 |
| Finished | Jul 06 08:30:11 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-13cd8866-5397-470c-94dd-bfb0b05926b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427284819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.1427284819 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.608515105 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 3518945690 ps |
| CPU time | 128.27 seconds |
| Started | Jul 06 08:19:15 PM PDT 24 |
| Finished | Jul 06 08:21:25 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-6dbd9982-c016-4b9b-8ebb-a8b131820cd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608515105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.608515105 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.263968228 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 7243552164 ps |
| CPU time | 499.09 seconds |
| Started | Jul 06 08:19:22 PM PDT 24 |
| Finished | Jul 06 08:27:43 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-59d98992-8e26-4dde-9c01-a24ff9791100 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263968228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_reset_error.263968228 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.591329900 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 409836535 ps |
| CPU time | 20.89 seconds |
| Started | Jul 06 08:19:13 PM PDT 24 |
| Finished | Jul 06 08:19:34 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-e8e5dab7-3561-4323-9ab3-8a2d587936fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591329900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.591329900 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.354668086 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 106799063 ps |
| CPU time | 12.36 seconds |
| Started | Jul 06 08:19:21 PM PDT 24 |
| Finished | Jul 06 08:19:35 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-51566686-690d-457e-87fb-f855836eaabc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354668086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device. 354668086 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.3343337692 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 321055504 ps |
| CPU time | 40.21 seconds |
| Started | Jul 06 08:19:26 PM PDT 24 |
| Finished | Jul 06 08:20:08 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-55b48a3e-7e54-4e23-bc20-127d7dbcef98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343337692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.3343337692 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.2973517886 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 2637112573 ps |
| CPU time | 78.88 seconds |
| Started | Jul 06 08:19:24 PM PDT 24 |
| Finished | Jul 06 08:20:44 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-d3a31022-1c22-403a-99ed-ef59a1fab397 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973517886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.2973517886 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.1767141851 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 275867017 ps |
| CPU time | 29.75 seconds |
| Started | Jul 06 08:19:20 PM PDT 24 |
| Finished | Jul 06 08:19:52 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-ca293c21-46cd-4345-b2d5-49d6e9a5ee4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767141851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.1767141851 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.1744031629 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 103481483942 ps |
| CPU time | 1073.97 seconds |
| Started | Jul 06 08:19:24 PM PDT 24 |
| Finished | Jul 06 08:37:19 PM PDT 24 |
| Peak memory | 576856 kb |
| Host | smart-ce45d5e9-b5df-429e-a7a9-1f4dd9a0ee23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744031629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.1744031629 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.1026062290 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 39690088116 ps |
| CPU time | 685.08 seconds |
| Started | Jul 06 08:19:22 PM PDT 24 |
| Finished | Jul 06 08:30:49 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-f7a83a23-e087-454a-9c41-c74468dd38e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026062290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.1026062290 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.2659613652 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 586214805 ps |
| CPU time | 62.58 seconds |
| Started | Jul 06 08:19:21 PM PDT 24 |
| Finished | Jul 06 08:20:26 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-b7fd8a47-156b-496d-910f-a2766b12f07b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659613652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.2659613652 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.3513978580 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 247448510 ps |
| CPU time | 18.39 seconds |
| Started | Jul 06 08:19:21 PM PDT 24 |
| Finished | Jul 06 08:19:42 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-1be5a6ed-5ab1-4483-b446-9724dfc951db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513978580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.3513978580 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.2441102422 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 177069578 ps |
| CPU time | 8.65 seconds |
| Started | Jul 06 08:19:19 PM PDT 24 |
| Finished | Jul 06 08:19:29 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-008aa2d8-b243-4cdf-b66d-60d5e82c092d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441102422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.2441102422 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.2293347295 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 9269166483 ps |
| CPU time | 100.83 seconds |
| Started | Jul 06 08:19:23 PM PDT 24 |
| Finished | Jul 06 08:21:05 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-0525881c-5433-4642-9b88-20ae5291833d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293347295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.2293347295 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2909207305 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 4684054275 ps |
| CPU time | 83.9 seconds |
| Started | Jul 06 08:19:20 PM PDT 24 |
| Finished | Jul 06 08:20:46 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-a2fda637-ecda-4822-a9e0-fc39e8bebcee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909207305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.2909207305 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1019460052 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 52291906 ps |
| CPU time | 7.51 seconds |
| Started | Jul 06 08:19:18 PM PDT 24 |
| Finished | Jul 06 08:19:26 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-38930b7d-84dc-4564-a2a1-3946fc94bc16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019460052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.1019460052 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.2970161312 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 5741654463 ps |
| CPU time | 225.84 seconds |
| Started | Jul 06 08:19:26 PM PDT 24 |
| Finished | Jul 06 08:23:14 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-539357a5-8b2e-4b99-97c0-6d5f2e19d3a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970161312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.2970161312 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.3827843980 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 6755055536 ps |
| CPU time | 214.57 seconds |
| Started | Jul 06 08:19:26 PM PDT 24 |
| Finished | Jul 06 08:23:02 PM PDT 24 |
| Peak memory | 576960 kb |
| Host | smart-b6af7631-0adf-484d-a083-e2012b6ce75a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827843980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.3827843980 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2197888283 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 7145322555 ps |
| CPU time | 333.39 seconds |
| Started | Jul 06 08:19:29 PM PDT 24 |
| Finished | Jul 06 08:25:04 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-384fd7ae-8695-47f0-a288-27fdc95ed8c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197888283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.2197888283 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.2436449100 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 518745434 ps |
| CPU time | 144.74 seconds |
| Started | Jul 06 08:19:28 PM PDT 24 |
| Finished | Jul 06 08:21:54 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-8ce8a824-fc07-40bd-8fa6-3e8bfcaaca6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436449100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.2436449100 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.2391879546 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 917321351 ps |
| CPU time | 38.2 seconds |
| Started | Jul 06 08:19:26 PM PDT 24 |
| Finished | Jul 06 08:20:06 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-9df373ad-2105-4c15-a4a9-3ef64dd667ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391879546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.2391879546 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.3106423945 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 256291721 ps |
| CPU time | 11.12 seconds |
| Started | Jul 06 08:19:36 PM PDT 24 |
| Finished | Jul 06 08:19:47 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-c76c0f2e-dce8-40e5-9bdf-ba28d94c2a82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106423945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .3106423945 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.2191362150 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 97745696884 ps |
| CPU time | 1626.88 seconds |
| Started | Jul 06 08:19:30 PM PDT 24 |
| Finished | Jul 06 08:46:38 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-1b8c57e3-2e5c-470c-a470-ddd816843722 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191362150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.2191362150 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.1348798840 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 288465382 ps |
| CPU time | 29.51 seconds |
| Started | Jul 06 08:19:32 PM PDT 24 |
| Finished | Jul 06 08:20:03 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-649ad132-7cf1-42a2-8072-d9da342a66a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348798840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.1348798840 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.2126878899 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 99759058 ps |
| CPU time | 11.48 seconds |
| Started | Jul 06 08:19:36 PM PDT 24 |
| Finished | Jul 06 08:19:48 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-dd878ca0-070e-4434-9855-9580ac9539aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126878899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.2126878899 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.194869411 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 291038471 ps |
| CPU time | 25.57 seconds |
| Started | Jul 06 08:19:26 PM PDT 24 |
| Finished | Jul 06 08:19:53 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-0607a181-cd0d-497f-83ee-ac71c5d24179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194869411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.194869411 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.568755392 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 97103127635 ps |
| CPU time | 991.89 seconds |
| Started | Jul 06 08:19:33 PM PDT 24 |
| Finished | Jul 06 08:36:06 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-4f59c4d5-e31e-49c7-82a4-0f13b2bb5a0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568755392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.568755392 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.19765256 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 43987317901 ps |
| CPU time | 770.01 seconds |
| Started | Jul 06 08:19:36 PM PDT 24 |
| Finished | Jul 06 08:32:27 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-86b31997-6dba-4d27-9b9d-42726dfc463f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19765256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.19765256 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.3185759607 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 489774829 ps |
| CPU time | 40.28 seconds |
| Started | Jul 06 08:19:26 PM PDT 24 |
| Finished | Jul 06 08:20:08 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-8c4aef30-18fc-41c2-9fc9-76c49b9b8911 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185759607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.3185759607 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.3534904351 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 1638703080 ps |
| CPU time | 59.02 seconds |
| Started | Jul 06 08:19:32 PM PDT 24 |
| Finished | Jul 06 08:20:32 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-07633e27-3330-4dc2-9b1b-99fd5c2ce8c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534904351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.3534904351 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.1477045354 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 46035613 ps |
| CPU time | 6.08 seconds |
| Started | Jul 06 08:19:26 PM PDT 24 |
| Finished | Jul 06 08:19:34 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-30be6d85-c0ff-4053-a45e-ee1f7381bd6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477045354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.1477045354 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.2023539101 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 9110076593 ps |
| CPU time | 94.33 seconds |
| Started | Jul 06 08:19:25 PM PDT 24 |
| Finished | Jul 06 08:21:01 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-70a335cd-3859-464f-a9f8-7abb751c746c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023539101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.2023539101 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.998878502 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 5937597646 ps |
| CPU time | 108.74 seconds |
| Started | Jul 06 08:19:28 PM PDT 24 |
| Finished | Jul 06 08:21:18 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-cb0d3e95-8d53-4a53-8c69-c5c7c8dd6cfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998878502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.998878502 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.3559974892 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 52455096 ps |
| CPU time | 7.18 seconds |
| Started | Jul 06 08:19:27 PM PDT 24 |
| Finished | Jul 06 08:19:36 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-4c74168d-ca98-4a0b-9913-4eb74cd7c3e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559974892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.3559974892 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.3036160343 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 5430613836 ps |
| CPU time | 210.33 seconds |
| Started | Jul 06 08:19:32 PM PDT 24 |
| Finished | Jul 06 08:23:03 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-4542b0e9-b1e8-421a-b1f3-b01d09d24676 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036160343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.3036160343 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.2331061646 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 16130336612 ps |
| CPU time | 564.83 seconds |
| Started | Jul 06 08:19:36 PM PDT 24 |
| Finished | Jul 06 08:29:02 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-d77a65a8-87b1-44e6-a99c-e870e4f83d96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331061646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.2331061646 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.300421418 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 570064332 ps |
| CPU time | 144.92 seconds |
| Started | Jul 06 08:19:33 PM PDT 24 |
| Finished | Jul 06 08:21:59 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-6cdf1407-9ee9-481c-a832-a76d7d71503e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300421418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_ with_rand_reset.300421418 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.3373424998 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 409366827 ps |
| CPU time | 96.78 seconds |
| Started | Jul 06 08:19:35 PM PDT 24 |
| Finished | Jul 06 08:21:12 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-7b904a46-b24a-40de-a5b4-b494fc51876a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373424998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.3373424998 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.3756892109 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 288332628 ps |
| CPU time | 16.24 seconds |
| Started | Jul 06 08:19:37 PM PDT 24 |
| Finished | Jul 06 08:19:54 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-49c0fca1-a5b2-46cd-81e3-9ea26e6a496d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756892109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.3756892109 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.1315563936 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 500414610 ps |
| CPU time | 31.04 seconds |
| Started | Jul 06 08:19:40 PM PDT 24 |
| Finished | Jul 06 08:20:11 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-37bb34d9-b32d-42b2-9a83-2af322e83992 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315563936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .1315563936 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.683378498 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 25012953236 ps |
| CPU time | 467.94 seconds |
| Started | Jul 06 08:19:39 PM PDT 24 |
| Finished | Jul 06 08:27:28 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-72d68e3c-9ce1-431a-b9c8-403fc9631859 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683378498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_d evice_slow_rsp.683378498 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.661593588 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 565595079 ps |
| CPU time | 22.42 seconds |
| Started | Jul 06 08:19:44 PM PDT 24 |
| Finished | Jul 06 08:20:07 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-b21fcb6d-b7fc-4b90-aaca-9a44b3f830aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661593588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_addr .661593588 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.145799837 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 615774188 ps |
| CPU time | 58.51 seconds |
| Started | Jul 06 08:19:46 PM PDT 24 |
| Finished | Jul 06 08:20:46 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-10c202ba-4a60-49ec-8c21-b2b8be9c1d53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145799837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.145799837 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.1245851632 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 533379387 ps |
| CPU time | 43.81 seconds |
| Started | Jul 06 08:19:38 PM PDT 24 |
| Finished | Jul 06 08:20:22 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-03a76c50-6c6c-44a0-a2a0-6ea8a05466b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245851632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.1245851632 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.887875008 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 75354838963 ps |
| CPU time | 830.02 seconds |
| Started | Jul 06 08:19:39 PM PDT 24 |
| Finished | Jul 06 08:33:30 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-d3e0fea9-6361-492f-8014-101538eb2993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887875008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.887875008 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.828062131 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 38762235948 ps |
| CPU time | 646.03 seconds |
| Started | Jul 06 08:19:38 PM PDT 24 |
| Finished | Jul 06 08:30:24 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-d2197726-e60d-4747-b336-d807ad5c9e55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828062131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.828062131 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.3216817647 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 378016894 ps |
| CPU time | 30.71 seconds |
| Started | Jul 06 08:19:39 PM PDT 24 |
| Finished | Jul 06 08:20:11 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-37ccddd4-33c5-4820-aad5-74953b254366 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216817647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.3216817647 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.3696879763 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 1859680121 ps |
| CPU time | 57.07 seconds |
| Started | Jul 06 08:19:44 PM PDT 24 |
| Finished | Jul 06 08:20:41 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-3ad77f19-eb27-4a48-a007-d5504582ddb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696879763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.3696879763 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.472726918 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 170501974 ps |
| CPU time | 8.11 seconds |
| Started | Jul 06 08:19:37 PM PDT 24 |
| Finished | Jul 06 08:19:46 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-19417317-6023-455e-a81b-62785b23fd3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472726918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.472726918 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.1126948786 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 8934087622 ps |
| CPU time | 92.36 seconds |
| Started | Jul 06 08:19:40 PM PDT 24 |
| Finished | Jul 06 08:21:13 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-f9fdda75-4f00-4391-aa08-49e4f3a38e81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126948786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.1126948786 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.162565349 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 5606287037 ps |
| CPU time | 100.88 seconds |
| Started | Jul 06 08:19:39 PM PDT 24 |
| Finished | Jul 06 08:21:20 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-6883952e-f039-480d-9beb-8d69438728e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162565349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.162565349 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.3422810685 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 50540997 ps |
| CPU time | 6.34 seconds |
| Started | Jul 06 08:19:40 PM PDT 24 |
| Finished | Jul 06 08:19:47 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-f380d16b-1539-4069-b8fb-6e4416e94d71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422810685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.3422810685 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.3219336252 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 7922741850 ps |
| CPU time | 319.15 seconds |
| Started | Jul 06 08:19:45 PM PDT 24 |
| Finished | Jul 06 08:25:05 PM PDT 24 |
| Peak memory | 576820 kb |
| Host | smart-6a430831-3a5e-4049-9e5f-6e19e8416059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219336252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.3219336252 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2591547116 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 2621409696 ps |
| CPU time | 77.95 seconds |
| Started | Jul 06 08:19:42 PM PDT 24 |
| Finished | Jul 06 08:21:01 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-310bb0b6-18d1-4eb9-a885-cafa5ebf9514 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591547116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.2591547116 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.4021425707 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 811495828 ps |
| CPU time | 219.73 seconds |
| Started | Jul 06 08:19:47 PM PDT 24 |
| Finished | Jul 06 08:23:28 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-214b195e-adc5-409f-9507-24842c4a0bea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021425707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.4021425707 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.2642009276 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 150354589 ps |
| CPU time | 23.13 seconds |
| Started | Jul 06 08:19:45 PM PDT 24 |
| Finished | Jul 06 08:20:09 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-b5a12d35-d834-49cb-b121-7bd687b50210 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642009276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.2642009276 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.1571620662 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 1917242155 ps |
| CPU time | 74.32 seconds |
| Started | Jul 06 08:19:46 PM PDT 24 |
| Finished | Jul 06 08:21:03 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-9b54897e-fa86-4899-9ba8-25d075189ac3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571620662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .1571620662 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.2833834365 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 94577102298 ps |
| CPU time | 1595.3 seconds |
| Started | Jul 06 08:19:53 PM PDT 24 |
| Finished | Jul 06 08:46:30 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-10dd2059-de7d-4583-84ed-8c640a681303 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833834365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.2833834365 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3901100306 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 943104515 ps |
| CPU time | 39.38 seconds |
| Started | Jul 06 08:19:52 PM PDT 24 |
| Finished | Jul 06 08:20:32 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-385accd2-947e-4c70-a21e-34a2bcb28154 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901100306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.3901100306 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.4239501040 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 268111594 ps |
| CPU time | 27.15 seconds |
| Started | Jul 06 08:19:50 PM PDT 24 |
| Finished | Jul 06 08:20:18 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-b98004b1-da7e-4071-a35b-c7cfa7a06955 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239501040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.4239501040 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.3545643332 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 406055291 ps |
| CPU time | 37.42 seconds |
| Started | Jul 06 08:19:47 PM PDT 24 |
| Finished | Jul 06 08:20:26 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-cead0931-f818-4a6a-aaee-14c0cbb3f81f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545643332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.3545643332 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.1783594977 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 117848214971 ps |
| CPU time | 1152.73 seconds |
| Started | Jul 06 08:19:45 PM PDT 24 |
| Finished | Jul 06 08:38:59 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-cbe2b4fd-57a8-4386-bb9d-af3d5b552c4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783594977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.1783594977 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.1528099137 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 43707758415 ps |
| CPU time | 738.98 seconds |
| Started | Jul 06 08:19:45 PM PDT 24 |
| Finished | Jul 06 08:32:05 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-84d72417-63a9-4d6a-aa5a-c635dd658be9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528099137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.1528099137 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.2804435055 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 487522156 ps |
| CPU time | 46.45 seconds |
| Started | Jul 06 08:19:45 PM PDT 24 |
| Finished | Jul 06 08:20:32 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-0868558b-b73a-42df-9177-fd372525060a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804435055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.2804435055 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.1045095830 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 142588784 ps |
| CPU time | 13.38 seconds |
| Started | Jul 06 08:19:53 PM PDT 24 |
| Finished | Jul 06 08:20:07 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-0068b18e-34a7-46ee-87d6-7ccbc505413a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045095830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.1045095830 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.1948015921 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 162866334 ps |
| CPU time | 8.53 seconds |
| Started | Jul 06 08:19:45 PM PDT 24 |
| Finished | Jul 06 08:19:54 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-a5a88b3d-ef44-4064-b687-e17c88a7add0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948015921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.1948015921 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.7324903 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 8223906297 ps |
| CPU time | 84.68 seconds |
| Started | Jul 06 08:19:44 PM PDT 24 |
| Finished | Jul 06 08:21:10 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-e0d3ce69-4bc0-4d10-a756-ca1d3aa18c5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7324903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.7324903 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1026554281 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 5636587876 ps |
| CPU time | 99.21 seconds |
| Started | Jul 06 08:19:44 PM PDT 24 |
| Finished | Jul 06 08:21:24 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-0720167e-3ebc-4859-bec6-ff65395d52c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026554281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.1026554281 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1675527196 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 44854127 ps |
| CPU time | 6.38 seconds |
| Started | Jul 06 08:19:45 PM PDT 24 |
| Finished | Jul 06 08:19:52 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-d5b672e2-0f33-4f54-b67b-9187aaf5fd80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675527196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.1675527196 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.2745657318 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 6880420226 ps |
| CPU time | 276.14 seconds |
| Started | Jul 06 08:19:53 PM PDT 24 |
| Finished | Jul 06 08:24:31 PM PDT 24 |
| Peak memory | 576828 kb |
| Host | smart-dbf42dae-a089-499e-9e40-602410ad84fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745657318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.2745657318 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.1526069234 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 6901600973 ps |
| CPU time | 250.27 seconds |
| Started | Jul 06 08:19:55 PM PDT 24 |
| Finished | Jul 06 08:24:07 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-5e518a40-c9e6-4b27-b9bd-38d5465693c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526069234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.1526069234 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3288778682 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 118566466 ps |
| CPU time | 69.29 seconds |
| Started | Jul 06 08:19:52 PM PDT 24 |
| Finished | Jul 06 08:21:02 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-de00610b-01bf-4069-83f0-78b13ca0fa70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288778682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.3288778682 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.1749939912 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 6312657650 ps |
| CPU time | 267.92 seconds |
| Started | Jul 06 08:19:51 PM PDT 24 |
| Finished | Jul 06 08:24:19 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-0f5d9154-920b-4be2-a529-24a89c27431e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749939912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.1749939912 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.3660281157 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 82960430 ps |
| CPU time | 10.66 seconds |
| Started | Jul 06 08:19:52 PM PDT 24 |
| Finished | Jul 06 08:20:03 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-fef09f53-9dc3-4522-b88d-3f9a3b3c3402 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660281157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.3660281157 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.131908306 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 1273650892 ps |
| CPU time | 63.61 seconds |
| Started | Jul 06 08:19:56 PM PDT 24 |
| Finished | Jul 06 08:21:02 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-bab07985-81b5-4608-8cb7-4cfc0b47432b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131908306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device. 131908306 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3319234260 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 98771923154 ps |
| CPU time | 1778.76 seconds |
| Started | Jul 06 08:19:57 PM PDT 24 |
| Finished | Jul 06 08:49:38 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-a4fc26d1-7063-484b-9b1a-d46708db9c13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319234260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.3319234260 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.191571975 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 1189033072 ps |
| CPU time | 49.96 seconds |
| Started | Jul 06 08:20:05 PM PDT 24 |
| Finished | Jul 06 08:20:55 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-90f0cd90-4f88-4c0c-9577-9b2a36336716 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191571975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_addr .191571975 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.3943972899 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 1723302953 ps |
| CPU time | 64.47 seconds |
| Started | Jul 06 08:20:00 PM PDT 24 |
| Finished | Jul 06 08:21:05 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-c6ad2168-e4c6-4798-9f3f-d59e5e5efb5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943972899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.3943972899 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.1298759914 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 1940738477 ps |
| CPU time | 76.92 seconds |
| Started | Jul 06 08:19:55 PM PDT 24 |
| Finished | Jul 06 08:21:14 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-9b4a59e4-fc0c-4831-9ef0-39261a3c5340 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298759914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.1298759914 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.2209963833 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 40312636970 ps |
| CPU time | 449.8 seconds |
| Started | Jul 06 08:19:56 PM PDT 24 |
| Finished | Jul 06 08:27:28 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-1e78e19b-8dfe-4ef7-b0c5-df750b05d12e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209963833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.2209963833 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.1829210425 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 20359980489 ps |
| CPU time | 361.84 seconds |
| Started | Jul 06 08:19:58 PM PDT 24 |
| Finished | Jul 06 08:26:01 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-7ee86b55-3fd6-48f1-8ad2-1d0af9055c53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829210425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.1829210425 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.1729381744 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 604658027 ps |
| CPU time | 55.36 seconds |
| Started | Jul 06 08:19:57 PM PDT 24 |
| Finished | Jul 06 08:20:54 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-1cf2047e-c5b9-46ab-a7b9-64ed417efc2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729381744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.1729381744 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.3708984804 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 1290848604 ps |
| CPU time | 43.57 seconds |
| Started | Jul 06 08:19:58 PM PDT 24 |
| Finished | Jul 06 08:20:43 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-276965ed-ea24-4d18-a921-a25fab22b818 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708984804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.3708984804 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.216932063 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 252765631 ps |
| CPU time | 10.72 seconds |
| Started | Jul 06 08:19:53 PM PDT 24 |
| Finished | Jul 06 08:20:05 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-823c9008-f4b8-41dc-b847-be133af9f068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216932063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.216932063 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.262322111 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 5916065884 ps |
| CPU time | 64.17 seconds |
| Started | Jul 06 08:19:57 PM PDT 24 |
| Finished | Jul 06 08:21:03 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-9c68cd0e-d36b-49af-8cb6-4aeeb9da82d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262322111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.262322111 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.1332738080 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 4758752962 ps |
| CPU time | 80.85 seconds |
| Started | Jul 06 08:20:02 PM PDT 24 |
| Finished | Jul 06 08:21:24 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-1753679d-22d9-4ff5-af48-a6e07b11ed06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332738080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.1332738080 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2188691772 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 49332782 ps |
| CPU time | 6.8 seconds |
| Started | Jul 06 08:19:55 PM PDT 24 |
| Finished | Jul 06 08:20:04 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-0dce82a0-5016-4a2e-8cf3-4724b593b068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188691772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.2188691772 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.1701370109 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 7388154774 ps |
| CPU time | 283.91 seconds |
| Started | Jul 06 08:20:04 PM PDT 24 |
| Finished | Jul 06 08:24:48 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-654f7bc6-783f-4458-b2ea-b00acff2d105 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701370109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.1701370109 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.2516617023 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 5640719330 ps |
| CPU time | 314.48 seconds |
| Started | Jul 06 08:20:02 PM PDT 24 |
| Finished | Jul 06 08:25:18 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-fbdd6d08-2837-403b-9c76-d0b9f12b3aa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516617023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.2516617023 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2091119351 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 12992864311 ps |
| CPU time | 472.99 seconds |
| Started | Jul 06 08:20:02 PM PDT 24 |
| Finished | Jul 06 08:27:56 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-0e00e382-996e-4b7b-94c2-4acccff5dbdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091119351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.2091119351 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.1241672575 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 254906194 ps |
| CPU time | 30.28 seconds |
| Started | Jul 06 08:20:02 PM PDT 24 |
| Finished | Jul 06 08:20:33 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-5e6e32c2-fa08-4d56-b774-9d303440cb26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241672575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.1241672575 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.4033397086 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 606334105 ps |
| CPU time | 50.93 seconds |
| Started | Jul 06 08:20:09 PM PDT 24 |
| Finished | Jul 06 08:21:00 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-37ab9120-f1a6-4a30-b876-c67918b8ba3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033397086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .4033397086 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.4165321489 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 110656359709 ps |
| CPU time | 1855.17 seconds |
| Started | Jul 06 08:20:15 PM PDT 24 |
| Finished | Jul 06 08:51:11 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-27477d62-986f-418d-961c-f2ff812552aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165321489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.4165321489 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.1104905666 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 235228875 ps |
| CPU time | 29.68 seconds |
| Started | Jul 06 08:22:12 PM PDT 24 |
| Finished | Jul 06 08:22:42 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-ef7e749a-148c-43f6-9d9a-f97578a0abdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104905666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.1104905666 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.4075594476 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 151226583 ps |
| CPU time | 15.42 seconds |
| Started | Jul 06 08:20:15 PM PDT 24 |
| Finished | Jul 06 08:20:31 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-84c8ddce-a631-4594-a3c2-557bc609f049 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075594476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.4075594476 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.3323623483 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 801097299 ps |
| CPU time | 33.51 seconds |
| Started | Jul 06 08:20:15 PM PDT 24 |
| Finished | Jul 06 08:20:49 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-80270b68-3d0b-4653-b450-7df081d68e23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323623483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.3323623483 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.1091484181 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 27104942534 ps |
| CPU time | 283.56 seconds |
| Started | Jul 06 08:20:09 PM PDT 24 |
| Finished | Jul 06 08:24:53 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-2cf7d766-2864-4011-8f2e-1f2db5b3e596 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091484181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.1091484181 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.997652646 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 16613026945 ps |
| CPU time | 300.46 seconds |
| Started | Jul 06 08:20:12 PM PDT 24 |
| Finished | Jul 06 08:25:13 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-937918b9-0377-45ba-b53f-b9cb8c4f6d82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997652646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.997652646 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.260931646 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 256859216 ps |
| CPU time | 24.65 seconds |
| Started | Jul 06 08:20:10 PM PDT 24 |
| Finished | Jul 06 08:20:35 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-35e24030-8093-4ea6-8678-48172d2c22f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260931646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_dela ys.260931646 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.1977675961 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 148881146 ps |
| CPU time | 8.11 seconds |
| Started | Jul 06 08:20:10 PM PDT 24 |
| Finished | Jul 06 08:20:18 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-cfdbc4f8-59f4-4160-ad33-eef869e55e88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977675961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.1977675961 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.1094216585 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 222012068 ps |
| CPU time | 9.87 seconds |
| Started | Jul 06 08:20:07 PM PDT 24 |
| Finished | Jul 06 08:20:18 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-87c32c38-d857-4604-8e7e-ac4a7159d717 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094216585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.1094216585 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.254240874 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 4797002541 ps |
| CPU time | 50.89 seconds |
| Started | Jul 06 08:20:09 PM PDT 24 |
| Finished | Jul 06 08:21:00 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-4e537310-7f12-436d-baf5-e0f78a3f1eb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254240874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.254240874 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.5613666 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 3594928183 ps |
| CPU time | 61.67 seconds |
| Started | Jul 06 08:20:15 PM PDT 24 |
| Finished | Jul 06 08:21:17 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-6df4d4bf-57ca-4c74-bac5-8fc2ebe7c43a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5613666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.5613666 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.37710239 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 40766420 ps |
| CPU time | 5.71 seconds |
| Started | Jul 06 08:20:07 PM PDT 24 |
| Finished | Jul 06 08:20:13 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-e38fcdde-46fa-43a8-9678-cd5a28d35062 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37710239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays.37710239 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.3752485010 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 1631210816 ps |
| CPU time | 141.17 seconds |
| Started | Jul 06 08:20:17 PM PDT 24 |
| Finished | Jul 06 08:22:39 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-5b8a02b3-aef3-4b31-9a7e-c69e06937c9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752485010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.3752485010 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.3027552814 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 12468959566 ps |
| CPU time | 489.44 seconds |
| Started | Jul 06 08:20:15 PM PDT 24 |
| Finished | Jul 06 08:28:25 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-001b28aa-20a4-42bb-9f7b-fa19d0ac5c4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027552814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.3027552814 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.2346133444 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 13689659 ps |
| CPU time | 19.12 seconds |
| Started | Jul 06 08:20:15 PM PDT 24 |
| Finished | Jul 06 08:20:34 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-211c2c9e-a71b-4be0-a20d-14419fef3f34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346133444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.2346133444 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.4244039153 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 167726649 ps |
| CPU time | 37.47 seconds |
| Started | Jul 06 08:20:14 PM PDT 24 |
| Finished | Jul 06 08:20:52 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-4fe25c93-c48a-455d-b73c-3df528bf7da3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244039153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.4244039153 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.3880106505 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 959793069 ps |
| CPU time | 42.58 seconds |
| Started | Jul 06 08:20:15 PM PDT 24 |
| Finished | Jul 06 08:20:58 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-4faaa546-a8b4-479f-beac-1693e4d1c7b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880106505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.3880106505 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.4169957363 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 1139678440 ps |
| CPU time | 91.24 seconds |
| Started | Jul 06 08:20:21 PM PDT 24 |
| Finished | Jul 06 08:21:53 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-121abcbc-0a99-4f9d-aa42-c3cf62175491 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169957363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .4169957363 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.1420954758 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 84619926533 ps |
| CPU time | 1484.17 seconds |
| Started | Jul 06 08:20:22 PM PDT 24 |
| Finished | Jul 06 08:45:06 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-80798aa1-8fb6-4393-8671-84fa947530e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420954758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.1420954758 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.1026386861 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 111595678 ps |
| CPU time | 7.66 seconds |
| Started | Jul 06 08:20:25 PM PDT 24 |
| Finished | Jul 06 08:20:33 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-75c34ca9-0e68-4884-8a1e-20e90335c831 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026386861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.1026386861 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.3139965599 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 436963638 ps |
| CPU time | 17.45 seconds |
| Started | Jul 06 08:20:21 PM PDT 24 |
| Finished | Jul 06 08:20:39 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-b46aa673-af9c-452b-8aae-1dc0bd3595b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139965599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.3139965599 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.615148708 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 2252027532 ps |
| CPU time | 85.86 seconds |
| Started | Jul 06 08:20:24 PM PDT 24 |
| Finished | Jul 06 08:21:50 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-93b187db-a4fa-441f-9aa5-81d4eb463f5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615148708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.615148708 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.2232279584 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 5726740776 ps |
| CPU time | 64.08 seconds |
| Started | Jul 06 08:20:21 PM PDT 24 |
| Finished | Jul 06 08:21:26 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-9ae86073-e0ea-4584-b217-68faa2c4bd5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232279584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.2232279584 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.4262335122 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 39301117523 ps |
| CPU time | 660.27 seconds |
| Started | Jul 06 08:20:22 PM PDT 24 |
| Finished | Jul 06 08:31:22 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-d1693b1a-241b-4168-9617-5b3928264b50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262335122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.4262335122 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.3965750412 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 465013143 ps |
| CPU time | 44.62 seconds |
| Started | Jul 06 08:20:22 PM PDT 24 |
| Finished | Jul 06 08:21:07 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-f333db76-72f7-4a4b-ae38-bae4f648109b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965750412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.3965750412 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.3938196933 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 129546137 ps |
| CPU time | 13.66 seconds |
| Started | Jul 06 08:20:22 PM PDT 24 |
| Finished | Jul 06 08:20:36 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-d4251cf7-2d4d-467c-a126-eee30d2e24df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938196933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.3938196933 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.2254842632 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 237138267 ps |
| CPU time | 10.31 seconds |
| Started | Jul 06 08:20:17 PM PDT 24 |
| Finished | Jul 06 08:20:27 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-bd6898c9-e456-404f-baff-deeef0e3d37b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254842632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.2254842632 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.46333373 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 5954148800 ps |
| CPU time | 66.31 seconds |
| Started | Jul 06 08:20:15 PM PDT 24 |
| Finished | Jul 06 08:21:22 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-f62ffd4f-e4df-4580-b4b5-5a6aef6d14d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46333373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.46333373 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.4130253138 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 3864635586 ps |
| CPU time | 67.35 seconds |
| Started | Jul 06 08:20:26 PM PDT 24 |
| Finished | Jul 06 08:21:33 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-046e64ea-72a3-44fa-9dda-13d6e1f58dc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130253138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.4130253138 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.2672187058 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 48528813 ps |
| CPU time | 6.86 seconds |
| Started | Jul 06 08:20:18 PM PDT 24 |
| Finished | Jul 06 08:20:25 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-05acb02e-21f8-4c85-b1c1-df3e6b8e0002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672187058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.2672187058 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.986338299 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 6582207 ps |
| CPU time | 3.88 seconds |
| Started | Jul 06 08:20:21 PM PDT 24 |
| Finished | Jul 06 08:20:25 PM PDT 24 |
| Peak memory | 566240 kb |
| Host | smart-66dd80df-78d1-4955-969b-654d9827d111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986338299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.986338299 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.256480694 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 3568335087 ps |
| CPU time | 158.41 seconds |
| Started | Jul 06 08:20:27 PM PDT 24 |
| Finished | Jul 06 08:23:06 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-3f2906f7-a01a-46bd-b465-f8797db7a5e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256480694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.256480694 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.37763846 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 256023277 ps |
| CPU time | 156.73 seconds |
| Started | Jul 06 08:20:20 PM PDT 24 |
| Finished | Jul 06 08:22:57 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-1000de0f-7a63-4a6e-a354-96dad1b5c0b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37763846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_w ith_rand_reset.37763846 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.247873638 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 390802728 ps |
| CPU time | 136.71 seconds |
| Started | Jul 06 08:20:29 PM PDT 24 |
| Finished | Jul 06 08:22:46 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-945189d2-39bd-4fbc-97a2-231e179f4b7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247873638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_reset_error.247873638 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.2404128591 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 1103440548 ps |
| CPU time | 46.17 seconds |
| Started | Jul 06 08:20:26 PM PDT 24 |
| Finished | Jul 06 08:21:12 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-d919f182-89ec-42e6-bfd3-eac2ace47f96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404128591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.2404128591 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.884788718 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 751136335 ps |
| CPU time | 61.94 seconds |
| Started | Jul 06 08:20:34 PM PDT 24 |
| Finished | Jul 06 08:21:36 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-795cf19d-546e-404d-aea1-bc36ca2c1ce5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884788718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device. 884788718 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.248392992 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 130034363 ps |
| CPU time | 15.07 seconds |
| Started | Jul 06 08:20:47 PM PDT 24 |
| Finished | Jul 06 08:21:02 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-beb8d86b-a871-4c25-90ba-b5a19de0b80a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248392992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_addr .248392992 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.988585895 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 467351618 ps |
| CPU time | 19.1 seconds |
| Started | Jul 06 08:20:36 PM PDT 24 |
| Finished | Jul 06 08:20:55 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-0c0ee6ca-1224-4d55-9af3-8d63d2173bb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988585895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.988585895 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.3635475213 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 1400214172 ps |
| CPU time | 52.46 seconds |
| Started | Jul 06 08:20:29 PM PDT 24 |
| Finished | Jul 06 08:21:21 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-6127a068-6f51-4e58-bc73-808f4c1eeee6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635475213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.3635475213 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.3834070202 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 16149140417 ps |
| CPU time | 176.54 seconds |
| Started | Jul 06 08:20:30 PM PDT 24 |
| Finished | Jul 06 08:23:27 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-2b540001-76ac-49e8-86b1-4e1d7378ff6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834070202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.3834070202 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.4096398491 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 27078411936 ps |
| CPU time | 454.96 seconds |
| Started | Jul 06 08:20:28 PM PDT 24 |
| Finished | Jul 06 08:28:03 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-6a331b8f-c8ac-43ca-99a0-8dbe2d18de38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096398491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.4096398491 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.829158632 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 416121045 ps |
| CPU time | 41.48 seconds |
| Started | Jul 06 08:20:32 PM PDT 24 |
| Finished | Jul 06 08:21:14 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-4c5ce7e4-793d-497d-a82e-53427448eb38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829158632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_dela ys.829158632 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.3327442913 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 232441678 ps |
| CPU time | 19.84 seconds |
| Started | Jul 06 08:20:40 PM PDT 24 |
| Finished | Jul 06 08:21:00 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-d63ce1a1-cb19-4b35-9d93-a2ee61d3d1e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327442913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.3327442913 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.1029824644 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 142770752 ps |
| CPU time | 8.07 seconds |
| Started | Jul 06 08:20:31 PM PDT 24 |
| Finished | Jul 06 08:20:40 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-6be3004c-f0ba-4675-9081-1a67ed8e2d44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029824644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.1029824644 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.1698791523 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 6820161408 ps |
| CPU time | 70.3 seconds |
| Started | Jul 06 08:20:28 PM PDT 24 |
| Finished | Jul 06 08:21:39 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-60412c31-a144-48f9-81a0-c5198cfe71d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698791523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.1698791523 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.1266248836 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 5193236448 ps |
| CPU time | 95.19 seconds |
| Started | Jul 06 08:20:29 PM PDT 24 |
| Finished | Jul 06 08:22:04 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-db5d80ab-6924-484b-a8fd-ea6ce1b6c9b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266248836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.1266248836 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.2044120996 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 58101884 ps |
| CPU time | 6.62 seconds |
| Started | Jul 06 08:20:31 PM PDT 24 |
| Finished | Jul 06 08:20:38 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-8a0c46a1-99f5-493d-9719-52090ef130d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044120996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.2044120996 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.2458011992 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 8835033375 ps |
| CPU time | 348.02 seconds |
| Started | Jul 06 08:20:40 PM PDT 24 |
| Finished | Jul 06 08:26:28 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-c6631471-4557-40e3-af9a-f039660d4941 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458011992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.2458011992 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.2853719515 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 7745090810 ps |
| CPU time | 336.9 seconds |
| Started | Jul 06 08:20:41 PM PDT 24 |
| Finished | Jul 06 08:26:19 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-7e3c288e-7efe-482b-995d-3338634677b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853719515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.2853719515 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.71798734 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 67197498 ps |
| CPU time | 28.34 seconds |
| Started | Jul 06 08:20:39 PM PDT 24 |
| Finished | Jul 06 08:21:08 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-e121cf1b-c7e6-4d7f-9616-c5396f91c7a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71798734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_w ith_rand_reset.71798734 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.2757447735 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 2476147706 ps |
| CPU time | 283.98 seconds |
| Started | Jul 06 08:20:48 PM PDT 24 |
| Finished | Jul 06 08:25:33 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-68b4ea68-4953-4004-b8f7-dd6de9ec14bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757447735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.2757447735 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.1437299065 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 56027191 ps |
| CPU time | 9 seconds |
| Started | Jul 06 08:20:41 PM PDT 24 |
| Finished | Jul 06 08:20:50 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-d907c0e8-b847-45d3-8cec-a839fc320b64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437299065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.1437299065 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.564867301 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 319693779 ps |
| CPU time | 33.8 seconds |
| Started | Jul 06 08:20:48 PM PDT 24 |
| Finished | Jul 06 08:21:22 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-f0556464-ff6b-494f-8b07-6b7bcd01bb3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564867301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device. 564867301 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.1556626172 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 34888143287 ps |
| CPU time | 652.66 seconds |
| Started | Jul 06 08:20:50 PM PDT 24 |
| Finished | Jul 06 08:31:43 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-8750fc6d-8587-461d-8b1b-6a4b8da6ebed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556626172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.1556626172 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.1487582985 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 67652066 ps |
| CPU time | 6.35 seconds |
| Started | Jul 06 08:20:48 PM PDT 24 |
| Finished | Jul 06 08:20:55 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-77864c8c-0c66-4a92-92bf-35a2b342ae55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487582985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.1487582985 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.960660827 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 509773152 ps |
| CPU time | 43.76 seconds |
| Started | Jul 06 08:20:47 PM PDT 24 |
| Finished | Jul 06 08:21:31 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-3aa1e0cd-182c-45aa-9e70-0df445392738 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960660827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.960660827 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.3059886273 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 1192190099 ps |
| CPU time | 42.93 seconds |
| Started | Jul 06 08:20:41 PM PDT 24 |
| Finished | Jul 06 08:21:25 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-8854b164-aee2-4a0f-8f45-8d40bf1e19ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059886273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.3059886273 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.2651608588 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 8577940981 ps |
| CPU time | 96.99 seconds |
| Started | Jul 06 08:20:48 PM PDT 24 |
| Finished | Jul 06 08:22:26 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-4fd2e183-5723-4376-8996-8d9c6b79c2ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651608588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.2651608588 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.1975453601 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 34605507825 ps |
| CPU time | 600.11 seconds |
| Started | Jul 06 08:20:50 PM PDT 24 |
| Finished | Jul 06 08:30:50 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-77fbd06e-4edd-4010-a56a-2096250854a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975453601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.1975453601 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.3721420664 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 632029503 ps |
| CPU time | 56.96 seconds |
| Started | Jul 06 08:20:47 PM PDT 24 |
| Finished | Jul 06 08:21:45 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-9ccf7aff-a27e-4238-ae1c-a71f2d865cd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721420664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.3721420664 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.1583020577 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 2419884574 ps |
| CPU time | 79.24 seconds |
| Started | Jul 06 08:20:50 PM PDT 24 |
| Finished | Jul 06 08:22:10 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-9248fff4-18f9-4d0d-85e1-872937f60ea5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583020577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.1583020577 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.527080874 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 193015610 ps |
| CPU time | 8.82 seconds |
| Started | Jul 06 08:20:41 PM PDT 24 |
| Finished | Jul 06 08:20:50 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-a446c3c1-95d4-435c-9baa-1af5272cd904 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527080874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.527080874 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.2180707465 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 7060250675 ps |
| CPU time | 72.84 seconds |
| Started | Jul 06 08:20:39 PM PDT 24 |
| Finished | Jul 06 08:21:52 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-56ab491e-95fe-4ff3-9c41-84d5df0f001e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180707465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.2180707465 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.256628918 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 4845832023 ps |
| CPU time | 88.42 seconds |
| Started | Jul 06 08:20:40 PM PDT 24 |
| Finished | Jul 06 08:22:08 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-9ef3a946-9890-452a-9d16-ee45bd3b7ddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256628918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.256628918 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.2111563485 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 48072534 ps |
| CPU time | 6.88 seconds |
| Started | Jul 06 08:20:47 PM PDT 24 |
| Finished | Jul 06 08:20:54 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-c619bbc1-ca86-47fe-a566-5a3dfa95c48e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111563485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.2111563485 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.4133568620 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1895915351 ps |
| CPU time | 165.95 seconds |
| Started | Jul 06 08:20:48 PM PDT 24 |
| Finished | Jul 06 08:23:34 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-76bfad21-b132-45df-9d51-ed2b4ab17b50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133568620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.4133568620 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.1528782547 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 9712892007 ps |
| CPU time | 357.76 seconds |
| Started | Jul 06 08:20:57 PM PDT 24 |
| Finished | Jul 06 08:26:55 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-fb7e9849-a383-40ac-a814-d8bbad820359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528782547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.1528782547 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.3913234350 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 109627884 ps |
| CPU time | 26.33 seconds |
| Started | Jul 06 08:20:53 PM PDT 24 |
| Finished | Jul 06 08:21:19 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-3ddd827b-a6d3-4f80-b03b-45c89478a4a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913234350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.3913234350 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.463265806 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 338468636 ps |
| CPU time | 18.96 seconds |
| Started | Jul 06 08:20:50 PM PDT 24 |
| Finished | Jul 06 08:21:09 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-3424bf53-7e6f-40ab-b71b-5022defe8922 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463265806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.463265806 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.2482710821 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 4024597672 ps |
| CPU time | 371.32 seconds |
| Started | Jul 06 08:05:23 PM PDT 24 |
| Finished | Jul 06 08:11:35 PM PDT 24 |
| Peak memory | 597648 kb |
| Host | smart-b14e284a-61eb-4c4f-86f0-e84a260464bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482710821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.2482710821 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.266120404 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 32512954021 ps |
| CPU time | 4214.06 seconds |
| Started | Jul 06 08:05:02 PM PDT 24 |
| Finished | Jul 06 09:15:16 PM PDT 24 |
| Peak memory | 592832 kb |
| Host | smart-d3411808-ece1-442a-920e-ad6b25db7e40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266120404 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.chip_same_csr_outstanding.266120404 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.4273296972 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 3850358928 ps |
| CPU time | 312.78 seconds |
| Started | Jul 06 08:04:54 PM PDT 24 |
| Finished | Jul 06 08:10:07 PM PDT 24 |
| Peak memory | 603628 kb |
| Host | smart-4bfc8293-fa57-46ac-961a-f7396ef28649 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273296972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.4273296972 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.197910976 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 471686618 ps |
| CPU time | 25.79 seconds |
| Started | Jul 06 08:05:06 PM PDT 24 |
| Finished | Jul 06 08:05:32 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-70d617c1-52ab-4ab8-9ef2-a795f8448d94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197910976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.197910976 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.4240406772 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 120772187844 ps |
| CPU time | 2072.57 seconds |
| Started | Jul 06 08:05:13 PM PDT 24 |
| Finished | Jul 06 08:39:46 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-9ac39f44-b931-44e4-ab3a-b8479edbf314 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240406772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d evice_slow_rsp.4240406772 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.929787944 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 1175889573 ps |
| CPU time | 48.15 seconds |
| Started | Jul 06 08:05:19 PM PDT 24 |
| Finished | Jul 06 08:06:07 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-8eb0df8a-fd2c-4e45-9d73-01acd5110f5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929787944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr. 929787944 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.1756940337 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 2030388047 ps |
| CPU time | 71.23 seconds |
| Started | Jul 06 08:05:08 PM PDT 24 |
| Finished | Jul 06 08:06:20 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-72239d2c-e2d5-4fb6-8d9d-3c36403684c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756940337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1756940337 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.338327612 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 632749083 ps |
| CPU time | 27.87 seconds |
| Started | Jul 06 08:05:05 PM PDT 24 |
| Finished | Jul 06 08:05:34 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-a63d4077-fd9a-4651-8d8d-2004cf51f4d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338327612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.338327612 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.3744910726 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 27521033505 ps |
| CPU time | 289.63 seconds |
| Started | Jul 06 08:05:07 PM PDT 24 |
| Finished | Jul 06 08:09:57 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-6418e935-1232-4d4a-a2cf-06adb3f37da3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744910726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3744910726 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.2047995759 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 6494370742 ps |
| CPU time | 112.15 seconds |
| Started | Jul 06 08:05:05 PM PDT 24 |
| Finished | Jul 06 08:06:58 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-03f17906-0250-46c5-a207-8ad02d9a5084 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047995759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2047995759 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.3533172478 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 549232975 ps |
| CPU time | 57.34 seconds |
| Started | Jul 06 08:05:10 PM PDT 24 |
| Finished | Jul 06 08:06:08 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-cbd0d8fc-c9ee-49d2-9ea9-6c3d7cd82fe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533172478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.3533172478 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.1500330281 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 205141088 ps |
| CPU time | 16.91 seconds |
| Started | Jul 06 08:05:09 PM PDT 24 |
| Finished | Jul 06 08:05:26 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-511cd044-3ff4-42e4-a628-142dbc221d2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500330281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1500330281 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.953504929 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 38706624 ps |
| CPU time | 6.8 seconds |
| Started | Jul 06 08:04:58 PM PDT 24 |
| Finished | Jul 06 08:05:05 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-02252706-d4ca-45b0-a64a-f1fb6a834c7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953504929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.953504929 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.1529414573 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 5604362437 ps |
| CPU time | 60.58 seconds |
| Started | Jul 06 08:04:59 PM PDT 24 |
| Finished | Jul 06 08:06:00 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-6a49ec66-047d-42a4-8862-52c049356a6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529414573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1529414573 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3592743595 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 4555646449 ps |
| CPU time | 75.85 seconds |
| Started | Jul 06 08:05:00 PM PDT 24 |
| Finished | Jul 06 08:06:16 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-3980e195-527b-4bd6-a9b4-e1d682b6cd5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592743595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3592743595 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.1097308882 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 37625389 ps |
| CPU time | 6.57 seconds |
| Started | Jul 06 08:04:59 PM PDT 24 |
| Finished | Jul 06 08:05:05 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-535ee517-161c-426a-91da-20cb171fb40d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097308882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .1097308882 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.4257871416 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 10410131180 ps |
| CPU time | 436.17 seconds |
| Started | Jul 06 08:05:20 PM PDT 24 |
| Finished | Jul 06 08:12:36 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-c4330979-9492-4cc1-891a-7a6911c4e823 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257871416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.4257871416 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.3755648702 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 1165766186 ps |
| CPU time | 87.86 seconds |
| Started | Jul 06 08:05:18 PM PDT 24 |
| Finished | Jul 06 08:06:47 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-a6cb44b3-ae79-40fa-ac0f-7bee7b8ca925 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755648702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3755648702 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.719545915 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 2610296952 ps |
| CPU time | 386.18 seconds |
| Started | Jul 06 08:05:13 PM PDT 24 |
| Finished | Jul 06 08:11:40 PM PDT 24 |
| Peak memory | 576852 kb |
| Host | smart-89b6da02-8756-4280-a052-451047bc9640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719545915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_w ith_rand_reset.719545915 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.380282893 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 8646993209 ps |
| CPU time | 360.23 seconds |
| Started | Jul 06 08:05:17 PM PDT 24 |
| Finished | Jul 06 08:11:17 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-7badb8e1-a907-4fa2-8911-654bec8cadbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380282893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_reset_error.380282893 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.4171864714 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 1331239055 ps |
| CPU time | 62.09 seconds |
| Started | Jul 06 08:05:19 PM PDT 24 |
| Finished | Jul 06 08:06:22 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-d832b114-2592-4b8d-94fa-ae786b24e352 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171864714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.4171864714 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.2207050609 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 102864373 ps |
| CPU time | 20.2 seconds |
| Started | Jul 06 08:20:53 PM PDT 24 |
| Finished | Jul 06 08:21:14 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-17823188-5726-45d4-8c54-a939a4f64849 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207050609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .2207050609 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.3729829835 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 298757096 ps |
| CPU time | 17.2 seconds |
| Started | Jul 06 08:20:54 PM PDT 24 |
| Finished | Jul 06 08:21:11 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-3e5e8035-2ed5-4121-9d24-3ab76d29f168 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729829835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.3729829835 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.251139700 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 76325461 ps |
| CPU time | 8.71 seconds |
| Started | Jul 06 08:20:52 PM PDT 24 |
| Finished | Jul 06 08:21:01 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-be27a228-ec59-478a-b4d8-aa3935fd67d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251139700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.251139700 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.4054122789 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 530608596 ps |
| CPU time | 20.41 seconds |
| Started | Jul 06 08:20:53 PM PDT 24 |
| Finished | Jul 06 08:21:13 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-2b8e1cc6-0c4f-4f4c-afbe-eb65b5da4183 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054122789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.4054122789 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.3157213716 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 74204210681 ps |
| CPU time | 757.31 seconds |
| Started | Jul 06 08:20:58 PM PDT 24 |
| Finished | Jul 06 08:33:36 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-31d33ba4-2d2d-4e71-bc92-a6cb5a68d19f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157213716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.3157213716 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.607406178 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 52965332622 ps |
| CPU time | 882.63 seconds |
| Started | Jul 06 08:20:53 PM PDT 24 |
| Finished | Jul 06 08:35:36 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-de3c8742-2de5-4b7e-a137-0d4d9b305307 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607406178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.607406178 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.986046990 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 119044531 ps |
| CPU time | 14.32 seconds |
| Started | Jul 06 08:20:55 PM PDT 24 |
| Finished | Jul 06 08:21:10 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-0e126e3d-9d62-4284-9ae0-ed322e5de2b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986046990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_dela ys.986046990 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.845925779 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 465336034 ps |
| CPU time | 36.49 seconds |
| Started | Jul 06 08:20:57 PM PDT 24 |
| Finished | Jul 06 08:21:35 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-6ac5b83f-d249-4620-9ee9-3e4ca4e572a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845925779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.845925779 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.2935198139 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 191521433 ps |
| CPU time | 9.35 seconds |
| Started | Jul 06 08:20:57 PM PDT 24 |
| Finished | Jul 06 08:21:07 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-29b3aee5-2edc-41e3-b3ab-b29a3d89ee3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935198139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.2935198139 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.1615569212 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 6006142656 ps |
| CPU time | 63.83 seconds |
| Started | Jul 06 08:20:57 PM PDT 24 |
| Finished | Jul 06 08:22:02 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-077a298b-7c42-4c36-8287-1d3f2ae761ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615569212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.1615569212 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.3670489309 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 6292685610 ps |
| CPU time | 114.25 seconds |
| Started | Jul 06 08:20:57 PM PDT 24 |
| Finished | Jul 06 08:22:52 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-467614ba-e6b1-40b9-b8f5-b16cf4650dc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670489309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.3670489309 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.4049859547 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 40490763 ps |
| CPU time | 6.49 seconds |
| Started | Jul 06 08:20:52 PM PDT 24 |
| Finished | Jul 06 08:20:59 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-c8c81dee-715a-4911-9883-651d2f7b8eb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049859547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.4049859547 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.673688399 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 21372441384 ps |
| CPU time | 812.7 seconds |
| Started | Jul 06 08:21:01 PM PDT 24 |
| Finished | Jul 06 08:34:34 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-c73ce584-2dd3-4052-bb2a-04faefccdfc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673688399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.673688399 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.2945618577 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 672710109 ps |
| CPU time | 65.76 seconds |
| Started | Jul 06 08:21:00 PM PDT 24 |
| Finished | Jul 06 08:22:07 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-d6dc28a5-e786-42a0-bfa6-927618fe1c5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945618577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.2945618577 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2395020334 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 13195061098 ps |
| CPU time | 637.35 seconds |
| Started | Jul 06 08:21:00 PM PDT 24 |
| Finished | Jul 06 08:31:38 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-edc20f08-fc34-47d3-8454-f55c8d5331e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395020334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.2395020334 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3584071926 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 4587186262 ps |
| CPU time | 356.38 seconds |
| Started | Jul 06 08:21:01 PM PDT 24 |
| Finished | Jul 06 08:26:58 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-a89423b5-c530-44bf-be35-4c0162d3fa7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584071926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.3584071926 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.2568210368 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 1320086002 ps |
| CPU time | 61.27 seconds |
| Started | Jul 06 08:20:53 PM PDT 24 |
| Finished | Jul 06 08:21:55 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-6a1ae703-f7ce-4b94-b479-18f9c49fccc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568210368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.2568210368 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.1050042350 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 1097788468 ps |
| CPU time | 54.15 seconds |
| Started | Jul 06 08:21:08 PM PDT 24 |
| Finished | Jul 06 08:22:03 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-9e8f9848-49d1-4901-afea-c9fed30260e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050042350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .1050042350 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.1496742474 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 92889108744 ps |
| CPU time | 1553.84 seconds |
| Started | Jul 06 08:21:08 PM PDT 24 |
| Finished | Jul 06 08:47:02 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-e0034901-ded7-4370-86ab-d57ac83e5e27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496742474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.1496742474 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.2303513645 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 298037801 ps |
| CPU time | 15.81 seconds |
| Started | Jul 06 08:21:14 PM PDT 24 |
| Finished | Jul 06 08:21:31 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-2e7416a9-ec77-46a4-8826-2d6fbaad9403 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303513645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.2303513645 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.3279087858 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 555936712 ps |
| CPU time | 20.85 seconds |
| Started | Jul 06 08:21:26 PM PDT 24 |
| Finished | Jul 06 08:21:47 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-cd80cafa-1918-448d-a6ba-c1e755ea1c1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279087858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.3279087858 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.4067298821 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 117489236 ps |
| CPU time | 8.14 seconds |
| Started | Jul 06 08:21:07 PM PDT 24 |
| Finished | Jul 06 08:21:16 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-39f4a545-20b5-492e-b2fa-092af989ed57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067298821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.4067298821 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.3372085012 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 96923000023 ps |
| CPU time | 1028.24 seconds |
| Started | Jul 06 08:21:09 PM PDT 24 |
| Finished | Jul 06 08:38:18 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-b6f71ba2-46ea-4609-8c8d-7022bdca5ba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372085012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.3372085012 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.2807363233 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 46716246609 ps |
| CPU time | 738.68 seconds |
| Started | Jul 06 08:21:10 PM PDT 24 |
| Finished | Jul 06 08:33:29 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-99b97f20-ce65-444a-b6c3-bb6c829e8e95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807363233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.2807363233 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.1219524708 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 225639524 ps |
| CPU time | 20.67 seconds |
| Started | Jul 06 08:21:05 PM PDT 24 |
| Finished | Jul 06 08:21:26 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-be718973-dbb9-40e3-a340-b53a5e0b4c78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219524708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.1219524708 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.925910317 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 1391197597 ps |
| CPU time | 44.14 seconds |
| Started | Jul 06 08:21:07 PM PDT 24 |
| Finished | Jul 06 08:21:51 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-f9a18830-ed00-4d87-8306-b4e016f29852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925910317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.925910317 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.3012943741 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 186721070 ps |
| CPU time | 9.47 seconds |
| Started | Jul 06 08:20:59 PM PDT 24 |
| Finished | Jul 06 08:21:09 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-60810033-7953-455a-8382-1e6f085e7fe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012943741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.3012943741 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.3817475826 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 7432518541 ps |
| CPU time | 76.61 seconds |
| Started | Jul 06 08:21:10 PM PDT 24 |
| Finished | Jul 06 08:22:27 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-f08cb6a0-a280-4f74-9bd8-32b0ea066768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817475826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.3817475826 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.1357734240 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 6687336008 ps |
| CPU time | 117.37 seconds |
| Started | Jul 06 08:21:06 PM PDT 24 |
| Finished | Jul 06 08:23:03 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-9cca9e70-ad1a-42cc-a4b5-6561a5b8078d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357734240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.1357734240 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.3441215987 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 48273837 ps |
| CPU time | 6.99 seconds |
| Started | Jul 06 08:21:00 PM PDT 24 |
| Finished | Jul 06 08:21:07 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-a0bea47e-a24f-4147-a6e6-483b4fbfa71c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441215987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.3441215987 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.4040699316 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 1572481523 ps |
| CPU time | 157.4 seconds |
| Started | Jul 06 08:21:12 PM PDT 24 |
| Finished | Jul 06 08:23:50 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-c496e9a6-5a4a-4bf4-94ab-3208c49fc239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040699316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.4040699316 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.2510720508 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 650059501 ps |
| CPU time | 57.82 seconds |
| Started | Jul 06 08:21:14 PM PDT 24 |
| Finished | Jul 06 08:22:13 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-549f6473-4d68-4208-ab1a-0f1ae60ba61a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510720508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.2510720508 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.3492825257 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 5088536313 ps |
| CPU time | 513.35 seconds |
| Started | Jul 06 08:21:12 PM PDT 24 |
| Finished | Jul 06 08:29:46 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-8ea3bd72-802e-4383-905e-ce6081295b9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492825257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.3492825257 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.4289041111 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 1374133590 ps |
| CPU time | 61.72 seconds |
| Started | Jul 06 08:21:13 PM PDT 24 |
| Finished | Jul 06 08:22:16 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-752da18e-345a-4ff3-94ba-59b3427bb129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289041111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.4289041111 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.2349962067 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 935834863 ps |
| CPU time | 80.01 seconds |
| Started | Jul 06 08:21:19 PM PDT 24 |
| Finished | Jul 06 08:22:40 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-12da97d9-f366-4c83-9f4a-9c9e859614db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349962067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .2349962067 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.3768372149 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 14437267882 ps |
| CPU time | 250.37 seconds |
| Started | Jul 06 08:21:19 PM PDT 24 |
| Finished | Jul 06 08:25:30 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-48cdb7f4-d963-4b42-98b6-5aac1fef9a25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768372149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.3768372149 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.896764841 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 295983429 ps |
| CPU time | 34.22 seconds |
| Started | Jul 06 08:21:19 PM PDT 24 |
| Finished | Jul 06 08:21:55 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-00bfacf1-d69f-4012-bb14-cf6528f5b925 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896764841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_addr .896764841 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.804323523 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 2184325548 ps |
| CPU time | 78.26 seconds |
| Started | Jul 06 08:21:19 PM PDT 24 |
| Finished | Jul 06 08:22:38 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-0566fe51-ab1d-4355-bc9f-c23976424417 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804323523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.804323523 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.3069750176 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 447763319 ps |
| CPU time | 45.26 seconds |
| Started | Jul 06 08:21:14 PM PDT 24 |
| Finished | Jul 06 08:22:00 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-9c6685b9-87ff-4890-8d97-03e15747c7e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069750176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.3069750176 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.3985440576 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 81595229102 ps |
| CPU time | 909.54 seconds |
| Started | Jul 06 08:21:12 PM PDT 24 |
| Finished | Jul 06 08:36:22 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-bbb5dd92-45b6-43ba-8cad-e01b8b044000 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985440576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.3985440576 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.3008095422 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 34297461389 ps |
| CPU time | 602.45 seconds |
| Started | Jul 06 08:21:14 PM PDT 24 |
| Finished | Jul 06 08:31:17 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-b844471b-30e0-4418-9e2c-7d0dc7fbb598 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008095422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.3008095422 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.465255523 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 235007432 ps |
| CPU time | 25.28 seconds |
| Started | Jul 06 08:21:13 PM PDT 24 |
| Finished | Jul 06 08:21:39 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-03d70866-76a1-4b5b-875d-16bf1156378b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465255523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_dela ys.465255523 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.2996960677 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 441720273 ps |
| CPU time | 35.68 seconds |
| Started | Jul 06 08:21:19 PM PDT 24 |
| Finished | Jul 06 08:21:55 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-5729f526-e4c0-4934-890c-5853c66ccba7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996960677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.2996960677 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.568973940 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 46230814 ps |
| CPU time | 5.96 seconds |
| Started | Jul 06 08:21:25 PM PDT 24 |
| Finished | Jul 06 08:21:31 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-7c0d8b55-5902-4c09-9246-ef3f72760c0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568973940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.568973940 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.2659217738 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 7950769916 ps |
| CPU time | 84.97 seconds |
| Started | Jul 06 08:21:24 PM PDT 24 |
| Finished | Jul 06 08:22:49 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-eef5fa71-9b08-4c21-919c-c5a145afc002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659217738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.2659217738 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.859686059 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 5020553285 ps |
| CPU time | 82.48 seconds |
| Started | Jul 06 08:21:13 PM PDT 24 |
| Finished | Jul 06 08:22:36 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-d2e26486-51aa-4bfb-a536-ac97dff1f2d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859686059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.859686059 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.70817758 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 41179046 ps |
| CPU time | 6.37 seconds |
| Started | Jul 06 08:21:13 PM PDT 24 |
| Finished | Jul 06 08:21:20 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-1b431eb4-51ac-4d75-bc7a-9fbcd01239ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70817758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays.70817758 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.3143190317 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 2687685420 ps |
| CPU time | 193.05 seconds |
| Started | Jul 06 08:21:19 PM PDT 24 |
| Finished | Jul 06 08:24:33 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-b2807fa7-45f3-4e3e-80eb-845affd1e6b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143190317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.3143190317 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.3030791523 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 3241166457 ps |
| CPU time | 121.15 seconds |
| Started | Jul 06 08:21:18 PM PDT 24 |
| Finished | Jul 06 08:23:20 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-288e4c8d-ebfc-4651-a18e-51f3e8cf8fa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030791523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.3030791523 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.2342432789 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 417796321 ps |
| CPU time | 89.97 seconds |
| Started | Jul 06 08:21:29 PM PDT 24 |
| Finished | Jul 06 08:23:00 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-fdd1f918-9c6d-46fd-a934-5ca4d5018aaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342432789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.2342432789 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.1546460481 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 269829171 ps |
| CPU time | 32.53 seconds |
| Started | Jul 06 08:21:25 PM PDT 24 |
| Finished | Jul 06 08:21:57 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-a3d99a62-cee8-4cda-a9bc-f5c2e7d1d7e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546460481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.1546460481 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.2520108530 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 303770297 ps |
| CPU time | 14.64 seconds |
| Started | Jul 06 08:21:25 PM PDT 24 |
| Finished | Jul 06 08:21:40 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-a9ec6c76-203b-4884-bc2a-5d9cc274fbd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520108530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .2520108530 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.3629728138 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 122918041610 ps |
| CPU time | 2034.32 seconds |
| Started | Jul 06 08:21:32 PM PDT 24 |
| Finished | Jul 06 08:55:26 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-b32179df-680e-4297-9064-d0f219784904 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629728138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.3629728138 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.3791638303 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 293937319 ps |
| CPU time | 33.51 seconds |
| Started | Jul 06 08:21:38 PM PDT 24 |
| Finished | Jul 06 08:22:12 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-907512fb-d951-4e61-95dd-51a849d992e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791638303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.3791638303 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.4275022485 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1172496454 ps |
| CPU time | 44.54 seconds |
| Started | Jul 06 08:21:25 PM PDT 24 |
| Finished | Jul 06 08:22:10 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-d3d79f79-b99f-4834-bd5e-9d1bd4cb2a5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275022485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.4275022485 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.869270032 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 1715796294 ps |
| CPU time | 62.04 seconds |
| Started | Jul 06 08:21:25 PM PDT 24 |
| Finished | Jul 06 08:22:28 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-3b4e200f-d17a-4f30-9988-f1b9be82679b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869270032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.869270032 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.1638185720 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 3490034095 ps |
| CPU time | 62.92 seconds |
| Started | Jul 06 08:21:25 PM PDT 24 |
| Finished | Jul 06 08:22:29 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-c66e24c5-c471-41d0-becb-02353dd30820 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638185720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.1638185720 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1264616959 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 351625836 ps |
| CPU time | 30.42 seconds |
| Started | Jul 06 08:22:43 PM PDT 24 |
| Finished | Jul 06 08:23:14 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-dcb25e3a-89fc-4b0c-97a8-65aab83df41a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264616959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.1264616959 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.1283613316 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 2466981992 ps |
| CPU time | 76.15 seconds |
| Started | Jul 06 08:21:25 PM PDT 24 |
| Finished | Jul 06 08:22:41 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-90cb2182-5e73-417d-90f3-f201c25d4bf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283613316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.1283613316 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.3967918647 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 45608566 ps |
| CPU time | 6.83 seconds |
| Started | Jul 06 08:21:29 PM PDT 24 |
| Finished | Jul 06 08:21:37 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-484dd371-6f6c-44fd-b356-b9246c2bd96d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967918647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.3967918647 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.1582847277 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 9704621775 ps |
| CPU time | 106.22 seconds |
| Started | Jul 06 08:21:25 PM PDT 24 |
| Finished | Jul 06 08:23:11 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-b17ed694-e126-4532-b3e2-3fd51f493bc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582847277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.1582847277 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3999113377 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 4348021551 ps |
| CPU time | 81.9 seconds |
| Started | Jul 06 08:21:25 PM PDT 24 |
| Finished | Jul 06 08:22:48 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-4dbefe7c-62f9-4c60-a666-4411caf963c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999113377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.3999113377 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.642354048 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 46377419 ps |
| CPU time | 6.72 seconds |
| Started | Jul 06 08:21:21 PM PDT 24 |
| Finished | Jul 06 08:21:28 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-83575a54-561e-4f7d-9169-625260f91b66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642354048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delays .642354048 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.2503316678 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 3365276353 ps |
| CPU time | 142.86 seconds |
| Started | Jul 06 08:21:38 PM PDT 24 |
| Finished | Jul 06 08:24:02 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-b8b41bd2-b42c-40db-9532-622d48915864 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503316678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.2503316678 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.4240601743 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 4351499675 ps |
| CPU time | 142.43 seconds |
| Started | Jul 06 08:21:30 PM PDT 24 |
| Finished | Jul 06 08:23:53 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-8dfe94a0-e529-4973-8575-aa970997c4a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240601743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.4240601743 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3982224698 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 72390624 ps |
| CPU time | 21.24 seconds |
| Started | Jul 06 08:21:30 PM PDT 24 |
| Finished | Jul 06 08:21:52 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-b856a780-3392-4372-b86f-f46dde480ccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982224698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.3982224698 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.225173670 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 686364887 ps |
| CPU time | 199.51 seconds |
| Started | Jul 06 08:21:38 PM PDT 24 |
| Finished | Jul 06 08:24:58 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-c5893d01-1807-469f-a052-301b57cfd817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225173670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_reset_error.225173670 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.872155744 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 97706214 ps |
| CPU time | 7.48 seconds |
| Started | Jul 06 08:21:27 PM PDT 24 |
| Finished | Jul 06 08:21:35 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-87df38c1-8d45-495f-a83f-12fea58fdba6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872155744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.872155744 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.4289547441 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 487057721 ps |
| CPU time | 39.24 seconds |
| Started | Jul 06 08:21:38 PM PDT 24 |
| Finished | Jul 06 08:22:18 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-7fd88400-6dd1-4498-9fd0-6fd539755f95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289547441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .4289547441 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.95658843 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 63054723681 ps |
| CPU time | 1113.31 seconds |
| Started | Jul 06 08:21:39 PM PDT 24 |
| Finished | Jul 06 08:40:13 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-175f466e-34f3-45c3-884f-99a4039cdf10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95658843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_de vice_slow_rsp.95658843 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.4045855899 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 302730113 ps |
| CPU time | 32.05 seconds |
| Started | Jul 06 08:21:37 PM PDT 24 |
| Finished | Jul 06 08:22:09 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-b1c0b5d2-51e7-4b04-b833-9af4d7ba7e19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045855899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.4045855899 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.1678895248 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 1235899960 ps |
| CPU time | 43.21 seconds |
| Started | Jul 06 08:21:44 PM PDT 24 |
| Finished | Jul 06 08:22:27 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-a34580fc-f53f-4b44-8283-135a5f2b8b01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678895248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.1678895248 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.3062216054 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 2586231483 ps |
| CPU time | 97.63 seconds |
| Started | Jul 06 08:21:30 PM PDT 24 |
| Finished | Jul 06 08:23:08 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-9ddbb015-a509-4491-98ba-24ad483d30fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062216054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.3062216054 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.1205631534 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 30668190156 ps |
| CPU time | 327.69 seconds |
| Started | Jul 06 08:21:31 PM PDT 24 |
| Finished | Jul 06 08:26:59 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-d5cc2d9a-0e2e-420f-aff4-9afa0ac0ec93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205631534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.1205631534 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.2778942466 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 8361406048 ps |
| CPU time | 156.23 seconds |
| Started | Jul 06 08:21:37 PM PDT 24 |
| Finished | Jul 06 08:24:15 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-7321115d-02ab-4a72-a576-d9c960953b19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778942466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.2778942466 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.3701774707 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 113353022 ps |
| CPU time | 16.11 seconds |
| Started | Jul 06 08:21:30 PM PDT 24 |
| Finished | Jul 06 08:21:46 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-d875a661-f16a-475e-abc8-ac2af1ffc433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701774707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.3701774707 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.246022489 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 161801264 ps |
| CPU time | 8.69 seconds |
| Started | Jul 06 08:21:43 PM PDT 24 |
| Finished | Jul 06 08:21:52 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-3277ee34-bbfd-46df-bfe2-7609636c92b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246022489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.246022489 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.3991119115 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 187022019 ps |
| CPU time | 9.69 seconds |
| Started | Jul 06 08:21:31 PM PDT 24 |
| Finished | Jul 06 08:21:41 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-e8d20b79-86cd-4689-a46a-073f3f822ed5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991119115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.3991119115 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.4185366295 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 8481344455 ps |
| CPU time | 94.37 seconds |
| Started | Jul 06 08:21:31 PM PDT 24 |
| Finished | Jul 06 08:23:06 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-37498898-c7f2-484c-82a1-d3978a4d70d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185366295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.4185366295 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.1778049492 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 5259778585 ps |
| CPU time | 96.97 seconds |
| Started | Jul 06 08:21:30 PM PDT 24 |
| Finished | Jul 06 08:23:07 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-48f9c60f-3021-4c0f-ada4-f1b9f3b466de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778049492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.1778049492 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.949142100 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 52960825 ps |
| CPU time | 6.75 seconds |
| Started | Jul 06 08:21:31 PM PDT 24 |
| Finished | Jul 06 08:21:38 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-4047e812-2db3-421d-80fe-179248d8964c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949142100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delays .949142100 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.1298549663 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 2317937872 ps |
| CPU time | 120.08 seconds |
| Started | Jul 06 08:21:38 PM PDT 24 |
| Finished | Jul 06 08:23:39 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-9d23b2ab-f47e-43f8-b903-1b8f21dd6684 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298549663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.1298549663 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.2464881236 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 2878439203 ps |
| CPU time | 105.37 seconds |
| Started | Jul 06 08:21:40 PM PDT 24 |
| Finished | Jul 06 08:23:26 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-3d176563-bc30-4937-9a4f-20164ec2a1e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464881236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.2464881236 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2987674853 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 575829934 ps |
| CPU time | 168.87 seconds |
| Started | Jul 06 08:21:44 PM PDT 24 |
| Finished | Jul 06 08:24:33 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-fcfe62b2-fa55-425d-85c9-649c701ea18c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987674853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.2987674853 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.3273273124 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 1461111000 ps |
| CPU time | 266.13 seconds |
| Started | Jul 06 08:21:37 PM PDT 24 |
| Finished | Jul 06 08:26:04 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-caec65b2-2b8f-4875-a4b1-18239bf192b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273273124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.3273273124 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.3079119497 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 182296638 ps |
| CPU time | 24.13 seconds |
| Started | Jul 06 08:21:38 PM PDT 24 |
| Finished | Jul 06 08:22:03 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-20a2d049-9e71-425a-ba52-28602ee0ad86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079119497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.3079119497 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.2216711420 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 298127332 ps |
| CPU time | 30.04 seconds |
| Started | Jul 06 08:21:42 PM PDT 24 |
| Finished | Jul 06 08:22:13 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-ed53a268-482a-4e95-a51a-f8658858ff82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216711420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .2216711420 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.1670989042 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 33375139785 ps |
| CPU time | 569.15 seconds |
| Started | Jul 06 08:21:52 PM PDT 24 |
| Finished | Jul 06 08:31:22 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-57f352c0-640f-46dc-8b1b-7880347807a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670989042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.1670989042 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.39702562 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 202208787 ps |
| CPU time | 12.32 seconds |
| Started | Jul 06 08:21:49 PM PDT 24 |
| Finished | Jul 06 08:22:02 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-d0e74d5b-57e3-4720-b0ad-d46e76252f69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39702562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_addr.39702562 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.2005661520 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 1590548141 ps |
| CPU time | 55.71 seconds |
| Started | Jul 06 08:21:43 PM PDT 24 |
| Finished | Jul 06 08:22:39 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-f2a9a405-a45b-4fd2-b0ef-bfef595003b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005661520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.2005661520 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.3759431224 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 1451012304 ps |
| CPU time | 50.96 seconds |
| Started | Jul 06 08:21:52 PM PDT 24 |
| Finished | Jul 06 08:22:43 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-f0874daa-dbd4-498b-9d34-1b19ebf73106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759431224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.3759431224 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.1786141365 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 31862092670 ps |
| CPU time | 312.06 seconds |
| Started | Jul 06 08:21:52 PM PDT 24 |
| Finished | Jul 06 08:27:04 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-d83b2f60-22e6-43bf-9b97-f53fd96535aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786141365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.1786141365 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.4313860 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 56011069588 ps |
| CPU time | 994.48 seconds |
| Started | Jul 06 08:21:41 PM PDT 24 |
| Finished | Jul 06 08:38:17 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-fc350058-a046-4780-a4e1-11f49c943110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4313860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.4313860 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.2102265218 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 234313652 ps |
| CPU time | 24.18 seconds |
| Started | Jul 06 08:21:52 PM PDT 24 |
| Finished | Jul 06 08:22:17 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-a56e10c0-8142-4394-af63-00b146252ebc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102265218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.2102265218 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.1110821255 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 256427807 ps |
| CPU time | 22.12 seconds |
| Started | Jul 06 08:21:44 PM PDT 24 |
| Finished | Jul 06 08:22:07 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-2706e641-07eb-4f12-9ce9-6f9fc6f9f63b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110821255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.1110821255 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.1015737027 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 243513924 ps |
| CPU time | 11.74 seconds |
| Started | Jul 06 08:21:39 PM PDT 24 |
| Finished | Jul 06 08:21:51 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-f57b633a-9a3d-42ac-b171-7db2a51d582c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015737027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.1015737027 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.1286209565 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 7993558420 ps |
| CPU time | 84.85 seconds |
| Started | Jul 06 08:21:42 PM PDT 24 |
| Finished | Jul 06 08:23:07 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-cc0918b4-7479-42a1-81c2-7268e08c4226 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286209565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.1286209565 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.888082797 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 5677012423 ps |
| CPU time | 97.43 seconds |
| Started | Jul 06 08:21:41 PM PDT 24 |
| Finished | Jul 06 08:23:19 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-56924f2d-6d5d-4261-88a1-960098d49c01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888082797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.888082797 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.530021602 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 42743396 ps |
| CPU time | 5.94 seconds |
| Started | Jul 06 08:21:43 PM PDT 24 |
| Finished | Jul 06 08:21:49 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-863aef9c-8454-4fb8-9d07-8e1924e3ffad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530021602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delays .530021602 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.1531738024 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 1244047598 ps |
| CPU time | 46.81 seconds |
| Started | Jul 06 08:21:49 PM PDT 24 |
| Finished | Jul 06 08:22:36 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-e838902c-ca0c-492c-b1d2-e231cdef41da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531738024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.1531738024 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.3402102516 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 5785581322 ps |
| CPU time | 245.87 seconds |
| Started | Jul 06 08:21:49 PM PDT 24 |
| Finished | Jul 06 08:25:56 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-adf19c8e-d4f9-452e-b439-16842bc275b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402102516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.3402102516 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.4064311285 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 2116974418 ps |
| CPU time | 352.44 seconds |
| Started | Jul 06 08:21:52 PM PDT 24 |
| Finished | Jul 06 08:27:45 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-1d780b38-35d3-4374-9b32-4164904cb022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064311285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.4064311285 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.979833585 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 5528284110 ps |
| CPU time | 498.19 seconds |
| Started | Jul 06 08:21:47 PM PDT 24 |
| Finished | Jul 06 08:30:06 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-5701dc70-4967-41ba-82fe-6b9458f37dc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979833585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_reset_error.979833585 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3127471334 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 1194526377 ps |
| CPU time | 48.72 seconds |
| Started | Jul 06 08:21:47 PM PDT 24 |
| Finished | Jul 06 08:22:36 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-7287f42d-6657-4b0c-bd46-5236d4a0792f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127471334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3127471334 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.3381333109 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 299146355 ps |
| CPU time | 23 seconds |
| Started | Jul 06 08:21:54 PM PDT 24 |
| Finished | Jul 06 08:22:17 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-4ffc7b55-5f3e-4755-bfda-5f92bda3f93e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381333109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .3381333109 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3290786803 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 85650269028 ps |
| CPU time | 1425.9 seconds |
| Started | Jul 06 08:21:53 PM PDT 24 |
| Finished | Jul 06 08:45:40 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-d2a7987b-14fe-4fd4-9467-1dc7e60ccc8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290786803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.3290786803 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.1721793848 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 221094238 ps |
| CPU time | 12.73 seconds |
| Started | Jul 06 08:21:58 PM PDT 24 |
| Finished | Jul 06 08:22:11 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-d92f246a-197c-485a-829e-e2f605446cb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721793848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.1721793848 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.3562138453 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 1804879602 ps |
| CPU time | 62.71 seconds |
| Started | Jul 06 08:21:52 PM PDT 24 |
| Finished | Jul 06 08:22:55 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-86ab0dc8-43ef-4268-9d6c-22aab467d392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562138453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.3562138453 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.3889020039 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 220121358 ps |
| CPU time | 22.36 seconds |
| Started | Jul 06 08:21:53 PM PDT 24 |
| Finished | Jul 06 08:22:16 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-b4679785-186e-4581-8803-1a8ae89a59f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889020039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.3889020039 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.587637846 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 16023254876 ps |
| CPU time | 166.67 seconds |
| Started | Jul 06 08:21:55 PM PDT 24 |
| Finished | Jul 06 08:24:42 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-29a28a15-7113-40fd-bb73-e582cfc5d842 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587637846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.587637846 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.2005850616 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 66469371918 ps |
| CPU time | 1162 seconds |
| Started | Jul 06 08:21:53 PM PDT 24 |
| Finished | Jul 06 08:41:16 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-549ab64a-4cb8-400e-af03-1dd0ccb0d29d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005850616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.2005850616 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.565660992 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 456184343 ps |
| CPU time | 40.06 seconds |
| Started | Jul 06 08:22:00 PM PDT 24 |
| Finished | Jul 06 08:22:40 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-4b9b6c67-c510-40f0-b082-5fd6780ed379 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565660992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_dela ys.565660992 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.1734018776 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 546103415 ps |
| CPU time | 44.51 seconds |
| Started | Jul 06 08:21:56 PM PDT 24 |
| Finished | Jul 06 08:22:41 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-8949ae90-2a2d-4dd7-a282-6ad966210260 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734018776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.1734018776 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.464450403 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 49546415 ps |
| CPU time | 6.79 seconds |
| Started | Jul 06 08:21:51 PM PDT 24 |
| Finished | Jul 06 08:21:58 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-23010711-7155-4335-a29c-b39cca76719d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464450403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.464450403 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.228672883 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 6424891614 ps |
| CPU time | 70.06 seconds |
| Started | Jul 06 08:21:49 PM PDT 24 |
| Finished | Jul 06 08:22:59 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-2626d69e-74c0-4164-be01-5399354773e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228672883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.228672883 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.3889081276 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 5369580528 ps |
| CPU time | 88.1 seconds |
| Started | Jul 06 08:21:52 PM PDT 24 |
| Finished | Jul 06 08:23:21 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-229996a9-0fd6-431f-913b-9078ac97bbe3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889081276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.3889081276 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.1602048148 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 50832264 ps |
| CPU time | 7.23 seconds |
| Started | Jul 06 08:21:47 PM PDT 24 |
| Finished | Jul 06 08:21:55 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-c29fb2e9-1050-44c2-9358-0474136266e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602048148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.1602048148 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.2783452551 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 6037445185 ps |
| CPU time | 241.3 seconds |
| Started | Jul 06 08:22:01 PM PDT 24 |
| Finished | Jul 06 08:26:02 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-ea79310f-9014-4fe3-950e-270b9d3e4e78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783452551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.2783452551 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.302763326 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 9020011003 ps |
| CPU time | 322.06 seconds |
| Started | Jul 06 08:21:58 PM PDT 24 |
| Finished | Jul 06 08:27:20 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-b58d08cb-a3dc-4666-a985-707841802003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302763326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.302763326 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.223338234 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 1598821726 ps |
| CPU time | 223.26 seconds |
| Started | Jul 06 08:21:58 PM PDT 24 |
| Finished | Jul 06 08:25:42 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-5a0f6322-7509-4d57-bd6c-2406bb052a8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223338234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_ with_rand_reset.223338234 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.969761092 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 651568482 ps |
| CPU time | 183.3 seconds |
| Started | Jul 06 08:22:03 PM PDT 24 |
| Finished | Jul 06 08:25:06 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-bc498049-6cdd-4ed5-8701-7382cde78da6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969761092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_reset_error.969761092 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.2219939621 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 149352811 ps |
| CPU time | 21.77 seconds |
| Started | Jul 06 08:22:03 PM PDT 24 |
| Finished | Jul 06 08:22:25 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-24bf71b6-397d-483d-a550-677128265f52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219939621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.2219939621 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.3600266558 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 527126842 ps |
| CPU time | 44.1 seconds |
| Started | Jul 06 08:22:21 PM PDT 24 |
| Finished | Jul 06 08:23:06 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-6ad4c3f4-6d42-41e7-abf8-37237d326057 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600266558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .3600266558 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1070896110 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 74291980475 ps |
| CPU time | 1305.52 seconds |
| Started | Jul 06 08:22:04 PM PDT 24 |
| Finished | Jul 06 08:43:50 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-1f7202c0-71b4-4df9-9134-eceec2502048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070896110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.1070896110 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2383462598 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 849650876 ps |
| CPU time | 36.9 seconds |
| Started | Jul 06 08:22:21 PM PDT 24 |
| Finished | Jul 06 08:22:58 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-10d21312-1512-4a7f-be9c-d0bf5fb952e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383462598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.2383462598 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.3380726798 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 479555391 ps |
| CPU time | 39.75 seconds |
| Started | Jul 06 08:22:21 PM PDT 24 |
| Finished | Jul 06 08:23:02 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-5fd8d453-dc0f-4581-97e6-664a6a4c4402 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380726798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.3380726798 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.4043999126 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 44194877 ps |
| CPU time | 7.03 seconds |
| Started | Jul 06 08:21:58 PM PDT 24 |
| Finished | Jul 06 08:22:05 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-f6cc3941-7735-458e-84cf-7c6eca0ca27d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043999126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.4043999126 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.486619491 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 65725027610 ps |
| CPU time | 689.69 seconds |
| Started | Jul 06 08:22:08 PM PDT 24 |
| Finished | Jul 06 08:33:38 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-85771c4b-0dcd-42dd-a855-5b70e6ddf7c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486619491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.486619491 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.4222215597 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 25595033153 ps |
| CPU time | 436.64 seconds |
| Started | Jul 06 08:22:07 PM PDT 24 |
| Finished | Jul 06 08:29:24 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-b0a47a50-832a-4c0c-9173-862bee492a2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222215597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.4222215597 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.2147628688 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 355652693 ps |
| CPU time | 30.44 seconds |
| Started | Jul 06 08:21:59 PM PDT 24 |
| Finished | Jul 06 08:22:30 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-8d14f546-8a6a-4eb4-87e2-a62118e77105 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147628688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.2147628688 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.2009620423 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 493096313 ps |
| CPU time | 17.25 seconds |
| Started | Jul 06 08:22:22 PM PDT 24 |
| Finished | Jul 06 08:22:39 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-2eeea716-d70a-41fe-9b8b-c4c5678d76e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009620423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.2009620423 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.1939471442 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 218575291 ps |
| CPU time | 9.96 seconds |
| Started | Jul 06 08:22:03 PM PDT 24 |
| Finished | Jul 06 08:22:13 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-7a95c0a5-812b-4f8c-a615-91c44893ae44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939471442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.1939471442 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.3828796273 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 8773418354 ps |
| CPU time | 96.71 seconds |
| Started | Jul 06 08:22:00 PM PDT 24 |
| Finished | Jul 06 08:23:37 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-2eb59e04-0090-4ff2-8ca1-3b18f8a9a273 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828796273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.3828796273 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.2109387107 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 4505609577 ps |
| CPU time | 80.72 seconds |
| Started | Jul 06 08:22:01 PM PDT 24 |
| Finished | Jul 06 08:23:22 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-bd449c1b-3bde-45cc-9e53-1f8c0a6474b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109387107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.2109387107 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2752241955 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 49873020 ps |
| CPU time | 7.02 seconds |
| Started | Jul 06 08:21:58 PM PDT 24 |
| Finished | Jul 06 08:22:06 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-0db2daf8-593a-4894-8653-30b82c04378c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752241955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.2752241955 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.2561129293 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 200133355 ps |
| CPU time | 20.73 seconds |
| Started | Jul 06 08:22:05 PM PDT 24 |
| Finished | Jul 06 08:22:26 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-c2aa7f5b-2935-49e5-923d-cb23fbfbdff4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561129293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.2561129293 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.3309170814 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 6084422244 ps |
| CPU time | 198.84 seconds |
| Started | Jul 06 08:22:21 PM PDT 24 |
| Finished | Jul 06 08:25:41 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-7919de83-d011-46dc-b51b-0a0f56151167 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309170814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.3309170814 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.2054797740 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 831906538 ps |
| CPU time | 425.24 seconds |
| Started | Jul 06 08:22:05 PM PDT 24 |
| Finished | Jul 06 08:29:10 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-b7faec6c-b9a1-4ad8-9e2b-57ad0f89a178 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054797740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.2054797740 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.2599302165 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 6749647932 ps |
| CPU time | 325.06 seconds |
| Started | Jul 06 08:22:05 PM PDT 24 |
| Finished | Jul 06 08:27:31 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-bf786a35-1d74-4ab8-b03d-8f4ddf22eec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599302165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.2599302165 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.215149209 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 586210076 ps |
| CPU time | 28.42 seconds |
| Started | Jul 06 08:22:21 PM PDT 24 |
| Finished | Jul 06 08:22:49 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-75a08c1c-2dbf-4319-9353-321f911304ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215149209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.215149209 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.3165586951 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 476203311 ps |
| CPU time | 19.34 seconds |
| Started | Jul 06 08:22:12 PM PDT 24 |
| Finished | Jul 06 08:22:32 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-7b3431a2-6677-4b05-9aba-256d005e9aac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165586951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .3165586951 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.2158066167 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 48772202522 ps |
| CPU time | 867.01 seconds |
| Started | Jul 06 08:22:17 PM PDT 24 |
| Finished | Jul 06 08:36:45 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-57f8a8f0-4905-4c44-a589-62f6d600121f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158066167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.2158066167 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.3550957843 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 110749928 ps |
| CPU time | 14.62 seconds |
| Started | Jul 06 08:22:22 PM PDT 24 |
| Finished | Jul 06 08:22:37 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-edb15aa2-39be-477e-ae04-8d0adf8fdce8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550957843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.3550957843 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.4268921883 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 127049709 ps |
| CPU time | 14.06 seconds |
| Started | Jul 06 08:22:15 PM PDT 24 |
| Finished | Jul 06 08:22:30 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-7b1e70a2-355e-4204-9fcc-62b0ecffd223 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268921883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.4268921883 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.2218973278 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 202520406 ps |
| CPU time | 19.74 seconds |
| Started | Jul 06 08:22:10 PM PDT 24 |
| Finished | Jul 06 08:22:31 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-3baf275c-f275-4f1e-8409-58c4357128f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218973278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.2218973278 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.3734879558 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 51823494449 ps |
| CPU time | 511.65 seconds |
| Started | Jul 06 08:22:12 PM PDT 24 |
| Finished | Jul 06 08:30:44 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-baf5ccd7-b070-4564-a2e0-64237227719f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734879558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.3734879558 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.3758563736 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 28105780814 ps |
| CPU time | 507.01 seconds |
| Started | Jul 06 08:22:11 PM PDT 24 |
| Finished | Jul 06 08:30:39 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-a4e2f9c2-52b0-4633-9454-7636a31e00f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758563736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.3758563736 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.1349783989 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 584554157 ps |
| CPU time | 60.35 seconds |
| Started | Jul 06 08:22:09 PM PDT 24 |
| Finished | Jul 06 08:23:10 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-611d28a5-9b2c-4c75-9434-4967d0bdd2c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349783989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.1349783989 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.299563573 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 885961798 ps |
| CPU time | 27.74 seconds |
| Started | Jul 06 08:22:16 PM PDT 24 |
| Finished | Jul 06 08:22:44 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-0cc89e87-f085-4244-abbd-006eed176e44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299563573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.299563573 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.608310495 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 160737366 ps |
| CPU time | 8.02 seconds |
| Started | Jul 06 08:22:10 PM PDT 24 |
| Finished | Jul 06 08:22:18 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-f61a2926-b8a2-4a5d-aba0-0783e5b6c9d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608310495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.608310495 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.394879569 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 7945100530 ps |
| CPU time | 81.63 seconds |
| Started | Jul 06 08:22:12 PM PDT 24 |
| Finished | Jul 06 08:23:34 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-e75d5aa9-3539-4c87-867e-37ba21b1116a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394879569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.394879569 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1197985325 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 5866726539 ps |
| CPU time | 109.64 seconds |
| Started | Jul 06 08:22:10 PM PDT 24 |
| Finished | Jul 06 08:24:00 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-d2b78279-3568-4ff2-b8a8-f91431984778 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197985325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.1197985325 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.1194115567 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 55998582 ps |
| CPU time | 6.84 seconds |
| Started | Jul 06 08:22:11 PM PDT 24 |
| Finished | Jul 06 08:22:18 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-7ef06807-17e5-49e3-9a6d-2ee5b0114f95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194115567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.1194115567 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.4207975182 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 7539401095 ps |
| CPU time | 301.53 seconds |
| Started | Jul 06 08:22:18 PM PDT 24 |
| Finished | Jul 06 08:27:20 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-92f334b9-0e32-4475-bb62-de00fe957132 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207975182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.4207975182 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.1827272468 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 2610097101 ps |
| CPU time | 186.97 seconds |
| Started | Jul 06 08:22:15 PM PDT 24 |
| Finished | Jul 06 08:25:23 PM PDT 24 |
| Peak memory | 576820 kb |
| Host | smart-ca85d740-7f61-4de5-be4f-9da589f2193e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827272468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.1827272468 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.1839303326 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 873820024 ps |
| CPU time | 327.82 seconds |
| Started | Jul 06 08:22:15 PM PDT 24 |
| Finished | Jul 06 08:27:44 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-b2c8ed69-9861-40a2-b5e7-72e2f49504d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839303326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.1839303326 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.1317106550 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 266710352 ps |
| CPU time | 34.24 seconds |
| Started | Jul 06 08:22:18 PM PDT 24 |
| Finished | Jul 06 08:22:52 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-db30355b-7f3e-4395-8636-0350ecdedea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317106550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.1317106550 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.1581244418 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 1047496899 ps |
| CPU time | 44.3 seconds |
| Started | Jul 06 08:22:21 PM PDT 24 |
| Finished | Jul 06 08:23:06 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-d9143566-ffbd-41f5-a727-fef1ca491b9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581244418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .1581244418 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.1636937625 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 35330770699 ps |
| CPU time | 664.2 seconds |
| Started | Jul 06 08:22:22 PM PDT 24 |
| Finished | Jul 06 08:33:27 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-d769c3dc-cb30-487d-ae9f-aefb84cf3e02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636937625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.1636937625 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.4098089239 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 674518403 ps |
| CPU time | 34.42 seconds |
| Started | Jul 06 08:22:20 PM PDT 24 |
| Finished | Jul 06 08:22:55 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-be6fd974-88e9-4253-ae88-95d0b54d4a06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098089239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.4098089239 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.3370905101 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 1839886075 ps |
| CPU time | 59.91 seconds |
| Started | Jul 06 08:22:22 PM PDT 24 |
| Finished | Jul 06 08:23:22 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-b1ffe3ef-ea4b-4624-a72a-b0a7f65d2f8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370905101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.3370905101 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.3293957858 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2380171441 ps |
| CPU time | 90.48 seconds |
| Started | Jul 06 08:22:15 PM PDT 24 |
| Finished | Jul 06 08:23:46 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-0ca99e40-0cd2-4eca-9410-78578fbd31cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293957858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.3293957858 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.3305677236 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 37002907053 ps |
| CPU time | 386.73 seconds |
| Started | Jul 06 08:22:21 PM PDT 24 |
| Finished | Jul 06 08:28:48 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-b087b55f-0dd6-481b-8d03-926ffdc8e46c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305677236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.3305677236 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.3947914860 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 63366311442 ps |
| CPU time | 1100.8 seconds |
| Started | Jul 06 08:22:24 PM PDT 24 |
| Finished | Jul 06 08:40:45 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-25f5275d-74c3-4ea3-9cce-b6523b2c8de8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947914860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.3947914860 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.1003078273 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 481448012 ps |
| CPU time | 45.52 seconds |
| Started | Jul 06 08:22:22 PM PDT 24 |
| Finished | Jul 06 08:23:08 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-3b16e39c-0cfc-4deb-9bf4-6bad880bbd97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003078273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.1003078273 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.4208472908 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 2494379510 ps |
| CPU time | 80.77 seconds |
| Started | Jul 06 08:22:22 PM PDT 24 |
| Finished | Jul 06 08:23:43 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-2b1253dc-ec2f-424d-97be-c8a16c213378 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208472908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.4208472908 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.3618810132 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 215180621 ps |
| CPU time | 10.19 seconds |
| Started | Jul 06 08:22:15 PM PDT 24 |
| Finished | Jul 06 08:22:26 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-5c796c43-e978-4a4a-a127-6bbb99cb32d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618810132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.3618810132 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.4511391 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 8777123840 ps |
| CPU time | 97.39 seconds |
| Started | Jul 06 08:22:16 PM PDT 24 |
| Finished | Jul 06 08:23:54 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-f2bd2fb4-1935-4e6c-bfca-6982560155b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4511391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.4511391 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.1591812655 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 5208135343 ps |
| CPU time | 93.28 seconds |
| Started | Jul 06 08:22:18 PM PDT 24 |
| Finished | Jul 06 08:23:52 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-8add14ef-5de8-442b-b48f-4c688f2f67c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591812655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.1591812655 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.2113248842 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 37254126 ps |
| CPU time | 5.9 seconds |
| Started | Jul 06 08:22:18 PM PDT 24 |
| Finished | Jul 06 08:22:24 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-22b89568-9ad5-46ae-82f7-9fe0aa7bcd3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113248842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.2113248842 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.967688466 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 2229865339 ps |
| CPU time | 164.98 seconds |
| Started | Jul 06 08:22:31 PM PDT 24 |
| Finished | Jul 06 08:25:17 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-af3194c4-1d07-4301-96ea-aa7520ac737e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967688466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.967688466 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.3752248001 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 238277616 ps |
| CPU time | 26.1 seconds |
| Started | Jul 06 08:22:21 PM PDT 24 |
| Finished | Jul 06 08:22:48 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-523e47ac-e855-44c8-8800-4fad5899f278 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752248001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.3752248001 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.3094559966 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 7416207695 ps |
| CPU time | 447.75 seconds |
| Started | Jul 06 08:22:27 PM PDT 24 |
| Finished | Jul 06 08:29:55 PM PDT 24 |
| Peak memory | 576820 kb |
| Host | smart-f36c430c-07b0-4c04-8d42-832ea2679147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094559966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al l_with_reset_error.3094559966 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1015735834 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 494251267 ps |
| CPU time | 22.63 seconds |
| Started | Jul 06 08:22:23 PM PDT 24 |
| Finished | Jul 06 08:22:46 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-617125fb-269b-49c6-aed4-1e675f2407a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015735834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.1015735834 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.2295667186 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 6201243448 ps |
| CPU time | 613.61 seconds |
| Started | Jul 06 08:05:54 PM PDT 24 |
| Finished | Jul 06 08:16:08 PM PDT 24 |
| Peak memory | 598116 kb |
| Host | smart-e01bed4e-0849-4431-92bd-6ecaad9885af |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295667186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.2295667186 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.4231097847 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 32662219210 ps |
| CPU time | 4033.67 seconds |
| Started | Jul 06 08:05:27 PM PDT 24 |
| Finished | Jul 06 09:12:41 PM PDT 24 |
| Peak memory | 593188 kb |
| Host | smart-39a097a3-39e9-4404-ba62-34a22ba092b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231097847 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.4231097847 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.848955190 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 208881758 ps |
| CPU time | 28.05 seconds |
| Started | Jul 06 08:05:38 PM PDT 24 |
| Finished | Jul 06 08:06:07 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-bbbdc1f8-9133-4a3e-8afa-1239ae930755 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848955190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.848955190 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.519036414 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 36283484407 ps |
| CPU time | 653.64 seconds |
| Started | Jul 06 08:05:37 PM PDT 24 |
| Finished | Jul 06 08:16:31 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-a63bacf1-ba5a-4503-acdc-a966558cd009 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519036414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_de vice_slow_rsp.519036414 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.1476944177 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 269753685 ps |
| CPU time | 14.67 seconds |
| Started | Jul 06 08:05:42 PM PDT 24 |
| Finished | Jul 06 08:05:57 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-d7692d22-7a47-45f2-be6c-36f1baf09163 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476944177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .1476944177 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.2846149360 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 1750369577 ps |
| CPU time | 63.9 seconds |
| Started | Jul 06 08:05:43 PM PDT 24 |
| Finished | Jul 06 08:06:47 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-c6543a27-1bfc-4d84-944b-c337dc2c2d70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846149360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2846149360 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.60292320 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 1322191966 ps |
| CPU time | 51.68 seconds |
| Started | Jul 06 08:05:37 PM PDT 24 |
| Finished | Jul 06 08:06:29 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-92f3d757-b31c-4cea-8118-f16412a198af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60292320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.60292320 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.1670694165 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 72045133496 ps |
| CPU time | 790.14 seconds |
| Started | Jul 06 08:05:34 PM PDT 24 |
| Finished | Jul 06 08:18:45 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-d846cd40-3449-4f1b-a807-8c7edb608551 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670694165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1670694165 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.1661148990 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 4214160972 ps |
| CPU time | 69.81 seconds |
| Started | Jul 06 08:05:33 PM PDT 24 |
| Finished | Jul 06 08:06:43 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-901bcc56-6824-482d-b698-1a8e1f681345 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661148990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1661148990 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.863680663 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 559619529 ps |
| CPU time | 55.68 seconds |
| Started | Jul 06 08:05:38 PM PDT 24 |
| Finished | Jul 06 08:06:34 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-829697b0-7515-45fc-a692-98a44e97013e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863680663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delay s.863680663 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.1986147969 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 2103474196 ps |
| CPU time | 68.05 seconds |
| Started | Jul 06 08:05:37 PM PDT 24 |
| Finished | Jul 06 08:06:45 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-7ad98194-0634-4619-8613-6c057375689e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986147969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1986147969 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.1952970825 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 192018872 ps |
| CPU time | 9.24 seconds |
| Started | Jul 06 08:05:58 PM PDT 24 |
| Finished | Jul 06 08:06:08 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-b02c01fe-5b9a-47a3-82af-6ef34797763f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952970825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1952970825 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.3907867251 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 10111219759 ps |
| CPU time | 110.37 seconds |
| Started | Jul 06 08:05:35 PM PDT 24 |
| Finished | Jul 06 08:07:26 PM PDT 24 |
| Peak memory | 574576 kb |
| Host | smart-f821f610-5d80-4eb3-9752-2b6a28df9cbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907867251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3907867251 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.795159103 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 4151521731 ps |
| CPU time | 70.47 seconds |
| Started | Jul 06 08:05:33 PM PDT 24 |
| Finished | Jul 06 08:06:44 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-817a3443-00c6-4786-85fc-8273d5e17ee1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795159103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.795159103 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.1294527035 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 49791657 ps |
| CPU time | 6.98 seconds |
| Started | Jul 06 08:05:29 PM PDT 24 |
| Finished | Jul 06 08:05:36 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-582a0cd9-dd8f-4ae2-9789-d7617357b8de |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294527035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .1294527035 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.4207989351 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 2257480082 ps |
| CPU time | 205.56 seconds |
| Started | Jul 06 08:05:48 PM PDT 24 |
| Finished | Jul 06 08:09:14 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-b04603f8-64fc-4cdd-b410-a64deaff54ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207989351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.4207989351 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3885462248 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 495600766 ps |
| CPU time | 108.79 seconds |
| Started | Jul 06 08:05:50 PM PDT 24 |
| Finished | Jul 06 08:07:39 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-d3384eae-2504-4339-947e-9756b26a6d8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885462248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.3885462248 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.3661118980 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 13200711575 ps |
| CPU time | 686.74 seconds |
| Started | Jul 06 08:05:47 PM PDT 24 |
| Finished | Jul 06 08:17:14 PM PDT 24 |
| Peak memory | 576852 kb |
| Host | smart-4c5f616a-0b85-4d7e-9148-8561e5f23383 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661118980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all _with_reset_error.3661118980 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.1980466106 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 333026652 ps |
| CPU time | 44.18 seconds |
| Started | Jul 06 08:05:43 PM PDT 24 |
| Finished | Jul 06 08:06:27 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-b4f9fc5c-71b4-412d-966a-377a01566d4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980466106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1980466106 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.4092866928 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 875427703 ps |
| CPU time | 37.6 seconds |
| Started | Jul 06 08:22:33 PM PDT 24 |
| Finished | Jul 06 08:23:11 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-4eecb70d-2e70-4183-b342-1560703a2756 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092866928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .4092866928 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.1641317015 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 232135520 ps |
| CPU time | 28.28 seconds |
| Started | Jul 06 08:22:33 PM PDT 24 |
| Finished | Jul 06 08:23:02 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-1855eef0-161c-4948-a11c-42276a932d2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641317015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.1641317015 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.1832556846 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 60527662 ps |
| CPU time | 6.24 seconds |
| Started | Jul 06 08:22:33 PM PDT 24 |
| Finished | Jul 06 08:22:40 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-ea207a84-e3bf-48e7-a25e-aa2c73e46f03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832556846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.1832556846 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.1622012103 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 452076335 ps |
| CPU time | 43.98 seconds |
| Started | Jul 06 08:22:28 PM PDT 24 |
| Finished | Jul 06 08:23:12 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-d6915865-1696-40c1-a8f2-9ebd026fdb2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622012103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.1622012103 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.91570294 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 85591157050 ps |
| CPU time | 950.17 seconds |
| Started | Jul 06 08:22:29 PM PDT 24 |
| Finished | Jul 06 08:38:20 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-6b07fcdd-5efb-4b78-ae14-817905c763c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91570294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.91570294 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.2521155731 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 66296244544 ps |
| CPU time | 1171.92 seconds |
| Started | Jul 06 08:22:33 PM PDT 24 |
| Finished | Jul 06 08:42:05 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-25876dc4-25eb-4f5d-aac8-2506182d69fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521155731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.2521155731 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.2742017316 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 412618746 ps |
| CPU time | 40.61 seconds |
| Started | Jul 06 08:22:31 PM PDT 24 |
| Finished | Jul 06 08:23:12 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-f30cb4c4-3bca-4433-9bfd-842d94276413 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742017316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.2742017316 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.1720910487 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 418374299 ps |
| CPU time | 15.36 seconds |
| Started | Jul 06 08:22:33 PM PDT 24 |
| Finished | Jul 06 08:22:49 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-1bbd1b85-c6d1-4f5b-aef4-fd56caa2c6cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720910487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.1720910487 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.3732351923 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 41281054 ps |
| CPU time | 6.59 seconds |
| Started | Jul 06 08:22:28 PM PDT 24 |
| Finished | Jul 06 08:22:35 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-168c8c12-3eb3-40c0-aaaf-0c3dc22b3070 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732351923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.3732351923 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.2879464027 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 6918452638 ps |
| CPU time | 72.37 seconds |
| Started | Jul 06 08:22:28 PM PDT 24 |
| Finished | Jul 06 08:23:41 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-e0d67879-47f8-45ef-be07-971ca38b5090 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879464027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.2879464027 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.3536498025 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 3090869890 ps |
| CPU time | 56.18 seconds |
| Started | Jul 06 08:22:29 PM PDT 24 |
| Finished | Jul 06 08:23:25 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-2f9d64e2-9308-4c6d-ad79-6afef97855d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536498025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.3536498025 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.703168929 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 49907087 ps |
| CPU time | 6.08 seconds |
| Started | Jul 06 08:22:29 PM PDT 24 |
| Finished | Jul 06 08:22:35 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-fd3c8151-4322-4d25-870f-ee8be58112a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703168929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delays .703168929 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.2376621534 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 5102487724 ps |
| CPU time | 444.05 seconds |
| Started | Jul 06 08:22:33 PM PDT 24 |
| Finished | Jul 06 08:29:57 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-00dff076-a1bf-4686-ac9b-549dabaf408d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376621534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.2376621534 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.94891850 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 3919386804 ps |
| CPU time | 329.81 seconds |
| Started | Jul 06 08:22:40 PM PDT 24 |
| Finished | Jul 06 08:28:10 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-f09f3440-0778-46bd-ac37-bbe512d3a822 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94891850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.94891850 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.1736150653 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 5603347850 ps |
| CPU time | 335.47 seconds |
| Started | Jul 06 08:22:32 PM PDT 24 |
| Finished | Jul 06 08:28:08 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-3fa3da1d-f38f-44b1-a327-f6f5c55273d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736150653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_rand_reset.1736150653 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.3300188367 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 3413879454 ps |
| CPU time | 240.5 seconds |
| Started | Jul 06 08:22:39 PM PDT 24 |
| Finished | Jul 06 08:26:40 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-96a0ca6a-7cb4-43d9-a2ae-fba9a4dfe5e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300188367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.3300188367 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.2568957564 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 1286569441 ps |
| CPU time | 52.12 seconds |
| Started | Jul 06 08:22:34 PM PDT 24 |
| Finished | Jul 06 08:23:26 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-623423ab-6788-43d9-a9a9-9e7485901104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568957564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.2568957564 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.1787580373 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 1628112918 ps |
| CPU time | 77.6 seconds |
| Started | Jul 06 08:22:47 PM PDT 24 |
| Finished | Jul 06 08:24:05 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-9d762188-17ec-4e29-9c0b-41f598336d0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787580373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .1787580373 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.4129369292 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 43848074952 ps |
| CPU time | 781.46 seconds |
| Started | Jul 06 08:22:49 PM PDT 24 |
| Finished | Jul 06 08:35:51 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-d51d1747-12a6-4fa2-8381-20f5f52fcc57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129369292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.4129369292 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2742863642 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 909977490 ps |
| CPU time | 36.33 seconds |
| Started | Jul 06 08:22:45 PM PDT 24 |
| Finished | Jul 06 08:23:22 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-396d21c1-f1fb-4a4e-9041-78350748521c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742863642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.2742863642 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.1668726662 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 1164407389 ps |
| CPU time | 39.76 seconds |
| Started | Jul 06 08:22:46 PM PDT 24 |
| Finished | Jul 06 08:23:26 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-2a3484f0-5051-4199-bfd5-27b5562e48c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668726662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.1668726662 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.686455409 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 2464581287 ps |
| CPU time | 93.43 seconds |
| Started | Jul 06 08:22:43 PM PDT 24 |
| Finished | Jul 06 08:24:16 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-d033cfed-6cd1-4941-849e-bebacdb6e304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686455409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.686455409 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.3181588501 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 16053729474 ps |
| CPU time | 164.57 seconds |
| Started | Jul 06 08:22:48 PM PDT 24 |
| Finished | Jul 06 08:25:32 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-0acdab51-83d5-4c31-83c5-3c7d074ac9e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181588501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.3181588501 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.765964784 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 39705020762 ps |
| CPU time | 676.86 seconds |
| Started | Jul 06 08:22:44 PM PDT 24 |
| Finished | Jul 06 08:34:01 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-5b090328-1bd4-4176-a5ad-5fe9a0f3dde2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765964784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.765964784 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.4162108430 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 198999748 ps |
| CPU time | 21.16 seconds |
| Started | Jul 06 08:22:42 PM PDT 24 |
| Finished | Jul 06 08:23:04 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-f4bc4c72-b554-486e-a24c-762c561d7522 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162108430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.4162108430 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.1121011525 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 1832252743 ps |
| CPU time | 59.81 seconds |
| Started | Jul 06 08:22:48 PM PDT 24 |
| Finished | Jul 06 08:23:48 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-c2109df0-7368-468c-a4aa-d2519448d55d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121011525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.1121011525 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.4269475510 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 43268534 ps |
| CPU time | 6.27 seconds |
| Started | Jul 06 08:22:40 PM PDT 24 |
| Finished | Jul 06 08:22:46 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-12985500-3691-48a7-8d81-54ab5daa4fb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269475510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.4269475510 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.91387092 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 8760732991 ps |
| CPU time | 97.9 seconds |
| Started | Jul 06 08:22:39 PM PDT 24 |
| Finished | Jul 06 08:24:17 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-26c3fcef-beb2-47fc-957d-ebe5cabb4d0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91387092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.91387092 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.598433347 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 4128064480 ps |
| CPU time | 72.28 seconds |
| Started | Jul 06 08:22:39 PM PDT 24 |
| Finished | Jul 06 08:23:52 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-fac5f993-2913-42c9-947d-9916e6cee3ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598433347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.598433347 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.887538776 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 46486811 ps |
| CPU time | 7.01 seconds |
| Started | Jul 06 08:22:43 PM PDT 24 |
| Finished | Jul 06 08:22:50 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-9dc7756a-8cc1-4b52-8022-834376f0dfca |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887538776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delays .887538776 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.1565278752 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 1700046486 ps |
| CPU time | 157.83 seconds |
| Started | Jul 06 08:22:51 PM PDT 24 |
| Finished | Jul 06 08:25:30 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-d0a26af3-66c3-4d29-a360-08ad65da8560 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565278752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.1565278752 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.1900452121 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 1431323946 ps |
| CPU time | 139.52 seconds |
| Started | Jul 06 08:22:53 PM PDT 24 |
| Finished | Jul 06 08:25:13 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-4af3002f-ecf1-41f0-ba1a-87daba38dfb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900452121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.1900452121 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.1562194961 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 151134597 ps |
| CPU time | 57.53 seconds |
| Started | Jul 06 08:22:53 PM PDT 24 |
| Finished | Jul 06 08:23:51 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-d428655d-2618-4cf1-af9a-a32872846854 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562194961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.1562194961 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.1615948433 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 2834702892 ps |
| CPU time | 278.86 seconds |
| Started | Jul 06 08:22:51 PM PDT 24 |
| Finished | Jul 06 08:27:30 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-6d273206-7408-41f8-b315-5946f64e4eca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615948433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.1615948433 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.439988128 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 1018533677 ps |
| CPU time | 44.15 seconds |
| Started | Jul 06 08:22:47 PM PDT 24 |
| Finished | Jul 06 08:23:32 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-a5866f9c-a653-4351-b409-0182d8285149 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439988128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.439988128 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.3024802175 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 317701049 ps |
| CPU time | 26.39 seconds |
| Started | Jul 06 08:22:57 PM PDT 24 |
| Finished | Jul 06 08:23:24 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-abddbd2a-13dc-4eac-90e4-d3a943332ce1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024802175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .3024802175 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.3128115108 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 79301711879 ps |
| CPU time | 1254.52 seconds |
| Started | Jul 06 08:23:00 PM PDT 24 |
| Finished | Jul 06 08:43:55 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-969d0171-2966-4d48-875d-3d6172b09b8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128115108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.3128115108 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1642018780 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 789709884 ps |
| CPU time | 35.22 seconds |
| Started | Jul 06 08:23:05 PM PDT 24 |
| Finished | Jul 06 08:23:40 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-8ea56632-bea7-4e6c-bad8-bb2e7c296d30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642018780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.1642018780 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.11863561 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 2002157540 ps |
| CPU time | 75.04 seconds |
| Started | Jul 06 08:22:57 PM PDT 24 |
| Finished | Jul 06 08:24:12 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-b29d2c81-1b4c-474a-8132-026b880202b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11863561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.11863561 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.374326313 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 2049713110 ps |
| CPU time | 80.71 seconds |
| Started | Jul 06 08:22:57 PM PDT 24 |
| Finished | Jul 06 08:24:18 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-634d36ca-5e4c-4ecc-8996-8610e67fb0b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374326313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.374326313 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.2480480566 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 35892627718 ps |
| CPU time | 373.4 seconds |
| Started | Jul 06 08:22:56 PM PDT 24 |
| Finished | Jul 06 08:29:10 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-9c6bb046-52c4-4e93-aa77-172c28b37f13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480480566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.2480480566 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.2561091527 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 64537153179 ps |
| CPU time | 1059.69 seconds |
| Started | Jul 06 08:22:59 PM PDT 24 |
| Finished | Jul 06 08:40:39 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-3a6f8869-1a01-4310-b421-3a8e1a5cc993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561091527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.2561091527 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.3991946105 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 136527007 ps |
| CPU time | 15.01 seconds |
| Started | Jul 06 08:22:58 PM PDT 24 |
| Finished | Jul 06 08:23:13 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-3ed8a6ad-dec2-411a-9b82-6d1d83a928d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991946105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.3991946105 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.3648564694 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 2390878268 ps |
| CPU time | 74.34 seconds |
| Started | Jul 06 08:22:59 PM PDT 24 |
| Finished | Jul 06 08:24:13 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-571c16ff-e961-4092-8a99-f4a6989a074f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648564694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.3648564694 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.4230760867 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 53692738 ps |
| CPU time | 7.58 seconds |
| Started | Jul 06 08:22:52 PM PDT 24 |
| Finished | Jul 06 08:23:00 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-4efe6168-a8dd-4f6f-a381-d44dd5c5b622 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230760867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.4230760867 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.3763824549 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 9971963605 ps |
| CPU time | 107.78 seconds |
| Started | Jul 06 08:23:00 PM PDT 24 |
| Finished | Jul 06 08:24:48 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-56694c20-d240-4159-9459-00acd1780712 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763824549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.3763824549 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.2942849037 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 4628101601 ps |
| CPU time | 78.56 seconds |
| Started | Jul 06 08:22:57 PM PDT 24 |
| Finished | Jul 06 08:24:15 PM PDT 24 |
| Peak memory | 574576 kb |
| Host | smart-5dcda7b6-3919-46ae-9eb7-3e6e7fd76ec1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942849037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.2942849037 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.1182500858 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 46242711 ps |
| CPU time | 6.83 seconds |
| Started | Jul 06 08:22:51 PM PDT 24 |
| Finished | Jul 06 08:22:58 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-8a66ea30-d54f-47a2-9e3e-10408bf24739 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182500858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.1182500858 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.2478271151 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 2966369773 ps |
| CPU time | 105.6 seconds |
| Started | Jul 06 08:23:04 PM PDT 24 |
| Finished | Jul 06 08:24:50 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-2fb7bece-fef7-4420-bc12-acbfc473acca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478271151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.2478271151 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.3874974501 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 4465036705 ps |
| CPU time | 342.62 seconds |
| Started | Jul 06 08:23:04 PM PDT 24 |
| Finished | Jul 06 08:28:47 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-bb43c34d-2ac7-4471-a768-363160b95838 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874974501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.3874974501 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.4270731788 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 3912470785 ps |
| CPU time | 374.78 seconds |
| Started | Jul 06 08:23:05 PM PDT 24 |
| Finished | Jul 06 08:29:21 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-89f60171-918a-463c-9ea3-9e69a6b7631c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270731788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.4270731788 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.2715898861 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 9671510493 ps |
| CPU time | 655.53 seconds |
| Started | Jul 06 08:23:04 PM PDT 24 |
| Finished | Jul 06 08:34:00 PM PDT 24 |
| Peak memory | 576928 kb |
| Host | smart-2fc979d0-2726-4f9f-a396-1f7a7061ab3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715898861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.2715898861 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.3151703623 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 272109332 ps |
| CPU time | 30.31 seconds |
| Started | Jul 06 08:22:57 PM PDT 24 |
| Finished | Jul 06 08:23:28 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-2ae775b6-61ac-4e3e-b043-457b1cbebb60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151703623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.3151703623 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.3273180803 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2687755493 ps |
| CPU time | 107.58 seconds |
| Started | Jul 06 08:23:09 PM PDT 24 |
| Finished | Jul 06 08:24:57 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-578760ca-f501-42db-ac63-81ff67e828b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273180803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .3273180803 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.904980872 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 127073472135 ps |
| CPU time | 2131.42 seconds |
| Started | Jul 06 08:23:17 PM PDT 24 |
| Finished | Jul 06 08:58:49 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-d943fd51-c4b8-4582-ab35-62036ec706ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904980872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_d evice_slow_rsp.904980872 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.3460349977 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 545342936 ps |
| CPU time | 23.24 seconds |
| Started | Jul 06 08:23:17 PM PDT 24 |
| Finished | Jul 06 08:23:40 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-88b1c944-2978-41d2-a4a9-643276ed2270 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460349977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.3460349977 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.3455831519 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 929141696 ps |
| CPU time | 30.91 seconds |
| Started | Jul 06 08:23:15 PM PDT 24 |
| Finished | Jul 06 08:23:46 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-50c26422-6294-41a7-8b48-96092c260d05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455831519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.3455831519 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.1427439653 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 1660646788 ps |
| CPU time | 59.06 seconds |
| Started | Jul 06 08:23:04 PM PDT 24 |
| Finished | Jul 06 08:24:03 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-bd96ac19-b746-4a93-bb7e-f3b940e11f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427439653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.1427439653 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.3850066678 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 57815557855 ps |
| CPU time | 634.26 seconds |
| Started | Jul 06 08:23:08 PM PDT 24 |
| Finished | Jul 06 08:33:43 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-7b04f75f-4193-4a0c-a691-028d97fa30c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850066678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.3850066678 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.2624431349 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 62972536109 ps |
| CPU time | 1116.03 seconds |
| Started | Jul 06 08:23:08 PM PDT 24 |
| Finished | Jul 06 08:41:44 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-cd3fdab5-4991-42e2-b152-47341ff15713 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624431349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.2624431349 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.1045730088 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 36228892 ps |
| CPU time | 6.86 seconds |
| Started | Jul 06 08:23:04 PM PDT 24 |
| Finished | Jul 06 08:23:11 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-192261f4-11dc-4751-a20b-9775cfba6fe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045730088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.1045730088 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.2034604251 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 1010908097 ps |
| CPU time | 30.02 seconds |
| Started | Jul 06 08:23:08 PM PDT 24 |
| Finished | Jul 06 08:23:38 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-56fa92fc-9ce5-4c34-bfb3-9acf90eb4bf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034604251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.2034604251 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.2258865229 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 43635955 ps |
| CPU time | 6.37 seconds |
| Started | Jul 06 08:23:04 PM PDT 24 |
| Finished | Jul 06 08:23:11 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-eec3e68d-c1b6-4e5d-b5c1-f230917f0d2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258865229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.2258865229 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.1906430136 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 9053188120 ps |
| CPU time | 99.42 seconds |
| Started | Jul 06 08:23:07 PM PDT 24 |
| Finished | Jul 06 08:24:47 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-b126cbc0-6f0e-43c1-82a2-5cacc95b9ce1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906430136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.1906430136 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.3815656559 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 4797564552 ps |
| CPU time | 82.62 seconds |
| Started | Jul 06 08:23:04 PM PDT 24 |
| Finished | Jul 06 08:24:27 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-b0ffe8dd-f8b9-4c21-b39a-c3d7e14b989d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815656559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.3815656559 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.474796359 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 43336719 ps |
| CPU time | 6.57 seconds |
| Started | Jul 06 08:23:07 PM PDT 24 |
| Finished | Jul 06 08:23:14 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-4811bcc7-0250-49f2-bc68-bcee92586aaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474796359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delays .474796359 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.1520287317 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 3960339602 ps |
| CPU time | 155.17 seconds |
| Started | Jul 06 08:23:18 PM PDT 24 |
| Finished | Jul 06 08:25:53 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-568e73d9-e35c-465a-a00f-6753ee878a17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520287317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.1520287317 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.557378258 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 2697422530 ps |
| CPU time | 96.99 seconds |
| Started | Jul 06 08:23:17 PM PDT 24 |
| Finished | Jul 06 08:24:54 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-7001d55c-8533-4d36-a5b2-cb3aa0ee65b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557378258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.557378258 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.3841442295 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 8103436551 ps |
| CPU time | 428.54 seconds |
| Started | Jul 06 08:23:20 PM PDT 24 |
| Finished | Jul 06 08:30:29 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-85205091-8685-4285-af23-29b55f8b727c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841442295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.3841442295 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2471606109 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 7970676141 ps |
| CPU time | 345.84 seconds |
| Started | Jul 06 08:23:19 PM PDT 24 |
| Finished | Jul 06 08:29:05 PM PDT 24 |
| Peak memory | 576828 kb |
| Host | smart-82b932b6-ddee-4a67-9452-0aac5c811f94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471606109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.2471606109 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.772945478 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 109543870 ps |
| CPU time | 16.71 seconds |
| Started | Jul 06 08:23:09 PM PDT 24 |
| Finished | Jul 06 08:23:26 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-70bd7952-e1fa-41cf-9d27-4c76be5c1796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772945478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.772945478 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.3565581773 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 394070659 ps |
| CPU time | 43.88 seconds |
| Started | Jul 06 08:23:23 PM PDT 24 |
| Finished | Jul 06 08:24:07 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-d6a73793-9660-41e0-b11f-a68cdb1588df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565581773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .3565581773 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.3181372493 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 87585619597 ps |
| CPU time | 1516.61 seconds |
| Started | Jul 06 08:23:21 PM PDT 24 |
| Finished | Jul 06 08:48:38 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-4643c636-247d-4c00-b689-e5c8f0ebf574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181372493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.3181372493 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.2283284267 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 318912351 ps |
| CPU time | 36.34 seconds |
| Started | Jul 06 08:23:22 PM PDT 24 |
| Finished | Jul 06 08:23:59 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-4b561528-b3a2-493e-aa3a-fd5b1713995a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283284267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.2283284267 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.263768894 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 588334972 ps |
| CPU time | 57.09 seconds |
| Started | Jul 06 08:23:21 PM PDT 24 |
| Finished | Jul 06 08:24:19 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-3b3fdb2c-dd87-47fc-bb59-132f91ae3c23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263768894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.263768894 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.2974244622 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 535755707 ps |
| CPU time | 40.66 seconds |
| Started | Jul 06 08:23:25 PM PDT 24 |
| Finished | Jul 06 08:24:06 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-4041813c-615d-4422-94c1-5a6bb88689cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974244622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.2974244622 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.3835776376 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 58004605250 ps |
| CPU time | 640.48 seconds |
| Started | Jul 06 08:23:22 PM PDT 24 |
| Finished | Jul 06 08:34:03 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-2ff2e71f-f75a-48fc-9b2b-99d12d1898d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835776376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.3835776376 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.116788991 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 36979428771 ps |
| CPU time | 638.56 seconds |
| Started | Jul 06 08:23:21 PM PDT 24 |
| Finished | Jul 06 08:34:00 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-89bf76e9-97c0-4763-9bba-8e7d008f633b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116788991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.116788991 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.963788045 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 301509556 ps |
| CPU time | 27.4 seconds |
| Started | Jul 06 08:23:21 PM PDT 24 |
| Finished | Jul 06 08:23:48 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-95acb4e9-3809-4314-95e4-43be3fe5a8de |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963788045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_dela ys.963788045 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.73310722 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 123396637 ps |
| CPU time | 12.56 seconds |
| Started | Jul 06 08:23:21 PM PDT 24 |
| Finished | Jul 06 08:23:34 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-13fd6da2-1e5b-483b-89d4-b0f75dec59cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73310722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.73310722 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.3256228130 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 165519883 ps |
| CPU time | 8.5 seconds |
| Started | Jul 06 08:23:19 PM PDT 24 |
| Finished | Jul 06 08:23:28 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-83e81e55-129b-443d-a1bc-a73d5c37635f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256228130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.3256228130 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.2937532484 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 10506103479 ps |
| CPU time | 117.7 seconds |
| Started | Jul 06 08:23:17 PM PDT 24 |
| Finished | Jul 06 08:25:15 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-874cd438-b790-4f12-9e89-370e5a888c89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937532484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.2937532484 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.889468487 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 5596351086 ps |
| CPU time | 102.19 seconds |
| Started | Jul 06 08:23:18 PM PDT 24 |
| Finished | Jul 06 08:25:01 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-adfe67ee-783d-4489-a1fd-90c1002811fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889468487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.889468487 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.3970338066 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 58488975 ps |
| CPU time | 7.14 seconds |
| Started | Jul 06 08:23:17 PM PDT 24 |
| Finished | Jul 06 08:23:25 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-7e82197f-07b5-4955-826d-d06dffbb8686 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970338066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.3970338066 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.3486533946 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 2040426519 ps |
| CPU time | 147.84 seconds |
| Started | Jul 06 08:23:20 PM PDT 24 |
| Finished | Jul 06 08:25:48 PM PDT 24 |
| Peak memory | 576924 kb |
| Host | smart-1ae033a8-fd91-4ea2-b4e9-9e24093a7c32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486533946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.3486533946 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.2312731657 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 975967322 ps |
| CPU time | 37.88 seconds |
| Started | Jul 06 08:23:22 PM PDT 24 |
| Finished | Jul 06 08:24:00 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-136a35a5-b7fd-4bda-91a4-e73a405ad5c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312731657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.2312731657 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3604417437 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 316877523 ps |
| CPU time | 141.73 seconds |
| Started | Jul 06 08:23:25 PM PDT 24 |
| Finished | Jul 06 08:25:47 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-f2f616d0-d7aa-4461-828d-365f9797e98d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604417437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.3604417437 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.3341209647 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 470945028 ps |
| CPU time | 142.6 seconds |
| Started | Jul 06 08:23:27 PM PDT 24 |
| Finished | Jul 06 08:25:50 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-5e0a0bc2-9cf0-4aaf-a33d-1ce33802730c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341209647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.3341209647 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.2508765251 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 335714357 ps |
| CPU time | 18.11 seconds |
| Started | Jul 06 08:23:24 PM PDT 24 |
| Finished | Jul 06 08:23:43 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-ba5a3678-bf5a-4c95-8058-3d679f2140c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508765251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.2508765251 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.1122208611 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 750315875 ps |
| CPU time | 37.16 seconds |
| Started | Jul 06 08:23:33 PM PDT 24 |
| Finished | Jul 06 08:24:11 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-55ea8587-68a8-402e-9c7c-715c306ca0b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122208611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .1122208611 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.711293446 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 89262718589 ps |
| CPU time | 1500.03 seconds |
| Started | Jul 06 08:23:34 PM PDT 24 |
| Finished | Jul 06 08:48:35 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-d73940c2-c974-49ec-b06d-aa35a506d251 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711293446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_d evice_slow_rsp.711293446 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.622038905 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 80416757 ps |
| CPU time | 6.45 seconds |
| Started | Jul 06 08:23:32 PM PDT 24 |
| Finished | Jul 06 08:23:39 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-b2445e86-fee3-4433-ad74-1bb937475ceb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622038905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_addr .622038905 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.3356859501 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 1321040651 ps |
| CPU time | 51.42 seconds |
| Started | Jul 06 08:23:32 PM PDT 24 |
| Finished | Jul 06 08:24:24 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-784b571e-9011-4020-b4db-ab6de505f8e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356859501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.3356859501 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.3026593641 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 1386755364 ps |
| CPU time | 46.51 seconds |
| Started | Jul 06 08:23:36 PM PDT 24 |
| Finished | Jul 06 08:24:23 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-1365489b-389a-493a-abea-e0652ff7260c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026593641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.3026593641 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.972715375 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 98775198739 ps |
| CPU time | 987.35 seconds |
| Started | Jul 06 08:23:37 PM PDT 24 |
| Finished | Jul 06 08:40:05 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-e781ee51-7116-4594-ab6f-58e5acf04278 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972715375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.972715375 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.4129975222 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 35732106806 ps |
| CPU time | 639.84 seconds |
| Started | Jul 06 08:23:33 PM PDT 24 |
| Finished | Jul 06 08:34:13 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-6b657a6a-13d2-4ecd-a5ad-b3c1f1f93605 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129975222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.4129975222 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.2952364091 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 468205629 ps |
| CPU time | 42.69 seconds |
| Started | Jul 06 08:23:30 PM PDT 24 |
| Finished | Jul 06 08:24:13 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-078c684b-50f2-493a-aab3-42605674a524 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952364091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.2952364091 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.4176216750 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 524922217 ps |
| CPU time | 41.99 seconds |
| Started | Jul 06 08:23:36 PM PDT 24 |
| Finished | Jul 06 08:24:18 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-031cd920-c172-472c-b458-8f306bc86af9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176216750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.4176216750 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.436114090 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 222066552 ps |
| CPU time | 10.48 seconds |
| Started | Jul 06 08:23:28 PM PDT 24 |
| Finished | Jul 06 08:23:38 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-a38a54d3-4ded-40cc-aecc-3c23a5a33fce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436114090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.436114090 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.796545560 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 8123433317 ps |
| CPU time | 91.04 seconds |
| Started | Jul 06 08:23:26 PM PDT 24 |
| Finished | Jul 06 08:24:57 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-a664c719-00d6-40d2-abcd-38ba5054af3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796545560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.796545560 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.2488855407 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 4883980982 ps |
| CPU time | 84.29 seconds |
| Started | Jul 06 08:23:27 PM PDT 24 |
| Finished | Jul 06 08:24:52 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-dc9ca254-5d0e-45cf-9996-d640ac8e0a0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488855407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.2488855407 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.3062347174 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 42237593 ps |
| CPU time | 6.82 seconds |
| Started | Jul 06 08:23:27 PM PDT 24 |
| Finished | Jul 06 08:23:34 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-18a87580-bf45-486a-9a06-d8c1e5b07a50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062347174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.3062347174 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.3045246936 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 4731260384 ps |
| CPU time | 172.52 seconds |
| Started | Jul 06 08:23:33 PM PDT 24 |
| Finished | Jul 06 08:26:25 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-9d2de917-e525-4ef8-a37d-f583c0eb679d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045246936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.3045246936 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.4146865397 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 7637204010 ps |
| CPU time | 276.76 seconds |
| Started | Jul 06 08:23:36 PM PDT 24 |
| Finished | Jul 06 08:28:14 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-79a362c4-0299-443d-bfb4-c7683774b340 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146865397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.4146865397 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.3612194448 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 3792428659 ps |
| CPU time | 413.26 seconds |
| Started | Jul 06 08:23:31 PM PDT 24 |
| Finished | Jul 06 08:30:24 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-8a6dcdb4-1686-473e-8597-a148176b2116 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612194448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.3612194448 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.3198741751 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 8630022491 ps |
| CPU time | 431.87 seconds |
| Started | Jul 06 08:23:36 PM PDT 24 |
| Finished | Jul 06 08:30:48 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-7f4db77f-0073-4030-ab39-fd7ac3c519b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198741751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.3198741751 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.1673467027 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 222486816 ps |
| CPU time | 14.42 seconds |
| Started | Jul 06 08:23:32 PM PDT 24 |
| Finished | Jul 06 08:23:47 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-1cd1a745-315c-4647-9fd5-79b4a6cfe7ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673467027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.1673467027 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.3478050716 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 101643360 ps |
| CPU time | 10.23 seconds |
| Started | Jul 06 08:23:38 PM PDT 24 |
| Finished | Jul 06 08:23:49 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-4cf76b82-c3d5-461b-a21a-504b80cc87ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478050716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .3478050716 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2419440733 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 68141801781 ps |
| CPU time | 1159.97 seconds |
| Started | Jul 06 08:23:40 PM PDT 24 |
| Finished | Jul 06 08:43:00 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-d982f5ab-4574-4b86-b65d-b9e36bad76e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419440733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.2419440733 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.4227023170 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 246652898 ps |
| CPU time | 29.94 seconds |
| Started | Jul 06 08:23:53 PM PDT 24 |
| Finished | Jul 06 08:24:23 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-61e8d4b3-813b-4184-8810-7b41637b245c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227023170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.4227023170 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.1290302106 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 447680771 ps |
| CPU time | 37.56 seconds |
| Started | Jul 06 08:23:41 PM PDT 24 |
| Finished | Jul 06 08:24:19 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-10ea52d6-f067-4518-9b39-b644a27c3782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290302106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.1290302106 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.1080306767 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 1619786496 ps |
| CPU time | 63.11 seconds |
| Started | Jul 06 08:23:42 PM PDT 24 |
| Finished | Jul 06 08:24:46 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-dec434c8-abc0-49e7-b45f-5fad08557bd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080306767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.1080306767 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.3625301820 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 5141834389 ps |
| CPU time | 56.27 seconds |
| Started | Jul 06 08:23:38 PM PDT 24 |
| Finished | Jul 06 08:24:34 PM PDT 24 |
| Peak memory | 574632 kb |
| Host | smart-bc395e4d-bfc6-4cb9-a127-dd4c0e57cb5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625301820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.3625301820 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.2565332887 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 46168223424 ps |
| CPU time | 787.4 seconds |
| Started | Jul 06 08:23:39 PM PDT 24 |
| Finished | Jul 06 08:36:47 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-590f1584-dad2-45ab-a57d-fab52a9683e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565332887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.2565332887 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.3501038710 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 526372157 ps |
| CPU time | 44.74 seconds |
| Started | Jul 06 08:23:38 PM PDT 24 |
| Finished | Jul 06 08:24:24 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-7d6ad8e6-418a-4737-ab5e-51ee8db5b7a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501038710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.3501038710 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.2426162979 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 2340877162 ps |
| CPU time | 74.57 seconds |
| Started | Jul 06 08:23:42 PM PDT 24 |
| Finished | Jul 06 08:24:57 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-6ee43adf-3d16-4f6d-a127-1917a181a940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426162979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.2426162979 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.770830316 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 45914368 ps |
| CPU time | 5.94 seconds |
| Started | Jul 06 08:23:36 PM PDT 24 |
| Finished | Jul 06 08:23:43 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-9562811e-5621-47e5-ac09-86de1e541895 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770830316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.770830316 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.2668246358 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 9581279580 ps |
| CPU time | 103.47 seconds |
| Started | Jul 06 08:23:37 PM PDT 24 |
| Finished | Jul 06 08:25:21 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-42e1d28a-427b-4a2d-b16d-9f2f0895835d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668246358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.2668246358 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.2445353178 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 4300974764 ps |
| CPU time | 73.8 seconds |
| Started | Jul 06 08:23:38 PM PDT 24 |
| Finished | Jul 06 08:24:52 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-92d3a72f-c9c6-421f-9c43-9729ef2947a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445353178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.2445353178 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.1262367778 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 49731972 ps |
| CPU time | 6.18 seconds |
| Started | Jul 06 08:23:37 PM PDT 24 |
| Finished | Jul 06 08:23:43 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-055d72fc-3a4f-484d-a61d-182917eefe41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262367778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.1262367778 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.2275127561 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 1222651039 ps |
| CPU time | 101.1 seconds |
| Started | Jul 06 08:23:46 PM PDT 24 |
| Finished | Jul 06 08:25:28 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-cd163fad-f90b-4eb3-81c2-989d51d933b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275127561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.2275127561 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.3650178125 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 3839495289 ps |
| CPU time | 329.85 seconds |
| Started | Jul 06 08:23:52 PM PDT 24 |
| Finished | Jul 06 08:29:22 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-ce3ca934-ac33-4dfe-ae0a-d13e691920d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650178125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.3650178125 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.3093628517 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 496171135 ps |
| CPU time | 243.72 seconds |
| Started | Jul 06 08:23:47 PM PDT 24 |
| Finished | Jul 06 08:27:51 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-8b52adc7-34e1-4379-965e-e015e2a4d08f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093628517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.3093628517 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.466587899 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 632026218 ps |
| CPU time | 147.07 seconds |
| Started | Jul 06 08:23:44 PM PDT 24 |
| Finished | Jul 06 08:26:12 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-fafa7bed-f320-44a8-8600-21ba9a819feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466587899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_reset_error.466587899 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.3630963629 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 1329118610 ps |
| CPU time | 50.48 seconds |
| Started | Jul 06 08:23:44 PM PDT 24 |
| Finished | Jul 06 08:24:35 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-d02a5f41-e65e-4b6e-853a-0870f07c281e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630963629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.3630963629 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.2256052907 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 424424448 ps |
| CPU time | 43.18 seconds |
| Started | Jul 06 08:23:44 PM PDT 24 |
| Finished | Jul 06 08:24:27 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-6ec72ac1-3307-4d3c-a230-6c609ce4ecd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256052907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .2256052907 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.3214126078 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 539480540 ps |
| CPU time | 24.01 seconds |
| Started | Jul 06 08:23:49 PM PDT 24 |
| Finished | Jul 06 08:24:14 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-a7d16799-67ab-449a-ab03-078bd9db4a28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214126078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.3214126078 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.1605910081 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 1167310117 ps |
| CPU time | 44.16 seconds |
| Started | Jul 06 08:23:53 PM PDT 24 |
| Finished | Jul 06 08:24:38 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-38d71e64-2216-43cf-b591-640b2ff5f9f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605910081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.1605910081 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.2806151703 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 361077980 ps |
| CPU time | 32.2 seconds |
| Started | Jul 06 08:23:44 PM PDT 24 |
| Finished | Jul 06 08:24:17 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-078d1145-2a23-41b5-8de2-d9b19c3a68a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806151703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.2806151703 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.3911639772 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 67471929410 ps |
| CPU time | 690.01 seconds |
| Started | Jul 06 08:23:53 PM PDT 24 |
| Finished | Jul 06 08:35:23 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-78068e51-6a06-4fb6-9cea-4cee7935c3a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911639772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.3911639772 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.746892466 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 56050371807 ps |
| CPU time | 941.55 seconds |
| Started | Jul 06 08:23:52 PM PDT 24 |
| Finished | Jul 06 08:39:34 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-124216ae-bf49-4fe9-98ec-15baecead92e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746892466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.746892466 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.1909076096 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 294419344 ps |
| CPU time | 25.8 seconds |
| Started | Jul 06 08:23:46 PM PDT 24 |
| Finished | Jul 06 08:24:12 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-8600b1a0-13f6-43d3-9cab-fc5abaaa26e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909076096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.1909076096 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.3908829679 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1712625787 ps |
| CPU time | 56.18 seconds |
| Started | Jul 06 08:23:45 PM PDT 24 |
| Finished | Jul 06 08:24:42 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-8abe0560-25aa-46cb-a9a7-250b6c91dff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908829679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.3908829679 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.2817570470 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 38377266 ps |
| CPU time | 5.96 seconds |
| Started | Jul 06 08:23:46 PM PDT 24 |
| Finished | Jul 06 08:23:52 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-6162a737-5e53-4f58-9ba2-e42ff7af337f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817570470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.2817570470 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.3934671943 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 8133312554 ps |
| CPU time | 82.25 seconds |
| Started | Jul 06 08:23:45 PM PDT 24 |
| Finished | Jul 06 08:25:07 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-6d582105-3942-4fcd-94fe-4ff40a841a94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934671943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.3934671943 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.4180660260 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 4974840297 ps |
| CPU time | 86.09 seconds |
| Started | Jul 06 08:23:47 PM PDT 24 |
| Finished | Jul 06 08:25:14 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-dace10da-024b-46e4-a132-26a24a2dbcaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180660260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.4180660260 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.1214387286 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 50472785 ps |
| CPU time | 6.68 seconds |
| Started | Jul 06 08:23:44 PM PDT 24 |
| Finished | Jul 06 08:23:52 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-095f4b1e-f67d-4916-8f58-8fe3888af1d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214387286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.1214387286 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.523191390 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 17618077219 ps |
| CPU time | 672.7 seconds |
| Started | Jul 06 08:23:49 PM PDT 24 |
| Finished | Jul 06 08:35:03 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-2938a6ca-1f8c-4f3b-90fc-850c0bec6b27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523191390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.523191390 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.3911068405 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 3209263020 ps |
| CPU time | 240.74 seconds |
| Started | Jul 06 08:23:52 PM PDT 24 |
| Finished | Jul 06 08:27:53 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-49bf9407-3d8b-41ca-8daf-90383e2645a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911068405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.3911068405 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1426941161 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 3460359465 ps |
| CPU time | 331.73 seconds |
| Started | Jul 06 08:23:50 PM PDT 24 |
| Finished | Jul 06 08:29:23 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-3ec07252-8570-48a3-b9bf-cc64c88de595 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426941161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.1426941161 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.2128896195 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 2072216041 ps |
| CPU time | 269.71 seconds |
| Started | Jul 06 08:23:48 PM PDT 24 |
| Finished | Jul 06 08:28:18 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-e5ae566e-d4c3-400b-9609-a3f41a69e423 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128896195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.2128896195 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.2624633304 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 315587709 ps |
| CPU time | 40.43 seconds |
| Started | Jul 06 08:23:53 PM PDT 24 |
| Finished | Jul 06 08:24:34 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-fb9b7c68-bf9c-4507-a8dc-356486ea4443 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624633304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.2624633304 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.575868992 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 1018667081 ps |
| CPU time | 50.64 seconds |
| Started | Jul 06 08:23:55 PM PDT 24 |
| Finished | Jul 06 08:24:46 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-27396b87-05de-4013-b540-7545dadf7f52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575868992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device. 575868992 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.4224570151 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 40425985134 ps |
| CPU time | 667.92 seconds |
| Started | Jul 06 08:23:54 PM PDT 24 |
| Finished | Jul 06 08:35:03 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-55e6e6fd-dc5f-40f0-a134-a6c0b2b6f9ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224570151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.4224570151 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.4144509824 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 35802679 ps |
| CPU time | 6.86 seconds |
| Started | Jul 06 08:23:56 PM PDT 24 |
| Finished | Jul 06 08:24:03 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-c3b2158a-21ba-49d8-8710-e01933d8de8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144509824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.4144509824 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.1585624310 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 198515187 ps |
| CPU time | 10.74 seconds |
| Started | Jul 06 08:23:56 PM PDT 24 |
| Finished | Jul 06 08:24:07 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-f0e2baa8-6b14-4c76-863d-6de09db694f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585624310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.1585624310 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.1721599668 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 111357333 ps |
| CPU time | 7.51 seconds |
| Started | Jul 06 08:23:58 PM PDT 24 |
| Finished | Jul 06 08:24:06 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-d524c5ca-bc1c-46ea-ba4c-a6313025f8c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721599668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.1721599668 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.2733997911 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 75266364477 ps |
| CPU time | 818.31 seconds |
| Started | Jul 06 08:23:57 PM PDT 24 |
| Finished | Jul 06 08:37:36 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-61da174b-d85a-46d0-8aa3-07c4c5621323 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733997911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.2733997911 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.2850080868 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 27831097871 ps |
| CPU time | 472.88 seconds |
| Started | Jul 06 08:23:57 PM PDT 24 |
| Finished | Jul 06 08:31:50 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-2480229f-1f9b-46c8-8d6e-451292790468 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850080868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.2850080868 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.1525899841 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 352423609 ps |
| CPU time | 34.93 seconds |
| Started | Jul 06 08:23:59 PM PDT 24 |
| Finished | Jul 06 08:24:34 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-d5d76a42-31c3-4dbf-960d-1315ef07b5c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525899841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.1525899841 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.4126503084 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 856222258 ps |
| CPU time | 28.55 seconds |
| Started | Jul 06 08:23:55 PM PDT 24 |
| Finished | Jul 06 08:24:24 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-42217923-0818-46d7-a79a-1edeea8e8751 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126503084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.4126503084 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.2257376117 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 211248566 ps |
| CPU time | 10.21 seconds |
| Started | Jul 06 08:23:50 PM PDT 24 |
| Finished | Jul 06 08:24:00 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-07a25f72-9928-416f-a5b1-714215ccc683 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257376117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.2257376117 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.3892636789 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 7573187220 ps |
| CPU time | 81.47 seconds |
| Started | Jul 06 08:23:49 PM PDT 24 |
| Finished | Jul 06 08:25:11 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-6fde169f-63e6-4915-9d58-dd9d1f9deff4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892636789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.3892636789 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.75517055 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 3957525588 ps |
| CPU time | 69.01 seconds |
| Started | Jul 06 08:23:54 PM PDT 24 |
| Finished | Jul 06 08:25:04 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-a456d66a-0a13-49d8-9058-989f32299dcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75517055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.75517055 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2336449286 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 48270778 ps |
| CPU time | 6.44 seconds |
| Started | Jul 06 08:23:51 PM PDT 24 |
| Finished | Jul 06 08:23:57 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-54e2e661-787d-4025-9913-86a2eefe3dcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336449286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.2336449286 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.970355963 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 1240120602 ps |
| CPU time | 87.55 seconds |
| Started | Jul 06 08:23:55 PM PDT 24 |
| Finished | Jul 06 08:25:22 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-8011050d-2e75-4509-90d7-d058d0c9c670 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970355963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.970355963 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.2714969586 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 8550969028 ps |
| CPU time | 284.68 seconds |
| Started | Jul 06 08:24:01 PM PDT 24 |
| Finished | Jul 06 08:28:46 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-e621171a-7524-47d0-8fd9-be00c96bd104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714969586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.2714969586 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3722517548 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 344854515 ps |
| CPU time | 138.44 seconds |
| Started | Jul 06 08:23:56 PM PDT 24 |
| Finished | Jul 06 08:26:15 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-25b4a4b6-5ded-4e45-b98d-4115ad598462 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722517548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.3722517548 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.723790223 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 152250394 ps |
| CPU time | 59.22 seconds |
| Started | Jul 06 08:24:00 PM PDT 24 |
| Finished | Jul 06 08:25:00 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-b9a72ecb-d6f5-4944-bfd0-93966c7a76cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723790223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_reset_error.723790223 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.3754180517 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 1336341980 ps |
| CPU time | 55.83 seconds |
| Started | Jul 06 08:23:55 PM PDT 24 |
| Finished | Jul 06 08:24:51 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-09362931-6d47-422d-9f8b-8f0603b43453 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754180517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.3754180517 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.1290011714 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 1598748753 ps |
| CPU time | 79.54 seconds |
| Started | Jul 06 08:24:08 PM PDT 24 |
| Finished | Jul 06 08:25:28 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-f3d38f40-bfa3-4648-bcc4-050ee15eb68b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290011714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .1290011714 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.2728769237 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 17813806480 ps |
| CPU time | 324.29 seconds |
| Started | Jul 06 08:24:11 PM PDT 24 |
| Finished | Jul 06 08:29:36 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-ec27d93f-312f-4064-acf7-cd4081e8395f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728769237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.2728769237 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.3484481952 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 35183564 ps |
| CPU time | 7.02 seconds |
| Started | Jul 06 08:24:06 PM PDT 24 |
| Finished | Jul 06 08:24:14 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-9b88e6e1-0904-4068-b3f3-0860e40b0e31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484481952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.3484481952 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.586488185 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 1769219740 ps |
| CPU time | 63.85 seconds |
| Started | Jul 06 08:24:06 PM PDT 24 |
| Finished | Jul 06 08:25:10 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-707a7dd8-4a0f-46a5-b50d-1a90a44752e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586488185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.586488185 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.2705683899 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 1048215640 ps |
| CPU time | 37.87 seconds |
| Started | Jul 06 08:24:06 PM PDT 24 |
| Finished | Jul 06 08:24:45 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-50d64b68-a586-468a-b4bd-0184da4a61ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705683899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.2705683899 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.2094914550 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 69579560128 ps |
| CPU time | 722.68 seconds |
| Started | Jul 06 08:24:11 PM PDT 24 |
| Finished | Jul 06 08:36:14 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-2c1af907-eda2-4981-8474-2c9cffc73a3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094914550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.2094914550 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.4232601691 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 54126418636 ps |
| CPU time | 934.59 seconds |
| Started | Jul 06 08:24:11 PM PDT 24 |
| Finished | Jul 06 08:39:46 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-5b651f8e-a3c7-4012-b5fe-38e98b970e77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232601691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.4232601691 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.4189235913 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 534311366 ps |
| CPU time | 42.09 seconds |
| Started | Jul 06 08:24:07 PM PDT 24 |
| Finished | Jul 06 08:24:49 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-b86d5202-117e-4a43-b7e3-b6b3862882e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189235913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.4189235913 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.1090853317 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 1017958554 ps |
| CPU time | 35.4 seconds |
| Started | Jul 06 08:24:08 PM PDT 24 |
| Finished | Jul 06 08:24:44 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-e659e444-dd39-46ae-94b2-b1a67d0c7c4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090853317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.1090853317 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.4015855898 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 183576947 ps |
| CPU time | 8.66 seconds |
| Started | Jul 06 08:24:01 PM PDT 24 |
| Finished | Jul 06 08:24:10 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-0eda1663-0c64-45c4-94cc-26f94a8ea353 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015855898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.4015855898 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.1609676922 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 8907424252 ps |
| CPU time | 87.24 seconds |
| Started | Jul 06 08:25:04 PM PDT 24 |
| Finished | Jul 06 08:26:31 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-9fa5de19-34c8-4020-b387-a83dda48783e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609676922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.1609676922 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.1532468685 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 3613993374 ps |
| CPU time | 60.94 seconds |
| Started | Jul 06 08:24:07 PM PDT 24 |
| Finished | Jul 06 08:25:09 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-982ff383-d511-44ce-932c-86de34be72c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532468685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.1532468685 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.2596436335 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 53368837 ps |
| CPU time | 6.66 seconds |
| Started | Jul 06 08:24:08 PM PDT 24 |
| Finished | Jul 06 08:24:15 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-1086e648-c8a1-4e01-910b-7dc8b67c7acc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596436335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.2596436335 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.2685231530 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 7311976192 ps |
| CPU time | 266.24 seconds |
| Started | Jul 06 08:24:14 PM PDT 24 |
| Finished | Jul 06 08:28:41 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-2b4d425c-9c11-4939-8100-ce3ed7bbc3d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685231530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.2685231530 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.3957195633 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2650529872 ps |
| CPU time | 201.18 seconds |
| Started | Jul 06 08:24:14 PM PDT 24 |
| Finished | Jul 06 08:27:35 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-a21b8770-dece-4792-82d5-e4a07b57357c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957195633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.3957195633 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.2715513765 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 6776211313 ps |
| CPU time | 579.21 seconds |
| Started | Jul 06 08:24:12 PM PDT 24 |
| Finished | Jul 06 08:33:52 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-35409d9b-a7ed-4011-9f66-84c82cdc4d4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715513765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.2715513765 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.606447042 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 165655569 ps |
| CPU time | 55.61 seconds |
| Started | Jul 06 08:24:12 PM PDT 24 |
| Finished | Jul 06 08:25:08 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-2032fed9-94b9-422e-b9fd-64475ce7bc50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606447042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_reset_error.606447042 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.2978309463 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 369932491 ps |
| CPU time | 19.23 seconds |
| Started | Jul 06 08:24:11 PM PDT 24 |
| Finished | Jul 06 08:24:31 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-758814f9-ff5e-40df-918f-6a5b64fc902e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978309463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.2978309463 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.3427181341 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 13563046346 ps |
| CPU time | 1864.44 seconds |
| Started | Jul 06 07:21:08 PM PDT 24 |
| Finished | Jul 06 07:52:14 PM PDT 24 |
| Peak memory | 607500 kb |
| Host | smart-a6663a6b-4b99-47b5-a995-f078ba2f5416 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427181341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.3 427181341 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2611601198 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4887949150 ps |
| CPU time | 539.98 seconds |
| Started | Jul 06 07:36:26 PM PDT 24 |
| Finished | Jul 06 07:45:26 PM PDT 24 |
| Peak memory | 623984 kb |
| Host | smart-7e71c4cd-46b6-41a2-ab88-65de0a3fc6db |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 611601198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.2611601198 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.1808281283 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 3208300550 ps |
| CPU time | 309.95 seconds |
| Started | Jul 06 07:28:45 PM PDT 24 |
| Finished | Jul 06 07:33:55 PM PDT 24 |
| Peak memory | 610356 kb |
| Host | smart-2fd40aba-f33c-474a-a79f-75ede2b234ea |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1808281283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.1808281283 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.2436131941 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 3195544160 ps |
| CPU time | 220.27 seconds |
| Started | Jul 06 07:28:35 PM PDT 24 |
| Finished | Jul 06 07:32:16 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-167bda20-f051-4535-b491-72c92718245b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436131941 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.2436131941 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1621113445 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2966958720 ps |
| CPU time | 232.36 seconds |
| Started | Jul 06 07:31:03 PM PDT 24 |
| Finished | Jul 06 07:34:57 PM PDT 24 |
| Peak memory | 608564 kb |
| Host | smart-88fd70fe-fedb-4a1b-9eb7-a55b3d4b8e10 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621 113445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.1621113445 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2143823114 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 3393203168 ps |
| CPU time | 355.39 seconds |
| Started | Jul 06 07:30:51 PM PDT 24 |
| Finished | Jul 06 07:36:47 PM PDT 24 |
| Peak memory | 608872 kb |
| Host | smart-02a77c71-f849-4ff2-b7bc-f3ea6a56bfec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143823114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.2143823114 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.3494416944 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 3150697528 ps |
| CPU time | 358.42 seconds |
| Started | Jul 06 07:29:59 PM PDT 24 |
| Finished | Jul 06 07:35:58 PM PDT 24 |
| Peak memory | 608708 kb |
| Host | smart-a11188a2-a3a4-43df-9976-b26500679f28 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494416944 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.3494416944 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.410795221 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 2119179440 ps |
| CPU time | 256.69 seconds |
| Started | Jul 06 07:28:27 PM PDT 24 |
| Finished | Jul 06 07:32:44 PM PDT 24 |
| Peak memory | 610216 kb |
| Host | smart-f777f94e-41b1-47da-843e-d763159ba2a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410795221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.410795221 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.3062338833 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 3359357692 ps |
| CPU time | 323.3 seconds |
| Started | Jul 06 07:31:25 PM PDT 24 |
| Finished | Jul 06 07:36:49 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-ac7676f5-9483-4d78-94e3-71fdc4d05e73 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062338833 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.3062338833 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.326150455 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 3374599864 ps |
| CPU time | 240.29 seconds |
| Started | Jul 06 07:31:33 PM PDT 24 |
| Finished | Jul 06 07:35:34 PM PDT 24 |
| Peak memory | 608852 kb |
| Host | smart-1e2d4974-aec3-4423-a7ad-3aa93fea493e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326150455 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.326150455 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.362969343 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 4199980786 ps |
| CPU time | 459.87 seconds |
| Started | Jul 06 07:30:28 PM PDT 24 |
| Finished | Jul 06 07:38:09 PM PDT 24 |
| Peak memory | 623676 kb |
| Host | smart-c5a9a0b3-f35c-482a-93d2-f7927cce6f5d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=362969343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.362969343 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.843988433 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 7905164396 ps |
| CPU time | 1868.76 seconds |
| Started | Jul 06 07:28:18 PM PDT 24 |
| Finished | Jul 06 07:59:28 PM PDT 24 |
| Peak memory | 609028 kb |
| Host | smart-7ea11da7-192f-4433-a8ed-0fc0bd5f4a7f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843988433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_toggle.843988433 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3426803081 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 8123424020 ps |
| CPU time | 1430.56 seconds |
| Started | Jul 06 07:33:44 PM PDT 24 |
| Finished | Jul 06 07:57:35 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-f4890035-5d6e-4da3-977b-636baab39593 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3426803081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.3426803081 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.4174357522 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 4671175100 ps |
| CPU time | 464.26 seconds |
| Started | Jul 06 07:30:34 PM PDT 24 |
| Finished | Jul 06 07:38:19 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-76131b95-c8e4-4498-9013-6977b9ba2916 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4174357522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.4174357522 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.286088269 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 255776656050 ps |
| CPU time | 13572.4 seconds |
| Started | Jul 06 07:28:17 PM PDT 24 |
| Finished | Jul 06 11:14:32 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-1ecef177-a722-43f7-bdc7-986cdc8c5afe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=286088269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.286088269 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.3632844406 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 4239505836 ps |
| CPU time | 378.83 seconds |
| Started | Jul 06 07:36:05 PM PDT 24 |
| Finished | Jul 06 07:42:25 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-8f68b921-616e-4fc3-a692-d66ff90c75a1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632844406 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.3632844406 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2233846981 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 7345145580 ps |
| CPU time | 508.85 seconds |
| Started | Jul 06 07:29:13 PM PDT 24 |
| Finished | Jul 06 07:37:42 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-629d8b96-09c3-4879-80d3-21345f9897e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2233846981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2233846981 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.538393213 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 3155642152 ps |
| CPU time | 282.21 seconds |
| Started | Jul 06 07:30:58 PM PDT 24 |
| Finished | Jul 06 07:35:41 PM PDT 24 |
| Peak memory | 608448 kb |
| Host | smart-fb6dbfcf-b876-4384-a702-adadc9d682c3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538393213 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_aon_timer_smoketest.538393213 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1590902913 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 10552432058 ps |
| CPU time | 1029.72 seconds |
| Started | Jul 06 07:33:23 PM PDT 24 |
| Finished | Jul 06 07:50:34 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-d46aee3c-df95-4403-8900-f169d9da0ec0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1590902913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.1590902913 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2710013850 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 5213522520 ps |
| CPU time | 631.97 seconds |
| Started | Jul 06 07:30:02 PM PDT 24 |
| Finished | Jul 06 07:40:35 PM PDT 24 |
| Peak memory | 609488 kb |
| Host | smart-f13bddfe-8f10-42b7-8ee8-72a34b5c054a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2710013850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.2710013850 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.3747648606 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 8107038548 ps |
| CPU time | 1111.99 seconds |
| Started | Jul 06 07:30:02 PM PDT 24 |
| Finished | Jul 06 07:48:35 PM PDT 24 |
| Peak memory | 615872 kb |
| Host | smart-50d38799-575e-4127-8a36-aa57bbe0e869 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747648606 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.3747648606 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.525752694 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 8794516994 ps |
| CPU time | 1150.47 seconds |
| Started | Jul 06 07:31:08 PM PDT 24 |
| Finished | Jul 06 07:50:20 PM PDT 24 |
| Peak memory | 622692 kb |
| Host | smart-832344f6-8e4e-4280-a7cb-f5fa5c1b8025 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=525752694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.525752694 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1484782045 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 3570826836 ps |
| CPU time | 601.84 seconds |
| Started | Jul 06 07:34:01 PM PDT 24 |
| Finished | Jul 06 07:44:04 PM PDT 24 |
| Peak memory | 612808 kb |
| Host | smart-8d391a72-38a3-4f0f-9748-32a596c85a2a |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484782045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1484782045 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1795497734 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 4708698488 ps |
| CPU time | 678.2 seconds |
| Started | Jul 06 07:29:27 PM PDT 24 |
| Finished | Jul 06 07:40:46 PM PDT 24 |
| Peak memory | 612988 kb |
| Host | smart-2f09b881-ea17-4720-b9d2-cce86389a3e8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795497734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1795497734 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.966781121 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 4348472312 ps |
| CPU time | 790.44 seconds |
| Started | Jul 06 07:29:23 PM PDT 24 |
| Finished | Jul 06 07:42:34 PM PDT 24 |
| Peak memory | 613068 kb |
| Host | smart-9e648b99-c805-47e0-98c2-24dcb16153af |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966781121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.966781121 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2018429917 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 4673419240 ps |
| CPU time | 771.71 seconds |
| Started | Jul 06 07:34:05 PM PDT 24 |
| Finished | Jul 06 07:46:58 PM PDT 24 |
| Peak memory | 612928 kb |
| Host | smart-1d7b843b-a981-4c20-9611-0a2883a679e8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018429917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2018429917 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1101344220 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 4739157180 ps |
| CPU time | 704.16 seconds |
| Started | Jul 06 07:29:04 PM PDT 24 |
| Finished | Jul 06 07:40:49 PM PDT 24 |
| Peak memory | 613068 kb |
| Host | smart-91247108-59f5-46cc-912a-eef8626c380c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101344220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1101344220 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3643937097 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 3991269646 ps |
| CPU time | 578.53 seconds |
| Started | Jul 06 07:33:40 PM PDT 24 |
| Finished | Jul 06 07:43:20 PM PDT 24 |
| Peak memory | 612936 kb |
| Host | smart-98073047-eb6d-4459-81ab-68d1cd346aef |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643937097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3643937097 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.749363152 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 2976350169 ps |
| CPU time | 152.35 seconds |
| Started | Jul 06 07:27:57 PM PDT 24 |
| Finished | Jul 06 07:30:31 PM PDT 24 |
| Peak memory | 608872 kb |
| Host | smart-e93cbec0-f91a-4375-8682-882d2d57e3ad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749363152 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_clkmgr_jitter.749363152 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.4172451222 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 3607410100 ps |
| CPU time | 445.26 seconds |
| Started | Jul 06 07:28:23 PM PDT 24 |
| Finished | Jul 06 07:35:49 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-a618ba45-c6b5-49b3-8572-265a9aa05fbd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172451222 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.4172451222 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.198383510 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 2622810751 ps |
| CPU time | 224.64 seconds |
| Started | Jul 06 07:36:34 PM PDT 24 |
| Finished | Jul 06 07:40:19 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-d863001f-43a4-495f-8572-1b0893e91742 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198383510 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.198383510 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.464207387 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 3935725500 ps |
| CPU time | 543.29 seconds |
| Started | Jul 06 07:30:42 PM PDT 24 |
| Finished | Jul 06 07:39:46 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-905dc5cc-168a-4f78-b0b6-13d3739ab638 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464207387 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.464207387 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.787553076 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 5022704256 ps |
| CPU time | 413.35 seconds |
| Started | Jul 06 07:34:12 PM PDT 24 |
| Finished | Jul 06 07:41:06 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-68550bcf-2af5-485b-a038-7cc0090f5e2b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787553076 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.787553076 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3830810064 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 5715174084 ps |
| CPU time | 596.36 seconds |
| Started | Jul 06 07:28:51 PM PDT 24 |
| Finished | Jul 06 07:38:48 PM PDT 24 |
| Peak memory | 610356 kb |
| Host | smart-c20d0933-fde0-4f69-9cc3-30deb5dc4631 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830810064 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.3830810064 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1310789816 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 4619702570 ps |
| CPU time | 606.81 seconds |
| Started | Jul 06 07:31:35 PM PDT 24 |
| Finished | Jul 06 07:41:43 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-32081685-95e7-41ac-9f78-280415b6d9ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310789816 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.1310789816 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2706599014 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 9037170904 ps |
| CPU time | 964.23 seconds |
| Started | Jul 06 07:31:44 PM PDT 24 |
| Finished | Jul 06 07:47:49 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-99e9813e-424e-491d-9437-ce977ed5c0c0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706599014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.2706599014 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.802268625 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 3546299496 ps |
| CPU time | 359.7 seconds |
| Started | Jul 06 07:36:25 PM PDT 24 |
| Finished | Jul 06 07:42:25 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-4ca13150-d598-42a4-a337-109afdcb9900 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802268625 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.802268625 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3415373460 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 4697413914 ps |
| CPU time | 710.93 seconds |
| Started | Jul 06 07:28:19 PM PDT 24 |
| Finished | Jul 06 07:40:11 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-9c5b12fa-2885-49ed-975c-c906490b6a3b |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415373460 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.3415373460 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.754201877 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 2353503170 ps |
| CPU time | 242.49 seconds |
| Started | Jul 06 07:31:50 PM PDT 24 |
| Finished | Jul 06 07:35:53 PM PDT 24 |
| Peak memory | 608916 kb |
| Host | smart-1d8c1822-95bf-40fc-a87d-bd8c16e42c4f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754201877 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_clkmgr_smoketest.754201877 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.1214386836 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 71658618896 ps |
| CPU time | 16410.8 seconds |
| Started | Jul 06 07:31:46 PM PDT 24 |
| Finished | Jul 07 12:05:20 AM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-60e37923-1b20-416b-9bfa-022bb4e729b9 |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1214386836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.1214386836 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1358034456 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 16423998032 ps |
| CPU time | 4693.56 seconds |
| Started | Jul 06 07:31:29 PM PDT 24 |
| Finished | Jul 06 08:49:44 PM PDT 24 |
| Peak memory | 609244 kb |
| Host | smart-36360722-c49b-46b4-bfbd-554ee8443740 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358034456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.1358034456 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.843924215 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 22497559042 ps |
| CPU time | 4468.56 seconds |
| Started | Jul 06 07:29:35 PM PDT 24 |
| Finished | Jul 06 08:44:05 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-680833a1-e901-460e-8135-296980caf670 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=843924215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.843924215 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.3050474432 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3204463424 ps |
| CPU time | 267.01 seconds |
| Started | Jul 06 07:31:25 PM PDT 24 |
| Finished | Jul 06 07:35:52 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-8f7c7450-771a-4417-87de-595902c12020 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050474432 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.3050474432 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.718330674 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 4828576355 ps |
| CPU time | 605.87 seconds |
| Started | Jul 06 07:29:01 PM PDT 24 |
| Finished | Jul 06 07:39:07 PM PDT 24 |
| Peak memory | 611508 kb |
| Host | smart-fe46683c-83d4-47f9-8649-5360a08c57f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718330674 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrn g_lc_hw_debug_en_test.718330674 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.4233908947 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2445287108 ps |
| CPU time | 197.66 seconds |
| Started | Jul 06 07:34:29 PM PDT 24 |
| Finished | Jul 06 07:37:47 PM PDT 24 |
| Peak memory | 608908 kb |
| Host | smart-0138b597-e062-4d6c-8ae4-254ec2775f1d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233908947 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.4233908947 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1703669399 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 5166719400 ps |
| CPU time | 672.35 seconds |
| Started | Jul 06 07:28:48 PM PDT 24 |
| Finished | Jul 06 07:40:01 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-c4fd5c63-584f-4f0d-bf90-0a51c4275c3c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1703669399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.1703669399 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.352833396 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 5886159180 ps |
| CPU time | 1125.43 seconds |
| Started | Jul 06 07:36:17 PM PDT 24 |
| Finished | Jul 06 07:55:03 PM PDT 24 |
| Peak memory | 611020 kb |
| Host | smart-e06a1e3e-8a03-4651-8085-c004f09516d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=352833396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.352833396 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3590424080 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 6699567959 ps |
| CPU time | 1280.65 seconds |
| Started | Jul 06 07:34:54 PM PDT 24 |
| Finished | Jul 06 07:56:15 PM PDT 24 |
| Peak memory | 611068 kb |
| Host | smart-5dbbbf0a-1d3b-4018-8998-6ae7f55a3310 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590424080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.3590424080 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.2687841905 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 3431171168 ps |
| CPU time | 678.68 seconds |
| Started | Jul 06 07:29:09 PM PDT 24 |
| Finished | Jul 06 07:40:28 PM PDT 24 |
| Peak memory | 615352 kb |
| Host | smart-90e91bf2-15bb-4556-9f68-3c9149c3129a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687841905 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.2687841905 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.3226015158 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 6816628360 ps |
| CPU time | 1232.5 seconds |
| Started | Jul 06 07:32:38 PM PDT 24 |
| Finished | Jul 06 07:53:11 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-2274cb5a-acc9-47fa-a4b0-bcbf7d5b1630 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226015158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.3226015158 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1759312937 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2740689130 ps |
| CPU time | 288.81 seconds |
| Started | Jul 06 07:28:18 PM PDT 24 |
| Finished | Jul 06 07:33:07 PM PDT 24 |
| Peak memory | 608520 kb |
| Host | smart-e2dbc999-4b0e-49ad-9b6f-162370bf654a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17 59312937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.1759312937 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1467688075 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 2372595320 ps |
| CPU time | 290.65 seconds |
| Started | Jul 06 07:29:48 PM PDT 24 |
| Finished | Jul 06 07:34:40 PM PDT 24 |
| Peak memory | 608588 kb |
| Host | smart-b4212b24-d0d6-40d9-8b13-8333f08c7ea8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467688075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.1467688075 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.4215843883 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 3062636256 ps |
| CPU time | 396.83 seconds |
| Started | Jul 06 07:36:05 PM PDT 24 |
| Finished | Jul 06 07:42:42 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-195a31e6-c4dd-4602-a771-85403bb0a8e3 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4215843883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.4215843883 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.1327257869 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2801125316 ps |
| CPU time | 232.05 seconds |
| Started | Jul 06 07:29:25 PM PDT 24 |
| Finished | Jul 06 07:33:18 PM PDT 24 |
| Peak memory | 608376 kb |
| Host | smart-34b473cd-a2d3-435a-8179-ce0729dbbacb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327257869 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.1327257869 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.3509373420 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 2867126410 ps |
| CPU time | 182.73 seconds |
| Started | Jul 06 07:28:33 PM PDT 24 |
| Finished | Jul 06 07:31:36 PM PDT 24 |
| Peak memory | 608396 kb |
| Host | smart-8976136c-0ac0-49ad-826e-10ba7c6345ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509373420 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.3509373420 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.1104301501 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 2117699280 ps |
| CPU time | 240.07 seconds |
| Started | Jul 06 07:27:49 PM PDT 24 |
| Finished | Jul 06 07:31:49 PM PDT 24 |
| Peak memory | 608688 kb |
| Host | smart-32c48beb-17c9-4d86-8bb6-b43f2a79240d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104301501 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.1104301501 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.2175953392 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 2107327032 ps |
| CPU time | 119.28 seconds |
| Started | Jul 06 07:28:31 PM PDT 24 |
| Finished | Jul 06 07:30:31 PM PDT 24 |
| Peak memory | 608004 kb |
| Host | smart-1a49f4ea-a1f3-41d3-bbe3-010854f9e867 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175953392 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.2175953392 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.2344284273 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4531284142 ps |
| CPU time | 617.61 seconds |
| Started | Jul 06 07:33:27 PM PDT 24 |
| Finished | Jul 06 07:43:46 PM PDT 24 |
| Peak memory | 610836 kb |
| Host | smart-bcefd23c-7582-4a63-bc57-0c3112d761cf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2344284273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.2344284273 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1909403070 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 6077676688 ps |
| CPU time | 1118.89 seconds |
| Started | Jul 06 07:27:12 PM PDT 24 |
| Finished | Jul 06 07:45:51 PM PDT 24 |
| Peak memory | 609332 kb |
| Host | smart-4bca8d0a-2656-4b27-8abb-f013dd9c7d6f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909403070 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.1909403070 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.556067243 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 5745934851 ps |
| CPU time | 1110.8 seconds |
| Started | Jul 06 07:28:15 PM PDT 24 |
| Finished | Jul 06 07:46:47 PM PDT 24 |
| Peak memory | 608844 kb |
| Host | smart-b43cfbc8-b1de-4a0d-a16f-9bb0c142045a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556067243 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.556067243 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3077327712 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 7032109124 ps |
| CPU time | 1263.38 seconds |
| Started | Jul 06 07:32:50 PM PDT 24 |
| Finished | Jul 06 07:53:54 PM PDT 24 |
| Peak memory | 610428 kb |
| Host | smart-3b4410df-26de-42bc-bba2-9ad475177f1c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077327712 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3077327712 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1494858729 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 6374244230 ps |
| CPU time | 1343.73 seconds |
| Started | Jul 06 07:27:29 PM PDT 24 |
| Finished | Jul 06 07:49:53 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-b0e5bf4f-14a8-49ee-a228-a177a108e777 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494858729 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.1494858729 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1312021732 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 3535715420 ps |
| CPU time | 334.87 seconds |
| Started | Jul 06 07:27:08 PM PDT 24 |
| Finished | Jul 06 07:32:44 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-7bce5be2-536a-4586-bdd1-4e51942e1944 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312021732 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.1312021732 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3025777556 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 5498105000 ps |
| CPU time | 637.25 seconds |
| Started | Jul 06 07:28:46 PM PDT 24 |
| Finished | Jul 06 07:39:24 PM PDT 24 |
| Peak memory | 610764 kb |
| Host | smart-17264b81-8400-4889-81d8-e7a15ce5bcfb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30 25777556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.3025777556 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3148845952 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 6009574280 ps |
| CPU time | 1458.96 seconds |
| Started | Jul 06 07:29:04 PM PDT 24 |
| Finished | Jul 06 07:53:23 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-921f1d9a-b237-498c-b735-ba613034b57d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148845952 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.3148845952 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2058331508 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4438791157 ps |
| CPU time | 805.74 seconds |
| Started | Jul 06 07:30:04 PM PDT 24 |
| Finished | Jul 06 07:43:31 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-8f6f04ab-3ce5-4192-ba6f-321777533cfe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2058331508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2058331508 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4163802694 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4979385720 ps |
| CPU time | 850.68 seconds |
| Started | Jul 06 07:32:02 PM PDT 24 |
| Finished | Jul 06 07:46:13 PM PDT 24 |
| Peak memory | 609140 kb |
| Host | smart-5c566530-8d16-40b0-87b1-340d91cc7ffa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=4163802694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4163802694 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1472036764 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 2954923304 ps |
| CPU time | 285.52 seconds |
| Started | Jul 06 07:29:58 PM PDT 24 |
| Finished | Jul 06 07:34:44 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-977b7b7a-f542-4401-bc22-90185c84ab98 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472036 764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.1472036764 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.607150224 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 23752031970 ps |
| CPU time | 2950.07 seconds |
| Started | Jul 06 07:29:24 PM PDT 24 |
| Finished | Jul 06 08:18:35 PM PDT 24 |
| Peak memory | 615240 kb |
| Host | smart-930ca48e-581f-426c-b492-5e88e741d3f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607150224 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.607150224 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.397050625 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 20107632377 ps |
| CPU time | 1853.55 seconds |
| Started | Jul 06 07:27:06 PM PDT 24 |
| Finished | Jul 06 07:58:00 PM PDT 24 |
| Peak memory | 612480 kb |
| Host | smart-c06fbd58-9499-47d9-baf7-f64d26818dea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=397050625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.397050625 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.311278218 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 2562977992 ps |
| CPU time | 196.21 seconds |
| Started | Jul 06 07:37:23 PM PDT 24 |
| Finished | Jul 06 07:40:40 PM PDT 24 |
| Peak memory | 608692 kb |
| Host | smart-f0726b36-d1db-42fc-98e1-b8239551a03f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=311278218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.311278218 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.4226439942 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 2504429169 ps |
| CPU time | 227.77 seconds |
| Started | Jul 06 07:33:31 PM PDT 24 |
| Finished | Jul 06 07:37:19 PM PDT 24 |
| Peak memory | 610164 kb |
| Host | smart-2fbd430f-4141-4893-8c55-c63e50ab769e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226439942 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.4226439942 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.4179276618 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 3163878710 ps |
| CPU time | 366.23 seconds |
| Started | Jul 06 07:31:14 PM PDT 24 |
| Finished | Jul 06 07:37:22 PM PDT 24 |
| Peak memory | 608856 kb |
| Host | smart-a4c9f76b-d891-49e9-90f5-1f559323c995 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179276618 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.4179276618 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.958982022 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 2907932723 ps |
| CPU time | 264.5 seconds |
| Started | Jul 06 07:31:55 PM PDT 24 |
| Finished | Jul 06 07:36:20 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-5e20bb16-aebc-4ba0-98b5-efb80c631c6e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958982022 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.958982022 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.1554863514 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 8956876618 ps |
| CPU time | 2120.03 seconds |
| Started | Jul 06 07:30:30 PM PDT 24 |
| Finished | Jul 06 08:05:51 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-b3a36772-353d-4c35-b17f-d5ff0d371a31 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554863514 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.1554863514 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.3018402669 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 2961363418 ps |
| CPU time | 347.12 seconds |
| Started | Jul 06 07:32:34 PM PDT 24 |
| Finished | Jul 06 07:38:22 PM PDT 24 |
| Peak memory | 608812 kb |
| Host | smart-b7b4091b-0944-46f6-83cd-07e896e40f85 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018402669 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.3018402669 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.787572074 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 3094512470 ps |
| CPU time | 305.92 seconds |
| Started | Jul 06 07:33:28 PM PDT 24 |
| Finished | Jul 06 07:38:35 PM PDT 24 |
| Peak memory | 608860 kb |
| Host | smart-a878ee41-3e54-40e8-bb22-d9606dba6813 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787572074 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_smoketest.787572074 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.165935967 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 3944052374 ps |
| CPU time | 722.73 seconds |
| Started | Jul 06 07:32:56 PM PDT 24 |
| Finished | Jul 06 07:45:01 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-bed1c2d4-f38a-4e30-907f-0f16e176edba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165935967 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.165935967 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2501671036 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 4550662076 ps |
| CPU time | 729.27 seconds |
| Started | Jul 06 07:28:13 PM PDT 24 |
| Finished | Jul 06 07:40:23 PM PDT 24 |
| Peak memory | 608916 kb |
| Host | smart-cb5ef603-df44-4abf-aee3-ae91d13eabd1 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501671036 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.2501671036 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1357090303 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 5319228840 ps |
| CPU time | 770.7 seconds |
| Started | Jul 06 07:29:47 PM PDT 24 |
| Finished | Jul 06 07:42:38 PM PDT 24 |
| Peak memory | 608936 kb |
| Host | smart-372ab906-3257-4c9f-9c9b-050aa905e37e |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357090303 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.1357090303 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.2981472484 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 64707741548 ps |
| CPU time | 11953.1 seconds |
| Started | Jul 06 07:29:00 PM PDT 24 |
| Finished | Jul 06 10:48:16 PM PDT 24 |
| Peak memory | 624644 kb |
| Host | smart-52c046fa-017c-451f-8454-19819ac33a40 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2981472484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.2981472484 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1051233797 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 7843260580 ps |
| CPU time | 1963.82 seconds |
| Started | Jul 06 07:30:24 PM PDT 24 |
| Finished | Jul 06 08:03:09 PM PDT 24 |
| Peak memory | 616440 kb |
| Host | smart-99a971a6-f861-40bf-8ef2-93d252be0972 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051 233797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.1051233797 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.912667504 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 12900837518 ps |
| CPU time | 2565.81 seconds |
| Started | Jul 06 07:30:11 PM PDT 24 |
| Finished | Jul 06 08:12:58 PM PDT 24 |
| Peak memory | 617060 kb |
| Host | smart-a1085edc-e228-4d40-b8d5-184db9db7070 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=912667504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en_ reduced_freq.912667504 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3925752193 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 11205499048 ps |
| CPU time | 2643.69 seconds |
| Started | Jul 06 07:31:40 PM PDT 24 |
| Finished | Jul 06 08:15:45 PM PDT 24 |
| Peak memory | 616444 kb |
| Host | smart-8115d123-096c-4e76-aa9d-58cc76521a53 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3925752193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.3925752193 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1707164662 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 8876210400 ps |
| CPU time | 1803.03 seconds |
| Started | Jul 06 07:35:22 PM PDT 24 |
| Finished | Jul 06 08:05:27 PM PDT 24 |
| Peak memory | 610972 kb |
| Host | smart-71dd88cc-8d14-4e12-94cf-06d2fc59dd61 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17071 64662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.1707164662 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.173240645 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 3073064016 ps |
| CPU time | 209.24 seconds |
| Started | Jul 06 07:32:10 PM PDT 24 |
| Finished | Jul 06 07:35:40 PM PDT 24 |
| Peak memory | 608396 kb |
| Host | smart-0af238c8-827a-48b0-bf59-44b7d5120d01 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173240645 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_app_rom.173240645 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.232803848 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 2937583728 ps |
| CPU time | 262.53 seconds |
| Started | Jul 06 07:30:43 PM PDT 24 |
| Finished | Jul 06 07:35:06 PM PDT 24 |
| Peak memory | 608864 kb |
| Host | smart-cc1b39ea-f3b3-421f-a00d-7a2a0b80d80b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232803848 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_entropy.232803848 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.3389041408 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 2762512824 ps |
| CPU time | 220.04 seconds |
| Started | Jul 06 07:32:03 PM PDT 24 |
| Finished | Jul 06 07:35:43 PM PDT 24 |
| Peak memory | 608788 kb |
| Host | smart-0d2ce143-17f0-4d82-9a66-b73f57963559 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389041408 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.3389041408 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2912207848 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 3008566816 ps |
| CPU time | 313.98 seconds |
| Started | Jul 06 07:29:19 PM PDT 24 |
| Finished | Jul 06 07:34:33 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-a2e1b08e-d3e2-468d-89ea-4268f39a65d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912207848 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.2912207848 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1944255002 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 3062067416 ps |
| CPU time | 348.05 seconds |
| Started | Jul 06 07:29:59 PM PDT 24 |
| Finished | Jul 06 07:35:47 PM PDT 24 |
| Peak memory | 608808 kb |
| Host | smart-9e36fa05-1f39-4fc7-803c-1f34d53d9894 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944255002 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.1944255002 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2970020859 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 3504904424 ps |
| CPU time | 307.28 seconds |
| Started | Jul 06 07:34:30 PM PDT 24 |
| Finished | Jul 06 07:39:38 PM PDT 24 |
| Peak memory | 608356 kb |
| Host | smart-7fec6432-1204-4c82-83e4-2836ca87117b |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970020859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.2970020859 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3546692881 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 2696387526 ps |
| CPU time | 284.97 seconds |
| Started | Jul 06 07:31:34 PM PDT 24 |
| Finished | Jul 06 07:36:19 PM PDT 24 |
| Peak memory | 608292 kb |
| Host | smart-c0475e14-52a3-4a63-8db3-8e1969825230 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35466928 81 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3546692881 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.804827514 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 2544864360 ps |
| CPU time | 278.66 seconds |
| Started | Jul 06 07:30:40 PM PDT 24 |
| Finished | Jul 06 07:35:20 PM PDT 24 |
| Peak memory | 608808 kb |
| Host | smart-4c6ab088-a076-4973-a940-15320e661631 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804827514 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_smoketest.804827514 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1169343727 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 3000012696 ps |
| CPU time | 403.93 seconds |
| Started | Jul 06 07:29:56 PM PDT 24 |
| Finished | Jul 06 07:36:40 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-2f0bca0d-e843-498d-8ca9-7ed5177d0162 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169343727 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.1169343727 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1815432910 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 3515582803 ps |
| CPU time | 174.39 seconds |
| Started | Jul 06 07:32:04 PM PDT 24 |
| Finished | Jul 06 07:34:58 PM PDT 24 |
| Peak memory | 620716 kb |
| Host | smart-919f6a8a-8a3b-4227-82ff-ee2e49d43b9a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815432910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.1815432910 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2644500295 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2884589406 ps |
| CPU time | 154.71 seconds |
| Started | Jul 06 07:30:15 PM PDT 24 |
| Finished | Jul 06 07:32:51 PM PDT 24 |
| Peak memory | 620856 kb |
| Host | smart-910b7d04-beba-460c-b281-bddeeaf0ce9c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644500295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.2644500295 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.4118724929 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 2651371386 ps |
| CPU time | 152.04 seconds |
| Started | Jul 06 07:30:23 PM PDT 24 |
| Finished | Jul 06 07:32:55 PM PDT 24 |
| Peak memory | 620644 kb |
| Host | smart-a24cc74a-2790-498c-b9ea-a539519e22e5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4118724929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.4118724929 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.4128954056 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 2664204462 ps |
| CPU time | 119.87 seconds |
| Started | Jul 06 07:28:45 PM PDT 24 |
| Finished | Jul 06 07:30:46 PM PDT 24 |
| Peak memory | 614808 kb |
| Host | smart-22bfa35d-56cb-4807-9a8d-087c7ef47126 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4128954056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.4128954056 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4207105073 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 2330352941 ps |
| CPU time | 124.34 seconds |
| Started | Jul 06 07:28:08 PM PDT 24 |
| Finished | Jul 06 07:30:13 PM PDT 24 |
| Peak memory | 617420 kb |
| Host | smart-48f338fc-aa43-48da-980a-32d705a76a96 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207105073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4207105073 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.130553346 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 10688588882 ps |
| CPU time | 985.99 seconds |
| Started | Jul 06 07:32:22 PM PDT 24 |
| Finished | Jul 06 07:48:50 PM PDT 24 |
| Peak memory | 618848 kb |
| Host | smart-017c3070-c755-4d44-a464-8bb9f2fa2b68 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=130553346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.130553346 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1993818129 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 46676967788 ps |
| CPU time | 5780.62 seconds |
| Started | Jul 06 07:28:33 PM PDT 24 |
| Finished | Jul 06 09:04:55 PM PDT 24 |
| Peak memory | 619264 kb |
| Host | smart-c0b3bf1e-9e58-4678-a308-22346ba7817b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993818129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.1993818129 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1089921820 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 19552306143 ps |
| CPU time | 3997.2 seconds |
| Started | Jul 06 07:31:48 PM PDT 24 |
| Finished | Jul 06 08:38:27 PM PDT 24 |
| Peak memory | 609432 kb |
| Host | smart-8b0645cf-ea8f-4f82-9109-0d800d4022f9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1089921820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1089921820 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4120026240 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 24973156476 ps |
| CPU time | 4705.74 seconds |
| Started | Jul 06 07:31:12 PM PDT 24 |
| Finished | Jul 06 08:49:39 PM PDT 24 |
| Peak memory | 609492 kb |
| Host | smart-694f97f7-8b84-4928-a324-4bdfd632b3fa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120026240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.4120026240 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2474381345 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4030675376 ps |
| CPU time | 536.72 seconds |
| Started | Jul 06 07:31:05 PM PDT 24 |
| Finished | Jul 06 07:40:03 PM PDT 24 |
| Peak memory | 608972 kb |
| Host | smart-b11e6e5f-e9ff-4da8-9803-5106d6eff4f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474381345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.2474381345 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.2221024558 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 5809749240 ps |
| CPU time | 1045.87 seconds |
| Started | Jul 06 07:29:59 PM PDT 24 |
| Finished | Jul 06 07:47:26 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-a1c11264-3bf8-4258-98b3-4eb259a2d17f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2221024558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.2221024558 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.2917333460 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 5248088560 ps |
| CPU time | 919.16 seconds |
| Started | Jul 06 07:31:44 PM PDT 24 |
| Finished | Jul 06 07:47:05 PM PDT 24 |
| Peak memory | 609032 kb |
| Host | smart-2a8ee663-3b6a-465f-a8ef-000df87c10c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917333460 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.2917333460 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.226119921 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 28274589450 ps |
| CPU time | 5927.22 seconds |
| Started | Jul 06 07:30:03 PM PDT 24 |
| Finished | Jul 06 09:08:51 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-28409182-4e8d-4a32-832c-5e5e519927e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226119 921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.226119921 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3205653884 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 2790574462 ps |
| CPU time | 294.72 seconds |
| Started | Jul 06 07:33:05 PM PDT 24 |
| Finished | Jul 06 07:38:00 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-06e80bbe-4adc-4789-887a-435af4195038 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205653884 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.3205653884 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1570383529 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 8357106228 ps |
| CPU time | 1337.28 seconds |
| Started | Jul 06 07:30:28 PM PDT 24 |
| Finished | Jul 06 07:52:46 PM PDT 24 |
| Peak memory | 610164 kb |
| Host | smart-81492231-3f75-4248-bb79-c75b1a07c736 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1570383529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.1570383529 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.760237993 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 8084981020 ps |
| CPU time | 1115.17 seconds |
| Started | Jul 06 07:30:31 PM PDT 24 |
| Finished | Jul 06 07:49:08 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-16062c18-77d0-487e-89b1-dd82a4be90dd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=760237993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.760237993 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4162141891 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 4582355300 ps |
| CPU time | 688.71 seconds |
| Started | Jul 06 07:31:02 PM PDT 24 |
| Finished | Jul 06 07:42:32 PM PDT 24 |
| Peak memory | 608712 kb |
| Host | smart-65ccdfe4-daa6-40d6-b571-ff76701156cf |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=4162141891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4162141891 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2252056143 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 2817857752 ps |
| CPU time | 246.95 seconds |
| Started | Jul 06 07:36:02 PM PDT 24 |
| Finished | Jul 06 07:40:10 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-24e3b922-7024-499f-9de6-7df0fecc4814 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252056143 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.2252056143 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.3996558385 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 2820350912 ps |
| CPU time | 282.61 seconds |
| Started | Jul 06 07:28:48 PM PDT 24 |
| Finished | Jul 06 07:33:31 PM PDT 24 |
| Peak memory | 611816 kb |
| Host | smart-7e552704-3ce5-4a4a-8ea6-ca9bbb567a46 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996558385 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.3996558385 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.672773312 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 2595370180 ps |
| CPU time | 313.05 seconds |
| Started | Jul 06 07:35:06 PM PDT 24 |
| Finished | Jul 06 07:40:20 PM PDT 24 |
| Peak memory | 608616 kb |
| Host | smart-76bf1677-b21f-4bac-ac2c-dc9f76dacb38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672773312 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_plic_sw_irq.672773312 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.4261800363 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 4146107020 ps |
| CPU time | 661.1 seconds |
| Started | Jul 06 07:31:08 PM PDT 24 |
| Finished | Jul 06 07:42:10 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-e28ae66e-b4f1-452a-9d0b-4ae6cf6012cb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261800363 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.4261800363 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.2044118013 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 11262942300 ps |
| CPU time | 643.37 seconds |
| Started | Jul 06 07:34:09 PM PDT 24 |
| Finished | Jul 06 07:44:53 PM PDT 24 |
| Peak memory | 610828 kb |
| Host | smart-1a0ceb69-2d55-4a59-87bb-37664c133faf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044118013 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.2044118013 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1266691204 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 10433621514 ps |
| CPU time | 2134.83 seconds |
| Started | Jul 06 07:26:56 PM PDT 24 |
| Finished | Jul 06 08:02:32 PM PDT 24 |
| Peak memory | 611136 kb |
| Host | smart-590e9340-1a5d-4a62-ad78-cb4684bd02ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266 691204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.1266691204 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2226001198 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 20700650540 ps |
| CPU time | 2303.1 seconds |
| Started | Jul 06 07:30:35 PM PDT 24 |
| Finished | Jul 06 08:08:59 PM PDT 24 |
| Peak memory | 610964 kb |
| Host | smart-cdc19970-68eb-43f3-b597-d153ec546fc5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222 6001198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.2226001198 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3660856364 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 15740832720 ps |
| CPU time | 1575.92 seconds |
| Started | Jul 06 07:32:27 PM PDT 24 |
| Finished | Jul 06 07:58:44 PM PDT 24 |
| Peak memory | 611196 kb |
| Host | smart-a79f7904-ed56-4ebc-a2f6-dab5571ef225 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3660856364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3660856364 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.4272885510 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 8587716570 ps |
| CPU time | 806.67 seconds |
| Started | Jul 06 07:30:50 PM PDT 24 |
| Finished | Jul 06 07:44:18 PM PDT 24 |
| Peak memory | 610428 kb |
| Host | smart-7cb3f9a7-65d3-4ec8-8bb1-6970fb6b8754 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272885510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.4272885510 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2632939933 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 3863359660 ps |
| CPU time | 343.87 seconds |
| Started | Jul 06 07:36:05 PM PDT 24 |
| Finished | Jul 06 07:41:50 PM PDT 24 |
| Peak memory | 615800 kb |
| Host | smart-ee65a844-fcc8-4b3c-b58e-b384de53c517 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2632939933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.2632939933 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1355747169 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 11625425512 ps |
| CPU time | 1419.25 seconds |
| Started | Jul 06 07:28:01 PM PDT 24 |
| Finished | Jul 06 07:51:41 PM PDT 24 |
| Peak memory | 611520 kb |
| Host | smart-c9c1ef54-c73c-469e-bcab-ed807645e9c2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355747169 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1355747169 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3787772082 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 7776394192 ps |
| CPU time | 514.68 seconds |
| Started | Jul 06 07:32:46 PM PDT 24 |
| Finished | Jul 06 07:41:21 PM PDT 24 |
| Peak memory | 609476 kb |
| Host | smart-260c21bc-cd92-4d19-80e9-51740ff338b8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787772082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3787772082 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.938996804 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 6091484195 ps |
| CPU time | 596.7 seconds |
| Started | Jul 06 07:32:32 PM PDT 24 |
| Finished | Jul 06 07:42:29 PM PDT 24 |
| Peak memory | 610464 kb |
| Host | smart-7c2158a2-40a9-4fe5-b508-5e0a1c0fec04 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938996804 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.938996804 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1614640196 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 19512682770 ps |
| CPU time | 1448.72 seconds |
| Started | Jul 06 07:28:32 PM PDT 24 |
| Finished | Jul 06 07:52:41 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-eca85c2d-3f60-4b61-8db3-1a0bc0b1a0d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1614640196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1614640196 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1114689290 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 44076890905 ps |
| CPU time | 3498.31 seconds |
| Started | Jul 06 07:29:12 PM PDT 24 |
| Finished | Jul 06 08:27:31 PM PDT 24 |
| Peak memory | 611860 kb |
| Host | smart-5473458c-73ce-457d-a1fc-419555348fbe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114689290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1114689290 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3199038654 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 3491378520 ps |
| CPU time | 280.38 seconds |
| Started | Jul 06 07:28:04 PM PDT 24 |
| Finished | Jul 06 07:32:45 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-318d0d00-ff3d-4cb5-83f7-7f4d4792cb81 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199038654 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.3199038654 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3111730049 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 6313509916 ps |
| CPU time | 497.75 seconds |
| Started | Jul 06 07:28:32 PM PDT 24 |
| Finished | Jul 06 07:36:51 PM PDT 24 |
| Peak memory | 616676 kb |
| Host | smart-8cc3da21-4513-4a05-9be4-f96a734411ac |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3111730049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.3111730049 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3480415803 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 5441998682 ps |
| CPU time | 475.65 seconds |
| Started | Jul 06 07:29:26 PM PDT 24 |
| Finished | Jul 06 07:37:22 PM PDT 24 |
| Peak memory | 610920 kb |
| Host | smart-c84e1a7c-d9e6-48b7-ab1f-122599fce3aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3480415803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.3480415803 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3803408246 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 6302676612 ps |
| CPU time | 462.87 seconds |
| Started | Jul 06 07:32:16 PM PDT 24 |
| Finished | Jul 06 07:40:00 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-ca6446fd-728c-4889-9121-03cd417589bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803408246 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.3803408246 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2035922864 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 6965473572 ps |
| CPU time | 1090.88 seconds |
| Started | Jul 06 07:32:03 PM PDT 24 |
| Finished | Jul 06 07:50:15 PM PDT 24 |
| Peak memory | 609540 kb |
| Host | smart-5b97a552-1d88-48ba-9da7-a3b93fd5b7d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035922864 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.2035922864 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3697154485 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 5717746348 ps |
| CPU time | 639.44 seconds |
| Started | Jul 06 07:35:54 PM PDT 24 |
| Finished | Jul 06 07:46:34 PM PDT 24 |
| Peak memory | 609120 kb |
| Host | smart-cf15c7fe-f4ef-489c-b6c3-56cc7cda4199 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697154485 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3697154485 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2244890495 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5489862904 ps |
| CPU time | 360.93 seconds |
| Started | Jul 06 07:30:59 PM PDT 24 |
| Finished | Jul 06 07:37:01 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-eaa3dbaf-3b80-4eee-afda-c0d4dbbc4f18 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244890495 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.2244890495 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.122128285 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 4643971598 ps |
| CPU time | 489.87 seconds |
| Started | Jul 06 07:32:35 PM PDT 24 |
| Finished | Jul 06 07:40:45 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-4dbc75d8-834f-42e0-982f-bd851d68fdd0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122 128285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.122128285 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.607808619 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 9638918361 ps |
| CPU time | 604.03 seconds |
| Started | Jul 06 07:31:02 PM PDT 24 |
| Finished | Jul 06 07:41:07 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-4405cf2c-c823-4392-8c39-e9cf2bbb63a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607808619 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.607808619 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2725950683 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 14318399480 ps |
| CPU time | 2316.29 seconds |
| Started | Jul 06 07:29:36 PM PDT 24 |
| Finished | Jul 06 08:08:13 PM PDT 24 |
| Peak memory | 611100 kb |
| Host | smart-becfbb21-400e-4073-8483-bb90e4c425dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2725950683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.2725950683 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1736292851 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 7034413400 ps |
| CPU time | 648.04 seconds |
| Started | Jul 06 07:28:41 PM PDT 24 |
| Finished | Jul 06 07:39:30 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-7dfece7c-09da-40df-aa09-ec8daf145928 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736292851 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.1736292851 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3700131785 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 5052022160 ps |
| CPU time | 767.52 seconds |
| Started | Jul 06 07:29:18 PM PDT 24 |
| Finished | Jul 06 07:42:07 PM PDT 24 |
| Peak memory | 641632 kb |
| Host | smart-705987fd-2adc-45ef-a860-f49c0f01e18a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3700131785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.3700131785 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2378422711 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 3321366182 ps |
| CPU time | 324.48 seconds |
| Started | Jul 06 07:37:15 PM PDT 24 |
| Finished | Jul 06 07:42:40 PM PDT 24 |
| Peak memory | 608916 kb |
| Host | smart-b3b41f43-50a1-491b-a054-d6f6a1e0269a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378422711 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.2378422711 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.347161233 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 5216210172 ps |
| CPU time | 375.27 seconds |
| Started | Jul 06 07:29:33 PM PDT 24 |
| Finished | Jul 06 07:35:49 PM PDT 24 |
| Peak memory | 609116 kb |
| Host | smart-fb420972-b3a5-4abc-85cb-9df45212b00f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347161233 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rstmgr_sw_req.347161233 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3240772884 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 3387334450 ps |
| CPU time | 300.65 seconds |
| Started | Jul 06 07:29:19 PM PDT 24 |
| Finished | Jul 06 07:34:21 PM PDT 24 |
| Peak memory | 610252 kb |
| Host | smart-6277ae69-47b8-4738-a299-6bb1c58b876e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240772884 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.3240772884 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3115734401 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3007799945 ps |
| CPU time | 332.01 seconds |
| Started | Jul 06 07:29:48 PM PDT 24 |
| Finished | Jul 06 07:35:20 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-6558561e-00a1-4cbd-9e79-797b82845f4f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115734401 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.3115734401 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3921449861 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 5924134794 ps |
| CPU time | 956.71 seconds |
| Started | Jul 06 07:36:29 PM PDT 24 |
| Finished | Jul 06 07:52:26 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-e9fe8d94-a185-4ca9-b681-c185624983b0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3921449861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.3921449861 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.3366355227 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 6773325128 ps |
| CPU time | 511.09 seconds |
| Started | Jul 06 07:29:11 PM PDT 24 |
| Finished | Jul 06 07:37:42 PM PDT 24 |
| Peak memory | 619972 kb |
| Host | smart-1f07f20e-8ef4-4f42-90ce-aa4f46636762 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366355227 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.3366355227 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2486907124 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2775913280 ps |
| CPU time | 323.91 seconds |
| Started | Jul 06 07:33:22 PM PDT 24 |
| Finished | Jul 06 07:38:46 PM PDT 24 |
| Peak memory | 608864 kb |
| Host | smart-22d76337-c58b-42c0-b746-3ed7382754d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486907124 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.2486907124 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.4166826350 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 3270258746 ps |
| CPU time | 285.16 seconds |
| Started | Jul 06 07:28:30 PM PDT 24 |
| Finished | Jul 06 07:33:16 PM PDT 24 |
| Peak memory | 608432 kb |
| Host | smart-83ef1bc4-67a7-49d8-89f6-7f59b7cebceb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166826350 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.4166826350 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2324100885 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 3531861722 ps |
| CPU time | 355.83 seconds |
| Started | Jul 06 07:32:54 PM PDT 24 |
| Finished | Jul 06 07:38:50 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-d281edfc-45a2-47cb-9bad-9e553f6b056a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324100885 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.2324100885 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.980464628 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 3171041537 ps |
| CPU time | 345.68 seconds |
| Started | Jul 06 07:32:19 PM PDT 24 |
| Finished | Jul 06 07:38:06 PM PDT 24 |
| Peak memory | 609068 kb |
| Host | smart-9da65ec5-55a9-4eb5-879b-73c385dbd4ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9804646 28 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.980464628 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3173520726 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 3430153256 ps |
| CPU time | 199.09 seconds |
| Started | Jul 06 07:28:19 PM PDT 24 |
| Finished | Jul 06 07:31:39 PM PDT 24 |
| Peak memory | 609108 kb |
| Host | smart-545d20c7-729e-4ed2-8cb4-9f298cc64050 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173520726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.3173520726 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2211444208 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 9052043860 ps |
| CPU time | 1260.96 seconds |
| Started | Jul 06 07:29:16 PM PDT 24 |
| Finished | Jul 06 07:50:18 PM PDT 24 |
| Peak memory | 609740 kb |
| Host | smart-7c1c8040-03d1-4a2f-abfd-184aa92d3d05 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211444208 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.2211444208 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3767815532 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 7462652364 ps |
| CPU time | 765.65 seconds |
| Started | Jul 06 07:29:21 PM PDT 24 |
| Finished | Jul 06 07:42:07 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-3aa6581d-e882-4342-8e24-4e910abde5bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767815532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.3767815532 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1376637301 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 6455737550 ps |
| CPU time | 521.16 seconds |
| Started | Jul 06 07:31:50 PM PDT 24 |
| Finished | Jul 06 07:40:32 PM PDT 24 |
| Peak memory | 610820 kb |
| Host | smart-889be827-8c50-42ca-bd10-63e53c9fadf2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376637301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.1376637301 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.4158178756 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 7647049178 ps |
| CPU time | 952.78 seconds |
| Started | Jul 06 07:28:24 PM PDT 24 |
| Finished | Jul 06 07:44:18 PM PDT 24 |
| Peak memory | 624820 kb |
| Host | smart-040b032b-1130-481d-b010-096157be2f5b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158178756 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.4158178756 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3369748139 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 4419398870 ps |
| CPU time | 632.78 seconds |
| Started | Jul 06 07:28:45 PM PDT 24 |
| Finished | Jul 06 07:39:18 PM PDT 24 |
| Peak memory | 624864 kb |
| Host | smart-52329576-3cbb-4854-a62c-3dffe4f24a88 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369748139 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.3369748139 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.1334518918 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3181843007 ps |
| CPU time | 436.11 seconds |
| Started | Jul 06 07:30:28 PM PDT 24 |
| Finished | Jul 06 07:37:47 PM PDT 24 |
| Peak memory | 619332 kb |
| Host | smart-ad193a24-b209-4154-8bb2-8736184836a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334518918 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.1334518918 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.161745446 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3070081224 ps |
| CPU time | 276.77 seconds |
| Started | Jul 06 07:34:01 PM PDT 24 |
| Finished | Jul 06 07:38:39 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-662a8ea2-ba8a-4074-908e-dbd0a73fad02 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161745446 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.161745446 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2708915245 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4735937144 ps |
| CPU time | 601.03 seconds |
| Started | Jul 06 07:31:23 PM PDT 24 |
| Finished | Jul 06 07:41:24 PM PDT 24 |
| Peak memory | 610904 kb |
| Host | smart-965ac860-26ec-4b0b-9bcd-2ad1de4dc7f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708915245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.2708915245 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.635026187 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 4034570357 ps |
| CPU time | 591.59 seconds |
| Started | Jul 06 07:31:34 PM PDT 24 |
| Finished | Jul 06 07:41:26 PM PDT 24 |
| Peak memory | 609596 kb |
| Host | smart-d09fe78d-f318-4236-8944-47e1de1d6d85 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635026187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.635026187 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2764209123 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 5839789947 ps |
| CPU time | 543.95 seconds |
| Started | Jul 06 07:32:35 PM PDT 24 |
| Finished | Jul 06 07:41:40 PM PDT 24 |
| Peak memory | 610916 kb |
| Host | smart-1941c155-dd51-4946-92f9-660ad04df371 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764209123 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2764209123 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2798600182 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 3637660200 ps |
| CPU time | 309.9 seconds |
| Started | Jul 06 07:34:44 PM PDT 24 |
| Finished | Jul 06 07:39:55 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-ca0f2301-7256-4b76-b2c9-39e0b130ec49 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798600182 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.2798600182 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.801409419 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 5609136920 ps |
| CPU time | 803.85 seconds |
| Started | Jul 06 07:28:53 PM PDT 24 |
| Finished | Jul 06 07:42:20 PM PDT 24 |
| Peak memory | 613828 kb |
| Host | smart-9ce8953f-1955-4a56-8627-8ad5f8cff5db |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801409419 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.801409419 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1333045403 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 2857156627 ps |
| CPU time | 337.28 seconds |
| Started | Jul 06 07:30:28 PM PDT 24 |
| Finished | Jul 06 07:36:08 PM PDT 24 |
| Peak memory | 612880 kb |
| Host | smart-2c9bf092-d31f-4f11-a1a8-ed7ddcf8091b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333045403 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.1333045403 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3041441729 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 3502739320 ps |
| CPU time | 389.47 seconds |
| Started | Jul 06 07:31:53 PM PDT 24 |
| Finished | Jul 06 07:38:24 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-b47acbdd-0206-43d3-a7f5-1a09b68161cc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041441729 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.3041441729 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2241700257 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 23079993616 ps |
| CPU time | 1706.36 seconds |
| Started | Jul 06 07:35:51 PM PDT 24 |
| Finished | Jul 06 08:04:19 PM PDT 24 |
| Peak memory | 615108 kb |
| Host | smart-989cf276-b782-435a-8963-b47e1dac09b2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22417002 57 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.2241700257 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2496983779 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 6300914868 ps |
| CPU time | 502.1 seconds |
| Started | Jul 06 07:28:59 PM PDT 24 |
| Finished | Jul 06 07:37:22 PM PDT 24 |
| Peak memory | 609500 kb |
| Host | smart-2618ea54-01bd-4b12-ae2e-13db7a2b16c8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496983779 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2496983779 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.189719909 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 2751453464 ps |
| CPU time | 352.29 seconds |
| Started | Jul 06 07:32:36 PM PDT 24 |
| Finished | Jul 06 07:38:29 PM PDT 24 |
| Peak memory | 614168 kb |
| Host | smart-70cb70fa-5c03-47e5-b67c-88fdd41e7450 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189719909 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_uart_smoketest.189719909 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.3522220743 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 3648051840 ps |
| CPU time | 700.94 seconds |
| Started | Jul 06 07:27:35 PM PDT 24 |
| Finished | Jul 06 07:39:17 PM PDT 24 |
| Peak memory | 624596 kb |
| Host | smart-a7f76a1b-e8e4-4a98-b06e-bd92d29896e8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522220743 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.3522220743 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.31135839 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 3974021916 ps |
| CPU time | 623.28 seconds |
| Started | Jul 06 07:33:21 PM PDT 24 |
| Finished | Jul 06 07:43:46 PM PDT 24 |
| Peak memory | 622820 kb |
| Host | smart-88e4e480-18c9-45f2-b200-5dd95b2ae762 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31135839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_bau drate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_a lt_clk_freq.31135839 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2192936567 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 78625465368 ps |
| CPU time | 14854.8 seconds |
| Started | Jul 06 07:30:36 PM PDT 24 |
| Finished | Jul 06 11:38:14 PM PDT 24 |
| Peak memory | 634972 kb |
| Host | smart-bcc4fa53-02d8-4f6b-94df-a4be063a20b3 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2192936567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.2192936567 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2733159095 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 4538329342 ps |
| CPU time | 678.12 seconds |
| Started | Jul 06 07:28:20 PM PDT 24 |
| Finished | Jul 06 07:39:39 PM PDT 24 |
| Peak memory | 624588 kb |
| Host | smart-5956c376-0bee-4786-8c12-7b076e1ec3aa |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733159095 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.2733159095 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.4240553167 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 4209458050 ps |
| CPU time | 663.33 seconds |
| Started | Jul 06 07:30:51 PM PDT 24 |
| Finished | Jul 06 07:41:55 PM PDT 24 |
| Peak memory | 624560 kb |
| Host | smart-5fdda300-e75a-449a-9025-6092b5de931e |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240553167 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.4240553167 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2591238165 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2791345808 ps |
| CPU time | 395.82 seconds |
| Started | Jul 06 07:34:27 PM PDT 24 |
| Finished | Jul 06 07:41:04 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-1e209f14-311f-4837-bbe7-dbc62742c5a3 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591238165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.2591238165 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.985581950 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 11744753928 ps |
| CPU time | 3156.24 seconds |
| Started | Jul 06 07:30:48 PM PDT 24 |
| Finished | Jul 06 08:23:25 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-e600935b-994c-411c-bd58-914d4221174b |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=985581950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.985581950 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.3347786648 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 31720946610 ps |
| CPU time | 7576.92 seconds |
| Started | Jul 06 07:30:47 PM PDT 24 |
| Finished | Jul 06 09:37:07 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-34d65c9c-33e0-4b22-9942-e68689d08a16 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3347786648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.3347786648 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.780066196 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 3004797748 ps |
| CPU time | 300.43 seconds |
| Started | Jul 06 07:28:16 PM PDT 24 |
| Finished | Jul 06 07:33:17 PM PDT 24 |
| Peak memory | 608312 kb |
| Host | smart-985c4220-1a15-4ba2-8542-b8ebf1e88d4b |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780066196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.780066196 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2859231889 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3558758576 ps |
| CPU time | 740.86 seconds |
| Started | Jul 06 07:32:17 PM PDT 24 |
| Finished | Jul 06 07:44:40 PM PDT 24 |
| Peak memory | 608372 kb |
| Host | smart-472253a9-00ea-4b6b-8ead-fbbe041fcb12 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285923188 9 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.2859231889 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.1955756093 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 18507232286 ps |
| CPU time | 4977.52 seconds |
| Started | Jul 06 07:29:49 PM PDT 24 |
| Finished | Jul 06 08:52:48 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-829e8ee5-ad37-413e-bf5d-7aeaab862726 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1955756093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.1955756093 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.3313178256 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 2637524350 ps |
| CPU time | 293.96 seconds |
| Started | Jul 06 07:31:36 PM PDT 24 |
| Finished | Jul 06 07:36:32 PM PDT 24 |
| Peak memory | 608332 kb |
| Host | smart-76916521-1c7f-4106-ab1c-7110fbaf56c0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313178256 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.3313178256 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.1945671217 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 3482243305 ps |
| CPU time | 315.09 seconds |
| Started | Jul 06 07:28:34 PM PDT 24 |
| Finished | Jul 06 07:33:50 PM PDT 24 |
| Peak memory | 621004 kb |
| Host | smart-d5b2eda3-3195-484c-989d-92d8adf52563 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1945671217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.1945671217 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.321431355 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 2189111667 ps |
| CPU time | 158.37 seconds |
| Started | Jul 06 07:31:07 PM PDT 24 |
| Finished | Jul 06 07:33:46 PM PDT 24 |
| Peak memory | 622240 kb |
| Host | smart-3491e1f0-888c-4b82-9fc9-06c7489da06f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321431355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.321431355 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.3824644874 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 4123685945 ps |
| CPU time | 387.73 seconds |
| Started | Jul 06 07:31:35 PM PDT 24 |
| Finished | Jul 06 07:38:05 PM PDT 24 |
| Peak memory | 620936 kb |
| Host | smart-78a780ee-22b8-4774-b210-14617d75185d |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824644874 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.3824644874 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.2610230014 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2465284339 ps |
| CPU time | 169.32 seconds |
| Started | Jul 06 07:28:45 PM PDT 24 |
| Finished | Jul 06 07:31:36 PM PDT 24 |
| Peak memory | 623504 kb |
| Host | smart-737defaa-8fed-4e8c-a29b-c40a8997a03f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2610230014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.2610230014 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.442909286 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 15767440648 ps |
| CPU time | 4490.36 seconds |
| Started | Jul 06 07:38:50 PM PDT 24 |
| Finished | Jul 06 08:53:41 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-e482cb5c-ae5d-4dcd-93e1-16b03824ee74 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442909286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .rom_e2e_asm_init_dev.442909286 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.128832718 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 15245439830 ps |
| CPU time | 4386.54 seconds |
| Started | Jul 06 07:35:44 PM PDT 24 |
| Finished | Jul 06 08:48:51 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-ba7bf9f3-9ea6-4b32-ae2f-f06ed32d2379 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128832718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.128832718 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2096061603 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 15603236260 ps |
| CPU time | 4456.33 seconds |
| Started | Jul 06 07:36:28 PM PDT 24 |
| Finished | Jul 06 08:50:45 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-03041642-2153-4b48-a90b-8b48bf346c8b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096061603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.2096061603 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.39719729 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 14938167356 ps |
| CPU time | 4975.27 seconds |
| Started | Jul 06 07:36:25 PM PDT 24 |
| Finished | Jul 06 08:59:21 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-ef228508-3b61-4602-9ffa-62b1c92ee0ca |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39719729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. rom_e2e_asm_init_rma.39719729 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2732067699 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 11772351683 ps |
| CPU time | 3654.45 seconds |
| Started | Jul 06 07:38:21 PM PDT 24 |
| Finished | Jul 06 08:39:17 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-19632369-3079-428d-897d-8bfead39fe4e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732067699 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.2732067699 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3391311415 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 24408021290 ps |
| CPU time | 7551.04 seconds |
| Started | Jul 06 07:38:47 PM PDT 24 |
| Finished | Jul 06 09:44:40 PM PDT 24 |
| Peak memory | 609512 kb |
| Host | smart-bd3f9352-1113-4a32-9e0d-662046508d8d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3391311415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3391311415 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3750962045 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 24299070120 ps |
| CPU time | 6908.22 seconds |
| Started | Jul 06 07:38:19 PM PDT 24 |
| Finished | Jul 06 09:33:29 PM PDT 24 |
| Peak memory | 609476 kb |
| Host | smart-8148c275-6188-41b2-81ef-9ee651851a0f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3750962045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3750962045 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.924364784 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 23722043264 ps |
| CPU time | 6229.71 seconds |
| Started | Jul 06 07:37:01 PM PDT 24 |
| Finished | Jul 06 09:20:52 PM PDT 24 |
| Peak memory | 609440 kb |
| Host | smart-b93fbeb7-7e0c-497c-ae5c-727f32f2d627 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=924364784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.924364784 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3365607298 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 18637812532 ps |
| CPU time | 5054.26 seconds |
| Started | Jul 06 07:34:08 PM PDT 24 |
| Finished | Jul 06 08:58:24 PM PDT 24 |
| Peak memory | 609504 kb |
| Host | smart-df5a385f-6b71-4a6a-8e6b-373347cb1135 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365607298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3365607298 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1536508927 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 15479051096 ps |
| CPU time | 4129.19 seconds |
| Started | Jul 06 07:35:39 PM PDT 24 |
| Finished | Jul 06 08:44:29 PM PDT 24 |
| Peak memory | 609412 kb |
| Host | smart-3d64b2fa-f279-411b-9d3f-78b4c452daef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1536508927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1536508927 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.486950870 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 15865964604 ps |
| CPU time | 4092.91 seconds |
| Started | Jul 06 07:40:43 PM PDT 24 |
| Finished | Jul 06 08:48:57 PM PDT 24 |
| Peak memory | 609452 kb |
| Host | smart-ded076d9-ed93-420b-95f8-94f531c34458 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=486950870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.486950870 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.193126082 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 14871393852 ps |
| CPU time | 3812.83 seconds |
| Started | Jul 06 07:35:47 PM PDT 24 |
| Finished | Jul 06 08:39:20 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-15648285-f2d6-49f6-a2e1-9fce4ac78d8f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=193126082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.193126082 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3931738364 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 15347491300 ps |
| CPU time | 4054.06 seconds |
| Started | Jul 06 07:36:59 PM PDT 24 |
| Finished | Jul 06 08:44:34 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-cda27d33-b8cd-4816-8713-23c46f3b1f72 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3931738364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3931738364 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.4036451416 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 11441164880 ps |
| CPU time | 3418.67 seconds |
| Started | Jul 06 07:37:48 PM PDT 24 |
| Finished | Jul 06 08:34:48 PM PDT 24 |
| Peak memory | 609492 kb |
| Host | smart-182d5ac4-2c43-41db-9103-60e669f778da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036451416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.4036451416 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.946314574 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 15558648388 ps |
| CPU time | 4552.79 seconds |
| Started | Jul 06 07:36:08 PM PDT 24 |
| Finished | Jul 06 08:52:02 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-395449e2-bf72-45be-b700-34b17a0b1402 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946314574 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.946314574 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4175029794 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 15127866372 ps |
| CPU time | 4636.8 seconds |
| Started | Jul 06 07:35:46 PM PDT 24 |
| Finished | Jul 06 08:53:03 PM PDT 24 |
| Peak memory | 609440 kb |
| Host | smart-63cb457c-6cdc-4809-85d0-927b0471f47e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175029794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4175029794 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1209414843 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 15715279100 ps |
| CPU time | 5476.3 seconds |
| Started | Jul 06 07:38:15 PM PDT 24 |
| Finished | Jul 06 09:09:32 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-b4a01213-a4a3-496b-a7fc-725fc16859cb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120941 4843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1209414843 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2501589947 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 14685835842 ps |
| CPU time | 3963.32 seconds |
| Started | Jul 06 07:35:33 PM PDT 24 |
| Finished | Jul 06 08:41:37 PM PDT 24 |
| Peak memory | 609440 kb |
| Host | smart-01f1c10f-b346-43f4-9256-ea79595566bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501589947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2501589947 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2457198939 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 11148144656 ps |
| CPU time | 3113.02 seconds |
| Started | Jul 06 07:36:16 PM PDT 24 |
| Finished | Jul 06 08:28:10 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-6d321556-884b-4418-b112-14b0a78e3fc8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2457198939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2457198939 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2978636065 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 28568382989 ps |
| CPU time | 3090.28 seconds |
| Started | Jul 06 07:29:55 PM PDT 24 |
| Finished | Jul 06 08:21:26 PM PDT 24 |
| Peak memory | 619604 kb |
| Host | smart-66e8d6ce-816f-46e8-a6d5-2f6b73919e24 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2978636065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.2978636065 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.769782284 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 24487955131 ps |
| CPU time | 3516.47 seconds |
| Started | Jul 06 07:31:01 PM PDT 24 |
| Finished | Jul 06 08:29:39 PM PDT 24 |
| Peak memory | 619292 kb |
| Host | smart-7781a446-bead-46ba-9962-53a392b26929 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=769782284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.769782284 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2381959540 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 28133644324 ps |
| CPU time | 2650.46 seconds |
| Started | Jul 06 07:33:47 PM PDT 24 |
| Finished | Jul 06 08:17:59 PM PDT 24 |
| Peak memory | 619324 kb |
| Host | smart-b87f17ed-0a00-47dd-861c-241799fc6a52 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381959540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.2381959540 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.4013216469 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 15067565292 ps |
| CPU time | 4490.53 seconds |
| Started | Jul 06 07:35:34 PM PDT 24 |
| Finished | Jul 06 08:50:25 PM PDT 24 |
| Peak memory | 609052 kb |
| Host | smart-9db8991c-0744-44dc-931e-1ac44de8eaca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013216469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.4013216469 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.341169603 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 15297234952 ps |
| CPU time | 4280.76 seconds |
| Started | Jul 06 07:35:19 PM PDT 24 |
| Finished | Jul 06 08:46:41 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-e0baf633-e349-4be1-bd74-4540e3be4d4e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341169603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.341169603 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1014961299 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 14384149100 ps |
| CPU time | 4395.13 seconds |
| Started | Jul 06 07:37:52 PM PDT 24 |
| Finished | Jul 06 08:51:09 PM PDT 24 |
| Peak memory | 609456 kb |
| Host | smart-388d49de-e487-4247-aaaf-9923070da4f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014961299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.1014961299 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3284339101 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 15160974432 ps |
| CPU time | 3890.31 seconds |
| Started | Jul 06 07:34:32 PM PDT 24 |
| Finished | Jul 06 08:39:23 PM PDT 24 |
| Peak memory | 608916 kb |
| Host | smart-38e62233-c338-4c17-be7c-125a310d4100 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284339101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.3284339101 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1019877256 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 23199000140 ps |
| CPU time | 6432.02 seconds |
| Started | Jul 06 07:36:29 PM PDT 24 |
| Finished | Jul 06 09:23:43 PM PDT 24 |
| Peak memory | 609500 kb |
| Host | smart-b81c62cb-0724-4745-bab7-dc6bcb044ba3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1019877256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.1019877256 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3290373749 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 23152605105 ps |
| CPU time | 6130.92 seconds |
| Started | Jul 06 07:38:18 PM PDT 24 |
| Finished | Jul 06 09:20:30 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-6773eece-34f7-4f30-afe9-5c857efdfb26 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3290373749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.3290373749 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1952900159 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 23949171050 ps |
| CPU time | 7204.6 seconds |
| Started | Jul 06 07:38:50 PM PDT 24 |
| Finished | Jul 06 09:38:56 PM PDT 24 |
| Peak memory | 609500 kb |
| Host | smart-a553db8e-8c0a-4721-abb3-0655d9c4bf9f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1952900159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_ bad_b_bad_prod_end.1952900159 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2629521468 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 23379906842 ps |
| CPU time | 6462.52 seconds |
| Started | Jul 06 07:38:05 PM PDT 24 |
| Finished | Jul 06 09:25:49 PM PDT 24 |
| Peak memory | 609492 kb |
| Host | smart-2eaa78a7-716e-486f-a17c-a2046ed3b6aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2629521468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.2629521468 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.62518534 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 18587785839 ps |
| CPU time | 5511.93 seconds |
| Started | Jul 06 07:34:40 PM PDT 24 |
| Finished | Jul 06 09:06:33 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-258818c0-fefc-400e-9ea4-d85cf8ba4093 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=62518534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_b ad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alway s_a_bad_b_bad_test_unlocked0.62518534 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2735402361 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 14669242811 ps |
| CPU time | 4273.24 seconds |
| Started | Jul 06 07:35:05 PM PDT 24 |
| Finished | Jul 06 08:46:19 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-00f95136-6e38-4b7f-a1e7-391dd4e3d7da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735402361 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2735402361 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.602272385 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 15024679329 ps |
| CPU time | 4208.07 seconds |
| Started | Jul 06 07:35:47 PM PDT 24 |
| Finished | Jul 06 08:45:56 PM PDT 24 |
| Peak memory | 611120 kb |
| Host | smart-69968f64-3b99-448e-ae7d-492b4398c369 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602272385 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.602272385 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3193690230 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 14519289284 ps |
| CPU time | 3858.16 seconds |
| Started | Jul 06 07:36:31 PM PDT 24 |
| Finished | Jul 06 08:40:51 PM PDT 24 |
| Peak memory | 611124 kb |
| Host | smart-247696f4-190c-4bea-9cd5-ae1f80c3421e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193690230 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3193690230 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3021770099 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 14414940955 ps |
| CPU time | 3482.92 seconds |
| Started | Jul 06 07:35:03 PM PDT 24 |
| Finished | Jul 06 08:33:07 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-dab930f2-9367-4144-9ea3-b77547861ed4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021770099 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3021770099 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1106511956 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 11367881756 ps |
| CPU time | 3491.22 seconds |
| Started | Jul 06 07:36:09 PM PDT 24 |
| Finished | Jul 06 08:34:21 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-326b1845-1ae7-497f-9cb1-b35ac054c9f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106511956 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1106511956 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1547508735 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 14587125688 ps |
| CPU time | 4354.02 seconds |
| Started | Jul 06 07:35:07 PM PDT 24 |
| Finished | Jul 06 08:47:42 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-736b79a8-3953-4a59-ad6c-07df618018de |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547508735 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1547508735 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3120674443 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 15410635262 ps |
| CPU time | 3860.28 seconds |
| Started | Jul 06 07:37:27 PM PDT 24 |
| Finished | Jul 06 08:41:48 PM PDT 24 |
| Peak memory | 611136 kb |
| Host | smart-cedd7c3b-30e1-4037-a6e9-99aa74f3349b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120674443 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3120674443 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2508323410 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 14602830644 ps |
| CPU time | 3910.08 seconds |
| Started | Jul 06 07:38:41 PM PDT 24 |
| Finished | Jul 06 08:43:52 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-8b98db83-0d4c-4b8d-8fe1-089c5cbefef5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508323410 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2508323410 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.568161129 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 13842338104 ps |
| CPU time | 4032.63 seconds |
| Started | Jul 06 07:36:06 PM PDT 24 |
| Finished | Jul 06 08:43:19 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-028fe3ad-0fe1-4d97-999c-5ff58f2ef8eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568161129 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.568161129 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3663308410 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 10957106424 ps |
| CPU time | 3125.53 seconds |
| Started | Jul 06 07:34:46 PM PDT 24 |
| Finished | Jul 06 08:26:53 PM PDT 24 |
| Peak memory | 611492 kb |
| Host | smart-b93c5cda-add5-4370-baf6-376d5d35ac96 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663308410 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3663308410 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.1735642820 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 14799763112 ps |
| CPU time | 4059.54 seconds |
| Started | Jul 06 07:35:27 PM PDT 24 |
| Finished | Jul 06 08:43:08 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-c7a1d0a2-832b-40cc-8452-e327e556ed99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1735642820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.1735642820 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.2270663075 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 16680391516 ps |
| CPU time | 4220.12 seconds |
| Started | Jul 06 07:35:29 PM PDT 24 |
| Finished | Jul 06 08:45:50 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-b71c79a1-cbf3-4354-b3e1-17d8daab7362 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270663075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.2270663075 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.1070008272 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 6054939160 ps |
| CPU time | 724.2 seconds |
| Started | Jul 06 07:30:08 PM PDT 24 |
| Finished | Jul 06 07:42:12 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-d31542f0-c22c-4991-9be0-ae0a199a0458 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070008272 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.1070008272 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.1957462962 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 6142225549 ps |
| CPU time | 270.93 seconds |
| Started | Jul 06 07:33:39 PM PDT 24 |
| Finished | Jul 06 07:38:10 PM PDT 24 |
| Peak memory | 619472 kb |
| Host | smart-9d75131f-f34a-4a0d-8d5c-5eeca77f890d |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1957462962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.1957462962 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.3455791671 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 2492415032 ps |
| CPU time | 104.84 seconds |
| Started | Jul 06 07:30:03 PM PDT 24 |
| Finished | Jul 06 07:31:48 PM PDT 24 |
| Peak memory | 617440 kb |
| Host | smart-feb6d2ac-4307-4464-b305-e5015285db5a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455791671 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.3455791671 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.2696456148 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 13816057204 ps |
| CPU time | 1435.49 seconds |
| Started | Jul 06 07:32:48 PM PDT 24 |
| Finished | Jul 06 07:56:45 PM PDT 24 |
| Peak memory | 607720 kb |
| Host | smart-5f6dbdec-6d85-4bd7-b04d-bce1d11398dc |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696456148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.2 696456148 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.693057514 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 3255853286 ps |
| CPU time | 331.53 seconds |
| Started | Jul 06 07:32:32 PM PDT 24 |
| Finished | Jul 06 07:38:04 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-c1972151-a082-4493-9c19-1bc36803f357 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=693057514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.693057514 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.719351703 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 18334045662 ps |
| CPU time | 597.41 seconds |
| Started | Jul 06 07:36:37 PM PDT 24 |
| Finished | Jul 06 07:46:35 PM PDT 24 |
| Peak memory | 619096 kb |
| Host | smart-f04ba148-5bd3-4a39-84ef-8a3db9248335 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=719351703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.719351703 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.2502370790 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 3553980984 ps |
| CPU time | 413.87 seconds |
| Started | Jul 06 07:36:49 PM PDT 24 |
| Finished | Jul 06 07:43:43 PM PDT 24 |
| Peak memory | 608656 kb |
| Host | smart-36805a76-8dbf-4acd-9e45-f24846453637 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502370790 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.2502370790 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2853079780 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 3030809552 ps |
| CPU time | 197.24 seconds |
| Started | Jul 06 07:37:01 PM PDT 24 |
| Finished | Jul 06 07:40:18 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-6fc608bf-7418-4432-bef4-3826057f9db6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853 079780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.2853079780 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.127841074 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 3319582657 ps |
| CPU time | 327.52 seconds |
| Started | Jul 06 07:42:26 PM PDT 24 |
| Finished | Jul 06 07:47:54 PM PDT 24 |
| Peak memory | 608816 kb |
| Host | smart-1607fab0-3780-4044-a24d-7544a6ea18c6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127841074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.127841074 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.1882975633 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 2845589500 ps |
| CPU time | 251.93 seconds |
| Started | Jul 06 07:37:18 PM PDT 24 |
| Finished | Jul 06 07:41:31 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-735f14d1-2a7f-46cd-82c4-1f4693e40b87 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882975633 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.1882975633 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.3644355226 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 2816636560 ps |
| CPU time | 241.56 seconds |
| Started | Jul 06 07:37:06 PM PDT 24 |
| Finished | Jul 06 07:41:08 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-c4792afe-e8d7-431f-8db7-a3ec0a594f8a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644355226 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.3644355226 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.3102950649 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 3233729087 ps |
| CPU time | 372.5 seconds |
| Started | Jul 06 07:37:47 PM PDT 24 |
| Finished | Jul 06 07:44:01 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-30f41c5d-6733-4249-88a8-29ee1eb8e2af |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102950649 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.3102950649 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.4216444169 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 2995075996 ps |
| CPU time | 278.14 seconds |
| Started | Jul 06 07:45:29 PM PDT 24 |
| Finished | Jul 06 07:50:08 PM PDT 24 |
| Peak memory | 608688 kb |
| Host | smart-3c56f791-78f1-4876-bf65-614ccdaca68d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216444169 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.4216444169 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3345703754 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 3295165188 ps |
| CPU time | 317.95 seconds |
| Started | Jul 06 07:36:35 PM PDT 24 |
| Finished | Jul 06 07:41:54 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-205f581b-1359-4a6c-9a82-4cbbde561b63 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3345703754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.3345703754 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.3038256268 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 4732896628 ps |
| CPU time | 419.79 seconds |
| Started | Jul 06 07:37:14 PM PDT 24 |
| Finished | Jul 06 07:44:15 PM PDT 24 |
| Peak memory | 623740 kb |
| Host | smart-a6c6df2e-0ab4-435f-9695-224a958f4b25 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3038256268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.3038256268 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.658623674 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 7539686388 ps |
| CPU time | 1599.13 seconds |
| Started | Jul 06 07:38:36 PM PDT 24 |
| Finished | Jul 06 08:05:16 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-6336c49d-117e-430d-a415-97ebf340fe81 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=658623674 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.658623674 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1588788301 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 5976396032 ps |
| CPU time | 1630.59 seconds |
| Started | Jul 06 07:37:04 PM PDT 24 |
| Finished | Jul 06 08:04:16 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-f6296988-9fbb-46f5-bcec-b96cc4cab8c6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588788301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.1588788301 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3359762885 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 10455421200 ps |
| CPU time | 944.59 seconds |
| Started | Jul 06 07:40:45 PM PDT 24 |
| Finished | Jul 06 07:56:30 PM PDT 24 |
| Peak memory | 610828 kb |
| Host | smart-199c75b4-06c4-4a7d-8056-da183159676e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359762885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.3359762885 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2017814369 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 7309317984 ps |
| CPU time | 1223 seconds |
| Started | Jul 06 07:37:47 PM PDT 24 |
| Finished | Jul 06 07:58:11 PM PDT 24 |
| Peak memory | 608960 kb |
| Host | smart-7b2030d5-997e-4d14-833f-842ee9c38096 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2017814369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.2017814369 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1879746561 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 4614007804 ps |
| CPU time | 550.1 seconds |
| Started | Jul 06 07:37:51 PM PDT 24 |
| Finished | Jul 06 07:47:02 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-326b9b15-4b0a-4d4e-80ca-93bd73cf01b3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1879746561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.1879746561 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3745601573 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 254859013530 ps |
| CPU time | 13524.5 seconds |
| Started | Jul 06 07:39:00 PM PDT 24 |
| Finished | Jul 06 11:24:26 PM PDT 24 |
| Peak memory | 610940 kb |
| Host | smart-b61d55f2-c088-4f7c-922c-106937048b18 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745601573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3745601573 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.2905736195 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3352666816 ps |
| CPU time | 355.41 seconds |
| Started | Jul 06 07:36:07 PM PDT 24 |
| Finished | Jul 06 07:42:03 PM PDT 24 |
| Peak memory | 609028 kb |
| Host | smart-6b3e8836-6419-4ed7-92a4-c1bde97abda3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905736195 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.2905736195 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.2182288126 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 4139947518 ps |
| CPU time | 389.31 seconds |
| Started | Jul 06 07:37:00 PM PDT 24 |
| Finished | Jul 06 07:43:29 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-9b9f28cf-4e96-4a11-9f2a-f93714ed013f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182288126 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.2182288126 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1307432272 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 6782323768 ps |
| CPU time | 474.86 seconds |
| Started | Jul 06 07:37:41 PM PDT 24 |
| Finished | Jul 06 07:45:37 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-15d2c18c-ff1e-4f8f-af30-6812dc7bfbb6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1307432272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1307432272 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.905558501 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 3120528588 ps |
| CPU time | 388.02 seconds |
| Started | Jul 06 07:43:19 PM PDT 24 |
| Finished | Jul 06 07:49:47 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-7cf9c065-56ba-4710-9396-d097a9b176be |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905558501 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_aon_timer_smoketest.905558501 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1638576226 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 8225999562 ps |
| CPU time | 832.58 seconds |
| Started | Jul 06 07:37:55 PM PDT 24 |
| Finished | Jul 06 07:51:48 PM PDT 24 |
| Peak memory | 610732 kb |
| Host | smart-cd31e8a9-cb47-4bee-8241-5e81a8db93a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1638576226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.1638576226 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.190204148 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 6034026810 ps |
| CPU time | 851.84 seconds |
| Started | Jul 06 07:36:40 PM PDT 24 |
| Finished | Jul 06 07:50:52 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-b355b1e6-a58c-456a-af75-e1fdd8464770 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =190204148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.190204148 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2672584651 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 7098452360 ps |
| CPU time | 1149.34 seconds |
| Started | Jul 06 07:39:05 PM PDT 24 |
| Finished | Jul 06 07:58:14 PM PDT 24 |
| Peak memory | 615872 kb |
| Host | smart-1336a317-0378-49eb-b28e-2188ecfbe8df |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672584651 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.2672584651 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1476264961 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 13663465018 ps |
| CPU time | 1156.09 seconds |
| Started | Jul 06 07:40:53 PM PDT 24 |
| Finished | Jul 06 08:00:10 PM PDT 24 |
| Peak memory | 623228 kb |
| Host | smart-7de96ae9-07a0-44cc-a11b-65b6e373c8b2 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1476264961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.1476264961 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1345015724 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 4000573392 ps |
| CPU time | 619.13 seconds |
| Started | Jul 06 07:39:39 PM PDT 24 |
| Finished | Jul 06 07:49:58 PM PDT 24 |
| Peak memory | 612924 kb |
| Host | smart-cdbb09fb-a9d9-46a6-853c-9ced86781a4b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345015724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1345015724 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3078935886 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 4095480984 ps |
| CPU time | 618.18 seconds |
| Started | Jul 06 07:40:16 PM PDT 24 |
| Finished | Jul 06 07:50:35 PM PDT 24 |
| Peak memory | 612784 kb |
| Host | smart-d9ddabbb-185f-44c4-9c29-859ab420a3ed |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078935886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3078935886 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1148512077 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 3688538512 ps |
| CPU time | 632.47 seconds |
| Started | Jul 06 07:40:02 PM PDT 24 |
| Finished | Jul 06 07:50:35 PM PDT 24 |
| Peak memory | 613012 kb |
| Host | smart-aa958464-d38a-4901-8e11-d7b9a204da3e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148512077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1148512077 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1633145745 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 4617787200 ps |
| CPU time | 633.48 seconds |
| Started | Jul 06 07:41:01 PM PDT 24 |
| Finished | Jul 06 07:51:35 PM PDT 24 |
| Peak memory | 612848 kb |
| Host | smart-8aebf8a7-3006-4454-a555-26bc0240db81 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633145745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1633145745 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.217355365 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 4665351780 ps |
| CPU time | 604.78 seconds |
| Started | Jul 06 07:40:54 PM PDT 24 |
| Finished | Jul 06 07:50:59 PM PDT 24 |
| Peak memory | 613060 kb |
| Host | smart-30604b75-528a-4152-b9fa-d69ec4101e19 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217355365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.217355365 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.466973762 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 2640880363 ps |
| CPU time | 301.47 seconds |
| Started | Jul 06 07:39:43 PM PDT 24 |
| Finished | Jul 06 07:44:45 PM PDT 24 |
| Peak memory | 608852 kb |
| Host | smart-854df2c0-0255-40cf-9f63-27dc9cff7f48 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466973762 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_clkmgr_jitter.466973762 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1831279978 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 3774881132 ps |
| CPU time | 489.02 seconds |
| Started | Jul 06 07:39:05 PM PDT 24 |
| Finished | Jul 06 07:47:14 PM PDT 24 |
| Peak memory | 608548 kb |
| Host | smart-08ebdc2b-60a0-40fd-80d3-dc0d2a1687f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831279978 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.1831279978 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3973907147 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 2798733679 ps |
| CPU time | 267.58 seconds |
| Started | Jul 06 07:41:10 PM PDT 24 |
| Finished | Jul 06 07:45:38 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-e521be17-da23-4354-921f-92e00cfdc885 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973907147 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.3973907147 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.307376114 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 5130950852 ps |
| CPU time | 605.03 seconds |
| Started | Jul 06 07:39:37 PM PDT 24 |
| Finished | Jul 06 07:49:43 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-e70e234c-e217-48a9-9965-073f8733db90 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307376114 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.307376114 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.92822655 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 4757704496 ps |
| CPU time | 489.56 seconds |
| Started | Jul 06 07:38:16 PM PDT 24 |
| Finished | Jul 06 07:46:27 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-0c4d10e7-8061-4472-929c-a23e7d905b5f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92822655 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.92822655 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3638504568 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 3644814756 ps |
| CPU time | 555.2 seconds |
| Started | Jul 06 07:39:52 PM PDT 24 |
| Finished | Jul 06 07:49:08 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-0fe492ac-bbf8-4ec6-ad69-add9d8a1fff7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638504568 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.3638504568 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1014116094 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 4360248816 ps |
| CPU time | 384.42 seconds |
| Started | Jul 06 07:41:00 PM PDT 24 |
| Finished | Jul 06 07:47:25 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-775c43c8-1a29-4c87-a332-0789dcf63018 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014116094 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.1014116094 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1656869753 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 10339640350 ps |
| CPU time | 1063.18 seconds |
| Started | Jul 06 07:39:30 PM PDT 24 |
| Finished | Jul 06 07:57:14 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-dc5c5441-0fc2-47a8-b4c6-7e51ba6c5b6a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656869753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.1656869753 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2904037494 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 3585356776 ps |
| CPU time | 477.9 seconds |
| Started | Jul 06 07:39:44 PM PDT 24 |
| Finished | Jul 06 07:47:43 PM PDT 24 |
| Peak memory | 608372 kb |
| Host | smart-025e6333-e708-4550-a348-86265cc0b61b |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904037494 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.2904037494 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1339130183 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 3846682280 ps |
| CPU time | 602.46 seconds |
| Started | Jul 06 07:40:21 PM PDT 24 |
| Finished | Jul 06 07:50:24 PM PDT 24 |
| Peak memory | 609528 kb |
| Host | smart-77ee02ef-0d99-4dd0-9904-1de04a1ebb8e |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339130183 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.1339130183 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3025728278 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 2463509412 ps |
| CPU time | 278.69 seconds |
| Started | Jul 06 07:45:11 PM PDT 24 |
| Finished | Jul 06 07:49:50 PM PDT 24 |
| Peak memory | 608812 kb |
| Host | smart-461211c6-977d-40ce-bad5-c90ef2bdebf0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025728278 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.3025728278 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3978946194 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 10428612782 ps |
| CPU time | 2914.95 seconds |
| Started | Jul 06 07:38:09 PM PDT 24 |
| Finished | Jul 06 08:26:45 PM PDT 24 |
| Peak memory | 609512 kb |
| Host | smart-767406fe-9092-4bf7-99a4-6a09843ac46f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978946194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.3978946194 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2821590443 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4750960792 ps |
| CPU time | 405.82 seconds |
| Started | Jul 06 07:36:34 PM PDT 24 |
| Finished | Jul 06 07:43:21 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-6952ca8a-1c3c-44b1-9a41-29e4b2cd272c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28215 90443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.2821590443 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.4118190793 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 2743118640 ps |
| CPU time | 213.77 seconds |
| Started | Jul 06 07:37:46 PM PDT 24 |
| Finished | Jul 06 07:41:20 PM PDT 24 |
| Peak memory | 610316 kb |
| Host | smart-d47f91e3-7047-484e-ba0d-9d552e8631cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118190793 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.4118190793 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.209154905 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 6906725680 ps |
| CPU time | 558.45 seconds |
| Started | Jul 06 07:38:04 PM PDT 24 |
| Finished | Jul 06 07:47:23 PM PDT 24 |
| Peak memory | 610984 kb |
| Host | smart-f88106aa-0f84-4fa1-ac48-5ff8cf81ee1f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209154905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrn g_lc_hw_debug_en_test.209154905 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.2235539702 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2347132376 ps |
| CPU time | 184.49 seconds |
| Started | Jul 06 07:45:18 PM PDT 24 |
| Finished | Jul 06 07:48:23 PM PDT 24 |
| Peak memory | 608804 kb |
| Host | smart-760f6cac-f04f-491d-824a-22fb1461a519 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235539702 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.2235539702 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.3295986896 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 4548672636 ps |
| CPU time | 1535.29 seconds |
| Started | Jul 06 07:38:11 PM PDT 24 |
| Finished | Jul 06 08:03:47 PM PDT 24 |
| Peak memory | 609420 kb |
| Host | smart-8580aed1-90e2-44bb-ade0-8a8c9fdc26b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295986896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.3295986896 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.347118728 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 3235835826 ps |
| CPU time | 620.53 seconds |
| Started | Jul 06 07:38:32 PM PDT 24 |
| Finished | Jul 06 07:48:53 PM PDT 24 |
| Peak memory | 609120 kb |
| Host | smart-e0a0db71-f360-4f73-9223-b0be4a0bcc3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347118728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_b oot_mode.347118728 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3799416614 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 6224127462 ps |
| CPU time | 1254.64 seconds |
| Started | Jul 06 07:38:10 PM PDT 24 |
| Finished | Jul 06 07:59:06 PM PDT 24 |
| Peak memory | 611048 kb |
| Host | smart-93fcb66e-c39e-4dd2-8c73-3277720045cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3799416614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.3799416614 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.4096941786 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 8250330740 ps |
| CPU time | 1694.53 seconds |
| Started | Jul 06 07:39:46 PM PDT 24 |
| Finished | Jul 06 08:08:02 PM PDT 24 |
| Peak memory | 610744 kb |
| Host | smart-85d3f9b9-fe9d-492c-ba81-ef94f5284dad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096941786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.4096941786 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.3065877805 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 3417241900 ps |
| CPU time | 606.86 seconds |
| Started | Jul 06 07:37:02 PM PDT 24 |
| Finished | Jul 06 07:47:10 PM PDT 24 |
| Peak memory | 615588 kb |
| Host | smart-5de03c34-d7a0-4edd-87ee-9f4ab89dcb28 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065877805 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.3065877805 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.512994575 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 5869946056 ps |
| CPU time | 1414.43 seconds |
| Started | Jul 06 07:36:48 PM PDT 24 |
| Finished | Jul 06 08:00:24 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-ff7bdd1e-36e4-495e-9282-527f4dc252f9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512994575 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.512994575 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2513781607 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 2942351650 ps |
| CPU time | 262.79 seconds |
| Started | Jul 06 07:39:24 PM PDT 24 |
| Finished | Jul 06 07:43:47 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-8bd85cd4-6ab4-49ea-bb0a-daceba821e18 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25 13781607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.2513781607 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.2422398499 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 6800916464 ps |
| CPU time | 1856.36 seconds |
| Started | Jul 06 07:38:56 PM PDT 24 |
| Finished | Jul 06 08:09:53 PM PDT 24 |
| Peak memory | 609448 kb |
| Host | smart-0a3efbfd-0315-4439-abcd-78f8c6a35d34 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2422398499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.2422398499 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.3360032961 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 3153949400 ps |
| CPU time | 312.47 seconds |
| Started | Jul 06 07:36:22 PM PDT 24 |
| Finished | Jul 06 07:41:35 PM PDT 24 |
| Peak memory | 608584 kb |
| Host | smart-a089c068-ca97-4b75-b75f-421bdb4683b4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360032961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.3360032961 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.842188123 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 3255640884 ps |
| CPU time | 452.9 seconds |
| Started | Jul 06 07:43:11 PM PDT 24 |
| Finished | Jul 06 07:50:45 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-c3915d0b-d5e2-49ce-9c6f-224c41e913d8 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=842188123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.842188123 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.2505671586 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 2986193750 ps |
| CPU time | 261.66 seconds |
| Started | Jul 06 07:36:05 PM PDT 24 |
| Finished | Jul 06 07:40:28 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-f19c50a9-fa48-41c2-a202-f4c937434f29 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505671586 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.2505671586 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.3949177768 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 2558734718 ps |
| CPU time | 153.88 seconds |
| Started | Jul 06 07:32:03 PM PDT 24 |
| Finished | Jul 06 07:34:37 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-9e2f803b-ce90-4320-ac50-26e51f9767bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949177768 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.3949177768 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.945284499 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 2872837752 ps |
| CPU time | 196.78 seconds |
| Started | Jul 06 07:31:51 PM PDT 24 |
| Finished | Jul 06 07:35:09 PM PDT 24 |
| Peak memory | 608360 kb |
| Host | smart-a46bfde8-02d2-4c9e-b4f0-5b3ee7ac31e3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945284499 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_example_manufacturer.945284499 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.1024365568 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2091427700 ps |
| CPU time | 135.36 seconds |
| Started | Jul 06 07:37:48 PM PDT 24 |
| Finished | Jul 06 07:40:04 PM PDT 24 |
| Peak memory | 609332 kb |
| Host | smart-3f678415-8db3-468f-a93e-d9ce4ec023f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024365568 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.1024365568 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3663457481 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 59505604983 ps |
| CPU time | 10888.6 seconds |
| Started | Jul 06 07:34:56 PM PDT 24 |
| Finished | Jul 06 10:36:27 PM PDT 24 |
| Peak memory | 623776 kb |
| Host | smart-9cbd13ef-d76d-4e3f-aa56-8e9453e0095d |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3663457481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.3663457481 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.147594473 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 5542299070 ps |
| CPU time | 1002.61 seconds |
| Started | Jul 06 07:42:31 PM PDT 24 |
| Finished | Jul 06 07:59:15 PM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-1911e93d-6585-411c-839e-c83e0483f1a4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=147594473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.147594473 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.654850477 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 6128472320 ps |
| CPU time | 824.39 seconds |
| Started | Jul 06 07:31:53 PM PDT 24 |
| Finished | Jul 06 07:45:38 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-dea30755-5a7d-4990-b480-bdd42f86ca6d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654850477 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_flash_ctrl_access.654850477 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2438542909 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 6143603440 ps |
| CPU time | 874.66 seconds |
| Started | Jul 06 07:34:16 PM PDT 24 |
| Finished | Jul 06 07:48:52 PM PDT 24 |
| Peak memory | 610452 kb |
| Host | smart-e7d62dec-184f-4fea-b059-39cce4314762 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438542909 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.2438542909 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2536683432 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 7074908973 ps |
| CPU time | 1223.14 seconds |
| Started | Jul 06 07:41:11 PM PDT 24 |
| Finished | Jul 06 08:01:34 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-611e9f11-9333-4d0e-aef7-01a58a2885e5 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536683432 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2536683432 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3993985449 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 6210254635 ps |
| CPU time | 1192.46 seconds |
| Started | Jul 06 07:33:09 PM PDT 24 |
| Finished | Jul 06 07:53:01 PM PDT 24 |
| Peak memory | 608732 kb |
| Host | smart-6f8dc6c1-90cf-47bd-bdea-4ba18a869292 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993985449 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.3993985449 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.4162630190 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 3236492436 ps |
| CPU time | 443.47 seconds |
| Started | Jul 06 07:36:46 PM PDT 24 |
| Finished | Jul 06 07:44:10 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-dbed1d1c-e1e2-4d09-9301-04d192ccb6db |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162630190 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.4162630190 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2435044149 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 5466554800 ps |
| CPU time | 676.93 seconds |
| Started | Jul 06 07:33:13 PM PDT 24 |
| Finished | Jul 06 07:44:31 PM PDT 24 |
| Peak memory | 610800 kb |
| Host | smart-906a0742-2800-4186-8018-9b1e4cb30d8d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24 35044149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.2435044149 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2796925715 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 5726463504 ps |
| CPU time | 1480.46 seconds |
| Started | Jul 06 07:42:42 PM PDT 24 |
| Finished | Jul 06 08:07:23 PM PDT 24 |
| Peak memory | 610412 kb |
| Host | smart-e32cbdf6-2925-461c-9ea1-6ca50f40ec45 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796925715 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.2796925715 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2291694489 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 3935811040 ps |
| CPU time | 618.51 seconds |
| Started | Jul 06 07:33:09 PM PDT 24 |
| Finished | Jul 06 07:43:29 PM PDT 24 |
| Peak memory | 608636 kb |
| Host | smart-2d298c01-c980-4961-a6f3-08cf0f0e3022 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291694489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.2291694489 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2181505186 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 4110595523 ps |
| CPU time | 823.34 seconds |
| Started | Jul 06 07:33:14 PM PDT 24 |
| Finished | Jul 06 07:46:58 PM PDT 24 |
| Peak memory | 610316 kb |
| Host | smart-bb9b6807-c2fe-449e-b0f5-57c8211fdd73 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2181505186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.2181505186 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.915630585 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 5636368413 ps |
| CPU time | 839.02 seconds |
| Started | Jul 06 07:41:17 PM PDT 24 |
| Finished | Jul 06 07:55:17 PM PDT 24 |
| Peak memory | 609476 kb |
| Host | smart-11cf7b00-a346-4947-83af-a9312f4fb76a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=915630585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.915630585 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.4232784395 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 2979485614 ps |
| CPU time | 298.49 seconds |
| Started | Jul 06 07:40:36 PM PDT 24 |
| Finished | Jul 06 07:45:35 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-8dc1f33f-726f-4fc1-b6da-1216563d9efd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232784 395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.4232784395 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.1502443179 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 15653273240 ps |
| CPU time | 2049.37 seconds |
| Started | Jul 06 07:33:43 PM PDT 24 |
| Finished | Jul 06 08:07:53 PM PDT 24 |
| Peak memory | 613144 kb |
| Host | smart-8e271625-8617-4d00-b941-c9abad8d807b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502443179 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.1502443179 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3681982964 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 2873267942 ps |
| CPU time | 252.53 seconds |
| Started | Jul 06 07:46:22 PM PDT 24 |
| Finished | Jul 06 07:50:35 PM PDT 24 |
| Peak memory | 608684 kb |
| Host | smart-ea737c95-fd01-4d69-9b2f-b19cb5fb318d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3681982964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.3681982964 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.3870228144 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2963625485 ps |
| CPU time | 406.46 seconds |
| Started | Jul 06 07:44:59 PM PDT 24 |
| Finished | Jul 06 07:51:46 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-795b335b-1430-45b9-af28-efb871019746 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870228144 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.3870228144 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.1922319471 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 3264360020 ps |
| CPU time | 362.39 seconds |
| Started | Jul 06 07:39:11 PM PDT 24 |
| Finished | Jul 06 07:45:14 PM PDT 24 |
| Peak memory | 608784 kb |
| Host | smart-98d862c0-b450-4dba-aa00-acd54f7ba715 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922319471 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.1922319471 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.715888569 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 3137638520 ps |
| CPU time | 358.14 seconds |
| Started | Jul 06 07:39:02 PM PDT 24 |
| Finished | Jul 06 07:45:01 PM PDT 24 |
| Peak memory | 608852 kb |
| Host | smart-0cb4ed78-4607-45fc-a441-0cbe2c57dc43 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715888569 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_hmac_enc_idle.715888569 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1382348883 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2743431614 ps |
| CPU time | 306.2 seconds |
| Started | Jul 06 07:37:43 PM PDT 24 |
| Finished | Jul 06 07:42:50 PM PDT 24 |
| Peak memory | 608416 kb |
| Host | smart-b6d78805-02dd-4f8d-b057-1fe1deb1e5fd |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382348883 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.1382348883 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2445393126 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2515935433 ps |
| CPU time | 259.47 seconds |
| Started | Jul 06 07:41:06 PM PDT 24 |
| Finished | Jul 06 07:45:26 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-d9e1644e-56b7-4c90-a150-1c0550f6c919 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445393126 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.2445393126 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.559806672 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 8190446740 ps |
| CPU time | 2366.58 seconds |
| Started | Jul 06 07:39:16 PM PDT 24 |
| Finished | Jul 06 08:18:44 PM PDT 24 |
| Peak memory | 608756 kb |
| Host | smart-762fba55-3ff7-4ce6-8b8d-eba240721c31 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559806672 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_hmac_multistream.559806672 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.2839230050 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 3330595784 ps |
| CPU time | 283.01 seconds |
| Started | Jul 06 07:38:37 PM PDT 24 |
| Finished | Jul 06 07:43:20 PM PDT 24 |
| Peak memory | 608916 kb |
| Host | smart-822ca746-2d3d-4c19-b73e-86e6805645ad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839230050 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.2839230050 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.2226082393 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 3596523520 ps |
| CPU time | 377.03 seconds |
| Started | Jul 06 07:43:24 PM PDT 24 |
| Finished | Jul 06 07:49:41 PM PDT 24 |
| Peak memory | 608776 kb |
| Host | smart-154db300-a40f-4dca-b2dd-30f8e3bd0c98 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226082393 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.2226082393 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1347650080 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 4439816900 ps |
| CPU time | 678.85 seconds |
| Started | Jul 06 07:32:56 PM PDT 24 |
| Finished | Jul 06 07:44:16 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-35ad3296-56b2-4305-b084-01b6f678357b |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347650080 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.1347650080 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.530506433 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 5935655398 ps |
| CPU time | 932.12 seconds |
| Started | Jul 06 07:32:47 PM PDT 24 |
| Finished | Jul 06 07:48:20 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-02a153af-fb9e-4f9a-9829-b690b2ce424a |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530506433 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.530506433 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1570284678 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 4616311080 ps |
| CPU time | 792.46 seconds |
| Started | Jul 06 07:32:50 PM PDT 24 |
| Finished | Jul 06 07:46:03 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-5fc50d9f-577d-48bd-ac95-4950363cc528 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570284678 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.1570284678 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.523564333 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 65718568327 ps |
| CPU time | 11207.4 seconds |
| Started | Jul 06 07:32:51 PM PDT 24 |
| Finished | Jul 06 10:39:41 PM PDT 24 |
| Peak memory | 624620 kb |
| Host | smart-d10b712d-db2d-4e96-828c-6ea7527b65df |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=523564333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.523564333 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3385736854 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 10300082756 ps |
| CPU time | 2504.12 seconds |
| Started | Jul 06 07:37:50 PM PDT 24 |
| Finished | Jul 06 08:19:35 PM PDT 24 |
| Peak memory | 617736 kb |
| Host | smart-989f47e1-91b9-4818-86e0-d251e8021daa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385 736854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.3385736854 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2156123454 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 7963200790 ps |
| CPU time | 1082.44 seconds |
| Started | Jul 06 07:42:54 PM PDT 24 |
| Finished | Jul 06 08:00:57 PM PDT 24 |
| Peak memory | 617732 kb |
| Host | smart-fcaf3d84-0f90-4d5d-b092-47c793d04e55 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2156123454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2156123454 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1151717394 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 9412844870 ps |
| CPU time | 2353.04 seconds |
| Started | Jul 06 07:36:47 PM PDT 24 |
| Finished | Jul 06 08:16:00 PM PDT 24 |
| Peak memory | 616784 kb |
| Host | smart-6c71014f-a9f0-45e2-852d-93b59d761e40 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1151717394 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.1151717394 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1854120799 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 8913006982 ps |
| CPU time | 1589.73 seconds |
| Started | Jul 06 07:37:00 PM PDT 24 |
| Finished | Jul 06 08:03:31 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-f84f7e4e-7c97-47be-9449-ecce0b42e0c0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18541 20799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.1854120799 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1709659765 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 16005443260 ps |
| CPU time | 4231.8 seconds |
| Started | Jul 06 07:37:16 PM PDT 24 |
| Finished | Jul 06 08:47:49 PM PDT 24 |
| Peak memory | 611088 kb |
| Host | smart-df236625-a6eb-4e35-8281-92326629f76b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17096 59765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.1709659765 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.2476571135 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 2658153622 ps |
| CPU time | 309.41 seconds |
| Started | Jul 06 07:38:41 PM PDT 24 |
| Finished | Jul 06 07:43:51 PM PDT 24 |
| Peak memory | 608844 kb |
| Host | smart-16bb5ae0-51e1-4fee-a155-1d0983842832 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476571135 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.2476571135 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.3062739097 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 2683807440 ps |
| CPU time | 327.56 seconds |
| Started | Jul 06 07:34:12 PM PDT 24 |
| Finished | Jul 06 07:39:41 PM PDT 24 |
| Peak memory | 608788 kb |
| Host | smart-9c49cbdd-4562-4f79-b1eb-a6006b1b1a11 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062739097 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.3062739097 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.1289463642 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3032500324 ps |
| CPU time | 196.09 seconds |
| Started | Jul 06 07:40:14 PM PDT 24 |
| Finished | Jul 06 07:43:31 PM PDT 24 |
| Peak memory | 608620 kb |
| Host | smart-4bf5c778-fcc5-4d3a-9c5e-de5b8b3263bb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289463642 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.1289463642 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.292719236 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 3426632432 ps |
| CPU time | 222.96 seconds |
| Started | Jul 06 07:40:46 PM PDT 24 |
| Finished | Jul 06 07:44:30 PM PDT 24 |
| Peak memory | 608424 kb |
| Host | smart-84a7286a-2f11-4998-9fd1-56170fe22dc0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292719236 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_kmac_mode_cshake.292719236 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.710493299 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 3430584048 ps |
| CPU time | 288.41 seconds |
| Started | Jul 06 07:37:53 PM PDT 24 |
| Finished | Jul 06 07:42:42 PM PDT 24 |
| Peak memory | 608748 kb |
| Host | smart-44ffc53f-c3c0-44b3-addd-0307490dbc30 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710493299 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_kmac_mode_kmac.710493299 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1607532333 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 3611991122 ps |
| CPU time | 324.88 seconds |
| Started | Jul 06 07:40:43 PM PDT 24 |
| Finished | Jul 06 07:46:08 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-31bf238e-9541-4613-8a6e-77af3e0ef717 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607532333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.1607532333 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3884580386 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 2320681946 ps |
| CPU time | 303.7 seconds |
| Started | Jul 06 07:43:20 PM PDT 24 |
| Finished | Jul 06 07:48:24 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-dd1b08ae-9f5f-4a40-8b7b-7571f01c5e46 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38845803 86 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3884580386 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.4222149431 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 2773715808 ps |
| CPU time | 307.21 seconds |
| Started | Jul 06 07:44:05 PM PDT 24 |
| Finished | Jul 06 07:49:12 PM PDT 24 |
| Peak memory | 608432 kb |
| Host | smart-359d1a63-e7db-48f4-bfda-0d4318ce701f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222149431 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.4222149431 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.4128653920 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 2754050992 ps |
| CPU time | 242.91 seconds |
| Started | Jul 06 07:34:55 PM PDT 24 |
| Finished | Jul 06 07:38:59 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-99775c11-7755-4a3e-8314-a84032d3228a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128653920 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.4128653920 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3567592731 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 4738246116 ps |
| CPU time | 378.15 seconds |
| Started | Jul 06 07:42:26 PM PDT 24 |
| Finished | Jul 06 07:48:44 PM PDT 24 |
| Peak memory | 609612 kb |
| Host | smart-7fed2eb8-2ae3-4e3d-8be2-a748d546e935 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3567592731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.3567592731 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1941562042 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4188003744 ps |
| CPU time | 166.9 seconds |
| Started | Jul 06 07:36:07 PM PDT 24 |
| Finished | Jul 06 07:38:55 PM PDT 24 |
| Peak memory | 619956 kb |
| Host | smart-a08feedc-a325-44ff-80f4-d297b4e0f607 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19415620 42 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.1941562042 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.4089203168 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 12583142720 ps |
| CPU time | 907.93 seconds |
| Started | Jul 06 07:36:30 PM PDT 24 |
| Finished | Jul 06 07:51:39 PM PDT 24 |
| Peak memory | 622760 kb |
| Host | smart-8732caa7-b9d4-4c66-9b33-8341a7e01ef3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089203168 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.4089203168 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3271443628 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 2605021412 ps |
| CPU time | 124.51 seconds |
| Started | Jul 06 07:34:56 PM PDT 24 |
| Finished | Jul 06 07:37:01 PM PDT 24 |
| Peak memory | 614844 kb |
| Host | smart-b7cc02f5-4b7c-492b-920d-920c0383d3aa |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3271443628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.3271443628 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.579453579 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 2740905433 ps |
| CPU time | 110.89 seconds |
| Started | Jul 06 07:35:05 PM PDT 24 |
| Finished | Jul 06 07:36:57 PM PDT 24 |
| Peak memory | 616712 kb |
| Host | smart-0780f548-4a10-4332-8144-ddda5465b8a6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579453579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.579453579 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3211413102 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 50347614540 ps |
| CPU time | 6246.78 seconds |
| Started | Jul 06 07:34:36 PM PDT 24 |
| Finished | Jul 06 09:18:44 PM PDT 24 |
| Peak memory | 619496 kb |
| Host | smart-a1a02db7-2e8a-4de6-8bfb-4428cd9e763d |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211413102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_dev.3211413102 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.765424594 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 47080079135 ps |
| CPU time | 6005.56 seconds |
| Started | Jul 06 07:37:54 PM PDT 24 |
| Finished | Jul 06 09:18:00 PM PDT 24 |
| Peak memory | 620240 kb |
| Host | smart-258f06df-24b1-4c41-af42-49400427fe62 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765424594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_prod.765424594 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3952831246 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 11214754976 ps |
| CPU time | 1168.73 seconds |
| Started | Jul 06 07:32:19 PM PDT 24 |
| Finished | Jul 06 07:51:49 PM PDT 24 |
| Peak memory | 624708 kb |
| Host | smart-76c53f81-9c1a-4533-8c07-6996ecf60adf |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952831246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.3952831246 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2486262151 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 47795712490 ps |
| CPU time | 5231.55 seconds |
| Started | Jul 06 07:37:12 PM PDT 24 |
| Finished | Jul 06 09:04:24 PM PDT 24 |
| Peak memory | 624988 kb |
| Host | smart-bd555f7b-dbbd-4021-be5d-a209fa7c1c2c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486262151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.2486262151 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3905772709 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 25430400828 ps |
| CPU time | 2651.2 seconds |
| Started | Jul 06 07:34:29 PM PDT 24 |
| Finished | Jul 06 08:18:42 PM PDT 24 |
| Peak memory | 620544 kb |
| Host | smart-74826861-0c96-4b37-8713-9019e368ec50 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3905772709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.3905772709 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3938310383 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 17196869410 ps |
| CPU time | 3902.31 seconds |
| Started | Jul 06 07:36:51 PM PDT 24 |
| Finished | Jul 06 08:41:55 PM PDT 24 |
| Peak memory | 609140 kb |
| Host | smart-ea51a1b4-c8f5-4a41-ad98-5c7329e0fbc1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3938310383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.3938310383 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3883335799 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 18638832200 ps |
| CPU time | 4224.81 seconds |
| Started | Jul 06 07:36:22 PM PDT 24 |
| Finished | Jul 06 08:46:48 PM PDT 24 |
| Peak memory | 609460 kb |
| Host | smart-475a4251-ec7b-43be-806f-dfa36621b740 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3883335799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3883335799 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.695602242 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 24536073208 ps |
| CPU time | 3885.31 seconds |
| Started | Jul 06 07:41:01 PM PDT 24 |
| Finished | Jul 06 08:45:47 PM PDT 24 |
| Peak memory | 609508 kb |
| Host | smart-acf1090b-4aa4-4365-a7dd-9c52dbf5bc7c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695602242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.695602242 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3322646245 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3160151100 ps |
| CPU time | 399.26 seconds |
| Started | Jul 06 07:37:41 PM PDT 24 |
| Finished | Jul 06 07:44:22 PM PDT 24 |
| Peak memory | 609028 kb |
| Host | smart-b3e54246-46cd-4a91-afe5-1724e1104785 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322646245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.3322646245 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.2161390212 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 6325911768 ps |
| CPU time | 986.71 seconds |
| Started | Jul 06 07:38:15 PM PDT 24 |
| Finished | Jul 06 07:54:43 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-0bf060c8-abcf-4f8c-a31d-20e208460003 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2161390212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.2161390212 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.1951199419 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 11025787120 ps |
| CPU time | 2477.63 seconds |
| Started | Jul 06 07:43:21 PM PDT 24 |
| Finished | Jul 06 08:24:39 PM PDT 24 |
| Peak memory | 609040 kb |
| Host | smart-b9adcd06-5963-416a-ab62-657ea25544a7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951199419 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.1951199419 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.822855453 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 3111178241 ps |
| CPU time | 347.64 seconds |
| Started | Jul 06 07:37:00 PM PDT 24 |
| Finished | Jul 06 07:42:49 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-0bcca70d-c058-4be1-b075-330b28a7cf2e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822855453 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.822855453 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3897152352 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 7536728200 ps |
| CPU time | 1555.67 seconds |
| Started | Jul 06 07:34:43 PM PDT 24 |
| Finished | Jul 06 08:00:39 PM PDT 24 |
| Peak memory | 610532 kb |
| Host | smart-9ee9cb36-eeaf-4173-ba0c-96f77db44f9d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3897152352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.3897152352 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2514740994 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 9872530736 ps |
| CPU time | 1370.92 seconds |
| Started | Jul 06 07:34:14 PM PDT 24 |
| Finished | Jul 06 07:57:05 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-2242fcae-7a92-4d56-baad-dc50476ae82c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2514740994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.2514740994 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2434580305 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 8823351372 ps |
| CPU time | 1364.32 seconds |
| Started | Jul 06 07:33:43 PM PDT 24 |
| Finished | Jul 06 07:56:29 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-30df4e0e-a0d2-4362-8cb5-b987a465e2fe |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2434580305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.2434580305 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3234551458 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 4263793034 ps |
| CPU time | 704.97 seconds |
| Started | Jul 06 07:35:18 PM PDT 24 |
| Finished | Jul 06 07:47:04 PM PDT 24 |
| Peak memory | 609228 kb |
| Host | smart-91118eef-d695-4e2f-90e6-08dc9c6b1e8e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3234551458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3234551458 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2536023056 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 3024183644 ps |
| CPU time | 251.82 seconds |
| Started | Jul 06 07:43:09 PM PDT 24 |
| Finished | Jul 06 07:47:21 PM PDT 24 |
| Peak memory | 608424 kb |
| Host | smart-ef20d11d-6566-4db9-a411-7a99b2b07827 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536023056 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.2536023056 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.1769469002 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 2482786870 ps |
| CPU time | 274.01 seconds |
| Started | Jul 06 07:40:12 PM PDT 24 |
| Finished | Jul 06 07:44:47 PM PDT 24 |
| Peak memory | 608464 kb |
| Host | smart-a6ca02a6-1def-47e5-9d12-1672a31a9643 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769469002 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.1769469002 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.2717435084 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4350325440 ps |
| CPU time | 689.7 seconds |
| Started | Jul 06 07:43:13 PM PDT 24 |
| Finished | Jul 06 07:54:43 PM PDT 24 |
| Peak memory | 609080 kb |
| Host | smart-28ac7fc1-408c-4a77-8698-fe60eeacb599 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717435084 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.2717435084 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.1698816581 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 4024165408 ps |
| CPU time | 483.9 seconds |
| Started | Jul 06 07:43:14 PM PDT 24 |
| Finished | Jul 06 07:51:19 PM PDT 24 |
| Peak memory | 608896 kb |
| Host | smart-d4199524-e368-4f58-baba-2fe1d31bf7d5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698816581 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.1698816581 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3010006921 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 8478382187 ps |
| CPU time | 1328.27 seconds |
| Started | Jul 06 07:35:31 PM PDT 24 |
| Finished | Jul 06 07:57:40 PM PDT 24 |
| Peak memory | 611400 kb |
| Host | smart-82ebd6d0-5c71-47a8-9e1c-f5bbfd990202 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010 006921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.3010006921 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.325036659 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 28467908254 ps |
| CPU time | 2996.84 seconds |
| Started | Jul 06 07:39:00 PM PDT 24 |
| Finished | Jul 06 08:28:58 PM PDT 24 |
| Peak memory | 610480 kb |
| Host | smart-0e326222-3877-4461-b257-d78c55d62430 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325 036659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.325036659 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2567368781 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 12601467329 ps |
| CPU time | 1244.13 seconds |
| Started | Jul 06 07:38:25 PM PDT 24 |
| Finished | Jul 06 07:59:10 PM PDT 24 |
| Peak memory | 611188 kb |
| Host | smart-c569d1ac-5a9b-4606-9271-8fbfc1d3da06 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2567368781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2567368781 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.66602949 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 21440908350 ps |
| CPU time | 1583.29 seconds |
| Started | Jul 06 07:42:54 PM PDT 24 |
| Finished | Jul 06 08:09:17 PM PDT 24 |
| Peak memory | 610632 kb |
| Host | smart-0f7023d2-d0c8-4060-952f-fb4faa137be4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 66602949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.66602949 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.509854967 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 9831740592 ps |
| CPU time | 780.02 seconds |
| Started | Jul 06 07:37:35 PM PDT 24 |
| Finished | Jul 06 07:50:36 PM PDT 24 |
| Peak memory | 609488 kb |
| Host | smart-07760bca-7465-43a0-add0-0aa1be5ecb6d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509854967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.509854967 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1878560043 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 6214940628 ps |
| CPU time | 412.15 seconds |
| Started | Jul 06 07:36:25 PM PDT 24 |
| Finished | Jul 06 07:43:19 PM PDT 24 |
| Peak memory | 617252 kb |
| Host | smart-07256c23-e151-44a5-a985-541093bedb7b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1878560043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1878560043 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2154659959 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 6295015580 ps |
| CPU time | 571.31 seconds |
| Started | Jul 06 07:34:16 PM PDT 24 |
| Finished | Jul 06 07:43:48 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-684bcd92-4679-48c5-bc53-46b7a8eb08df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154659959 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.2154659959 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3585376578 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 4321305816 ps |
| CPU time | 449.07 seconds |
| Started | Jul 06 07:41:45 PM PDT 24 |
| Finished | Jul 06 07:49:15 PM PDT 24 |
| Peak memory | 610412 kb |
| Host | smart-b0e917b9-8ff1-4a3c-b014-840d5890a4da |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585376578 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.3585376578 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1530185027 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 4439597992 ps |
| CPU time | 420.85 seconds |
| Started | Jul 06 07:36:49 PM PDT 24 |
| Finished | Jul 06 07:43:50 PM PDT 24 |
| Peak memory | 616164 kb |
| Host | smart-b6d9da23-27d9-4cbb-9f2d-5a8d97f5480d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1530185027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.1530185027 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.242307322 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 12777681652 ps |
| CPU time | 1334.78 seconds |
| Started | Jul 06 07:33:55 PM PDT 24 |
| Finished | Jul 06 07:56:11 PM PDT 24 |
| Peak memory | 611464 kb |
| Host | smart-74f1c295-a0f3-4f00-986f-66ff1e3d3d10 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242307322 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.242307322 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2584556174 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 7258733224 ps |
| CPU time | 432.33 seconds |
| Started | Jul 06 07:41:09 PM PDT 24 |
| Finished | Jul 06 07:48:22 PM PDT 24 |
| Peak memory | 609708 kb |
| Host | smart-a8091bc7-3e4f-45d5-9eb0-5c5f5de2e4b4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584556174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2584556174 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3521128022 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 6768178718 ps |
| CPU time | 683.84 seconds |
| Started | Jul 06 07:34:27 PM PDT 24 |
| Finished | Jul 06 07:45:51 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-9033e96e-7f69-4e67-8fe4-09f559344fbf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521128022 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.3521128022 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1223651373 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 20339915239 ps |
| CPU time | 2061.47 seconds |
| Started | Jul 06 07:34:36 PM PDT 24 |
| Finished | Jul 06 08:08:59 PM PDT 24 |
| Peak memory | 611188 kb |
| Host | smart-d094c7fb-d8a2-45bb-9503-ea1ae0d61a2f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1223651373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1223651373 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1638843982 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 20748635340 ps |
| CPU time | 1505.7 seconds |
| Started | Jul 06 07:41:14 PM PDT 24 |
| Finished | Jul 06 08:06:20 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-d9851e50-851c-49ff-b0bc-4ea494cebc58 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1638843982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1638843982 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2378675803 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 36481985300 ps |
| CPU time | 3551.41 seconds |
| Started | Jul 06 07:37:22 PM PDT 24 |
| Finished | Jul 06 08:36:34 PM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-3bdbb476-af0e-4807-8686-cbd1660b3ffc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378675803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2378675803 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2986594879 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 6127116312 ps |
| CPU time | 348.16 seconds |
| Started | Jul 06 07:42:03 PM PDT 24 |
| Finished | Jul 06 07:47:52 PM PDT 24 |
| Peak memory | 610892 kb |
| Host | smart-1ce92978-fd7e-4d6f-affe-7020c911db15 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2986594879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2986594879 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2784704561 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2965140746 ps |
| CPU time | 335.99 seconds |
| Started | Jul 06 07:36:14 PM PDT 24 |
| Finished | Jul 06 07:41:51 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-fd6881ff-1aff-4a54-bee5-6c40d45772ec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784704561 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.2784704561 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1634997267 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 5362380966 ps |
| CPU time | 304.04 seconds |
| Started | Jul 06 07:35:31 PM PDT 24 |
| Finished | Jul 06 07:40:36 PM PDT 24 |
| Peak memory | 617384 kb |
| Host | smart-2502ee55-529a-4b15-804d-5f918a912fb2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1634997267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.1634997267 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3982529888 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 4600210698 ps |
| CPU time | 496.61 seconds |
| Started | Jul 06 07:38:09 PM PDT 24 |
| Finished | Jul 06 07:46:26 PM PDT 24 |
| Peak memory | 610448 kb |
| Host | smart-52f3cd1b-a1e5-40e3-9329-95f30082a089 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39825298 88 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3982529888 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.283693661 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 4729028856 ps |
| CPU time | 358.21 seconds |
| Started | Jul 06 07:42:15 PM PDT 24 |
| Finished | Jul 06 07:48:13 PM PDT 24 |
| Peak memory | 610888 kb |
| Host | smart-6b54cd7d-1449-44eb-bf0d-897a5e9f611a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=283693661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.283693661 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3650794802 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 6076525528 ps |
| CPU time | 403.68 seconds |
| Started | Jul 06 07:46:11 PM PDT 24 |
| Finished | Jul 06 07:52:56 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-e7049555-c0ce-4515-bef5-7b123e4c5a78 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650794802 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.3650794802 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3268308538 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 7626775546 ps |
| CPU time | 1340.07 seconds |
| Started | Jul 06 07:36:10 PM PDT 24 |
| Finished | Jul 06 07:58:31 PM PDT 24 |
| Peak memory | 609500 kb |
| Host | smart-9397a34c-e213-4376-ac4c-b02c2a434e3e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268308538 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.3268308538 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.666016227 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 4148889470 ps |
| CPU time | 509.56 seconds |
| Started | Jul 06 07:34:17 PM PDT 24 |
| Finished | Jul 06 07:42:47 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-88f7d951-ff08-4d6b-94e0-05c6a8b11770 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666016227 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.666016227 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.551339822 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 7021313264 ps |
| CPU time | 697.75 seconds |
| Started | Jul 06 07:44:55 PM PDT 24 |
| Finished | Jul 06 07:56:33 PM PDT 24 |
| Peak memory | 609084 kb |
| Host | smart-d85d7cdc-fe86-4dff-b062-bca30c83e8f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551339822 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.551339822 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2632311161 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 4398764624 ps |
| CPU time | 605.86 seconds |
| Started | Jul 06 07:36:31 PM PDT 24 |
| Finished | Jul 06 07:46:38 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-0e2291d4-df65-45b3-a8df-5fa175f7b7ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263 2311161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.2632311161 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.619736616 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 9190382510 ps |
| CPU time | 668.98 seconds |
| Started | Jul 06 07:37:48 PM PDT 24 |
| Finished | Jul 06 07:48:57 PM PDT 24 |
| Peak memory | 609472 kb |
| Host | smart-ec3a6504-164d-4c83-ac5d-96730ee1832d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619736616 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.619736616 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1401231084 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 11175664832 ps |
| CPU time | 1936.14 seconds |
| Started | Jul 06 07:36:14 PM PDT 24 |
| Finished | Jul 06 08:08:32 PM PDT 24 |
| Peak memory | 611172 kb |
| Host | smart-8909a6a9-f173-405c-91b8-286235c7e9bf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1401231084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.1401231084 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3903492960 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 6579823544 ps |
| CPU time | 673.45 seconds |
| Started | Jul 06 07:36:49 PM PDT 24 |
| Finished | Jul 06 07:48:03 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-9a2f7249-72d0-4551-a3ec-bafd2dc3c9c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903492960 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.3903492960 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2302973675 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5091582052 ps |
| CPU time | 725.05 seconds |
| Started | Jul 06 07:35:57 PM PDT 24 |
| Finished | Jul 06 07:48:02 PM PDT 24 |
| Peak memory | 641612 kb |
| Host | smart-1b4356d1-7eaa-4dd9-b2cc-55b1b4aeea1a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2302973675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.2302973675 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.274365459 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 3501808720 ps |
| CPU time | 291.62 seconds |
| Started | Jul 06 07:43:06 PM PDT 24 |
| Finished | Jul 06 07:47:58 PM PDT 24 |
| Peak memory | 608704 kb |
| Host | smart-7786c5cb-a79e-4d12-a739-5c0de77d34d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274365459 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_rstmgr_smoketest.274365459 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2907275005 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 5116538700 ps |
| CPU time | 529.8 seconds |
| Started | Jul 06 07:34:51 PM PDT 24 |
| Finished | Jul 06 07:43:42 PM PDT 24 |
| Peak memory | 609444 kb |
| Host | smart-6514c7fc-257d-44fd-ac98-017947ea498b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907275005 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.2907275005 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2740417946 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 2625179750 ps |
| CPU time | 292.08 seconds |
| Started | Jul 06 07:36:02 PM PDT 24 |
| Finished | Jul 06 07:40:55 PM PDT 24 |
| Peak memory | 608428 kb |
| Host | smart-ffc08072-834d-4445-8458-98fd806808f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740417946 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.2740417946 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1809966247 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2798517000 ps |
| CPU time | 234.26 seconds |
| Started | Jul 06 07:41:54 PM PDT 24 |
| Finished | Jul 06 07:45:49 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-8bc6de5e-67d1-4223-9c1e-94aa19d87e6b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1809966247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.1809966247 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2726099331 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2949562958 ps |
| CPU time | 265.82 seconds |
| Started | Jul 06 07:41:31 PM PDT 24 |
| Finished | Jul 06 07:45:57 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-18299325-cef6-4a36-a2aa-4c3695e2ad6b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726099331 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.2726099331 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1520812549 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2179886258 ps |
| CPU time | 250.85 seconds |
| Started | Jul 06 07:41:39 PM PDT 24 |
| Finished | Jul 06 07:45:51 PM PDT 24 |
| Peak memory | 616592 kb |
| Host | smart-4680d0d5-dc5b-4385-8070-1dd986e7a6b1 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520812549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.1520812549 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1848506874 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 4642074536 ps |
| CPU time | 790.21 seconds |
| Started | Jul 06 07:36:44 PM PDT 24 |
| Finished | Jul 06 07:49:54 PM PDT 24 |
| Peak memory | 610428 kb |
| Host | smart-6d4983c3-9929-411d-84cb-77453bd3927d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18485 06874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.1848506874 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3671854366 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 5277460000 ps |
| CPU time | 1208.62 seconds |
| Started | Jul 06 07:36:38 PM PDT 24 |
| Finished | Jul 06 07:56:47 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-b594cf48-b38f-4a43-b20b-7a06edcf96ac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3671854366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.3671854366 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.770923566 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 6061255032 ps |
| CPU time | 717.94 seconds |
| Started | Jul 06 07:42:37 PM PDT 24 |
| Finished | Jul 06 07:54:36 PM PDT 24 |
| Peak memory | 623712 kb |
| Host | smart-8490d01d-7f30-4ee8-b03c-611a7145f903 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770923566 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.770923566 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1993135430 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 5747507356 ps |
| CPU time | 446.91 seconds |
| Started | Jul 06 07:41:26 PM PDT 24 |
| Finished | Jul 06 07:48:54 PM PDT 24 |
| Peak memory | 624132 kb |
| Host | smart-8c4129a5-4ed1-4305-b322-0381746a0851 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993135430 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.1993135430 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2436192705 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 4877043720 ps |
| CPU time | 625.98 seconds |
| Started | Jul 06 07:40:53 PM PDT 24 |
| Finished | Jul 06 07:51:20 PM PDT 24 |
| Peak memory | 621032 kb |
| Host | smart-a3925bbd-bc17-4cd3-b54a-ea5d72cc77ce |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243619 2705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2436192705 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1257613379 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 3025270460 ps |
| CPU time | 307.08 seconds |
| Started | Jul 06 07:43:46 PM PDT 24 |
| Finished | Jul 06 07:48:55 PM PDT 24 |
| Peak memory | 608804 kb |
| Host | smart-18bc478c-abc4-4c34-b13a-9ffd06a421b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257613379 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.1257613379 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.2653893777 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 2477373528 ps |
| CPU time | 212.71 seconds |
| Started | Jul 06 07:37:44 PM PDT 24 |
| Finished | Jul 06 07:41:18 PM PDT 24 |
| Peak memory | 608468 kb |
| Host | smart-41535a6c-faea-471d-a32a-a3a599bf5cba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653893777 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.2653893777 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3631761997 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 2679372440 ps |
| CPU time | 331.94 seconds |
| Started | Jul 06 07:44:46 PM PDT 24 |
| Finished | Jul 06 07:50:19 PM PDT 24 |
| Peak memory | 608328 kb |
| Host | smart-7f78be97-86f2-4402-8418-c3367ee3fb41 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631761997 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.3631761997 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2790455028 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 3478492878 ps |
| CPU time | 319.48 seconds |
| Started | Jul 06 07:39:52 PM PDT 24 |
| Finished | Jul 06 07:45:12 PM PDT 24 |
| Peak memory | 609092 kb |
| Host | smart-69f35599-81b4-457c-9022-62036c516b9b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790455 028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.2790455028 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1139877905 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4571018760 ps |
| CPU time | 432.04 seconds |
| Started | Jul 06 07:32:16 PM PDT 24 |
| Finished | Jul 06 07:39:29 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-49d34004-c3c3-4c8e-aba1-c52b4840de87 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139877905 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.1139877905 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.4289725148 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7858536408 ps |
| CPU time | 1226.95 seconds |
| Started | Jul 06 07:33:21 PM PDT 24 |
| Finished | Jul 06 07:53:49 PM PDT 24 |
| Peak memory | 609456 kb |
| Host | smart-f0e7bbca-f74d-430f-9fdb-60f3e65a2bb9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289725148 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.4289725148 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2327058098 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 9540670520 ps |
| CPU time | 788.25 seconds |
| Started | Jul 06 07:39:12 PM PDT 24 |
| Finished | Jul 06 07:52:21 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-2d288172-14ac-4d10-b3ce-deaf4349eaca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327058098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.2327058098 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3699395684 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 7337847659 ps |
| CPU time | 748.66 seconds |
| Started | Jul 06 07:34:50 PM PDT 24 |
| Finished | Jul 06 07:47:19 PM PDT 24 |
| Peak memory | 624840 kb |
| Host | smart-baa344cd-afde-4164-b963-3bf6ea90a413 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699395684 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.3699395684 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.1737216711 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 3669053637 ps |
| CPU time | 367.61 seconds |
| Started | Jul 06 07:32:19 PM PDT 24 |
| Finished | Jul 06 07:38:27 PM PDT 24 |
| Peak memory | 618272 kb |
| Host | smart-a90815cf-03da-41b3-a573-af012806bb9b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737216711 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.1737216711 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1657172402 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3321926688 ps |
| CPU time | 327.13 seconds |
| Started | Jul 06 07:33:53 PM PDT 24 |
| Finished | Jul 06 07:39:21 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-86eec1a4-382d-4e0b-a8a8-87389a388b59 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657172402 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.1657172402 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1503791717 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 8119972303 ps |
| CPU time | 1009.22 seconds |
| Started | Jul 06 07:40:15 PM PDT 24 |
| Finished | Jul 06 07:57:05 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-dd03cc07-3117-4e4c-8dda-9fd9c29cbe9f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503791717 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.1503791717 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1552955599 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 3807373144 ps |
| CPU time | 491.85 seconds |
| Started | Jul 06 07:39:31 PM PDT 24 |
| Finished | Jul 06 07:47:44 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-2f674f44-d30c-4ebd-a564-9e83f704b0ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552955599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.1552955599 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4074609156 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 4823242448 ps |
| CPU time | 603.3 seconds |
| Started | Jul 06 07:38:28 PM PDT 24 |
| Finished | Jul 06 07:48:32 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-a5deecd8-91cc-48a8-81ef-68154e09d909 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074609156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4074609156 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1520418396 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 4729431544 ps |
| CPU time | 519.73 seconds |
| Started | Jul 06 07:41:16 PM PDT 24 |
| Finished | Jul 06 07:49:56 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-0d4bba7a-33fb-4bc7-90ff-aca3d36ded6a |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520418396 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1520418396 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2941212499 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3157659448 ps |
| CPU time | 189.38 seconds |
| Started | Jul 06 07:44:37 PM PDT 24 |
| Finished | Jul 06 07:47:47 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-8bef89ac-380a-43f3-a5b2-f8e6414af6b4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941212499 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.2941212499 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.130796796 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 20279453395 ps |
| CPU time | 3631.85 seconds |
| Started | Jul 06 07:35:22 PM PDT 24 |
| Finished | Jul 06 08:35:55 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-53df60dd-f595-490c-b565-c5d12bc32972 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130796796 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.130796796 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2785067020 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 4259431766 ps |
| CPU time | 638.59 seconds |
| Started | Jul 06 07:37:51 PM PDT 24 |
| Finished | Jul 06 07:48:32 PM PDT 24 |
| Peak memory | 613472 kb |
| Host | smart-f0e5c96e-53bd-4bef-94cd-deacbf696f04 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785067020 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.2785067020 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3628650787 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 3066281077 ps |
| CPU time | 354.46 seconds |
| Started | Jul 06 07:36:27 PM PDT 24 |
| Finished | Jul 06 07:42:23 PM PDT 24 |
| Peak memory | 613480 kb |
| Host | smart-cb2c90ce-fdd5-4f9a-8568-207dac76d60f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628650787 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.3628650787 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2137612543 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 3611944356 ps |
| CPU time | 473.42 seconds |
| Started | Jul 06 07:35:37 PM PDT 24 |
| Finished | Jul 06 07:43:32 PM PDT 24 |
| Peak memory | 608716 kb |
| Host | smart-9e54521b-91ce-4802-92df-9bcde7d3049f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137612543 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.2137612543 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1966569770 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 24241739436 ps |
| CPU time | 1828.63 seconds |
| Started | Jul 06 07:34:56 PM PDT 24 |
| Finished | Jul 06 08:05:25 PM PDT 24 |
| Peak memory | 615216 kb |
| Host | smart-05dcf394-b61c-40bc-a3ba-7e199ac17426 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19665697 70 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.1966569770 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.4269238584 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 8276713864 ps |
| CPU time | 1790.83 seconds |
| Started | Jul 06 07:33:06 PM PDT 24 |
| Finished | Jul 06 08:02:58 PM PDT 24 |
| Peak memory | 621720 kb |
| Host | smart-7a2096d0-b44b-4ba2-a3c6-b7881bb19fc2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4269238584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.4269238584 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.3646458524 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 2913472084 ps |
| CPU time | 224.15 seconds |
| Started | Jul 06 07:43:21 PM PDT 24 |
| Finished | Jul 06 07:47:06 PM PDT 24 |
| Peak memory | 614196 kb |
| Host | smart-fd18558c-dfc8-4654-b23f-d784d334c7a6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646458524 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.3646458524 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.375294980 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 4557729500 ps |
| CPU time | 773.87 seconds |
| Started | Jul 06 07:36:33 PM PDT 24 |
| Finished | Jul 06 07:49:28 PM PDT 24 |
| Peak memory | 624692 kb |
| Host | smart-9d9329e5-d6ff-400b-948f-62400fc66dad |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375294980 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.375294980 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1527876259 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 8003303150 ps |
| CPU time | 1969.35 seconds |
| Started | Jul 06 07:35:21 PM PDT 24 |
| Finished | Jul 06 08:08:12 PM PDT 24 |
| Peak memory | 622852 kb |
| Host | smart-ddb1efdd-a43a-4964-9123-3b20c42e3d58 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527876259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.1527876259 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1084694959 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 4353516293 ps |
| CPU time | 509.02 seconds |
| Started | Jul 06 07:36:48 PM PDT 24 |
| Finished | Jul 06 07:45:18 PM PDT 24 |
| Peak memory | 623152 kb |
| Host | smart-5a8b013c-388b-4201-b7c0-8222c804ef4c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084694959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1084694959 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3354798439 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 78468517178 ps |
| CPU time | 12943 seconds |
| Started | Jul 06 07:38:46 PM PDT 24 |
| Finished | Jul 06 11:14:31 PM PDT 24 |
| Peak memory | 634968 kb |
| Host | smart-a315ea70-d21f-415a-b8a4-4a46c3cf8d6d |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3354798439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.3354798439 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3311281434 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 4259601832 ps |
| CPU time | 633.33 seconds |
| Started | Jul 06 07:32:45 PM PDT 24 |
| Finished | Jul 06 07:43:19 PM PDT 24 |
| Peak memory | 624604 kb |
| Host | smart-7a11faa1-9707-4948-a387-72cc9f297e37 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311281434 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.3311281434 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2601016372 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 4119157060 ps |
| CPU time | 734.69 seconds |
| Started | Jul 06 07:36:13 PM PDT 24 |
| Finished | Jul 06 07:48:28 PM PDT 24 |
| Peak memory | 624588 kb |
| Host | smart-093070de-9697-484b-8aa4-9d7ff823e5fc |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601016372 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.2601016372 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.652483066 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4544101024 ps |
| CPU time | 559.38 seconds |
| Started | Jul 06 07:38:21 PM PDT 24 |
| Finished | Jul 06 07:47:41 PM PDT 24 |
| Peak memory | 624608 kb |
| Host | smart-2178c121-02d5-4a99-b9bf-66b9a5cbb7d5 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652483066 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.652483066 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.3389948327 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 2055163935 ps |
| CPU time | 115.68 seconds |
| Started | Jul 06 07:40:19 PM PDT 24 |
| Finished | Jul 06 07:42:16 PM PDT 24 |
| Peak memory | 621752 kb |
| Host | smart-13e6b723-d76c-453f-865f-0d084c5bf08e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3389948327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.3389948327 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.1095564725 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 2830230460 ps |
| CPU time | 170.76 seconds |
| Started | Jul 06 07:41:17 PM PDT 24 |
| Finished | Jul 06 07:44:08 PM PDT 24 |
| Peak memory | 620020 kb |
| Host | smart-1c6d97f5-5f59-4392-8f09-d2c4d99ed6d1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095564725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.1095564725 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.2211213001 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 3012989015 ps |
| CPU time | 201.35 seconds |
| Started | Jul 06 07:39:45 PM PDT 24 |
| Finished | Jul 06 07:43:06 PM PDT 24 |
| Peak memory | 624364 kb |
| Host | smart-e3d383c6-9ac1-48f1-9a52-fbff6fbf167d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2211213001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.2211213001 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.1941185619 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 15429291428 ps |
| CPU time | 4473.51 seconds |
| Started | Jul 06 07:49:18 PM PDT 24 |
| Finished | Jul 06 09:03:53 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-6d4ec5fe-6fca-4cec-aab7-b06a7b9fbb07 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941185619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.1941185619 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.253293164 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 14917754891 ps |
| CPU time | 4173.02 seconds |
| Started | Jul 06 07:48:49 PM PDT 24 |
| Finished | Jul 06 08:58:22 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-63fec453-776a-42f0-860f-be4d1b5b2a1e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253293164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.253293164 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.447159690 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 15661150308 ps |
| CPU time | 4154.43 seconds |
| Started | Jul 06 07:48:24 PM PDT 24 |
| Finished | Jul 06 08:57:41 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-83e62ae3-4b18-4aaf-96d3-d2068af3866d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447159690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.rom_e2e_asm_init_prod_end.447159690 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.3308051874 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 14937260844 ps |
| CPU time | 3768.66 seconds |
| Started | Jul 06 07:47:37 PM PDT 24 |
| Finished | Jul 06 08:50:26 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-34aecf18-0308-4905-96df-2af69961ed02 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308051874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.3308051874 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3759049929 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 11982388978 ps |
| CPU time | 3023.07 seconds |
| Started | Jul 06 07:49:42 PM PDT 24 |
| Finished | Jul 06 08:40:06 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-49897f16-ba83-45e2-96d8-bab0cc502153 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759049929 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.3759049929 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1000377950 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 14756328954 ps |
| CPU time | 3453.48 seconds |
| Started | Jul 06 07:47:34 PM PDT 24 |
| Finished | Jul 06 08:45:09 PM PDT 24 |
| Peak memory | 609072 kb |
| Host | smart-11371dac-61d2-40ca-9435-7fb25849cfa1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000377950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1000377950 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2060181346 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 15125132228 ps |
| CPU time | 3980.27 seconds |
| Started | Jul 06 07:48:23 PM PDT 24 |
| Finished | Jul 06 08:54:44 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-cc5bf466-6410-49f7-b57a-e141b9852ad1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060181346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.2060181346 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3334089014 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 15006843880 ps |
| CPU time | 4125.12 seconds |
| Started | Jul 06 07:48:20 PM PDT 24 |
| Finished | Jul 06 08:57:06 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-8df7ed93-7033-47d3-9f5f-194bc0f44dcf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334089014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.3334089014 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.229121020 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 15426068886 ps |
| CPU time | 3930.81 seconds |
| Started | Jul 06 07:48:45 PM PDT 24 |
| Finished | Jul 06 08:54:17 PM PDT 24 |
| Peak memory | 608912 kb |
| Host | smart-267a2ce4-dd44-4899-b1ac-4dfa0c8a1d79 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229121020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_s hutdown_exception_c.229121020 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.1859883857 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 22952205508 ps |
| CPU time | 3438.04 seconds |
| Started | Jul 06 07:49:40 PM PDT 24 |
| Finished | Jul 06 08:46:59 PM PDT 24 |
| Peak memory | 611404 kb |
| Host | smart-b30a75f3-7f42-4d05-a05b-8423edc6f471 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859883857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.1859883857 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.2742732345 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 15204288184 ps |
| CPU time | 4009.69 seconds |
| Started | Jul 06 07:46:40 PM PDT 24 |
| Finished | Jul 06 08:53:30 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-3d0c214e-3893-4622-bb1c-2214b35ba2dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=2742732345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.2742732345 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.3129773942 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 18019771538 ps |
| CPU time | 5038.24 seconds |
| Started | Jul 06 07:49:07 PM PDT 24 |
| Finished | Jul 06 09:13:07 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-3533dd58-bc37-4750-b12b-b564051642a6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129773942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.3129773942 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.2275560075 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3413147682 ps |
| CPU time | 446.6 seconds |
| Started | Jul 06 07:42:38 PM PDT 24 |
| Finished | Jul 06 07:50:05 PM PDT 24 |
| Peak memory | 608944 kb |
| Host | smart-14a23e8b-0404-42a1-84b6-4b386698e276 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275560075 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.2275560075 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.3438375540 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 4852354633 ps |
| CPU time | 235.01 seconds |
| Started | Jul 06 07:44:31 PM PDT 24 |
| Finished | Jul 06 07:48:27 PM PDT 24 |
| Peak memory | 623112 kb |
| Host | smart-6a112758-a0cb-4890-b217-13db0634898b |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3438375540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.3438375540 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.1072177642 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 3109803597 ps |
| CPU time | 124.41 seconds |
| Started | Jul 06 07:42:54 PM PDT 24 |
| Finished | Jul 06 07:44:59 PM PDT 24 |
| Peak memory | 617876 kb |
| Host | smart-9619c155-640c-4a9b-8195-bbfb82749a41 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072177642 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.1072177642 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1112718472 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 3439806930 ps |
| CPU time | 400.98 seconds |
| Started | Jul 06 07:57:09 PM PDT 24 |
| Finished | Jul 06 08:03:50 PM PDT 24 |
| Peak memory | 649428 kb |
| Host | smart-f7ab320e-ed75-4b3e-86c0-38de73e38c3e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112718472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1112718472 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1050712936 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 12428411228 ps |
| CPU time | 1190.03 seconds |
| Started | Jul 06 07:56:42 PM PDT 24 |
| Finished | Jul 06 08:16:33 PM PDT 24 |
| Peak memory | 622504 kb |
| Host | smart-aa0eceb7-54cd-4c7f-8e3c-e3f8b221edc0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050712936 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.1050712936 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3302778290 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 8255939248 ps |
| CPU time | 1553.15 seconds |
| Started | Jul 06 07:56:29 PM PDT 24 |
| Finished | Jul 06 08:22:22 PM PDT 24 |
| Peak memory | 622004 kb |
| Host | smart-604e033a-6463-4fae-ade0-39b2f292fb2e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3302778290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.3302778290 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1472971421 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 3623515052 ps |
| CPU time | 392.55 seconds |
| Started | Jul 06 07:57:29 PM PDT 24 |
| Finished | Jul 06 08:04:02 PM PDT 24 |
| Peak memory | 618704 kb |
| Host | smart-532c6d67-40f0-421b-a65a-c7a06670ea9e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472971421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1472971421 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.4092449717 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 11023745423 ps |
| CPU time | 997.27 seconds |
| Started | Jul 06 07:56:49 PM PDT 24 |
| Finished | Jul 06 08:13:27 PM PDT 24 |
| Peak memory | 623656 kb |
| Host | smart-3f90b19e-bea2-4c61-b79f-e303676077df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092449717 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.4092449717 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.62864921 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 7559467278 ps |
| CPU time | 1464.87 seconds |
| Started | Jul 06 07:56:09 PM PDT 24 |
| Finished | Jul 06 08:20:35 PM PDT 24 |
| Peak memory | 618544 kb |
| Host | smart-eafcfd10-29d7-43a0-9c42-2346dcb171d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=62864921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.62864921 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2419102640 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 11738008205 ps |
| CPU time | 774.1 seconds |
| Started | Jul 06 07:56:24 PM PDT 24 |
| Finished | Jul 06 08:09:18 PM PDT 24 |
| Peak memory | 623740 kb |
| Host | smart-c51d5ae0-1e19-407c-aac1-67dda344e3f1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419102640 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.2419102640 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.824448998 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 8851576994 ps |
| CPU time | 1836.81 seconds |
| Started | Jul 06 08:00:20 PM PDT 24 |
| Finished | Jul 06 08:30:59 PM PDT 24 |
| Peak memory | 622004 kb |
| Host | smart-0e7aeadf-82c0-400d-ae7b-e02c1b0caba3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=824448998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.824448998 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2095118640 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 4733049193 ps |
| CPU time | 358.42 seconds |
| Started | Jul 06 07:57:01 PM PDT 24 |
| Finished | Jul 06 08:03:00 PM PDT 24 |
| Peak memory | 621364 kb |
| Host | smart-d00e78b6-7436-4c51-8796-95b856a43032 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095118640 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.2095118640 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1241899693 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 7570230304 ps |
| CPU time | 1677.88 seconds |
| Started | Jul 06 07:57:52 PM PDT 24 |
| Finished | Jul 06 08:25:51 PM PDT 24 |
| Peak memory | 621752 kb |
| Host | smart-b53e3806-aa1d-42f4-b890-56b674225e70 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1241899693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.1241899693 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3240512103 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 4634597567 ps |
| CPU time | 478.14 seconds |
| Started | Jul 06 07:57:03 PM PDT 24 |
| Finished | Jul 06 08:05:01 PM PDT 24 |
| Peak memory | 621364 kb |
| Host | smart-e1e34fdf-5f9d-4fca-9081-6a01320170cc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240512103 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.3240512103 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2643330506 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 8614394136 ps |
| CPU time | 1645.18 seconds |
| Started | Jul 06 08:01:46 PM PDT 24 |
| Finished | Jul 06 08:29:13 PM PDT 24 |
| Peak memory | 621620 kb |
| Host | smart-cab3b1b6-f95d-485b-a5a5-fcdb7c546683 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2643330506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.2643330506 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2452259188 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 3887994080 ps |
| CPU time | 422.3 seconds |
| Started | Jul 06 07:58:12 PM PDT 24 |
| Finished | Jul 06 08:05:15 PM PDT 24 |
| Peak memory | 618704 kb |
| Host | smart-800bd2c0-b674-46dd-928b-d3728a23c223 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452259188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2452259188 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1408484105 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 8237306172 ps |
| CPU time | 1493.05 seconds |
| Started | Jul 06 07:57:35 PM PDT 24 |
| Finished | Jul 06 08:22:29 PM PDT 24 |
| Peak memory | 621980 kb |
| Host | smart-bdcf704c-27ab-4888-ac5d-349a281e578d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1408484105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.1408484105 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3224142883 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 8911509260 ps |
| CPU time | 2149.27 seconds |
| Started | Jul 06 07:58:28 PM PDT 24 |
| Finished | Jul 06 08:34:19 PM PDT 24 |
| Peak memory | 622012 kb |
| Host | smart-0118c8fe-c2a8-467d-a738-a029691079f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3224142883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.3224142883 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.1187897716 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 6351352872 ps |
| CPU time | 988.34 seconds |
| Started | Jul 06 07:59:52 PM PDT 24 |
| Finished | Jul 06 08:16:21 PM PDT 24 |
| Peak memory | 649820 kb |
| Host | smart-ac9a7ac8-8154-4fc0-87cf-c281dac1b487 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1187897716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.1187897716 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2869668949 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 3672477550 ps |
| CPU time | 537.34 seconds |
| Started | Jul 06 07:58:22 PM PDT 24 |
| Finished | Jul 06 08:07:20 PM PDT 24 |
| Peak memory | 621720 kb |
| Host | smart-46bcf920-d24c-4716-a66a-496acb5fba3e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2869668949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.2869668949 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3864761612 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 9035068234 ps |
| CPU time | 1692.97 seconds |
| Started | Jul 06 07:58:44 PM PDT 24 |
| Finished | Jul 06 08:26:58 PM PDT 24 |
| Peak memory | 618732 kb |
| Host | smart-9304ca0f-e095-412f-b621-3a1837501d14 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3864761612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.3864761612 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.228925252 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 13772673386 ps |
| CPU time | 1343.15 seconds |
| Started | Jul 06 07:43:35 PM PDT 24 |
| Finished | Jul 06 08:05:59 PM PDT 24 |
| Peak memory | 607664 kb |
| Host | smart-25903a8f-8869-442d-be75-65c682640637 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228925252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.228925252 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4244548502 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5039939950 ps |
| CPU time | 543.24 seconds |
| Started | Jul 06 07:51:29 PM PDT 24 |
| Finished | Jul 06 08:00:32 PM PDT 24 |
| Peak memory | 620596 kb |
| Host | smart-d5cde818-87f0-4f40-bc47-d9bafe360e38 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4 244548502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.4244548502 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.3919028021 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 3404400888 ps |
| CPU time | 445.76 seconds |
| Started | Jul 06 07:43:46 PM PDT 24 |
| Finished | Jul 06 07:51:12 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-b8e6ee50-55ea-4718-81d9-b5bef655eb84 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3919028021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.3919028021 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.565337683 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 20133432236 ps |
| CPU time | 727.14 seconds |
| Started | Jul 06 07:48:16 PM PDT 24 |
| Finished | Jul 06 08:00:24 PM PDT 24 |
| Peak memory | 619160 kb |
| Host | smart-d5b40894-1c62-4be1-9a33-b40e511ee379 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=565337683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.565337683 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.4064464696 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 2395379790 ps |
| CPU time | 240.55 seconds |
| Started | Jul 06 07:49:17 PM PDT 24 |
| Finished | Jul 06 07:53:18 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-52fa0a71-3d80-43bf-9f5f-8d36e7476731 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064464696 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.4064464696 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.734935909 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 2795264673 ps |
| CPU time | 247.33 seconds |
| Started | Jul 06 07:47:36 PM PDT 24 |
| Finished | Jul 06 07:51:44 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-b7a83d82-4e4a-4cf2-9511-dd21f6ef8f65 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7349 35909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.734935909 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2442836037 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 2903412934 ps |
| CPU time | 227.87 seconds |
| Started | Jul 06 07:51:44 PM PDT 24 |
| Finished | Jul 06 07:55:32 PM PDT 24 |
| Peak memory | 608732 kb |
| Host | smart-360ca514-c15d-456e-812b-786c533703b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442836037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.2442836037 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.3945027347 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2619300352 ps |
| CPU time | 208.34 seconds |
| Started | Jul 06 07:49:39 PM PDT 24 |
| Finished | Jul 06 07:53:07 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-e9de8986-9d78-40c1-8809-401cb1218f7f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945027347 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.3945027347 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.2402056920 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 2691429784 ps |
| CPU time | 241.1 seconds |
| Started | Jul 06 07:48:40 PM PDT 24 |
| Finished | Jul 06 07:52:42 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-cdb0277d-a6e5-468a-9e2e-5c0a87f6c58e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402056920 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.2402056920 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.177634365 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 3620772345 ps |
| CPU time | 353.58 seconds |
| Started | Jul 06 07:49:25 PM PDT 24 |
| Finished | Jul 06 07:55:20 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-01c9430b-0f0d-4664-93e7-418272132c94 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177634365 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.177634365 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.1107453941 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 3319261662 ps |
| CPU time | 269.86 seconds |
| Started | Jul 06 07:52:13 PM PDT 24 |
| Finished | Jul 06 07:56:43 PM PDT 24 |
| Peak memory | 608776 kb |
| Host | smart-6cd2c595-3997-43c7-9399-f2b740f5ec64 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107453941 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.1107453941 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.762364957 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 3247435367 ps |
| CPU time | 309.66 seconds |
| Started | Jul 06 07:49:25 PM PDT 24 |
| Finished | Jul 06 07:54:35 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-a85a4384-3dd2-4732-88a9-7b95200bcaa0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=762364957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.762364957 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1472123146 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 4449049030 ps |
| CPU time | 582.57 seconds |
| Started | Jul 06 07:49:47 PM PDT 24 |
| Finished | Jul 06 07:59:30 PM PDT 24 |
| Peak memory | 619284 kb |
| Host | smart-cd4f8195-0849-4231-8df3-d5649ab6aa5b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1472123146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.1472123146 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1586414403 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 6258994836 ps |
| CPU time | 1485.8 seconds |
| Started | Jul 06 07:48:34 PM PDT 24 |
| Finished | Jul 06 08:13:21 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-90437ae1-e9ea-4cff-b768-731d88ff0247 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1586414403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.1586414403 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2351367165 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 8912430004 ps |
| CPU time | 2284.62 seconds |
| Started | Jul 06 07:50:10 PM PDT 24 |
| Finished | Jul 06 08:28:15 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-0261ac63-b721-41cf-88c3-4163849c43fe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351367165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.2351367165 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2329797170 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 4349541212 ps |
| CPU time | 451.15 seconds |
| Started | Jul 06 07:48:40 PM PDT 24 |
| Finished | Jul 06 07:56:12 PM PDT 24 |
| Peak memory | 649556 kb |
| Host | smart-8640cef7-56b5-44be-b8f4-bd15acba73c3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329797170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.2329797170 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3423903176 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 14273943580 ps |
| CPU time | 1889.42 seconds |
| Started | Jul 06 07:49:21 PM PDT 24 |
| Finished | Jul 06 08:20:51 PM PDT 24 |
| Peak memory | 611144 kb |
| Host | smart-3a8cb224-c3b7-4a0f-84e5-eceef513617c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423903176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.3423903176 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2184982463 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 7942046866 ps |
| CPU time | 1462.18 seconds |
| Started | Jul 06 07:48:03 PM PDT 24 |
| Finished | Jul 06 08:12:25 PM PDT 24 |
| Peak memory | 608936 kb |
| Host | smart-c3c5fdee-2d27-4b77-b821-a4a8ae24933a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2184982463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.2184982463 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1047194128 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 4420413258 ps |
| CPU time | 573.75 seconds |
| Started | Jul 06 07:49:25 PM PDT 24 |
| Finished | Jul 06 07:59:00 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-de5faaaa-30ec-4dc9-b2a6-107071b2fa3b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1047194128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.1047194128 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4125093319 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 255284736000 ps |
| CPU time | 12784.6 seconds |
| Started | Jul 06 07:49:44 PM PDT 24 |
| Finished | Jul 06 11:22:50 PM PDT 24 |
| Peak memory | 610996 kb |
| Host | smart-47abde00-814d-44fa-97bf-3ca6f6d099c2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4125093319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4125093319 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.2282299703 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2856010536 ps |
| CPU time | 352.89 seconds |
| Started | Jul 06 07:49:26 PM PDT 24 |
| Finished | Jul 06 07:55:20 PM PDT 24 |
| Peak memory | 609000 kb |
| Host | smart-a9ebc931-758a-4bbe-bf79-48284119fb74 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282299703 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.2282299703 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.3158228594 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 3890694348 ps |
| CPU time | 454.89 seconds |
| Started | Jul 06 07:50:43 PM PDT 24 |
| Finished | Jul 06 07:58:19 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-ea2c5df5-d346-4dce-ab97-78f175bc17be |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158228594 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.3158228594 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1548043447 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 7580492440 ps |
| CPU time | 624.23 seconds |
| Started | Jul 06 07:48:56 PM PDT 24 |
| Finished | Jul 06 07:59:21 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-16469b05-63ee-4d86-8ce9-5a0f4fbf5f02 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1548043447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1548043447 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1712983109 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 3703562064 ps |
| CPU time | 393.23 seconds |
| Started | Jul 06 07:53:40 PM PDT 24 |
| Finished | Jul 06 08:00:13 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-8f0238fb-0b95-4a8f-964e-7fc83bdf306f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712983109 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.1712983109 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.4288677916 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 7480174112 ps |
| CPU time | 773.91 seconds |
| Started | Jul 06 07:50:09 PM PDT 24 |
| Finished | Jul 06 08:03:04 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-4779126a-3bd0-442e-b555-68511a8699bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4288677916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.4288677916 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1288540302 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 4558369726 ps |
| CPU time | 823.09 seconds |
| Started | Jul 06 07:50:26 PM PDT 24 |
| Finished | Jul 06 08:04:10 PM PDT 24 |
| Peak memory | 610472 kb |
| Host | smart-3177698a-5ae2-4761-ad96-81b16898ce5b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1288540302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.1288540302 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.2612131453 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 7816782352 ps |
| CPU time | 940.75 seconds |
| Started | Jul 06 07:54:21 PM PDT 24 |
| Finished | Jul 06 08:10:02 PM PDT 24 |
| Peak memory | 617260 kb |
| Host | smart-f699d5ec-e625-4534-94c9-3262f41c9bb9 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612131453 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.2612131453 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1461358692 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 12485805340 ps |
| CPU time | 880.04 seconds |
| Started | Jul 06 07:49:53 PM PDT 24 |
| Finished | Jul 06 08:04:34 PM PDT 24 |
| Peak memory | 622680 kb |
| Host | smart-fe7fcaac-b666-47e3-9fd5-ec2339af5703 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1461358692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.1461358692 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3447290865 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 4192169384 ps |
| CPU time | 828.36 seconds |
| Started | Jul 06 07:50:40 PM PDT 24 |
| Finished | Jul 06 08:04:29 PM PDT 24 |
| Peak memory | 612724 kb |
| Host | smart-62fa8741-a97d-4e6d-81a8-4098e1c0d54c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447290865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3447290865 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.500300532 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 4490043884 ps |
| CPU time | 695.03 seconds |
| Started | Jul 06 07:50:43 PM PDT 24 |
| Finished | Jul 06 08:02:18 PM PDT 24 |
| Peak memory | 612880 kb |
| Host | smart-ec5d4ae7-bba1-4971-ac44-16f5ab43523f |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500300532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.500300532 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4133432721 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 4170908340 ps |
| CPU time | 770.16 seconds |
| Started | Jul 06 07:50:38 PM PDT 24 |
| Finished | Jul 06 08:03:28 PM PDT 24 |
| Peak memory | 612936 kb |
| Host | smart-8b727ed5-c703-4685-b4ee-f967da15e436 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133432721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4133432721 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4052159217 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 4461496562 ps |
| CPU time | 676.03 seconds |
| Started | Jul 06 07:51:36 PM PDT 24 |
| Finished | Jul 06 08:02:52 PM PDT 24 |
| Peak memory | 612980 kb |
| Host | smart-d8b7549a-3321-4934-aeaa-ad3994bfa151 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052159217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.4052159217 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4000434080 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 4282159450 ps |
| CPU time | 646.74 seconds |
| Started | Jul 06 07:50:31 PM PDT 24 |
| Finished | Jul 06 08:01:18 PM PDT 24 |
| Peak memory | 612912 kb |
| Host | smart-32afcbc0-677c-46d1-9bce-b5ba7f3f2919 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000434080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.4000434080 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.559829088 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 5053374984 ps |
| CPU time | 891.32 seconds |
| Started | Jul 06 07:50:08 PM PDT 24 |
| Finished | Jul 06 08:04:59 PM PDT 24 |
| Peak memory | 612980 kb |
| Host | smart-1cc024bd-ec3c-43dd-9544-5d5c4143d8f0 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559829088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.559829088 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3956135470 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 2340076650 ps |
| CPU time | 200.02 seconds |
| Started | Jul 06 07:51:40 PM PDT 24 |
| Finished | Jul 06 07:55:00 PM PDT 24 |
| Peak memory | 608852 kb |
| Host | smart-a756c596-0d5e-44ef-8032-27da2a53029e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956135470 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.3956135470 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2350458351 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 2739441316 ps |
| CPU time | 503.39 seconds |
| Started | Jul 06 07:50:55 PM PDT 24 |
| Finished | Jul 06 07:59:19 PM PDT 24 |
| Peak memory | 608472 kb |
| Host | smart-c9ec9084-9e44-4080-8fdd-8eb9acc1813b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350458351 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.2350458351 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3430517887 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 2621834249 ps |
| CPU time | 217.74 seconds |
| Started | Jul 06 07:54:48 PM PDT 24 |
| Finished | Jul 06 07:58:26 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-6e944086-fc5d-4c60-822a-c9266817b963 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430517887 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.3430517887 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.7695919 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 4866812350 ps |
| CPU time | 444.41 seconds |
| Started | Jul 06 07:50:38 PM PDT 24 |
| Finished | Jul 06 07:58:03 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-b95e5901-580b-4564-ba3d-3849513e93cc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7695919 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.7695919 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2001705430 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3446944678 ps |
| CPU time | 409.76 seconds |
| Started | Jul 06 07:50:24 PM PDT 24 |
| Finished | Jul 06 07:57:14 PM PDT 24 |
| Peak memory | 608592 kb |
| Host | smart-b1a45187-4fec-4a0a-b0a4-380b4e4bce92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001705430 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.2001705430 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1286873240 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 3985857752 ps |
| CPU time | 535.95 seconds |
| Started | Jul 06 07:52:14 PM PDT 24 |
| Finished | Jul 06 08:01:11 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-7d2fc0a7-786f-4b4e-8f31-1284a79f1c22 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286873240 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.1286873240 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1932055890 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 4312287936 ps |
| CPU time | 411.17 seconds |
| Started | Jul 06 07:50:35 PM PDT 24 |
| Finished | Jul 06 07:57:26 PM PDT 24 |
| Peak memory | 608988 kb |
| Host | smart-b00ffb63-c43a-4f08-9ec2-9b3cebac798c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932055890 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.1932055890 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.4025996857 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 9775003128 ps |
| CPU time | 1421.2 seconds |
| Started | Jul 06 07:49:50 PM PDT 24 |
| Finished | Jul 06 08:13:32 PM PDT 24 |
| Peak memory | 610752 kb |
| Host | smart-bdecd530-f227-43b4-9f71-978c530b35d8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025996857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.4025996857 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2561579185 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 3263648535 ps |
| CPU time | 447.01 seconds |
| Started | Jul 06 07:50:51 PM PDT 24 |
| Finished | Jul 06 07:58:19 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-cdb3e435-ada5-4c40-bcfe-788bf282f7be |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561579185 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.2561579185 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.155363407 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 4101336958 ps |
| CPU time | 574.46 seconds |
| Started | Jul 06 07:53:31 PM PDT 24 |
| Finished | Jul 06 08:03:05 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-611a4e1f-cb35-4319-85f0-c2e93aecaeef |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155363407 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.155363407 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.701787739 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 2972589536 ps |
| CPU time | 270.52 seconds |
| Started | Jul 06 07:53:09 PM PDT 24 |
| Finished | Jul 06 07:57:40 PM PDT 24 |
| Peak memory | 608444 kb |
| Host | smart-b0e5e929-4e13-414f-a2c7-d8e7e733e81f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701787739 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_clkmgr_smoketest.701787739 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1941027572 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 28042130980 ps |
| CPU time | 7842.36 seconds |
| Started | Jul 06 07:49:42 PM PDT 24 |
| Finished | Jul 06 10:00:26 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-9ec6f733-ad0f-481e-ae16-8459b8f5c773 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941027572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.1941027572 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3730685873 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 25837014795 ps |
| CPU time | 5252.06 seconds |
| Started | Jul 06 07:56:51 PM PDT 24 |
| Finished | Jul 06 09:24:24 PM PDT 24 |
| Peak memory | 609528 kb |
| Host | smart-8437b975-dcb0-439d-addd-179c20594503 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3730685873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.3730685873 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2446147290 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 4599719536 ps |
| CPU time | 674.58 seconds |
| Started | Jul 06 07:49:13 PM PDT 24 |
| Finished | Jul 06 08:00:28 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-ccbe8ab7-0b63-4813-b0f9-df7334261fd5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24461 47290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.2446147290 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.3949905656 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 2487164356 ps |
| CPU time | 294.57 seconds |
| Started | Jul 06 07:50:16 PM PDT 24 |
| Finished | Jul 06 07:55:11 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-826c02aa-e68e-4080-974b-0843e977e5b0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949905656 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.3949905656 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.524343896 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 5567276580 ps |
| CPU time | 922.5 seconds |
| Started | Jul 06 07:49:02 PM PDT 24 |
| Finished | Jul 06 08:04:25 PM PDT 24 |
| Peak memory | 611512 kb |
| Host | smart-06d99b91-0c82-4fa5-a527-06eeaeff20c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524343896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrn g_lc_hw_debug_en_test.524343896 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.1505277429 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 3078142208 ps |
| CPU time | 325.58 seconds |
| Started | Jul 06 07:53:34 PM PDT 24 |
| Finished | Jul 06 07:59:00 PM PDT 24 |
| Peak memory | 608908 kb |
| Host | smart-d9e4fdea-5bef-4789-a038-e99a47e5ef07 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505277429 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.1505277429 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3748298063 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 5817627390 ps |
| CPU time | 653.75 seconds |
| Started | Jul 06 07:43:48 PM PDT 24 |
| Finished | Jul 06 07:54:43 PM PDT 24 |
| Peak memory | 610884 kb |
| Host | smart-e888981b-aa6d-4c0d-9d21-1a9972e1f999 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3748298063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.3748298063 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.3734102902 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 4626910608 ps |
| CPU time | 1161.75 seconds |
| Started | Jul 06 07:51:25 PM PDT 24 |
| Finished | Jul 06 08:10:48 PM PDT 24 |
| Peak memory | 609464 kb |
| Host | smart-d219344b-6b95-460a-8e95-8a5189ab10c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734102902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.3734102902 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.2558353747 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 3420039080 ps |
| CPU time | 600.21 seconds |
| Started | Jul 06 07:51:25 PM PDT 24 |
| Finished | Jul 06 08:01:26 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-9fb676f9-1e26-44f5-a233-f8829b5e53e0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558353747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.2558353747 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3506592928 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 6624209915 ps |
| CPU time | 833.29 seconds |
| Started | Jul 06 07:49:13 PM PDT 24 |
| Finished | Jul 06 08:03:06 PM PDT 24 |
| Peak memory | 610996 kb |
| Host | smart-191aae45-6525-4af4-ab02-a13cdfbea29e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506592928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.3506592928 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.427298371 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 3314637580 ps |
| CPU time | 602.31 seconds |
| Started | Jul 06 07:51:32 PM PDT 24 |
| Finished | Jul 06 08:01:35 PM PDT 24 |
| Peak memory | 615352 kb |
| Host | smart-c7b38637-ef5e-4286-9e15-69346ed8e384 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427298371 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_edn_kat.427298371 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.918556605 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 9388890312 ps |
| CPU time | 2294.6 seconds |
| Started | Jul 06 07:48:39 PM PDT 24 |
| Finished | Jul 06 08:26:55 PM PDT 24 |
| Peak memory | 610356 kb |
| Host | smart-9940a47b-621b-42d8-b697-176d87548bfc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918556605 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.918556605 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.671130312 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2764071800 ps |
| CPU time | 190.35 seconds |
| Started | Jul 06 07:50:17 PM PDT 24 |
| Finished | Jul 06 07:53:28 PM PDT 24 |
| Peak memory | 608600 kb |
| Host | smart-6849d037-4989-4643-92c2-d436b994f1f9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67 1130312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.671130312 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.3747288579 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 6144293528 ps |
| CPU time | 1643.68 seconds |
| Started | Jul 06 07:48:54 PM PDT 24 |
| Finished | Jul 06 08:16:18 PM PDT 24 |
| Peak memory | 609476 kb |
| Host | smart-37d485bd-4dee-4932-955e-3220a970fd04 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3747288579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.3747288579 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2740387949 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 3342047012 ps |
| CPU time | 301.54 seconds |
| Started | Jul 06 07:48:41 PM PDT 24 |
| Finished | Jul 06 07:53:43 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-05299fea-e86d-4b83-823f-fd249f47e751 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740387949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.2740387949 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.713512397 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 3756500224 ps |
| CPU time | 557.88 seconds |
| Started | Jul 06 07:52:54 PM PDT 24 |
| Finished | Jul 06 08:02:13 PM PDT 24 |
| Peak memory | 608276 kb |
| Host | smart-84d0247e-8b36-4123-9c6c-eefdcef2d70c |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=713512397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.713512397 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.4235986329 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 2225434486 ps |
| CPU time | 220.09 seconds |
| Started | Jul 06 07:44:27 PM PDT 24 |
| Finished | Jul 06 07:48:08 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-6f4aa3fb-e32c-4abf-9b83-23a16d728667 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235986329 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.4235986329 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.218946318 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 2226741680 ps |
| CPU time | 167.75 seconds |
| Started | Jul 06 07:44:53 PM PDT 24 |
| Finished | Jul 06 07:47:41 PM PDT 24 |
| Peak memory | 608844 kb |
| Host | smart-d442bf44-aaa4-4c98-a726-ab0621e589a0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218946318 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.218946318 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.2937319295 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 1939871280 ps |
| CPU time | 171.46 seconds |
| Started | Jul 06 07:48:09 PM PDT 24 |
| Finished | Jul 06 07:51:02 PM PDT 24 |
| Peak memory | 608708 kb |
| Host | smart-75bdecea-56e9-4240-a82c-462f9dab67fb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937319295 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.2937319295 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.84220233 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 3028834832 ps |
| CPU time | 145.55 seconds |
| Started | Jul 06 07:42:55 PM PDT 24 |
| Finished | Jul 06 07:45:21 PM PDT 24 |
| Peak memory | 608320 kb |
| Host | smart-8d3baa49-e7ec-45c6-8461-313e7ba1c108 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84220233 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_example_rom.84220233 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2361414318 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 59152481276 ps |
| CPU time | 10148.3 seconds |
| Started | Jul 06 07:44:44 PM PDT 24 |
| Finished | Jul 06 10:33:54 PM PDT 24 |
| Peak memory | 623720 kb |
| Host | smart-9a09483e-980f-4f69-9c2e-cc996c2a7abb |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2361414318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.2361414318 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.529129912 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 6277997734 ps |
| CPU time | 974.89 seconds |
| Started | Jul 06 07:52:31 PM PDT 24 |
| Finished | Jul 06 08:08:46 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-142af765-28dd-45d7-b43c-4bbbc6f0b487 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=529129912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.529129912 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.864567615 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 5463949320 ps |
| CPU time | 1110.86 seconds |
| Started | Jul 06 07:45:44 PM PDT 24 |
| Finished | Jul 06 08:04:15 PM PDT 24 |
| Peak memory | 609344 kb |
| Host | smart-2517b21a-9ae7-4932-8077-e0fa3a4569ba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864567615 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_flash_ctrl_access.864567615 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.4104077895 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 6218541215 ps |
| CPU time | 1310.69 seconds |
| Started | Jul 06 07:47:18 PM PDT 24 |
| Finished | Jul 06 08:09:09 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-60fe9242-7b37-4dff-b3fd-281b219c71e5 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104077895 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.4104077895 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.957056109 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 7128578449 ps |
| CPU time | 1285.23 seconds |
| Started | Jul 06 07:50:57 PM PDT 24 |
| Finished | Jul 06 08:12:23 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-bba3aac9-64e2-4f32-a91c-d73958e047f0 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957056109 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.957056109 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3607675879 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 5087633282 ps |
| CPU time | 1257.45 seconds |
| Started | Jul 06 07:45:47 PM PDT 24 |
| Finished | Jul 06 08:06:45 PM PDT 24 |
| Peak memory | 608776 kb |
| Host | smart-3acbe676-1893-43a5-99e5-02a1c2d95ee3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607675879 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.3607675879 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.267992020 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 3665576600 ps |
| CPU time | 452.46 seconds |
| Started | Jul 06 07:47:34 PM PDT 24 |
| Finished | Jul 06 07:55:07 PM PDT 24 |
| Peak memory | 609528 kb |
| Host | smart-801312a6-583d-41e6-ae8e-ba64f942fd58 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267992020 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.267992020 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2929725726 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 5824590060 ps |
| CPU time | 1359.85 seconds |
| Started | Jul 06 07:54:45 PM PDT 24 |
| Finished | Jul 06 08:17:25 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-1ef5d297-91bf-499b-b316-55706aeb559c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929725726 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.2929725726 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.4164857046 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3456552140 ps |
| CPU time | 702.8 seconds |
| Started | Jul 06 07:45:45 PM PDT 24 |
| Finished | Jul 06 07:57:28 PM PDT 24 |
| Peak memory | 610316 kb |
| Host | smart-265dc31c-3c88-4583-9c3b-f42fa3a56683 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164857046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.4164857046 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3345190800 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3967857733 ps |
| CPU time | 707.72 seconds |
| Started | Jul 06 07:46:21 PM PDT 24 |
| Finished | Jul 06 07:58:10 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-d2ad4961-303b-4e6a-ab36-c854f0649359 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3345190800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.3345190800 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2797387457 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 3072874180 ps |
| CPU time | 341.27 seconds |
| Started | Jul 06 07:56:40 PM PDT 24 |
| Finished | Jul 06 08:02:21 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-761187dd-377c-4ed0-bbd0-67b42b65ceae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797387 457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.2797387457 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.3820606620 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 21870630974 ps |
| CPU time | 2020.84 seconds |
| Started | Jul 06 07:45:02 PM PDT 24 |
| Finished | Jul 06 08:18:44 PM PDT 24 |
| Peak memory | 614548 kb |
| Host | smart-78b9eac5-7f08-496e-8f73-3a54ce296900 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820606620 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.3820606620 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2868324173 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 20747102940 ps |
| CPU time | 2343.26 seconds |
| Started | Jul 06 07:51:53 PM PDT 24 |
| Finished | Jul 06 08:30:57 PM PDT 24 |
| Peak memory | 612448 kb |
| Host | smart-622e2056-d303-4331-9324-ba6893e55a66 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2868324173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.2868324173 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.970347353 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 2521358902 ps |
| CPU time | 232.23 seconds |
| Started | Jul 06 07:55:49 PM PDT 24 |
| Finished | Jul 06 07:59:42 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-506a3fe8-7a26-4424-8905-f50aeeb9a59c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=970347353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.970347353 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.2837631502 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 2487777039 ps |
| CPU time | 212.94 seconds |
| Started | Jul 06 07:53:21 PM PDT 24 |
| Finished | Jul 06 07:56:55 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-a1f4d818-4caa-4e4e-b23c-d37298b422f4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837631502 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.2837631502 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.2570142794 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 2729541164 ps |
| CPU time | 279.08 seconds |
| Started | Jul 06 07:49:19 PM PDT 24 |
| Finished | Jul 06 07:53:59 PM PDT 24 |
| Peak memory | 608888 kb |
| Host | smart-c668bc75-7421-4e1e-b7cf-416060c98fb9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570142794 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.2570142794 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.476997259 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 3069446372 ps |
| CPU time | 321.77 seconds |
| Started | Jul 06 07:49:37 PM PDT 24 |
| Finished | Jul 06 07:55:00 PM PDT 24 |
| Peak memory | 608852 kb |
| Host | smart-53ef2a69-c3be-45e8-a040-2f5c64f91fce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476997259 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_hmac_enc_idle.476997259 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.4210876299 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 3186397851 ps |
| CPU time | 299.06 seconds |
| Started | Jul 06 07:49:42 PM PDT 24 |
| Finished | Jul 06 07:54:41 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-a341c384-455c-49cd-98e1-0e61cc572484 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210876299 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.4210876299 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3449431875 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 3486680828 ps |
| CPU time | 284.7 seconds |
| Started | Jul 06 07:52:24 PM PDT 24 |
| Finished | Jul 06 07:57:09 PM PDT 24 |
| Peak memory | 608388 kb |
| Host | smart-bc4e824e-cc78-4579-b4d7-269b65f5b6d9 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449431875 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.3449431875 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.1891619326 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 7474981448 ps |
| CPU time | 1871.04 seconds |
| Started | Jul 06 07:51:04 PM PDT 24 |
| Finished | Jul 06 08:22:16 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-bd6717e8-e1af-455b-9099-60f8639c9d12 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891619326 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.1891619326 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.3015420616 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 2923362344 ps |
| CPU time | 364.01 seconds |
| Started | Jul 06 07:48:46 PM PDT 24 |
| Finished | Jul 06 07:54:50 PM PDT 24 |
| Peak memory | 608812 kb |
| Host | smart-e310319f-aabd-4f67-8ab0-d5bb7ad4ee99 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015420616 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.3015420616 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.438457499 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 3490814752 ps |
| CPU time | 350.45 seconds |
| Started | Jul 06 07:53:01 PM PDT 24 |
| Finished | Jul 06 07:58:52 PM PDT 24 |
| Peak memory | 608764 kb |
| Host | smart-c73523ee-4733-49b5-aaef-0f57f9be7fb3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438457499 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_smoketest.438457499 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.136314317 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4454646470 ps |
| CPU time | 649.27 seconds |
| Started | Jul 06 07:45:17 PM PDT 24 |
| Finished | Jul 06 07:56:07 PM PDT 24 |
| Peak memory | 609532 kb |
| Host | smart-87337a30-c5d4-4b13-8b26-27611bced1af |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136314317 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.136314317 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.768130654 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 5146991978 ps |
| CPU time | 739.66 seconds |
| Started | Jul 06 07:45:10 PM PDT 24 |
| Finished | Jul 06 07:57:30 PM PDT 24 |
| Peak memory | 608920 kb |
| Host | smart-deaa4481-8659-4cca-832c-751f182d5623 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768130654 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.768130654 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.1142752788 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 63278104487 ps |
| CPU time | 12008.3 seconds |
| Started | Jul 06 07:44:12 PM PDT 24 |
| Finished | Jul 06 11:04:23 PM PDT 24 |
| Peak memory | 623668 kb |
| Host | smart-3c0b7309-b3b8-48e3-98c0-486b978bf57b |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1142752788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.1142752788 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1979556227 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 11185145126 ps |
| CPU time | 2554.75 seconds |
| Started | Jul 06 07:48:59 PM PDT 24 |
| Finished | Jul 06 08:31:34 PM PDT 24 |
| Peak memory | 616460 kb |
| Host | smart-edca86f3-fb84-44ad-955e-8c21d79f9166 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979 556227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.1979556227 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3009192879 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 11866281784 ps |
| CPU time | 2476 seconds |
| Started | Jul 06 07:49:06 PM PDT 24 |
| Finished | Jul 06 08:30:22 PM PDT 24 |
| Peak memory | 616820 kb |
| Host | smart-9dfdbd74-4cf8-4230-873b-14012164823e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3009192879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.3009192879 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.329629697 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 8212897494 ps |
| CPU time | 1291.01 seconds |
| Started | Jul 06 07:52:04 PM PDT 24 |
| Finished | Jul 06 08:13:36 PM PDT 24 |
| Peak memory | 617760 kb |
| Host | smart-fc3fed3c-58c9-4a6d-a457-8e2dd705badc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=329629697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en_ reduced_freq.329629697 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3277483391 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 11854315324 ps |
| CPU time | 2178.55 seconds |
| Started | Jul 06 07:54:02 PM PDT 24 |
| Finished | Jul 06 08:30:21 PM PDT 24 |
| Peak memory | 610996 kb |
| Host | smart-2491ff9c-c2da-43f3-8e00-57e923f41332 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327748 3391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.3277483391 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3888762401 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 9593523760 ps |
| CPU time | 1854.83 seconds |
| Started | Jul 06 07:49:11 PM PDT 24 |
| Finished | Jul 06 08:20:07 PM PDT 24 |
| Peak memory | 610988 kb |
| Host | smart-dacbb99e-8a1c-423f-860d-70862ef7520a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38887 62401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.3888762401 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.4266903220 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 13743827408 ps |
| CPU time | 3854.11 seconds |
| Started | Jul 06 07:50:02 PM PDT 24 |
| Finished | Jul 06 08:54:18 PM PDT 24 |
| Peak memory | 611160 kb |
| Host | smart-1e859aaf-6fb4-496e-b4cf-db193e0ecb4e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42669 03220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.4266903220 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.496236165 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 3050440304 ps |
| CPU time | 300.24 seconds |
| Started | Jul 06 07:53:21 PM PDT 24 |
| Finished | Jul 06 07:58:21 PM PDT 24 |
| Peak memory | 608420 kb |
| Host | smart-5a25cd4c-2228-4142-828d-a4df02337c4c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496236165 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_app_rom.496236165 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.273543326 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 2519911664 ps |
| CPU time | 223.71 seconds |
| Started | Jul 06 07:49:50 PM PDT 24 |
| Finished | Jul 06 07:53:34 PM PDT 24 |
| Peak memory | 608892 kb |
| Host | smart-bfd6a012-299c-42af-8be7-e25402e4e7cc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273543326 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_idle.273543326 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2424296003 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 3209976000 ps |
| CPU time | 272.63 seconds |
| Started | Jul 06 07:53:27 PM PDT 24 |
| Finished | Jul 06 07:58:00 PM PDT 24 |
| Peak memory | 608356 kb |
| Host | smart-ccf8379f-bad0-45d2-ab84-eca9d4512eea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424296003 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.2424296003 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.4274578353 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 3571054668 ps |
| CPU time | 401.2 seconds |
| Started | Jul 06 07:49:12 PM PDT 24 |
| Finished | Jul 06 07:55:53 PM PDT 24 |
| Peak memory | 608452 kb |
| Host | smart-632f51f9-0733-49c0-82b5-31f3e26f456b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274578353 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.4274578353 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.23822141 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 2609989379 ps |
| CPU time | 228.31 seconds |
| Started | Jul 06 07:54:04 PM PDT 24 |
| Finished | Jul 06 07:57:53 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-7d06bd15-2b09-4755-9e36-e46980091fdc |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23822141 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.23822141 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.561884507 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 2912118083 ps |
| CPU time | 271.47 seconds |
| Started | Jul 06 07:52:23 PM PDT 24 |
| Finished | Jul 06 07:56:54 PM PDT 24 |
| Peak memory | 608352 kb |
| Host | smart-2ff14c49-7fe2-4ee6-af05-dadf413c3d99 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56188450 7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.561884507 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.2519807995 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 2653056240 ps |
| CPU time | 353.45 seconds |
| Started | Jul 06 07:56:19 PM PDT 24 |
| Finished | Jul 06 08:02:13 PM PDT 24 |
| Peak memory | 608884 kb |
| Host | smart-b6542d8b-208b-440f-83cd-cb295776908c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519807995 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.2519807995 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3054120501 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 2336736010 ps |
| CPU time | 279.43 seconds |
| Started | Jul 06 07:46:27 PM PDT 24 |
| Finished | Jul 06 07:51:07 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-6b548083-7200-4510-9a28-abe9457eb39a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054120501 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.3054120501 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.2851728662 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 5986072040 ps |
| CPU time | 569.48 seconds |
| Started | Jul 06 07:51:34 PM PDT 24 |
| Finished | Jul 06 08:01:04 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-83cb2a31-afe6-4484-a30d-65421fb682f6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2851728662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.2851728662 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2456852229 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 3879552211 ps |
| CPU time | 156.4 seconds |
| Started | Jul 06 07:45:45 PM PDT 24 |
| Finished | Jul 06 07:48:22 PM PDT 24 |
| Peak memory | 620612 kb |
| Host | smart-f36cc477-ad08-4cc4-9bf8-8bec7b7eca81 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24568522 29 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.2456852229 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.597961727 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 13284551858 ps |
| CPU time | 820.23 seconds |
| Started | Jul 06 07:45:39 PM PDT 24 |
| Finished | Jul 06 07:59:20 PM PDT 24 |
| Peak memory | 624776 kb |
| Host | smart-ff9154ca-fe7c-44a3-a501-ec9b94bd8b17 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597961727 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.597961727 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2845310509 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 3102293890 ps |
| CPU time | 135.03 seconds |
| Started | Jul 06 07:48:35 PM PDT 24 |
| Finished | Jul 06 07:50:51 PM PDT 24 |
| Peak memory | 614840 kb |
| Host | smart-8b4ff01a-8fa9-4fc6-850f-d53809b8c0ed |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2845310509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.2845310509 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3916661207 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2380631992 ps |
| CPU time | 113.68 seconds |
| Started | Jul 06 07:48:37 PM PDT 24 |
| Finished | Jul 06 07:50:32 PM PDT 24 |
| Peak memory | 616708 kb |
| Host | smart-b18a0b27-ebf4-4c4b-b7e4-bf4189d6eeff |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916661207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3916661207 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3361102601 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 50959943006 ps |
| CPU time | 6005.38 seconds |
| Started | Jul 06 07:46:00 PM PDT 24 |
| Finished | Jul 06 09:26:06 PM PDT 24 |
| Peak memory | 615748 kb |
| Host | smart-902fba16-a525-4832-b00e-1a2a222d7d53 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361102601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.3361102601 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.917946112 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 49711037465 ps |
| CPU time | 5412.48 seconds |
| Started | Jul 06 07:46:23 PM PDT 24 |
| Finished | Jul 06 09:16:36 PM PDT 24 |
| Peak memory | 615744 kb |
| Host | smart-5622081c-a350-4c5a-a08c-70467c744ed0 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917946112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_prod.917946112 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2021568760 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 10092520287 ps |
| CPU time | 769.67 seconds |
| Started | Jul 06 07:46:35 PM PDT 24 |
| Finished | Jul 06 07:59:26 PM PDT 24 |
| Peak memory | 618036 kb |
| Host | smart-463b28b8-900f-4fcf-b34d-45366016407a |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021568760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.2021568760 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.597129813 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 49120057400 ps |
| CPU time | 4984.53 seconds |
| Started | Jul 06 07:46:37 PM PDT 24 |
| Finished | Jul 06 09:09:42 PM PDT 24 |
| Peak memory | 615744 kb |
| Host | smart-b7627479-f55b-4310-bf43-b0a586b53093 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597129813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_lc_walkthrough_rma.597129813 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3648280180 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 26889321658 ps |
| CPU time | 2142.8 seconds |
| Started | Jul 06 07:46:30 PM PDT 24 |
| Finished | Jul 06 08:22:14 PM PDT 24 |
| Peak memory | 624772 kb |
| Host | smart-71719c2a-5af8-4606-9915-654a486161a5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3648280180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.3648280180 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1553739040 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 17169435720 ps |
| CPU time | 4147.11 seconds |
| Started | Jul 06 07:50:38 PM PDT 24 |
| Finished | Jul 06 08:59:46 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-1b565189-3d61-43d0-8ba8-769bc5956ffb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1553739040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.1553739040 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2544273904 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 19375337768 ps |
| CPU time | 3660.69 seconds |
| Started | Jul 06 07:48:24 PM PDT 24 |
| Finished | Jul 06 08:49:26 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-a8e60f33-d237-471f-aa12-99c491004c7b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2544273904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2544273904 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3068636401 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 24792474086 ps |
| CPU time | 4308.49 seconds |
| Started | Jul 06 07:52:36 PM PDT 24 |
| Finished | Jul 06 09:04:27 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-6010ca4c-1cda-45ad-baeb-df5ac8ac530e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068636401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3068636401 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.4117903485 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 3420149298 ps |
| CPU time | 634.18 seconds |
| Started | Jul 06 07:47:53 PM PDT 24 |
| Finished | Jul 06 07:58:28 PM PDT 24 |
| Peak memory | 609144 kb |
| Host | smart-8fb27ba1-c2ca-4a80-bd2f-6b8bb954638c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117903485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.4117903485 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.4162931144 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 6405430740 ps |
| CPU time | 1107.02 seconds |
| Started | Jul 06 07:49:09 PM PDT 24 |
| Finished | Jul 06 08:07:37 PM PDT 24 |
| Peak memory | 610468 kb |
| Host | smart-ca762b5c-bbc3-45b2-ab3f-a6c82370d3a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4162931144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.4162931144 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.1233500132 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 6158275742 ps |
| CPU time | 1177.77 seconds |
| Started | Jul 06 07:54:48 PM PDT 24 |
| Finished | Jul 06 08:14:26 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-424df771-dea7-487c-95f7-6fa8dfceeb58 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233500132 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.1233500132 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.518780566 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 2480942243 ps |
| CPU time | 233.36 seconds |
| Started | Jul 06 07:46:05 PM PDT 24 |
| Finished | Jul 06 07:49:59 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-a4cd8d66-1140-4f4f-a54d-64c9da381600 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518780566 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.518780566 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3127991933 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 9576142302 ps |
| CPU time | 1551.58 seconds |
| Started | Jul 06 07:45:28 PM PDT 24 |
| Finished | Jul 06 08:11:20 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-35e6453c-ba9c-4805-bf0b-9e0d81d7566a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3127991933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.3127991933 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1664073434 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 8414332984 ps |
| CPU time | 1629.44 seconds |
| Started | Jul 06 07:47:21 PM PDT 24 |
| Finished | Jul 06 08:14:31 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-3c1078c9-e858-4455-a515-900baa1fd0c7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1664073434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.1664073434 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.302744695 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 8964896440 ps |
| CPU time | 1561.02 seconds |
| Started | Jul 06 07:46:27 PM PDT 24 |
| Finished | Jul 06 08:12:29 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-5c8aaa6c-0047-4d97-b167-b7bc0d60a437 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=302744695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.302744695 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3782265736 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 4731769720 ps |
| CPU time | 850.71 seconds |
| Started | Jul 06 07:46:00 PM PDT 24 |
| Finished | Jul 06 08:00:11 PM PDT 24 |
| Peak memory | 609048 kb |
| Host | smart-66c396d9-f576-4799-ac33-49c96a0eb28a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3782265736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3782265736 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1426824918 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 3375921590 ps |
| CPU time | 240.24 seconds |
| Started | Jul 06 07:53:15 PM PDT 24 |
| Finished | Jul 06 07:57:16 PM PDT 24 |
| Peak memory | 608384 kb |
| Host | smart-cecd43d1-5e82-4445-8e66-ab11811aff9c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426824918 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.1426824918 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.3130046386 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 2426093660 ps |
| CPU time | 274.71 seconds |
| Started | Jul 06 07:52:26 PM PDT 24 |
| Finished | Jul 06 07:57:01 PM PDT 24 |
| Peak memory | 608764 kb |
| Host | smart-55d83582-36d0-485d-82df-088bed20ff1e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130046386 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.3130046386 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.4111300044 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 4199193968 ps |
| CPU time | 686.38 seconds |
| Started | Jul 06 07:52:59 PM PDT 24 |
| Finished | Jul 06 08:04:26 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-9d16be5a-26fa-4207-a6c3-e44972ae0224 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111300044 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.4111300044 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.2169503125 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 9592738648 ps |
| CPU time | 680.31 seconds |
| Started | Jul 06 07:52:30 PM PDT 24 |
| Finished | Jul 06 08:03:51 PM PDT 24 |
| Peak memory | 610916 kb |
| Host | smart-d43cd17d-e233-4d1f-9bea-14141479dfec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169503125 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.2169503125 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4155818341 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 11080549716 ps |
| CPU time | 2034.24 seconds |
| Started | Jul 06 07:46:33 PM PDT 24 |
| Finished | Jul 06 08:20:28 PM PDT 24 |
| Peak memory | 611380 kb |
| Host | smart-210cc0b4-5a14-44cb-8b2b-137496deefed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155 818341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.4155818341 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3084442317 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 23116647598 ps |
| CPU time | 1954.68 seconds |
| Started | Jul 06 07:50:37 PM PDT 24 |
| Finished | Jul 06 08:23:12 PM PDT 24 |
| Peak memory | 610448 kb |
| Host | smart-0a6be227-2784-43ea-a3ec-6882a737a9bf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308 4442317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.3084442317 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2049714759 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 17742718956 ps |
| CPU time | 1727.85 seconds |
| Started | Jul 06 07:48:06 PM PDT 24 |
| Finished | Jul 06 08:16:55 PM PDT 24 |
| Peak memory | 611480 kb |
| Host | smart-2ae220ba-928b-4619-b9d0-75949a8b6c4d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2049714759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2049714759 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3322319294 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 21517921718 ps |
| CPU time | 2162.88 seconds |
| Started | Jul 06 07:51:17 PM PDT 24 |
| Finished | Jul 06 08:27:21 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-653b0fc4-566a-4bd6-9f49-e911426fab39 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3322319294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3322319294 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3748437428 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 7954551480 ps |
| CPU time | 508.01 seconds |
| Started | Jul 06 07:46:49 PM PDT 24 |
| Finished | Jul 06 07:55:18 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-6b38716b-4478-45b7-a286-66ecceaa57ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748437428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.3748437428 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1000328291 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 5998613576 ps |
| CPU time | 566.99 seconds |
| Started | Jul 06 07:46:49 PM PDT 24 |
| Finished | Jul 06 07:56:17 PM PDT 24 |
| Peak memory | 616260 kb |
| Host | smart-75970a4f-0a81-4985-bd9b-45a4d358eff1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1000328291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1000328291 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2929410050 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 8313185212 ps |
| CPU time | 469.32 seconds |
| Started | Jul 06 07:46:29 PM PDT 24 |
| Finished | Jul 06 07:54:19 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-da8b726c-88fd-46ee-9eba-5e595f88ec5c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929410050 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.2929410050 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.517653612 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 3189009688 ps |
| CPU time | 487.05 seconds |
| Started | Jul 06 07:53:21 PM PDT 24 |
| Finished | Jul 06 08:01:28 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-a39136a3-cafb-41f4-87fa-d129929ce66d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517653612 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.517653612 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2300462340 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 3624009251 ps |
| CPU time | 361.6 seconds |
| Started | Jul 06 07:47:14 PM PDT 24 |
| Finished | Jul 06 07:53:16 PM PDT 24 |
| Peak memory | 617132 kb |
| Host | smart-0bfab9c0-eb9b-476e-bf6c-b977ae7147c9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2300462340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.2300462340 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1155686792 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 13854544027 ps |
| CPU time | 1512.29 seconds |
| Started | Jul 06 07:48:02 PM PDT 24 |
| Finished | Jul 06 08:13:14 PM PDT 24 |
| Peak memory | 611464 kb |
| Host | smart-086b759b-a95b-4a7d-818c-c7565397c49d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155686792 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1155686792 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2334639499 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7222335114 ps |
| CPU time | 411.51 seconds |
| Started | Jul 06 07:53:18 PM PDT 24 |
| Finished | Jul 06 08:00:10 PM PDT 24 |
| Peak memory | 609420 kb |
| Host | smart-1b198d43-b5a8-459e-bf94-8b2b33fda013 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334639499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2334639499 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.519759981 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 6155493490 ps |
| CPU time | 778.37 seconds |
| Started | Jul 06 07:47:23 PM PDT 24 |
| Finished | Jul 06 08:00:22 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-35d62cb7-fbda-492c-84ff-f0b829bb8983 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519759981 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.519759981 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.471735576 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 24179405300 ps |
| CPU time | 2636.8 seconds |
| Started | Jul 06 07:47:25 PM PDT 24 |
| Finished | Jul 06 08:31:22 PM PDT 24 |
| Peak memory | 611428 kb |
| Host | smart-b4e6b613-cc40-488b-9cd0-b1539eb2de97 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=471735576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.471735576 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2566565119 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 23230178568 ps |
| CPU time | 1590.44 seconds |
| Started | Jul 06 07:52:18 PM PDT 24 |
| Finished | Jul 06 08:18:49 PM PDT 24 |
| Peak memory | 610832 kb |
| Host | smart-a10fabbd-525c-42aa-8da5-41081fafe80a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2566565119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2566565119 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3718333284 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 32867434202 ps |
| CPU time | 3112.84 seconds |
| Started | Jul 06 07:46:53 PM PDT 24 |
| Finished | Jul 06 08:38:46 PM PDT 24 |
| Peak memory | 611660 kb |
| Host | smart-83ba559a-943f-4fa3-8a6b-0c97215910d6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718333284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s leep_power_glitch_reset.3718333284 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2904957836 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 5800991648 ps |
| CPU time | 532.08 seconds |
| Started | Jul 06 07:51:50 PM PDT 24 |
| Finished | Jul 06 08:00:42 PM PDT 24 |
| Peak memory | 610888 kb |
| Host | smart-b027fab3-3de1-4b55-adfa-43bc0f4ee8cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2904957836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2904957836 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.258959211 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 3397372464 ps |
| CPU time | 278.74 seconds |
| Started | Jul 06 07:46:35 PM PDT 24 |
| Finished | Jul 06 07:51:14 PM PDT 24 |
| Peak memory | 608396 kb |
| Host | smart-23e1f7f6-05a0-4be8-b9be-88ad15df6c14 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258959211 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.258959211 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1207415435 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 4704159233 ps |
| CPU time | 365.26 seconds |
| Started | Jul 06 07:47:11 PM PDT 24 |
| Finished | Jul 06 07:53:17 PM PDT 24 |
| Peak memory | 616392 kb |
| Host | smart-8cbb93a6-f096-4325-9a3d-05726fe39cca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1207415435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.1207415435 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.633254552 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 5706612136 ps |
| CPU time | 480.24 seconds |
| Started | Jul 06 07:51:14 PM PDT 24 |
| Finished | Jul 06 07:59:15 PM PDT 24 |
| Peak memory | 608864 kb |
| Host | smart-637b966b-9a1a-4fc4-ace7-0dcaa0dfa7c9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63325455 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.633254552 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1185931835 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 5726181276 ps |
| CPU time | 575.4 seconds |
| Started | Jul 06 07:51:16 PM PDT 24 |
| Finished | Jul 06 08:00:52 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-9da34da5-35a6-4a47-b676-040ce1b99e54 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1185931835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.1185931835 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1374232948 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 5736456746 ps |
| CPU time | 550.05 seconds |
| Started | Jul 06 07:52:50 PM PDT 24 |
| Finished | Jul 06 08:02:01 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-b7564403-97a3-4081-b4b2-a2ac47c64cf0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374232948 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.1374232948 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3040240192 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 8126964628 ps |
| CPU time | 1282.53 seconds |
| Started | Jul 06 07:46:32 PM PDT 24 |
| Finished | Jul 06 08:07:55 PM PDT 24 |
| Peak memory | 609492 kb |
| Host | smart-ab6f8f85-06bd-420e-8101-6b1697e01f58 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040240192 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.3040240192 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.483409902 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 5073467374 ps |
| CPU time | 441.02 seconds |
| Started | Jul 06 07:48:22 PM PDT 24 |
| Finished | Jul 06 07:55:43 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-ed758b8c-99da-4a76-bb65-7ecf0ae09e60 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483409902 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.483409902 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2300611518 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 4872315880 ps |
| CPU time | 351.35 seconds |
| Started | Jul 06 07:53:11 PM PDT 24 |
| Finished | Jul 06 07:59:03 PM PDT 24 |
| Peak memory | 610460 kb |
| Host | smart-b52a221a-6f14-45c9-85e7-df5f0525091a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300611518 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.2300611518 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.4033625405 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 5504692984 ps |
| CPU time | 474.93 seconds |
| Started | Jul 06 07:47:06 PM PDT 24 |
| Finished | Jul 06 07:55:01 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-2d514cfd-c20b-4487-9b41-00729acc5449 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403 3625405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.4033625405 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3334208772 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 8350880926 ps |
| CPU time | 570.16 seconds |
| Started | Jul 06 07:49:18 PM PDT 24 |
| Finished | Jul 06 07:58:49 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-a168c886-72bb-477a-a484-6cdd89e8b698 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334208772 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.3334208772 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.714687367 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 6508823512 ps |
| CPU time | 637.73 seconds |
| Started | Jul 06 07:46:11 PM PDT 24 |
| Finished | Jul 06 07:56:49 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-725653e2-ac1e-44ab-a608-dc987aae36fa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714687367 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_rstmgr_cpu_info.714687367 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.4050052390 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 5298998090 ps |
| CPU time | 861.94 seconds |
| Started | Jul 06 07:45:00 PM PDT 24 |
| Finished | Jul 06 07:59:23 PM PDT 24 |
| Peak memory | 641616 kb |
| Host | smart-a9294ed6-e741-4933-8099-b3093bb76a14 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4050052390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.4050052390 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.4246825400 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 2207615052 ps |
| CPU time | 196.62 seconds |
| Started | Jul 06 07:54:13 PM PDT 24 |
| Finished | Jul 06 07:57:30 PM PDT 24 |
| Peak memory | 608712 kb |
| Host | smart-9e85d409-5b69-41a1-9655-e2a64cf4b1f8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246825400 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.4246825400 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2533686393 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3735903720 ps |
| CPU time | 324.54 seconds |
| Started | Jul 06 07:48:34 PM PDT 24 |
| Finished | Jul 06 07:53:59 PM PDT 24 |
| Peak memory | 609064 kb |
| Host | smart-2e4853c8-bd4b-4dca-ab86-869778a09cee |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533686393 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.2533686393 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2985174242 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 2535409768 ps |
| CPU time | 273.13 seconds |
| Started | Jul 06 07:46:41 PM PDT 24 |
| Finished | Jul 06 07:51:15 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-33f0c8c3-bf70-4f0b-a5f1-fe151c3057dd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985174242 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.2985174242 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1279249677 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2912717896 ps |
| CPU time | 270.61 seconds |
| Started | Jul 06 07:51:39 PM PDT 24 |
| Finished | Jul 06 07:56:10 PM PDT 24 |
| Peak memory | 608568 kb |
| Host | smart-0d947856-b072-4758-8a7b-d5a201a33aa3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1279249677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.1279249677 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1065622352 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2886805972 ps |
| CPU time | 251.85 seconds |
| Started | Jul 06 07:51:40 PM PDT 24 |
| Finished | Jul 06 07:55:53 PM PDT 24 |
| Peak memory | 610316 kb |
| Host | smart-c4ee971a-04b6-409e-8b42-babd3962eef3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065622352 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.1065622352 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.146494717 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 4493895088 ps |
| CPU time | 935.46 seconds |
| Started | Jul 06 07:48:16 PM PDT 24 |
| Finished | Jul 06 08:03:52 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-7f06fe70-bf36-4c7d-87ba-827767bfbd16 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14649 4717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.146494717 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.448000679 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 5461729768 ps |
| CPU time | 1024.98 seconds |
| Started | Jul 06 07:47:01 PM PDT 24 |
| Finished | Jul 06 08:04:06 PM PDT 24 |
| Peak memory | 610364 kb |
| Host | smart-fb36c0f4-188e-4eb3-8aa3-f6a8fa075a07 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=448000679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.448000679 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.158652432 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 4947541759 ps |
| CPU time | 710.03 seconds |
| Started | Jul 06 07:51:16 PM PDT 24 |
| Finished | Jul 06 08:03:06 PM PDT 24 |
| Peak memory | 624160 kb |
| Host | smart-544e148c-dd00-4f0a-8632-9c3c8f405e71 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158652432 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.158652432 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.4249054443 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 5610395760 ps |
| CPU time | 431.39 seconds |
| Started | Jul 06 07:50:31 PM PDT 24 |
| Finished | Jul 06 07:57:43 PM PDT 24 |
| Peak memory | 624136 kb |
| Host | smart-c607b79d-16b8-41de-9ad8-6743e264b670 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249054443 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.4249054443 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1383296118 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 4535057076 ps |
| CPU time | 606.45 seconds |
| Started | Jul 06 07:50:48 PM PDT 24 |
| Finished | Jul 06 08:00:55 PM PDT 24 |
| Peak memory | 621048 kb |
| Host | smart-85f18da1-a618-4979-a61e-294ba55747a2 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138329 6118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1383296118 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1626470428 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 2518736372 ps |
| CPU time | 259.13 seconds |
| Started | Jul 06 07:54:52 PM PDT 24 |
| Finished | Jul 06 07:59:12 PM PDT 24 |
| Peak memory | 608840 kb |
| Host | smart-cf03ad12-c19e-4951-aeb0-3963970fe4f6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626470428 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.1626470428 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.1513782765 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 2757172968 ps |
| CPU time | 304.32 seconds |
| Started | Jul 06 07:47:55 PM PDT 24 |
| Finished | Jul 06 07:53:00 PM PDT 24 |
| Peak memory | 608788 kb |
| Host | smart-74ba7572-0550-44ee-9299-b433c0dc4359 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513782765 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.1513782765 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2428538131 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2938062660 ps |
| CPU time | 239.73 seconds |
| Started | Jul 06 07:54:34 PM PDT 24 |
| Finished | Jul 06 07:58:34 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-19b02c7b-ee8a-481d-ace5-d2aeb67ab134 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428538131 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.2428538131 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3821263818 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 2637044938 ps |
| CPU time | 313.65 seconds |
| Started | Jul 06 07:49:26 PM PDT 24 |
| Finished | Jul 06 07:54:40 PM PDT 24 |
| Peak memory | 609424 kb |
| Host | smart-f7414a3a-8b3d-4aa9-b54c-ef677e1a930a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821263 818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.3821263818 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1178924677 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3132660432 ps |
| CPU time | 237.05 seconds |
| Started | Jul 06 07:43:40 PM PDT 24 |
| Finished | Jul 06 07:47:38 PM PDT 24 |
| Peak memory | 608768 kb |
| Host | smart-2c4e0f04-3d7f-4ef4-9816-7171387b7bcd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178924677 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.1178924677 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1384024407 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 8768401500 ps |
| CPU time | 1507.62 seconds |
| Started | Jul 06 07:48:04 PM PDT 24 |
| Finished | Jul 06 08:13:12 PM PDT 24 |
| Peak memory | 609464 kb |
| Host | smart-e802d7e3-86ee-4e3d-84c1-b7790aa5daaa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384024407 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.1384024407 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1584057876 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 6576606680 ps |
| CPU time | 641.73 seconds |
| Started | Jul 06 07:49:55 PM PDT 24 |
| Finished | Jul 06 08:00:37 PM PDT 24 |
| Peak memory | 610888 kb |
| Host | smart-ec18dee1-48b4-4881-97e8-fe2246d0466f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584057876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.1584057876 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2421841573 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 6833910648 ps |
| CPU time | 725.52 seconds |
| Started | Jul 06 07:51:53 PM PDT 24 |
| Finished | Jul 06 08:03:59 PM PDT 24 |
| Peak memory | 610908 kb |
| Host | smart-8a2b6e34-7338-4870-bb66-1b359cc20487 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421841573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.2421841573 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.223792101 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 7336453410 ps |
| CPU time | 862.08 seconds |
| Started | Jul 06 07:45:28 PM PDT 24 |
| Finished | Jul 06 07:59:51 PM PDT 24 |
| Peak memory | 624772 kb |
| Host | smart-3bd98bea-6cfa-4424-9ebf-4bd8fee64729 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223792101 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.223792101 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1763301349 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 4131474774 ps |
| CPU time | 514.54 seconds |
| Started | Jul 06 07:45:36 PM PDT 24 |
| Finished | Jul 06 07:54:12 PM PDT 24 |
| Peak memory | 624760 kb |
| Host | smart-a8d79124-dd20-4d24-b056-24d1c116dabc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763301349 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.1763301349 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.562145868 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3230811829 ps |
| CPU time | 375.55 seconds |
| Started | Jul 06 07:47:43 PM PDT 24 |
| Finished | Jul 06 07:53:59 PM PDT 24 |
| Peak memory | 618168 kb |
| Host | smart-a0e7ce41-c4e1-4401-8aa4-c7befbd57605 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562145868 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.562145868 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.237224036 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 7090882464 ps |
| CPU time | 1093.57 seconds |
| Started | Jul 06 07:49:35 PM PDT 24 |
| Finished | Jul 06 08:07:49 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-b7433a8f-dbb3-4a66-ad12-1bcc0fd388ed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237224036 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.237224036 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1871392732 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 5440002044 ps |
| CPU time | 822.85 seconds |
| Started | Jul 06 07:49:46 PM PDT 24 |
| Finished | Jul 06 08:03:30 PM PDT 24 |
| Peak memory | 610912 kb |
| Host | smart-3f45abe0-68f9-4393-b668-464d733957db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871392732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1871392732 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.424508456 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 4561656228 ps |
| CPU time | 665.47 seconds |
| Started | Jul 06 07:52:21 PM PDT 24 |
| Finished | Jul 06 08:03:28 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-542bb238-a531-4458-b102-d4cd5dc8ba86 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424508456 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.424508456 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1729782920 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 3030354744 ps |
| CPU time | 248.59 seconds |
| Started | Jul 06 07:52:47 PM PDT 24 |
| Finished | Jul 06 07:56:56 PM PDT 24 |
| Peak memory | 610316 kb |
| Host | smart-c6c01f82-f518-4625-8710-0efb29d6a19d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729782920 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.1729782920 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.512641710 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 20865916670 ps |
| CPU time | 3500.86 seconds |
| Started | Jul 06 07:47:38 PM PDT 24 |
| Finished | Jul 06 08:45:59 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-a233148c-a460-4f6c-a118-46c06825c64d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512641710 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.512641710 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2834460901 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 3398754424 ps |
| CPU time | 362.3 seconds |
| Started | Jul 06 07:47:56 PM PDT 24 |
| Finished | Jul 06 07:54:00 PM PDT 24 |
| Peak memory | 613364 kb |
| Host | smart-a1c9ca41-c7a8-4759-8637-13b717c77fa3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834460901 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.2834460901 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3894344076 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3686925490 ps |
| CPU time | 427.29 seconds |
| Started | Jul 06 07:46:42 PM PDT 24 |
| Finished | Jul 06 07:53:50 PM PDT 24 |
| Peak memory | 608724 kb |
| Host | smart-b6b5bffb-2a04-4b7f-8401-4819a7a0ae64 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894344076 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.3894344076 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.287209116 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 22832850040 ps |
| CPU time | 1631.4 seconds |
| Started | Jul 06 07:47:53 PM PDT 24 |
| Finished | Jul 06 08:15:05 PM PDT 24 |
| Peak memory | 614784 kb |
| Host | smart-eeb51859-f229-43ef-b7fe-71e1febd4e5e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28720911 6 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.287209116 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1845631271 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 6221377768 ps |
| CPU time | 444.19 seconds |
| Started | Jul 06 07:47:30 PM PDT 24 |
| Finished | Jul 06 07:54:55 PM PDT 24 |
| Peak memory | 610496 kb |
| Host | smart-46889097-0b45-4499-8cfc-3753aa5d78fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845631271 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1845631271 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3101502352 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 12834847078 ps |
| CPU time | 2722.58 seconds |
| Started | Jul 06 07:44:04 PM PDT 24 |
| Finished | Jul 06 08:29:27 PM PDT 24 |
| Peak memory | 618532 kb |
| Host | smart-1ff05fe7-d92d-4abc-9723-938e268c57cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3101502352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.3101502352 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.3592650982 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 3448193192 ps |
| CPU time | 416 seconds |
| Started | Jul 06 07:54:07 PM PDT 24 |
| Finished | Jul 06 08:01:03 PM PDT 24 |
| Peak memory | 614212 kb |
| Host | smart-94c75c49-5eb8-47b8-b655-2c8f75ec053f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592650982 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.3592650982 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.396475551 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 4091047128 ps |
| CPU time | 691.76 seconds |
| Started | Jul 06 07:48:52 PM PDT 24 |
| Finished | Jul 06 08:00:24 PM PDT 24 |
| Peak memory | 624556 kb |
| Host | smart-9080d23c-1dc4-43f0-85ae-1a28e74135dc |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396475551 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.396475551 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1925528587 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 13319119990 ps |
| CPU time | 2999.39 seconds |
| Started | Jul 06 07:44:25 PM PDT 24 |
| Finished | Jul 06 08:34:26 PM PDT 24 |
| Peak memory | 622824 kb |
| Host | smart-cefe53f0-1502-476a-9d74-e879ddea9123 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925528587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.1925528587 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3052867912 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 13658941801 ps |
| CPU time | 1829.86 seconds |
| Started | Jul 06 07:45:58 PM PDT 24 |
| Finished | Jul 06 08:16:29 PM PDT 24 |
| Peak memory | 623128 kb |
| Host | smart-4823686f-161b-4b7b-a49c-e6dc46bf2411 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052867912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3052867912 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3412080043 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 79236757736 ps |
| CPU time | 15319.7 seconds |
| Started | Jul 06 07:45:17 PM PDT 24 |
| Finished | Jul 07 12:00:39 AM PDT 24 |
| Peak memory | 634992 kb |
| Host | smart-ccbfc3a3-2442-41ee-a1cf-3462347295e5 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3412080043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.3412080043 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2453707681 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 3726530454 ps |
| CPU time | 746.94 seconds |
| Started | Jul 06 07:48:41 PM PDT 24 |
| Finished | Jul 06 08:01:09 PM PDT 24 |
| Peak memory | 624588 kb |
| Host | smart-b8108472-aca4-4433-baf3-9af82b6544e1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453707681 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.2453707681 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3165316870 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 4462341250 ps |
| CPU time | 714.36 seconds |
| Started | Jul 06 07:44:57 PM PDT 24 |
| Finished | Jul 06 07:56:52 PM PDT 24 |
| Peak memory | 624700 kb |
| Host | smart-8e5e08f3-bd4a-4acb-9942-b6ef696e3cf5 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165316870 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.3165316870 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.550455363 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 3560638210 ps |
| CPU time | 616.26 seconds |
| Started | Jul 06 07:44:21 PM PDT 24 |
| Finished | Jul 06 07:54:37 PM PDT 24 |
| Peak memory | 623336 kb |
| Host | smart-c5e6b104-a596-4778-af2d-d356f12ee7dd |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550455363 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.550455363 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.3855258612 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 7620752848 ps |
| CPU time | 824.55 seconds |
| Started | Jul 06 07:50:38 PM PDT 24 |
| Finished | Jul 06 08:04:23 PM PDT 24 |
| Peak memory | 620948 kb |
| Host | smart-eca26327-1c13-4c33-b2fc-f2999542bd8a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855258612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.3855258612 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.2675830962 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 2624104036 ps |
| CPU time | 167.58 seconds |
| Started | Jul 06 07:50:46 PM PDT 24 |
| Finished | Jul 06 07:53:34 PM PDT 24 |
| Peak memory | 620876 kb |
| Host | smart-8ed65bb5-7420-4a15-b2c4-efb1c5a42318 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675830962 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.2675830962 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.1932099818 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 4224981130 ps |
| CPU time | 418.17 seconds |
| Started | Jul 06 07:53:51 PM PDT 24 |
| Finished | Jul 06 08:00:49 PM PDT 24 |
| Peak memory | 620888 kb |
| Host | smart-584eca43-6c6c-43df-be7c-6b185cb518cc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932099818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.1932099818 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.174051661 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 15580985801 ps |
| CPU time | 3631.19 seconds |
| Started | Jul 06 07:57:05 PM PDT 24 |
| Finished | Jul 06 08:57:37 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-dd50604e-0a6f-4631-a4f4-f7707bc99112 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174051661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_dev.174051661 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.1081041144 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 15438027454 ps |
| CPU time | 3528.27 seconds |
| Started | Jul 06 07:57:02 PM PDT 24 |
| Finished | Jul 06 08:55:51 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-28661db3-ebad-4237-afb5-45b41f00b8f0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081041144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.1081041144 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.2155136651 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 14826821817 ps |
| CPU time | 3758.93 seconds |
| Started | Jul 06 07:58:49 PM PDT 24 |
| Finished | Jul 06 09:01:29 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-da9c1a99-174b-4637-b093-174bad827043 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155136651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.2155136651 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2844959660 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 11523898135 ps |
| CPU time | 2754.48 seconds |
| Started | Jul 06 07:57:43 PM PDT 24 |
| Finished | Jul 06 08:43:38 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-b86f3f9e-5535-4d33-9b87-8714d99021b6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844959660 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.2844959660 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.821017576 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 14917739784 ps |
| CPU time | 3615.12 seconds |
| Started | Jul 06 07:57:36 PM PDT 24 |
| Finished | Jul 06 08:57:52 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-1f429cd0-aa8e-4d4d-993a-6fc443a65506 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821017576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_ini t_rom_ext_invalid_meas.821017576 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1276119729 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 14876034320 ps |
| CPU time | 3754.4 seconds |
| Started | Jul 06 07:56:46 PM PDT 24 |
| Finished | Jul 06 08:59:21 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-4e1eaf60-e7ed-406f-a885-5298bad3ce8d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276119729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.1276119729 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3196671137 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 15301717932 ps |
| CPU time | 3450.05 seconds |
| Started | Jul 06 07:56:59 PM PDT 24 |
| Finished | Jul 06 08:54:30 PM PDT 24 |
| Peak memory | 609456 kb |
| Host | smart-820c9dd6-5760-417f-b820-d27c04975bdf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196671137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.3196671137 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.261182020 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 15045063796 ps |
| CPU time | 3349.69 seconds |
| Started | Jul 06 07:59:09 PM PDT 24 |
| Finished | Jul 06 08:55:00 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-34ea1ba1-71ae-471e-8d28-7fbc88a14efc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261182020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_s hutdown_exception_c.261182020 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.527365623 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 28386304184 ps |
| CPU time | 3623.53 seconds |
| Started | Jul 06 07:57:02 PM PDT 24 |
| Finished | Jul 06 08:57:26 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-76853a6a-6a0b-4e43-b63d-3e386db4150f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527365623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.527365623 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.1618426303 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 14970736830 ps |
| CPU time | 4105.41 seconds |
| Started | Jul 06 07:59:13 PM PDT 24 |
| Finished | Jul 06 09:07:40 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-02abfbcf-2ae4-422a-9310-9475f814540c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1618426303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.1618426303 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.353152907 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 17181674800 ps |
| CPU time | 4215 seconds |
| Started | Jul 06 07:56:09 PM PDT 24 |
| Finished | Jul 06 09:06:25 PM PDT 24 |
| Peak memory | 609012 kb |
| Host | smart-f0dc4db5-3b59-4b5e-89db-079778ba8cde |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353152907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.353152907 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.2453329287 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 4206720668 ps |
| CPU time | 892.4 seconds |
| Started | Jul 06 07:53:17 PM PDT 24 |
| Finished | Jul 06 08:08:10 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-94c0260c-8105-49c2-a7f0-93cf111503d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453329287 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.2453329287 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.3406737010 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 5711768144 ps |
| CPU time | 277.02 seconds |
| Started | Jul 06 07:53:07 PM PDT 24 |
| Finished | Jul 06 07:57:44 PM PDT 24 |
| Peak memory | 619396 kb |
| Host | smart-67c1e2b6-299c-40c6-baeb-d84eba3f47c6 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3406737010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.3406737010 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.2139511022 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 2004982314 ps |
| CPU time | 107.87 seconds |
| Started | Jul 06 07:52:57 PM PDT 24 |
| Finished | Jul 06 07:54:46 PM PDT 24 |
| Peak memory | 617416 kb |
| Host | smart-445e80a8-704b-4530-b3a8-10ecc391f091 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139511022 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.2139511022 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3176547854 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 3481355832 ps |
| CPU time | 443.58 seconds |
| Started | Jul 06 07:58:03 PM PDT 24 |
| Finished | Jul 06 08:05:27 PM PDT 24 |
| Peak memory | 648896 kb |
| Host | smart-4b243538-7e81-4f00-96fc-3aafd09fd549 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176547854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3176547854 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.75155972 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 3814049092 ps |
| CPU time | 370.89 seconds |
| Started | Jul 06 08:05:37 PM PDT 24 |
| Finished | Jul 06 08:11:49 PM PDT 24 |
| Peak memory | 648712 kb |
| Host | smart-bf063442-f30b-41c9-90b9-e14a1b416401 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75155972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw _alert_handler_lpg_sleep_mode_alerts.75155972 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1245925854 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 4332995056 ps |
| CPU time | 475.69 seconds |
| Started | Jul 06 07:59:25 PM PDT 24 |
| Finished | Jul 06 08:07:21 PM PDT 24 |
| Peak memory | 649184 kb |
| Host | smart-329ab64a-c281-4453-9db0-97aa3727c9f9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245925854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1245925854 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.4028492693 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 3710121712 ps |
| CPU time | 340.68 seconds |
| Started | Jul 06 07:59:11 PM PDT 24 |
| Finished | Jul 06 08:04:52 PM PDT 24 |
| Peak memory | 649216 kb |
| Host | smart-ba60fbaf-81a0-457b-8b7d-a1e9db43866a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028492693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4028492693 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.2258320440 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 5242734422 ps |
| CPU time | 925.58 seconds |
| Started | Jul 06 07:58:17 PM PDT 24 |
| Finished | Jul 06 08:13:43 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-4febbca8-f424-4446-aa9d-81f664d43a70 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2258320440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.2258320440 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1090189738 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 4196141088 ps |
| CPU time | 436.83 seconds |
| Started | Jul 06 07:58:20 PM PDT 24 |
| Finished | Jul 06 08:05:37 PM PDT 24 |
| Peak memory | 648688 kb |
| Host | smart-1d62b6d0-df30-4626-a75f-927d705e055f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090189738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1090189738 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.544480693 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 5606495110 ps |
| CPU time | 588.19 seconds |
| Started | Jul 06 07:58:53 PM PDT 24 |
| Finished | Jul 06 08:08:41 PM PDT 24 |
| Peak memory | 650148 kb |
| Host | smart-5e7e5600-0a0c-45e3-b157-dc249015797f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 544480693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.544480693 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2336811713 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3743355936 ps |
| CPU time | 585.24 seconds |
| Started | Jul 06 07:59:40 PM PDT 24 |
| Finished | Jul 06 08:09:26 PM PDT 24 |
| Peak memory | 648724 kb |
| Host | smart-c640bad1-e83c-40d8-8665-a74fb1e76206 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336811713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2336811713 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.807769003 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 3108787536 ps |
| CPU time | 381.38 seconds |
| Started | Jul 06 07:58:55 PM PDT 24 |
| Finished | Jul 06 08:05:17 PM PDT 24 |
| Peak memory | 618752 kb |
| Host | smart-2c4c822d-481c-4861-b7b6-f933897fc2cf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807769003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_s w_alert_handler_lpg_sleep_mode_alerts.807769003 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.3539282121 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 5662797376 ps |
| CPU time | 632.05 seconds |
| Started | Jul 06 07:54:26 PM PDT 24 |
| Finished | Jul 06 08:04:58 PM PDT 24 |
| Peak memory | 649940 kb |
| Host | smart-874139a9-3973-4f1c-b6ab-6061bfc203a7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3539282121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.3539282121 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1087156616 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 6190638796 ps |
| CPU time | 459.05 seconds |
| Started | Jul 06 07:55:03 PM PDT 24 |
| Finished | Jul 06 08:02:42 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-4be8bec9-cdd5-4e04-8de3-d83c9a337841 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1087156616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1087156616 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1610713154 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 29869558516 ps |
| CPU time | 7003.51 seconds |
| Started | Jul 06 07:53:46 PM PDT 24 |
| Finished | Jul 06 09:50:31 PM PDT 24 |
| Peak memory | 610508 kb |
| Host | smart-36d0d95e-f517-46d7-8724-fd3a76f55c00 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610713154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.1610713154 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.2341436433 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 6517826940 ps |
| CPU time | 1003.9 seconds |
| Started | Jul 06 07:55:23 PM PDT 24 |
| Finished | Jul 06 08:12:07 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-8807a84c-b2a1-4f7b-b1f2-ef2c3678a2f4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2341436433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.2341436433 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1489068170 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 13311752406 ps |
| CPU time | 1271.01 seconds |
| Started | Jul 06 07:53:23 PM PDT 24 |
| Finished | Jul 06 08:14:35 PM PDT 24 |
| Peak memory | 622480 kb |
| Host | smart-f01bea7a-8f4a-4811-87a1-ba67b7d3aed2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489068170 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.1489068170 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1988679004 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 6763717310 ps |
| CPU time | 953.41 seconds |
| Started | Jul 06 07:55:07 PM PDT 24 |
| Finished | Jul 06 08:11:01 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-88edb049-b4d7-44c5-9b60-17abce3effda |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19886790 04 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.1988679004 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.204278863 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 13519148044 ps |
| CPU time | 2513.33 seconds |
| Started | Jul 06 07:53:37 PM PDT 24 |
| Finished | Jul 06 08:35:32 PM PDT 24 |
| Peak memory | 618712 kb |
| Host | smart-88128ef9-c94f-4f6e-b813-0b169f51ae15 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=204278863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.204278863 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.1483129525 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 4564027340 ps |
| CPU time | 690.2 seconds |
| Started | Jul 06 07:54:33 PM PDT 24 |
| Finished | Jul 06 08:06:04 PM PDT 24 |
| Peak memory | 623712 kb |
| Host | smart-f5865ccd-ab32-4845-9a96-8b9ca0336cc7 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483129525 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.1483129525 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.961559476 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 12873696735 ps |
| CPU time | 2889.11 seconds |
| Started | Jul 06 07:54:52 PM PDT 24 |
| Finished | Jul 06 08:43:01 PM PDT 24 |
| Peak memory | 622908 kb |
| Host | smart-71d11ab7-7d8b-4373-89ae-273e5248eb18 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961559476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_ alt_clk_freq.961559476 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1303200741 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 4450851402 ps |
| CPU time | 374.19 seconds |
| Started | Jul 06 07:55:45 PM PDT 24 |
| Finished | Jul 06 08:02:01 PM PDT 24 |
| Peak memory | 623192 kb |
| Host | smart-0dea62e7-f7de-416f-8867-6bff2f850926 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303200741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1303200741 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3522477234 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 4805383218 ps |
| CPU time | 781.42 seconds |
| Started | Jul 06 07:53:58 PM PDT 24 |
| Finished | Jul 06 08:07:01 PM PDT 24 |
| Peak memory | 624704 kb |
| Host | smart-20257fdb-c3ca-49f6-b035-8e2987e8a029 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522477234 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.3522477234 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.522293107 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 4259685120 ps |
| CPU time | 716.53 seconds |
| Started | Jul 06 07:56:34 PM PDT 24 |
| Finished | Jul 06 08:08:31 PM PDT 24 |
| Peak memory | 624572 kb |
| Host | smart-836afa47-150c-44c5-8997-340c3af82b2f |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522293107 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.522293107 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.51017004 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 4480541802 ps |
| CPU time | 780.73 seconds |
| Started | Jul 06 07:54:07 PM PDT 24 |
| Finished | Jul 06 08:07:08 PM PDT 24 |
| Peak memory | 624668 kb |
| Host | smart-31dfac40-fdd6-4f73-8596-2a02914aaa8b |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51017004 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.51017004 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.4011439605 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4275076524 ps |
| CPU time | 299.97 seconds |
| Started | Jul 06 07:53:39 PM PDT 24 |
| Finished | Jul 06 07:58:39 PM PDT 24 |
| Peak memory | 622016 kb |
| Host | smart-3c39f358-d533-4eb2-8d0b-7d2ede502eef |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4011439605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.4011439605 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.183780843 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 2542602289 ps |
| CPU time | 183.66 seconds |
| Started | Jul 06 07:54:38 PM PDT 24 |
| Finished | Jul 06 07:57:42 PM PDT 24 |
| Peak memory | 621692 kb |
| Host | smart-77be226a-d556-4ee8-b69f-bf768940a860 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183780843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.183780843 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.1170148947 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 4825002676 ps |
| CPU time | 855.42 seconds |
| Started | Jul 06 07:59:40 PM PDT 24 |
| Finished | Jul 06 08:13:56 PM PDT 24 |
| Peak memory | 650124 kb |
| Host | smart-ebcaa3aa-7161-4638-9d52-4e0fb774747c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1170148947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.1170148947 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2459633596 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 4144103428 ps |
| CPU time | 457.17 seconds |
| Started | Jul 06 07:59:41 PM PDT 24 |
| Finished | Jul 06 08:07:19 PM PDT 24 |
| Peak memory | 649148 kb |
| Host | smart-a4551e37-a4c8-4507-b4ae-9e5b5b95f40f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459633596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2459633596 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115277716 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 3820024624 ps |
| CPU time | 411.17 seconds |
| Started | Jul 06 08:00:17 PM PDT 24 |
| Finished | Jul 06 08:07:09 PM PDT 24 |
| Peak memory | 648824 kb |
| Host | smart-9836475d-8494-4689-9958-4edcf5cb5d99 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115277716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1115277716 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1614032564 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 4227636772 ps |
| CPU time | 431.72 seconds |
| Started | Jul 06 07:59:27 PM PDT 24 |
| Finished | Jul 06 08:06:39 PM PDT 24 |
| Peak memory | 648840 kb |
| Host | smart-ed3e31a9-7580-4212-9f76-fb10f1f485b6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614032564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1614032564 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.3736022418 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 4755863496 ps |
| CPU time | 545.06 seconds |
| Started | Jul 06 08:00:15 PM PDT 24 |
| Finished | Jul 06 08:09:21 PM PDT 24 |
| Peak memory | 619728 kb |
| Host | smart-83635116-8235-4ca3-8245-5b451699475a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3736022418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.3736022418 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1718324491 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 3934998160 ps |
| CPU time | 405.41 seconds |
| Started | Jul 06 08:00:04 PM PDT 24 |
| Finished | Jul 06 08:06:50 PM PDT 24 |
| Peak memory | 648744 kb |
| Host | smart-e1a8f2bd-0791-4a36-97f3-d95b65cc82ee |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718324491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1718324491 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3729242554 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 7155711416 ps |
| CPU time | 463.83 seconds |
| Started | Jul 06 07:56:07 PM PDT 24 |
| Finished | Jul 06 08:03:51 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-858c0cd4-baa2-41d1-b9f0-3fb9531e9023 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3729242554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3729242554 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2414730275 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 9561833960 ps |
| CPU time | 2460.65 seconds |
| Started | Jul 06 07:56:00 PM PDT 24 |
| Finished | Jul 06 08:37:01 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-25131e3b-1ec9-4e02-9c45-1be5fee88fb2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414730275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.2414730275 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2346083464 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 4991425166 ps |
| CPU time | 827.69 seconds |
| Started | Jul 06 07:54:35 PM PDT 24 |
| Finished | Jul 06 08:08:24 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-22198263-2200-48ce-829f-eade7a467a59 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2346083464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.2346083464 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2392297538 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 10834509342 ps |
| CPU time | 687.04 seconds |
| Started | Jul 06 07:55:04 PM PDT 24 |
| Finished | Jul 06 08:06:31 PM PDT 24 |
| Peak memory | 622916 kb |
| Host | smart-c80d07f3-3888-497e-8ae7-bb08a9ca2796 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392297538 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.2392297538 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.464162550 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 6292744856 ps |
| CPU time | 1062.43 seconds |
| Started | Jul 06 07:55:42 PM PDT 24 |
| Finished | Jul 06 08:13:24 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-c6cb456a-383a-48d9-9e29-61c7004cfdec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46416255 0 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.464162550 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.62484810 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 4511068808 ps |
| CPU time | 660.14 seconds |
| Started | Jul 06 07:56:18 PM PDT 24 |
| Finished | Jul 06 08:07:18 PM PDT 24 |
| Peak memory | 621980 kb |
| Host | smart-25cf865c-3cb6-4bff-98c6-73c886c680d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=62484810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.62484810 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.1766494952 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 4264254850 ps |
| CPU time | 670.91 seconds |
| Started | Jul 06 07:54:23 PM PDT 24 |
| Finished | Jul 06 08:05:35 PM PDT 24 |
| Peak memory | 624528 kb |
| Host | smart-213c0cdf-897e-46b1-a3fd-a2fc2485ef56 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766494952 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.1766494952 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.716353356 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 7915441865 ps |
| CPU time | 1659.23 seconds |
| Started | Jul 06 07:55:26 PM PDT 24 |
| Finished | Jul 06 08:23:06 PM PDT 24 |
| Peak memory | 618588 kb |
| Host | smart-36c97dec-5f72-4266-b685-9f4dfccfe723 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716353356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_ alt_clk_freq.716353356 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4111467760 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 3822591621 ps |
| CPU time | 640.72 seconds |
| Started | Jul 06 07:55:23 PM PDT 24 |
| Finished | Jul 06 08:06:05 PM PDT 24 |
| Peak memory | 622844 kb |
| Host | smart-fc8f8bce-e504-48ab-a1cb-4c406915c97f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111467760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.4111467760 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2870311391 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 4200410576 ps |
| CPU time | 512.42 seconds |
| Started | Jul 06 07:54:13 PM PDT 24 |
| Finished | Jul 06 08:02:46 PM PDT 24 |
| Peak memory | 623352 kb |
| Host | smart-7047d63c-e403-4944-85b4-5d4eef1de4ab |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870311391 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.2870311391 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.25705700 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 3783051380 ps |
| CPU time | 690.25 seconds |
| Started | Jul 06 07:55:28 PM PDT 24 |
| Finished | Jul 06 08:06:59 PM PDT 24 |
| Peak memory | 623372 kb |
| Host | smart-15814628-038e-4f78-adaf-5fbbbe7e1910 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25705700 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.25705700 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2886986309 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 4479347640 ps |
| CPU time | 605.79 seconds |
| Started | Jul 06 07:55:13 PM PDT 24 |
| Finished | Jul 06 08:05:19 PM PDT 24 |
| Peak memory | 624688 kb |
| Host | smart-c91201a7-e567-41b5-b76c-ed13d462f331 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886986309 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.2886986309 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.2944427728 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 2906780563 ps |
| CPU time | 249.5 seconds |
| Started | Jul 06 07:55:37 PM PDT 24 |
| Finished | Jul 06 07:59:47 PM PDT 24 |
| Peak memory | 620732 kb |
| Host | smart-beae0a7f-191f-4f57-9cf3-702cc2577f4e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2944427728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.2944427728 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.3585056054 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 3097196326 ps |
| CPU time | 131.23 seconds |
| Started | Jul 06 07:55:26 PM PDT 24 |
| Finished | Jul 06 07:57:38 PM PDT 24 |
| Peak memory | 623284 kb |
| Host | smart-7701d661-6fba-4aa4-bed9-9fc0d4b3a3c1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585056054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.3585056054 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.1264742642 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 6198842267 ps |
| CPU time | 675.99 seconds |
| Started | Jul 06 07:55:07 PM PDT 24 |
| Finished | Jul 06 08:06:23 PM PDT 24 |
| Peak memory | 624368 kb |
| Host | smart-042aed39-d260-4f1a-9506-211a40ae61ec |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1264742642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.1264742642 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3099710199 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 4153505578 ps |
| CPU time | 337.64 seconds |
| Started | Jul 06 08:00:24 PM PDT 24 |
| Finished | Jul 06 08:06:02 PM PDT 24 |
| Peak memory | 648800 kb |
| Host | smart-2eabdc15-770e-4f17-9068-097a2adeb92c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099710199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3099710199 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.3621281211 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 5123507024 ps |
| CPU time | 697.71 seconds |
| Started | Jul 06 07:59:39 PM PDT 24 |
| Finished | Jul 06 08:11:18 PM PDT 24 |
| Peak memory | 649800 kb |
| Host | smart-c6f50ea7-9c94-4c17-bb3b-ed8fe20f9433 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3621281211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.3621281211 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.163949658 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 5034833848 ps |
| CPU time | 776.19 seconds |
| Started | Jul 06 08:00:15 PM PDT 24 |
| Finished | Jul 06 08:13:12 PM PDT 24 |
| Peak memory | 650332 kb |
| Host | smart-f7a52349-b1d2-4188-a752-cf51a5da07f6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 163949658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.163949658 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.4027330379 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 4387908288 ps |
| CPU time | 360.84 seconds |
| Started | Jul 06 08:00:39 PM PDT 24 |
| Finished | Jul 06 08:06:40 PM PDT 24 |
| Peak memory | 619104 kb |
| Host | smart-e7c9f864-3d98-430d-b700-5818338e15c0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027330379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4027330379 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.1050108084 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 6129239168 ps |
| CPU time | 772.32 seconds |
| Started | Jul 06 08:01:19 PM PDT 24 |
| Finished | Jul 06 08:14:13 PM PDT 24 |
| Peak memory | 650072 kb |
| Host | smart-62aab2da-5809-48fd-b0ae-5b5633c97ab7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1050108084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.1050108084 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1733437303 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 4097799476 ps |
| CPU time | 440.95 seconds |
| Started | Jul 06 08:00:41 PM PDT 24 |
| Finished | Jul 06 08:08:03 PM PDT 24 |
| Peak memory | 618768 kb |
| Host | smart-5c983c51-a001-465f-87e5-5a5b78c0357a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733437303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1733437303 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.3198486171 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 4774858582 ps |
| CPU time | 634.75 seconds |
| Started | Jul 06 07:59:39 PM PDT 24 |
| Finished | Jul 06 08:10:15 PM PDT 24 |
| Peak memory | 650040 kb |
| Host | smart-7fa064e5-d8a8-415e-9cac-afc422edd288 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3198486171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.3198486171 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2872098762 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 4008806784 ps |
| CPU time | 461.14 seconds |
| Started | Jul 06 08:00:38 PM PDT 24 |
| Finished | Jul 06 08:08:20 PM PDT 24 |
| Peak memory | 648628 kb |
| Host | smart-ead039bf-0ae0-49de-9f0e-ef2aff3e7e85 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872098762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2872098762 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1489347743 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 3326302264 ps |
| CPU time | 415.31 seconds |
| Started | Jul 06 08:04:00 PM PDT 24 |
| Finished | Jul 06 08:10:56 PM PDT 24 |
| Peak memory | 648732 kb |
| Host | smart-12538af4-4592-4c80-a66d-1def05d32876 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489347743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1489347743 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3012212536 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3642873086 ps |
| CPU time | 451.07 seconds |
| Started | Jul 06 08:04:32 PM PDT 24 |
| Finished | Jul 06 08:12:04 PM PDT 24 |
| Peak memory | 648564 kb |
| Host | smart-d0c2a887-22b8-4319-9fb0-d13d62ae27e2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012212536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3012212536 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.3105711799 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 5393209610 ps |
| CPU time | 620.17 seconds |
| Started | Jul 06 08:04:16 PM PDT 24 |
| Finished | Jul 06 08:14:36 PM PDT 24 |
| Peak memory | 619568 kb |
| Host | smart-257e2b27-f2a3-4c9c-9371-bd894ac317ca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3105711799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.3105711799 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.1526560403 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 4049598124 ps |
| CPU time | 672.65 seconds |
| Started | Jul 06 08:00:38 PM PDT 24 |
| Finished | Jul 06 08:11:51 PM PDT 24 |
| Peak memory | 649692 kb |
| Host | smart-435d3c17-efe0-4bfc-ac87-c197989f9c80 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1526560403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.1526560403 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3193756489 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 21317852862 ps |
| CPU time | 4887.7 seconds |
| Started | Jul 06 07:56:06 PM PDT 24 |
| Finished | Jul 06 09:17:35 PM PDT 24 |
| Peak memory | 610532 kb |
| Host | smart-aecbace7-aca3-4dde-bae0-a65f9f26c15c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193756489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.3193756489 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2915813424 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 4966472080 ps |
| CPU time | 887.89 seconds |
| Started | Jul 06 07:56:16 PM PDT 24 |
| Finished | Jul 06 08:11:05 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-d21e3250-f6c6-4eee-a140-7716f46eb46c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2915813424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.2915813424 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3164717889 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 5311633909 ps |
| CPU time | 575.95 seconds |
| Started | Jul 06 07:55:07 PM PDT 24 |
| Finished | Jul 06 08:04:43 PM PDT 24 |
| Peak memory | 621180 kb |
| Host | smart-694c3709-3552-407e-86dd-edf365f9ca0a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164717889 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.3164717889 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3151082433 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 8578759732 ps |
| CPU time | 1736.42 seconds |
| Started | Jul 06 07:55:12 PM PDT 24 |
| Finished | Jul 06 08:24:10 PM PDT 24 |
| Peak memory | 621796 kb |
| Host | smart-fd142d74-be1e-4c75-8864-b460515eff35 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3151082433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.3151082433 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1514148462 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 3398106254 ps |
| CPU time | 490.1 seconds |
| Started | Jul 06 08:04:26 PM PDT 24 |
| Finished | Jul 06 08:12:36 PM PDT 24 |
| Peak memory | 648980 kb |
| Host | smart-0e3d5588-3678-436d-af47-f150f27cbe10 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514148462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1514148462 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.4054064177 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 5023717288 ps |
| CPU time | 626.31 seconds |
| Started | Jul 06 08:01:09 PM PDT 24 |
| Finished | Jul 06 08:11:35 PM PDT 24 |
| Peak memory | 649868 kb |
| Host | smart-8419ad93-22eb-4e8d-9547-6537c1f2fbb4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4054064177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.4054064177 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2127551754 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 4445308018 ps |
| CPU time | 399.35 seconds |
| Started | Jul 06 08:01:34 PM PDT 24 |
| Finished | Jul 06 08:08:13 PM PDT 24 |
| Peak memory | 649296 kb |
| Host | smart-323da8db-510a-4803-9b99-5b5b595f911b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127551754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2127551754 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.2910488556 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 5527530444 ps |
| CPU time | 737.88 seconds |
| Started | Jul 06 08:00:36 PM PDT 24 |
| Finished | Jul 06 08:12:54 PM PDT 24 |
| Peak memory | 649768 kb |
| Host | smart-feb85d1a-a4d1-4c79-82f4-54d7a26531b6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2910488556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.2910488556 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3137016286 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 3887387072 ps |
| CPU time | 473.56 seconds |
| Started | Jul 06 08:01:20 PM PDT 24 |
| Finished | Jul 06 08:09:14 PM PDT 24 |
| Peak memory | 618736 kb |
| Host | smart-4c032d6b-7b9f-44a2-a548-4f8a0e238362 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137016286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3137016286 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.944194434 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 5488735414 ps |
| CPU time | 588.98 seconds |
| Started | Jul 06 08:01:08 PM PDT 24 |
| Finished | Jul 06 08:10:57 PM PDT 24 |
| Peak memory | 649760 kb |
| Host | smart-6d6ecb1e-d4dc-4b03-b306-18f7a5108fc3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 944194434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.944194434 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3423105582 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 4284790192 ps |
| CPU time | 469.77 seconds |
| Started | Jul 06 08:01:32 PM PDT 24 |
| Finished | Jul 06 08:09:22 PM PDT 24 |
| Peak memory | 648816 kb |
| Host | smart-942e2363-7262-4bbb-8202-a6441820b91a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423105582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3423105582 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.3144668015 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 6504489128 ps |
| CPU time | 747.13 seconds |
| Started | Jul 06 08:01:27 PM PDT 24 |
| Finished | Jul 06 08:13:55 PM PDT 24 |
| Peak memory | 651196 kb |
| Host | smart-a5ae7d7b-2a66-43fb-9438-92fca6d7e10e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3144668015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.3144668015 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3907466585 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 4591827270 ps |
| CPU time | 455.82 seconds |
| Started | Jul 06 08:02:25 PM PDT 24 |
| Finished | Jul 06 08:10:01 PM PDT 24 |
| Peak memory | 649308 kb |
| Host | smart-e8972c48-b03a-4d06-95af-e760de70baef |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907466585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3907466585 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2204637978 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 4698166444 ps |
| CPU time | 491.77 seconds |
| Started | Jul 06 08:03:57 PM PDT 24 |
| Finished | Jul 06 08:12:09 PM PDT 24 |
| Peak memory | 649084 kb |
| Host | smart-d9ba7557-434c-48c6-bfd9-b1f8e7de9947 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204637978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2204637978 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.1611893892 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 4402582962 ps |
| CPU time | 544.65 seconds |
| Started | Jul 06 08:01:17 PM PDT 24 |
| Finished | Jul 06 08:10:22 PM PDT 24 |
| Peak memory | 649888 kb |
| Host | smart-ca3e628d-f06a-43f4-aa59-59e29a40c509 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1611893892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.1611893892 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3287056493 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 3832707320 ps |
| CPU time | 378.92 seconds |
| Started | Jul 06 08:02:38 PM PDT 24 |
| Finished | Jul 06 08:08:57 PM PDT 24 |
| Peak memory | 648856 kb |
| Host | smart-b69901b7-a556-4e8a-bbb9-f6151c889fb7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287056493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3287056493 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.271744391 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 5183295208 ps |
| CPU time | 653.43 seconds |
| Started | Jul 06 08:02:48 PM PDT 24 |
| Finished | Jul 06 08:13:42 PM PDT 24 |
| Peak memory | 649872 kb |
| Host | smart-78b47b22-fddc-4e4f-a20a-b484aef5a5b0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 271744391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.271744391 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.2844609632 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 4467315930 ps |
| CPU time | 609.18 seconds |
| Started | Jul 06 08:03:01 PM PDT 24 |
| Finished | Jul 06 08:13:10 PM PDT 24 |
| Peak memory | 619324 kb |
| Host | smart-70dbf664-6d5a-4cd0-8c16-2a1b88c75dde |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2844609632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.2844609632 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.3549532407 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 5143909324 ps |
| CPU time | 571.7 seconds |
| Started | Jul 06 08:02:20 PM PDT 24 |
| Finished | Jul 06 08:11:52 PM PDT 24 |
| Peak memory | 650292 kb |
| Host | smart-0f152a25-3f9a-40bd-81a1-f351a0f951f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3549532407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.3549532407 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.2054452668 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 5203806900 ps |
| CPU time | 623.76 seconds |
| Started | Jul 06 07:55:48 PM PDT 24 |
| Finished | Jul 06 08:06:12 PM PDT 24 |
| Peak memory | 649880 kb |
| Host | smart-ab1e97f0-6425-46ec-9236-7d67db60e203 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2054452668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.2054452668 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2217967441 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 15452641290 ps |
| CPU time | 3208.74 seconds |
| Started | Jul 06 07:56:56 PM PDT 24 |
| Finished | Jul 06 08:50:26 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-4fea0eae-dcfc-4aa5-8391-e0fef4cb208e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217967441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.2217967441 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.4142188142 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 11957226636 ps |
| CPU time | 1346.35 seconds |
| Started | Jul 06 07:56:16 PM PDT 24 |
| Finished | Jul 06 08:18:43 PM PDT 24 |
| Peak memory | 624808 kb |
| Host | smart-9b093c3f-14d5-4217-907e-225a0d4c96dc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142188142 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.4142188142 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3437433903 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 4069631570 ps |
| CPU time | 562.62 seconds |
| Started | Jul 06 07:56:44 PM PDT 24 |
| Finished | Jul 06 08:06:07 PM PDT 24 |
| Peak memory | 618668 kb |
| Host | smart-c07e6428-6146-4124-8f9b-b5ca52a0c58a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3437433903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.3437433903 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3398721804 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 3566728252 ps |
| CPU time | 475.94 seconds |
| Started | Jul 06 08:03:42 PM PDT 24 |
| Finished | Jul 06 08:11:38 PM PDT 24 |
| Peak memory | 648592 kb |
| Host | smart-0db5daf3-5a21-44cf-8643-fd07be23828e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398721804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3398721804 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.3449850696 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 6077745580 ps |
| CPU time | 683.24 seconds |
| Started | Jul 06 08:03:40 PM PDT 24 |
| Finished | Jul 06 08:15:04 PM PDT 24 |
| Peak memory | 619668 kb |
| Host | smart-a8d47f0b-7afe-4b00-a6db-e97e60aa0fcf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3449850696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.3449850696 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.800329304 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 3173173500 ps |
| CPU time | 376.59 seconds |
| Started | Jul 06 08:02:24 PM PDT 24 |
| Finished | Jul 06 08:08:41 PM PDT 24 |
| Peak memory | 648904 kb |
| Host | smart-f11a36cb-8939-465d-b942-035f867ca3a3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800329304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_s w_alert_handler_lpg_sleep_mode_alerts.800329304 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.215540308 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3886128260 ps |
| CPU time | 415.48 seconds |
| Started | Jul 06 08:03:34 PM PDT 24 |
| Finished | Jul 06 08:10:31 PM PDT 24 |
| Peak memory | 649140 kb |
| Host | smart-8247bfb0-d21e-478c-9f3e-a029f48b7279 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215540308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_s w_alert_handler_lpg_sleep_mode_alerts.215540308 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.3294657851 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 4174577698 ps |
| CPU time | 529.52 seconds |
| Started | Jul 06 08:02:41 PM PDT 24 |
| Finished | Jul 06 08:11:31 PM PDT 24 |
| Peak memory | 649704 kb |
| Host | smart-47e7f6c1-73bf-4ed1-891d-dd3e81a59b48 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3294657851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.3294657851 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.1968089639 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 4947645920 ps |
| CPU time | 648.38 seconds |
| Started | Jul 06 08:03:10 PM PDT 24 |
| Finished | Jul 06 08:13:59 PM PDT 24 |
| Peak memory | 650104 kb |
| Host | smart-9b273594-4661-4243-ba13-3a0061941ed8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1968089639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.1968089639 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3295217569 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 3771167560 ps |
| CPU time | 431.54 seconds |
| Started | Jul 06 08:02:18 PM PDT 24 |
| Finished | Jul 06 08:09:30 PM PDT 24 |
| Peak memory | 648784 kb |
| Host | smart-0268c58d-3d00-4607-beec-357f9fce545b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295217569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3295217569 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.162867108 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 4844668224 ps |
| CPU time | 591.79 seconds |
| Started | Jul 06 08:04:18 PM PDT 24 |
| Finished | Jul 06 08:14:11 PM PDT 24 |
| Peak memory | 619708 kb |
| Host | smart-8f79a456-c8a1-4a4a-aeee-85fc49b48d01 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 162867108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.162867108 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.876723664 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 3566073688 ps |
| CPU time | 410.08 seconds |
| Started | Jul 06 08:02:07 PM PDT 24 |
| Finished | Jul 06 08:08:58 PM PDT 24 |
| Peak memory | 648640 kb |
| Host | smart-e72115d3-175d-409c-8a37-2103a62778f4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876723664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_s w_alert_handler_lpg_sleep_mode_alerts.876723664 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.3096764364 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 5168446408 ps |
| CPU time | 739.18 seconds |
| Started | Jul 06 08:02:27 PM PDT 24 |
| Finished | Jul 06 08:14:46 PM PDT 24 |
| Peak memory | 650144 kb |
| Host | smart-2d733fa9-c504-4b16-b609-1e643e9134ce |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3096764364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.3096764364 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2867517972 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 3530242376 ps |
| CPU time | 443.28 seconds |
| Started | Jul 06 08:04:25 PM PDT 24 |
| Finished | Jul 06 08:11:48 PM PDT 24 |
| Peak memory | 648824 kb |
| Host | smart-5b8c02e5-feef-49f5-aa2e-a961c7fe30b6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867517972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2867517972 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1540053533 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 3395949780 ps |
| CPU time | 369.23 seconds |
| Started | Jul 06 08:03:55 PM PDT 24 |
| Finished | Jul 06 08:10:05 PM PDT 24 |
| Peak memory | 648836 kb |
| Host | smart-827ae0fe-51b9-476b-858c-0e7866dc8f17 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540053533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1540053533 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.44344951 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 5069851720 ps |
| CPU time | 681.46 seconds |
| Started | Jul 06 08:04:21 PM PDT 24 |
| Finished | Jul 06 08:15:43 PM PDT 24 |
| Peak memory | 650080 kb |
| Host | smart-1a033632-91a7-437e-81ea-ba23f6a652d3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 44344951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.44344951 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.948842586 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 3424465956 ps |
| CPU time | 455.76 seconds |
| Started | Jul 06 07:56:09 PM PDT 24 |
| Finished | Jul 06 08:03:45 PM PDT 24 |
| Peak memory | 648908 kb |
| Host | smart-2682967a-ad75-49bb-a31d-d77756d6bea7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948842586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw _alert_handler_lpg_sleep_mode_alerts.948842586 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.3147643299 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 5876237606 ps |
| CPU time | 779.63 seconds |
| Started | Jul 06 07:56:15 PM PDT 24 |
| Finished | Jul 06 08:09:16 PM PDT 24 |
| Peak memory | 650000 kb |
| Host | smart-40c89593-b865-490b-8925-698cd2ddc86f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3147643299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.3147643299 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2564062315 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 14517487160 ps |
| CPU time | 3258.42 seconds |
| Started | Jul 06 07:57:54 PM PDT 24 |
| Finished | Jul 06 08:52:14 PM PDT 24 |
| Peak memory | 610460 kb |
| Host | smart-d95193ee-17bf-4827-8a4a-8dfbe3e8fe4d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564062315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.2564062315 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.827857402 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 6025460159 ps |
| CPU time | 409.18 seconds |
| Started | Jul 06 07:56:36 PM PDT 24 |
| Finished | Jul 06 08:03:26 PM PDT 24 |
| Peak memory | 622236 kb |
| Host | smart-30f19ad7-4e5c-47e6-a24f-65b40df20503 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827857402 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.827857402 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.261271027 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 12928265472 ps |
| CPU time | 2572.82 seconds |
| Started | Jul 06 07:55:29 PM PDT 24 |
| Finished | Jul 06 08:38:22 PM PDT 24 |
| Peak memory | 621820 kb |
| Host | smart-dce6ebeb-ccd5-4cfe-959a-76cd9c591d3f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=261271027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.261271027 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2038362924 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 3807507192 ps |
| CPU time | 469.5 seconds |
| Started | Jul 06 08:03:00 PM PDT 24 |
| Finished | Jul 06 08:10:50 PM PDT 24 |
| Peak memory | 648652 kb |
| Host | smart-96ba2dcf-18a9-4bb3-a8e1-233cc4a96be0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038362924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2038362924 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.1773128911 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 5484687892 ps |
| CPU time | 590.59 seconds |
| Started | Jul 06 08:03:44 PM PDT 24 |
| Finished | Jul 06 08:13:36 PM PDT 24 |
| Peak memory | 619664 kb |
| Host | smart-cb8aca87-3e1b-485e-b191-7c2509e744b3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1773128911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.1773128911 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1302556652 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 4016741500 ps |
| CPU time | 455.49 seconds |
| Started | Jul 06 08:03:26 PM PDT 24 |
| Finished | Jul 06 08:11:02 PM PDT 24 |
| Peak memory | 648924 kb |
| Host | smart-f25633d8-5e3b-4628-ae8f-c7536128b206 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302556652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1302556652 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.3162060584 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 6117287680 ps |
| CPU time | 575.06 seconds |
| Started | Jul 06 08:04:05 PM PDT 24 |
| Finished | Jul 06 08:13:41 PM PDT 24 |
| Peak memory | 650088 kb |
| Host | smart-eb323398-c126-49c0-83db-7cf445f1e795 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3162060584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.3162060584 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1313768365 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3941319480 ps |
| CPU time | 349 seconds |
| Started | Jul 06 08:03:19 PM PDT 24 |
| Finished | Jul 06 08:09:08 PM PDT 24 |
| Peak memory | 648768 kb |
| Host | smart-e7078096-e4b0-4475-94a0-459c9ff62a5f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313768365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1313768365 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.3536780105 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 5039781708 ps |
| CPU time | 710.7 seconds |
| Started | Jul 06 08:05:34 PM PDT 24 |
| Finished | Jul 06 08:17:25 PM PDT 24 |
| Peak memory | 650036 kb |
| Host | smart-e1064368-ba5b-486e-a961-cf71e4a2637e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3536780105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.3536780105 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2786774894 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3633514832 ps |
| CPU time | 320.04 seconds |
| Started | Jul 06 08:03:36 PM PDT 24 |
| Finished | Jul 06 08:08:57 PM PDT 24 |
| Peak memory | 649016 kb |
| Host | smart-1a4f3837-dfd0-4590-ae1a-a0c728c5e4bb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786774894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2786774894 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.1088139065 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 5366368060 ps |
| CPU time | 666.02 seconds |
| Started | Jul 06 08:03:03 PM PDT 24 |
| Finished | Jul 06 08:14:10 PM PDT 24 |
| Peak memory | 649868 kb |
| Host | smart-791f7ec1-dd79-485c-8fe9-2ac1b682dfe2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1088139065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.1088139065 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3606957299 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3500082268 ps |
| CPU time | 334.24 seconds |
| Started | Jul 06 08:03:14 PM PDT 24 |
| Finished | Jul 06 08:08:49 PM PDT 24 |
| Peak memory | 648896 kb |
| Host | smart-abbee65d-1d72-4bad-b426-b4793e3dafb2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606957299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3606957299 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.2663997952 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 6254447506 ps |
| CPU time | 960.59 seconds |
| Started | Jul 06 08:04:16 PM PDT 24 |
| Finished | Jul 06 08:20:17 PM PDT 24 |
| Peak memory | 650016 kb |
| Host | smart-11533bd8-26f6-4a93-a180-73d4b8b8ae2f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2663997952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.2663997952 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4062655625 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 3527771910 ps |
| CPU time | 523.36 seconds |
| Started | Jul 06 08:04:52 PM PDT 24 |
| Finished | Jul 06 08:13:36 PM PDT 24 |
| Peak memory | 649220 kb |
| Host | smart-fb941b0a-ee9a-4153-94b1-788a3021ce9f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062655625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4062655625 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1906084706 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 3690033238 ps |
| CPU time | 396.75 seconds |
| Started | Jul 06 08:05:26 PM PDT 24 |
| Finished | Jul 06 08:12:04 PM PDT 24 |
| Peak memory | 648804 kb |
| Host | smart-f988797a-0949-420d-8815-8421a7397b5c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906084706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1906084706 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.368912858 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 4409168118 ps |
| CPU time | 605.8 seconds |
| Started | Jul 06 08:05:24 PM PDT 24 |
| Finished | Jul 06 08:15:30 PM PDT 24 |
| Peak memory | 619356 kb |
| Host | smart-2e33d7e6-2195-42f9-b92a-fc36948476ce |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 368912858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.368912858 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3756017125 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 3848741240 ps |
| CPU time | 462.89 seconds |
| Started | Jul 06 08:03:34 PM PDT 24 |
| Finished | Jul 06 08:11:17 PM PDT 24 |
| Peak memory | 648744 kb |
| Host | smart-6300d328-cea7-462c-b243-60bfb5a08111 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756017125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3756017125 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3933499002 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 3575343352 ps |
| CPU time | 480.45 seconds |
| Started | Jul 06 08:04:31 PM PDT 24 |
| Finished | Jul 06 08:12:32 PM PDT 24 |
| Peak memory | 648648 kb |
| Host | smart-1b66ebb9-6aeb-4e90-87fe-8f4cefdcaaab |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933499002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3933499002 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.3814705677 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 6063456200 ps |
| CPU time | 602.56 seconds |
| Started | Jul 06 08:03:38 PM PDT 24 |
| Finished | Jul 06 08:13:41 PM PDT 24 |
| Peak memory | 650112 kb |
| Host | smart-452e1b4d-f152-4cfd-8c75-384cf4fa643b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3814705677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.3814705677 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3384685420 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3892547896 ps |
| CPU time | 456.83 seconds |
| Started | Jul 06 08:04:37 PM PDT 24 |
| Finished | Jul 06 08:12:14 PM PDT 24 |
| Peak memory | 648620 kb |
| Host | smart-7ccd64a2-5ddd-459b-a385-596e98f2b597 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384685420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3384685420 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.212624037 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 5754431272 ps |
| CPU time | 556.76 seconds |
| Started | Jul 06 08:04:07 PM PDT 24 |
| Finished | Jul 06 08:13:24 PM PDT 24 |
| Peak memory | 650296 kb |
| Host | smart-608c9d86-0855-4edc-8bfc-2f76888ef6cc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 212624037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.212624037 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4238744963 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 3706605384 ps |
| CPU time | 476.3 seconds |
| Started | Jul 06 07:56:29 PM PDT 24 |
| Finished | Jul 06 08:04:26 PM PDT 24 |
| Peak memory | 648824 kb |
| Host | smart-d9b58ddf-4730-4753-a8b3-26b77f3106a9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238744963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.4238744963 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2428671230 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 13392059096 ps |
| CPU time | 2991.88 seconds |
| Started | Jul 06 07:56:24 PM PDT 24 |
| Finished | Jul 06 08:46:17 PM PDT 24 |
| Peak memory | 609500 kb |
| Host | smart-4b77dab9-5601-4629-950f-973a91e0b27e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428671230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.2428671230 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3828344778 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 8806958608 ps |
| CPU time | 1125.83 seconds |
| Started | Jul 06 07:56:33 PM PDT 24 |
| Finished | Jul 06 08:15:20 PM PDT 24 |
| Peak memory | 623080 kb |
| Host | smart-025f888c-65b8-456d-82e8-0b9f6480988a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828344778 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.3828344778 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.184189435 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 8640286200 ps |
| CPU time | 1527.07 seconds |
| Started | Jul 06 07:56:28 PM PDT 24 |
| Finished | Jul 06 08:21:56 PM PDT 24 |
| Peak memory | 621720 kb |
| Host | smart-34466f0f-7355-4347-923a-5fa803ab373d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=184189435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.184189435 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1769063609 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 3681611918 ps |
| CPU time | 451.89 seconds |
| Started | Jul 06 08:03:41 PM PDT 24 |
| Finished | Jul 06 08:11:13 PM PDT 24 |
| Peak memory | 649120 kb |
| Host | smart-f79b67ce-5688-4b2e-9b9e-286ecb46c2bf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769063609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1769063609 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.7803701 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 5403500568 ps |
| CPU time | 716.42 seconds |
| Started | Jul 06 08:04:46 PM PDT 24 |
| Finished | Jul 06 08:16:43 PM PDT 24 |
| Peak memory | 650060 kb |
| Host | smart-5d6273aa-bbb6-48ac-84b9-10474dfb92d5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 7803701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.7803701 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2032460846 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 3436277840 ps |
| CPU time | 333.46 seconds |
| Started | Jul 06 08:04:08 PM PDT 24 |
| Finished | Jul 06 08:09:42 PM PDT 24 |
| Peak memory | 648868 kb |
| Host | smart-0b890637-16ff-4540-8163-dc429ef9557a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032460846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2032460846 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.100386325 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 5730289784 ps |
| CPU time | 779.78 seconds |
| Started | Jul 06 08:03:21 PM PDT 24 |
| Finished | Jul 06 08:16:21 PM PDT 24 |
| Peak memory | 649964 kb |
| Host | smart-e4a7ce4b-34a8-40ad-9f92-39607aef08ac |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 100386325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.100386325 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.42640107 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 5609940750 ps |
| CPU time | 756.84 seconds |
| Started | Jul 06 08:04:31 PM PDT 24 |
| Finished | Jul 06 08:17:09 PM PDT 24 |
| Peak memory | 649952 kb |
| Host | smart-30558b21-dcb3-491b-9714-eea1a69ac7a1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 42640107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.42640107 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3856935680 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 3886935288 ps |
| CPU time | 398.17 seconds |
| Started | Jul 06 08:04:40 PM PDT 24 |
| Finished | Jul 06 08:11:19 PM PDT 24 |
| Peak memory | 648940 kb |
| Host | smart-5151ee8c-cd23-41b8-a8c2-c278751ad944 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856935680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3856935680 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.3338745302 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 5645602664 ps |
| CPU time | 793.62 seconds |
| Started | Jul 06 08:04:03 PM PDT 24 |
| Finished | Jul 06 08:17:17 PM PDT 24 |
| Peak memory | 649828 kb |
| Host | smart-2ab7daff-0c91-41ae-9665-2f58fcda5fbb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3338745302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.3338745302 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2174673039 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 4212487880 ps |
| CPU time | 379.49 seconds |
| Started | Jul 06 08:04:10 PM PDT 24 |
| Finished | Jul 06 08:10:30 PM PDT 24 |
| Peak memory | 648988 kb |
| Host | smart-3e4b94e9-a1d1-4a46-8379-d37fe91028c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174673039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2174673039 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.2929725536 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 5310821024 ps |
| CPU time | 599.5 seconds |
| Started | Jul 06 08:04:43 PM PDT 24 |
| Finished | Jul 06 08:14:43 PM PDT 24 |
| Peak memory | 649880 kb |
| Host | smart-faa16305-a080-444e-b7c8-21a86b719810 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2929725536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.2929725536 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.326414446 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 3847527728 ps |
| CPU time | 403.47 seconds |
| Started | Jul 06 08:04:15 PM PDT 24 |
| Finished | Jul 06 08:10:59 PM PDT 24 |
| Peak memory | 648932 kb |
| Host | smart-41415d3e-107d-492e-9436-baf2033b63c1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326414446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_s w_alert_handler_lpg_sleep_mode_alerts.326414446 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1932952596 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3873016616 ps |
| CPU time | 325.04 seconds |
| Started | Jul 06 08:04:55 PM PDT 24 |
| Finished | Jul 06 08:10:21 PM PDT 24 |
| Peak memory | 648632 kb |
| Host | smart-efd5d74c-7557-48b0-8444-875a99ae48cb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932952596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1932952596 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1860245743 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 3688553610 ps |
| CPU time | 347.85 seconds |
| Started | Jul 06 08:05:12 PM PDT 24 |
| Finished | Jul 06 08:11:01 PM PDT 24 |
| Peak memory | 648652 kb |
| Host | smart-9645df40-1bcc-4779-ab30-487af46f43cd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860245743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1860245743 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3494340419 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 4495805136 ps |
| CPU time | 457.82 seconds |
| Started | Jul 06 08:05:55 PM PDT 24 |
| Finished | Jul 06 08:13:33 PM PDT 24 |
| Peak memory | 649224 kb |
| Host | smart-5844eb90-2555-4901-a791-f8df199d51ce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494340419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3494340419 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.1375148315 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 5784318640 ps |
| CPU time | 760.72 seconds |
| Started | Jul 06 08:05:08 PM PDT 24 |
| Finished | Jul 06 08:17:49 PM PDT 24 |
| Peak memory | 649728 kb |
| Host | smart-08d42d14-2e09-4be5-ab96-e3d87ffaae77 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1375148315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.1375148315 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4043224540 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 3675154040 ps |
| CPU time | 577.44 seconds |
| Started | Jul 06 07:56:16 PM PDT 24 |
| Finished | Jul 06 08:05:54 PM PDT 24 |
| Peak memory | 649048 kb |
| Host | smart-691ea9c9-aeec-4b6c-91cc-1b0e44740883 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043224540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.4043224540 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.620116630 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 6399484624 ps |
| CPU time | 704.09 seconds |
| Started | Jul 06 07:56:31 PM PDT 24 |
| Finished | Jul 06 08:08:16 PM PDT 24 |
| Peak memory | 650036 kb |
| Host | smart-d293bb9d-d0c9-4f56-8aab-4af823b8963f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 620116630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.620116630 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.4085097823 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 12992861492 ps |
| CPU time | 4100.71 seconds |
| Started | Jul 06 07:56:40 PM PDT 24 |
| Finished | Jul 06 09:05:02 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-fe5636b6-d175-494a-a227-9eac864a2da4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085097823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.4085097823 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3300505429 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 5171065298 ps |
| CPU time | 472.11 seconds |
| Started | Jul 06 07:56:57 PM PDT 24 |
| Finished | Jul 06 08:04:49 PM PDT 24 |
| Peak memory | 621364 kb |
| Host | smart-60248d51-295d-4600-afae-9e28281855b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300505429 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.3300505429 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3847290666 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 3657151022 ps |
| CPU time | 509.81 seconds |
| Started | Jul 06 07:56:42 PM PDT 24 |
| Finished | Jul 06 08:05:13 PM PDT 24 |
| Peak memory | 621748 kb |
| Host | smart-855e001b-b605-4ec7-882c-028b592c4d61 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3847290666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.3847290666 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.2556907250 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 6294835100 ps |
| CPU time | 774.07 seconds |
| Started | Jul 06 08:07:25 PM PDT 24 |
| Finished | Jul 06 08:20:19 PM PDT 24 |
| Peak memory | 651400 kb |
| Host | smart-c321e4f9-fbfc-46fd-abb1-853c290ac7ba |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2556907250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.2556907250 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.3513021026 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 5899845780 ps |
| CPU time | 742.45 seconds |
| Started | Jul 06 08:04:47 PM PDT 24 |
| Finished | Jul 06 08:17:10 PM PDT 24 |
| Peak memory | 650024 kb |
| Host | smart-68f5948a-2c79-4cc0-88a0-4fa6134c935e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3513021026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.3513021026 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.2674458196 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 4746803920 ps |
| CPU time | 777.36 seconds |
| Started | Jul 06 08:07:32 PM PDT 24 |
| Finished | Jul 06 08:20:30 PM PDT 24 |
| Peak memory | 649808 kb |
| Host | smart-f8849224-8dee-418a-b507-a7b3fdcd7736 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2674458196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.2674458196 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.1560767021 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 5165819888 ps |
| CPU time | 608.53 seconds |
| Started | Jul 06 08:05:23 PM PDT 24 |
| Finished | Jul 06 08:15:32 PM PDT 24 |
| Peak memory | 649968 kb |
| Host | smart-5a8358e9-6607-4955-b402-acd487840579 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1560767021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.1560767021 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.3354375052 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 4491961700 ps |
| CPU time | 594.32 seconds |
| Started | Jul 06 08:05:08 PM PDT 24 |
| Finished | Jul 06 08:15:03 PM PDT 24 |
| Peak memory | 610908 kb |
| Host | smart-99baf405-f338-4907-9472-c1afb73c2e2e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3354375052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.3354375052 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.662173602 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 5498548882 ps |
| CPU time | 632.79 seconds |
| Started | Jul 06 08:04:59 PM PDT 24 |
| Finished | Jul 06 08:15:32 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-b0ff09dc-bef3-4f77-966b-d9ad22a86d5e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 662173602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.662173602 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.2955674697 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 5821444606 ps |
| CPU time | 583.42 seconds |
| Started | Jul 06 08:06:24 PM PDT 24 |
| Finished | Jul 06 08:16:08 PM PDT 24 |
| Peak memory | 650324 kb |
| Host | smart-55ec8a45-6adc-46c4-a25c-2fad1b803663 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2955674697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.2955674697 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.2112765559 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 5816270888 ps |
| CPU time | 575.98 seconds |
| Started | Jul 06 08:05:39 PM PDT 24 |
| Finished | Jul 06 08:15:15 PM PDT 24 |
| Peak memory | 650688 kb |
| Host | smart-db0165f2-869c-47a2-be63-6cd3740824ac |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2112765559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.2112765559 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3261427342 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 4429056640 ps |
| CPU time | 275.23 seconds |
| Started | Jul 06 07:20:22 PM PDT 24 |
| Finished | Jul 06 07:24:57 PM PDT 24 |
| Peak memory | 657244 kb |
| Host | smart-f2ff367b-466f-4e82-acff-c18e447229f1 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261427342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.3261427342 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2173966058 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 4509411720 ps |
| CPU time | 310.42 seconds |
| Started | Jul 06 07:20:23 PM PDT 24 |
| Finished | Jul 06 07:25:34 PM PDT 24 |
| Peak memory | 640784 kb |
| Host | smart-83273b5a-bd8a-49fb-bb7e-faf7c95710d0 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173966058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.2173966058 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1437215675 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4106531850 ps |
| CPU time | 192.01 seconds |
| Started | Jul 06 07:20:34 PM PDT 24 |
| Finished | Jul 06 07:23:47 PM PDT 24 |
| Peak memory | 649116 kb |
| Host | smart-d08e0e43-0f3b-4e4b-a7af-f5f25cafdd4b |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437215675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.1437215675 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2146837834 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 4981859741 ps |
| CPU time | 257.21 seconds |
| Started | Jul 06 07:20:32 PM PDT 24 |
| Finished | Jul 06 07:24:50 PM PDT 24 |
| Peak memory | 652008 kb |
| Host | smart-f63ea407-6c15-401f-8585-86e2609551e2 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146837834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.2146837834 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.248489283 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 4720816882 ps |
| CPU time | 302.38 seconds |
| Started | Jul 06 07:20:32 PM PDT 24 |
| Finished | Jul 06 07:25:35 PM PDT 24 |
| Peak memory | 657156 kb |
| Host | smart-2b88bc09-75ff-4733-99c0-e03a78cd8d49 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248489283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 5.chip_padctrl_attributes.248489283 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1607215817 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4420035378 ps |
| CPU time | 240.67 seconds |
| Started | Jul 06 07:20:34 PM PDT 24 |
| Finished | Jul 06 07:24:35 PM PDT 24 |
| Peak memory | 640800 kb |
| Host | smart-f377e620-1cf2-4056-989b-5097c5027e83 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607215817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.1607215817 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3501073323 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3913272400 ps |
| CPU time | 253.18 seconds |
| Started | Jul 06 07:20:31 PM PDT 24 |
| Finished | Jul 06 07:24:45 PM PDT 24 |
| Peak memory | 657036 kb |
| Host | smart-ff60d56d-8452-4424-8572-9107a3c2dfcf |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501073323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.3501073323 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3457965336 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 4523026300 ps |
| CPU time | 227.64 seconds |
| Started | Jul 06 07:20:38 PM PDT 24 |
| Finished | Jul 06 07:24:27 PM PDT 24 |
| Peak memory | 649972 kb |
| Host | smart-c994baa7-4dbb-47cb-a53e-9c97d7b18441 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457965336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.3457965336 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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