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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.26 95.58 94.27 95.49 95.12 97.53 99.58


Total test records in report: 2900
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T190 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1977871828 Jul 09 07:49:17 PM PDT 24 Jul 09 09:28:07 PM PDT 24 43644994621 ps
T387 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3160352316 Jul 09 08:17:07 PM PDT 24 Jul 09 08:25:12 PM PDT 24 5868049750 ps
T916 /workspace/coverage/default/2.chip_sw_hmac_smoketest.728770926 Jul 09 08:17:26 PM PDT 24 Jul 09 08:22:03 PM PDT 24 2958041280 ps
T714 /workspace/coverage/default/71.chip_sw_all_escalation_resets.2715952626 Jul 09 08:22:23 PM PDT 24 Jul 09 08:31:34 PM PDT 24 4695313370 ps
T206 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.33838821 Jul 09 07:56:13 PM PDT 24 Jul 09 08:02:35 PM PDT 24 3327159204 ps
T254 /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3921735435 Jul 09 07:52:54 PM PDT 24 Jul 09 08:21:02 PM PDT 24 11177890165 ps
T917 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1055444004 Jul 09 08:16:50 PM PDT 24 Jul 09 08:28:15 PM PDT 24 4463737540 ps
T734 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1691645791 Jul 09 07:58:31 PM PDT 24 Jul 09 08:04:12 PM PDT 24 3633092040 ps
T207 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3626977598 Jul 09 07:53:29 PM PDT 24 Jul 09 07:57:59 PM PDT 24 2855120142 ps
T176 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.382895520 Jul 09 07:49:24 PM PDT 24 Jul 09 08:29:26 PM PDT 24 29646428360 ps
T918 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3072433703 Jul 09 07:50:00 PM PDT 24 Jul 09 08:40:05 PM PDT 24 13103475654 ps
T677 /workspace/coverage/default/58.chip_sw_all_escalation_resets.1258210077 Jul 09 08:21:00 PM PDT 24 Jul 09 08:35:09 PM PDT 24 5915907856 ps
T333 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3211757773 Jul 09 07:50:53 PM PDT 24 Jul 09 08:00:35 PM PDT 24 17940154820 ps
T919 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.726141447 Jul 09 07:52:32 PM PDT 24 Jul 09 07:58:13 PM PDT 24 2762093544 ps
T920 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3976543701 Jul 09 08:16:46 PM PDT 24 Jul 09 08:29:33 PM PDT 24 11672802900 ps
T135 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3427145554 Jul 09 08:19:22 PM PDT 24 Jul 09 08:31:31 PM PDT 24 7327032686 ps
T10 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1719901334 Jul 09 08:00:35 PM PDT 24 Jul 09 08:20:41 PM PDT 24 22366347000 ps
T921 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2855035656 Jul 09 08:17:30 PM PDT 24 Jul 09 08:40:18 PM PDT 24 5049304200 ps
T922 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3706375210 Jul 09 07:50:43 PM PDT 24 Jul 09 07:55:08 PM PDT 24 2453403998 ps
T146 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3901399729 Jul 09 07:52:24 PM PDT 24 Jul 09 07:55:42 PM PDT 24 2573601722 ps
T923 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2322855389 Jul 09 08:03:48 PM PDT 24 Jul 09 08:07:30 PM PDT 24 2809130632 ps
T924 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2256161661 Jul 09 08:13:15 PM PDT 24 Jul 09 08:23:52 PM PDT 24 3937429290 ps
T759 /workspace/coverage/default/35.chip_sw_all_escalation_resets.3781414426 Jul 09 08:22:59 PM PDT 24 Jul 09 08:32:10 PM PDT 24 4941870616 ps
T925 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2398680165 Jul 09 08:15:42 PM PDT 24 Jul 09 08:24:25 PM PDT 24 5618028478 ps
T262 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2107586430 Jul 09 07:58:51 PM PDT 24 Jul 09 09:38:21 PM PDT 24 22715276183 ps
T208 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.279737165 Jul 09 07:56:26 PM PDT 24 Jul 09 08:26:10 PM PDT 24 24690405500 ps
T746 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3006635794 Jul 09 08:22:06 PM PDT 24 Jul 09 08:26:50 PM PDT 24 3735827424 ps
T187 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3320623469 Jul 09 08:02:08 PM PDT 24 Jul 09 08:06:21 PM PDT 24 2853570557 ps
T327 /workspace/coverage/default/1.chip_sival_flash_info_access.3523837836 Jul 09 07:56:39 PM PDT 24 Jul 09 08:02:10 PM PDT 24 3101624600 ps
T926 /workspace/coverage/default/0.rom_e2e_asm_init_dev.677852413 Jul 09 07:56:29 PM PDT 24 Jul 09 09:19:37 PM PDT 24 15645385659 ps
T263 /workspace/coverage/default/0.rom_e2e_shutdown_output.3867921502 Jul 09 08:00:33 PM PDT 24 Jul 09 09:03:10 PM PDT 24 26942010000 ps
T11 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1606200474 Jul 09 08:15:32 PM PDT 24 Jul 09 08:46:10 PM PDT 24 22220715542 ps
T927 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2730476907 Jul 09 08:13:30 PM PDT 24 Jul 09 08:21:13 PM PDT 24 5740198068 ps
T156 /workspace/coverage/default/0.chip_plic_all_irqs_10.2849061365 Jul 09 07:51:00 PM PDT 24 Jul 09 07:59:41 PM PDT 24 3914438300 ps
T928 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.782343192 Jul 09 07:52:31 PM PDT 24 Jul 09 08:55:26 PM PDT 24 18634285366 ps
T929 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3405012368 Jul 09 07:51:48 PM PDT 24 Jul 09 08:09:14 PM PDT 24 8177309000 ps
T336 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2005319859 Jul 09 07:56:19 PM PDT 24 Jul 09 08:02:15 PM PDT 24 3200889598 ps
T930 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3511862556 Jul 09 08:16:28 PM PDT 24 Jul 09 08:34:08 PM PDT 24 7123046637 ps
T342 /workspace/coverage/default/46.chip_sw_all_escalation_resets.2879904683 Jul 09 08:21:09 PM PDT 24 Jul 09 08:32:26 PM PDT 24 4873117626 ps
T781 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1294360449 Jul 09 08:26:07 PM PDT 24 Jul 09 08:31:43 PM PDT 24 3944379372 ps
T931 /workspace/coverage/default/2.rom_keymgr_functest.4063574267 Jul 09 08:15:59 PM PDT 24 Jul 09 08:25:55 PM PDT 24 5010110780 ps
T728 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3834365928 Jul 09 08:20:10 PM PDT 24 Jul 09 08:27:03 PM PDT 24 3433419788 ps
T932 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2639936870 Jul 09 07:53:00 PM PDT 24 Jul 09 08:15:33 PM PDT 24 5616460314 ps
T735 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.326155422 Jul 09 08:03:22 PM PDT 24 Jul 09 08:24:52 PM PDT 24 7751961674 ps
T933 /workspace/coverage/default/2.chip_sw_uart_tx_rx.1530965232 Jul 09 08:03:40 PM PDT 24 Jul 09 08:12:55 PM PDT 24 4514945596 ps
T743 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.938189713 Jul 09 08:29:14 PM PDT 24 Jul 09 08:35:07 PM PDT 24 3225487860 ps
T727 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2860371819 Jul 09 08:23:32 PM PDT 24 Jul 09 08:29:29 PM PDT 24 3838324568 ps
T934 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.4187017603 Jul 09 07:57:19 PM PDT 24 Jul 09 08:01:46 PM PDT 24 3195596910 ps
T935 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1762492417 Jul 09 07:58:32 PM PDT 24 Jul 09 09:05:46 PM PDT 24 18684989168 ps
T184 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2026168139 Jul 09 08:14:33 PM PDT 24 Jul 09 08:25:24 PM PDT 24 7015687544 ps
T936 /workspace/coverage/default/1.chip_sw_csrng_smoketest.1947981079 Jul 09 08:03:58 PM PDT 24 Jul 09 08:08:44 PM PDT 24 3258765500 ps
T329 /workspace/coverage/default/53.chip_sw_all_escalation_resets.1260726246 Jul 09 08:20:23 PM PDT 24 Jul 09 08:31:18 PM PDT 24 6069006720 ps
T937 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.578764338 Jul 09 08:20:58 PM PDT 24 Jul 09 08:26:48 PM PDT 24 3441768514 ps
T938 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1763359120 Jul 09 07:51:44 PM PDT 24 Jul 09 07:59:16 PM PDT 24 3968448792 ps
T939 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2931462536 Jul 09 08:00:09 PM PDT 24 Jul 09 08:11:02 PM PDT 24 4002187038 ps
T940 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.12850136 Jul 09 07:53:41 PM PDT 24 Jul 09 07:57:50 PM PDT 24 2798241570 ps
T941 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.99059382 Jul 09 08:05:56 PM PDT 24 Jul 09 08:22:36 PM PDT 24 5590823824 ps
T942 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1979625421 Jul 09 07:58:02 PM PDT 24 Jul 09 08:13:04 PM PDT 24 5454665512 ps
T943 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2835249381 Jul 09 07:58:30 PM PDT 24 Jul 09 08:09:21 PM PDT 24 7136751560 ps
T249 /workspace/coverage/default/0.chip_sw_plic_sw_irq.3073041584 Jul 09 07:50:12 PM PDT 24 Jul 09 07:53:32 PM PDT 24 3383926706 ps
T944 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3112494178 Jul 09 08:22:25 PM PDT 24 Jul 09 08:31:07 PM PDT 24 5602749464 ps
T945 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2038688408 Jul 09 07:49:11 PM PDT 24 Jul 09 08:06:27 PM PDT 24 10673450985 ps
T946 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1956108050 Jul 09 07:53:06 PM PDT 24 Jul 09 08:05:18 PM PDT 24 3668556252 ps
T947 /workspace/coverage/default/0.chip_sw_hmac_multistream.1077189411 Jul 09 07:50:43 PM PDT 24 Jul 09 08:21:01 PM PDT 24 7278757472 ps
T218 /workspace/coverage/default/0.chip_sw_power_idle_load.1780640487 Jul 09 07:53:36 PM PDT 24 Jul 09 08:04:03 PM PDT 24 4921463464 ps
T46 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3236830256 Jul 09 08:12:40 PM PDT 24 Jul 09 08:20:16 PM PDT 24 6247506840 ps
T665 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4045137008 Jul 09 08:03:03 PM PDT 24 Jul 09 08:15:58 PM PDT 24 5291280873 ps
T740 /workspace/coverage/default/33.chip_sw_all_escalation_resets.2872766989 Jul 09 08:21:29 PM PDT 24 Jul 09 08:33:39 PM PDT 24 5521102472 ps
T948 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.354782759 Jul 09 07:58:09 PM PDT 24 Jul 09 08:23:08 PM PDT 24 8436261944 ps
T949 /workspace/coverage/default/1.chip_sw_edn_sw_mode.1203606328 Jul 09 07:57:47 PM PDT 24 Jul 09 08:25:08 PM PDT 24 8098163912 ps
T377 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1471157381 Jul 09 08:16:39 PM PDT 24 Jul 09 08:38:48 PM PDT 24 9682118088 ps
T950 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3045057667 Jul 09 07:52:38 PM PDT 24 Jul 09 07:56:26 PM PDT 24 2220430180 ps
T795 /workspace/coverage/default/73.chip_sw_all_escalation_resets.3877227024 Jul 09 08:25:59 PM PDT 24 Jul 09 08:35:36 PM PDT 24 5567429904 ps
T951 /workspace/coverage/default/0.chip_sw_csrng_kat_test.2555819415 Jul 09 07:51:08 PM PDT 24 Jul 09 07:54:21 PM PDT 24 2807991416 ps
T952 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.344295456 Jul 09 07:50:50 PM PDT 24 Jul 09 07:58:37 PM PDT 24 4597802552 ps
T264 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.1842217146 Jul 09 08:06:38 PM PDT 24 Jul 09 09:01:53 PM PDT 24 14751007458 ps
T330 /workspace/coverage/default/75.chip_sw_all_escalation_resets.1228399906 Jul 09 08:26:50 PM PDT 24 Jul 09 08:35:40 PM PDT 24 5755988072 ps
T338 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2292825957 Jul 09 08:19:14 PM PDT 24 Jul 09 09:01:38 PM PDT 24 13263983624 ps
T93 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2888406650 Jul 09 07:50:49 PM PDT 24 Jul 09 08:05:31 PM PDT 24 10850440256 ps
T953 /workspace/coverage/default/2.chip_sw_otbn_randomness.2900358459 Jul 09 08:13:09 PM PDT 24 Jul 09 08:29:52 PM PDT 24 5657404274 ps
T954 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1857091558 Jul 09 08:03:23 PM PDT 24 Jul 09 08:07:45 PM PDT 24 3814600613 ps
T955 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.72382499 Jul 09 08:19:39 PM PDT 24 Jul 09 08:55:14 PM PDT 24 9462632000 ps
T956 /workspace/coverage/default/2.rom_e2e_asm_init_dev.3807125595 Jul 09 08:22:45 PM PDT 24 Jul 09 09:16:48 PM PDT 24 15319885096 ps
T957 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1068900196 Jul 09 08:03:54 PM PDT 24 Jul 09 08:07:21 PM PDT 24 3612203816 ps
T37 /workspace/coverage/default/2.chip_sw_gpio.700185334 Jul 09 08:05:30 PM PDT 24 Jul 09 08:13:02 PM PDT 24 4164876096 ps
T177 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1568724750 Jul 09 07:55:31 PM PDT 24 Jul 09 08:41:19 PM PDT 24 29130998875 ps
T958 /workspace/coverage/default/0.chip_sw_hmac_oneshot.1162775226 Jul 09 07:50:19 PM PDT 24 Jul 09 07:57:24 PM PDT 24 3589581290 ps
T959 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.296500577 Jul 09 07:51:51 PM PDT 24 Jul 09 07:58:05 PM PDT 24 4491164388 ps
T230 /workspace/coverage/default/2.chip_sw_flash_init.2458958352 Jul 09 08:05:42 PM PDT 24 Jul 09 08:38:19 PM PDT 24 24181392020 ps
T960 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1835439664 Jul 09 08:14:05 PM PDT 24 Jul 09 08:19:11 PM PDT 24 2622811480 ps
T961 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.795459677 Jul 09 08:17:19 PM PDT 24 Jul 09 08:23:18 PM PDT 24 3201445566 ps
T345 /workspace/coverage/default/2.chip_sw_aon_timer_irq.2848141447 Jul 09 08:15:12 PM PDT 24 Jul 09 08:23:14 PM PDT 24 4166585330 ps
T256 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1070842078 Jul 09 07:53:01 PM PDT 24 Jul 09 07:57:53 PM PDT 24 2895009677 ps
T204 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.1789847320 Jul 09 07:48:55 PM PDT 24 Jul 09 11:00:00 PM PDT 24 62943535641 ps
T962 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1567535900 Jul 09 08:19:39 PM PDT 24 Jul 09 08:30:38 PM PDT 24 4034971992 ps
T679 /workspace/coverage/default/2.chip_sw_power_idle_load.435277462 Jul 09 08:18:37 PM PDT 24 Jul 09 08:29:51 PM PDT 24 4151137320 ps
T963 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.118658890 Jul 09 07:55:39 PM PDT 24 Jul 09 08:13:45 PM PDT 24 5501298486 ps
T964 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1356025202 Jul 09 08:05:09 PM PDT 24 Jul 09 08:13:26 PM PDT 24 5162229274 ps
T965 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.479787504 Jul 09 07:50:01 PM PDT 24 Jul 09 07:54:10 PM PDT 24 2742611730 ps
T739 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3283672950 Jul 09 08:21:25 PM PDT 24 Jul 09 08:27:03 PM PDT 24 3101500462 ps
T132 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2274194262 Jul 09 08:15:13 PM PDT 24 Jul 09 08:29:17 PM PDT 24 5381992308 ps
T966 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1407336511 Jul 09 08:15:17 PM PDT 24 Jul 09 08:40:28 PM PDT 24 7617249028 ps
T295 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1074487150 Jul 09 07:59:59 PM PDT 24 Jul 09 08:14:36 PM PDT 24 7588135620 ps
T178 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3001884993 Jul 09 08:01:07 PM PDT 24 Jul 09 08:03:13 PM PDT 24 2906068586 ps
T967 /workspace/coverage/default/1.chip_tap_straps_dev.1201780131 Jul 09 08:00:17 PM PDT 24 Jul 09 08:04:11 PM PDT 24 3396501457 ps
T968 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1140692184 Jul 09 08:21:37 PM PDT 24 Jul 09 09:18:34 PM PDT 24 17499471046 ps
T969 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1189651731 Jul 09 08:15:46 PM PDT 24 Jul 09 08:45:31 PM PDT 24 10285165744 ps
T970 /workspace/coverage/default/32.chip_sw_all_escalation_resets.3054461025 Jul 09 08:21:41 PM PDT 24 Jul 09 08:31:24 PM PDT 24 5087560584 ps
T971 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.109563110 Jul 09 08:01:57 PM PDT 24 Jul 09 08:05:33 PM PDT 24 2504351999 ps
T731 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.522981711 Jul 09 08:26:39 PM PDT 24 Jul 09 08:32:10 PM PDT 24 3541747624 ps
T972 /workspace/coverage/default/2.chip_sw_aes_idle.2537512169 Jul 09 08:13:24 PM PDT 24 Jul 09 08:17:29 PM PDT 24 2712665486 ps
T22 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.105834781 Jul 09 07:55:13 PM PDT 24 Jul 09 07:59:57 PM PDT 24 2826368730 ps
T973 /workspace/coverage/default/0.chip_sw_example_manufacturer.420455813 Jul 09 07:50:23 PM PDT 24 Jul 09 07:56:22 PM PDT 24 3219708600 ps
T974 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.83432287 Jul 09 08:23:03 PM PDT 24 Jul 09 09:08:17 PM PDT 24 11577402640 ps
T506 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2530940132 Jul 09 08:14:12 PM PDT 24 Jul 09 08:29:51 PM PDT 24 4285012168 ps
T296 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3666853762 Jul 09 08:14:16 PM PDT 24 Jul 09 08:24:37 PM PDT 24 7219231675 ps
T85 /workspace/coverage/default/0.chip_jtag_csr_rw.1139350503 Jul 09 07:43:32 PM PDT 24 Jul 09 08:05:40 PM PDT 24 12610966216 ps
T975 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.877171511 Jul 09 08:17:42 PM PDT 24 Jul 09 08:26:32 PM PDT 24 6596743200 ps
T729 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3389124867 Jul 09 08:19:59 PM PDT 24 Jul 09 08:29:20 PM PDT 24 3634975272 ps
T976 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.676693053 Jul 09 07:55:50 PM PDT 24 Jul 09 07:59:59 PM PDT 24 3479528768 ps
T228 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.4257773271 Jul 09 07:59:29 PM PDT 24 Jul 09 09:03:16 PM PDT 24 17912437730 ps
T276 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.209726246 Jul 09 08:13:26 PM PDT 24 Jul 09 08:23:49 PM PDT 24 4652775830 ps
T23 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.318824349 Jul 09 07:49:12 PM PDT 24 Jul 09 07:55:18 PM PDT 24 3419880493 ps
T977 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1029604042 Jul 09 07:59:09 PM PDT 24 Jul 09 08:09:12 PM PDT 24 6824471828 ps
T772 /workspace/coverage/default/1.chip_sw_all_escalation_resets.3957595941 Jul 09 07:56:01 PM PDT 24 Jul 09 08:07:11 PM PDT 24 5324428856 ps
T788 /workspace/coverage/default/21.chip_sw_all_escalation_resets.2516970608 Jul 09 08:24:05 PM PDT 24 Jul 09 08:34:42 PM PDT 24 5122396420 ps
T978 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1220894262 Jul 09 08:18:45 PM PDT 24 Jul 09 08:45:38 PM PDT 24 8247074352 ps
T800 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.779194377 Jul 09 08:21:10 PM PDT 24 Jul 09 08:27:07 PM PDT 24 3841198160 ps
T979 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2899739942 Jul 09 08:22:12 PM PDT 24 Jul 09 09:22:51 PM PDT 24 15481050350 ps
T980 /workspace/coverage/default/2.chip_sw_example_flash.4098453516 Jul 09 08:04:56 PM PDT 24 Jul 09 08:09:07 PM PDT 24 2694968300 ps
T981 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1064411358 Jul 09 08:16:45 PM PDT 24 Jul 09 08:24:00 PM PDT 24 6847980824 ps
T982 /workspace/coverage/default/2.chip_sw_flash_crash_alert.3697693465 Jul 09 08:16:06 PM PDT 24 Jul 09 08:26:32 PM PDT 24 6456304394 ps
T209 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3323878706 Jul 09 07:52:22 PM PDT 24 Jul 09 08:04:15 PM PDT 24 4994798347 ps
T741 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1035304518 Jul 09 08:22:53 PM PDT 24 Jul 09 08:29:49 PM PDT 24 3675746324 ps
T803 /workspace/coverage/default/60.chip_sw_all_escalation_resets.3420586300 Jul 09 08:22:07 PM PDT 24 Jul 09 08:32:04 PM PDT 24 4637380304 ps
T983 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2064069473 Jul 09 08:14:02 PM PDT 24 Jul 09 08:17:22 PM PDT 24 2731762962 ps
T210 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.275551369 Jul 09 08:13:01 PM PDT 24 Jul 09 08:19:19 PM PDT 24 3346796337 ps
T47 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3441153061 Jul 09 07:50:09 PM PDT 24 Jul 09 07:58:06 PM PDT 24 5729365300 ps
T984 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2898710859 Jul 09 07:49:30 PM PDT 24 Jul 09 07:57:50 PM PDT 24 3672675060 ps
T783 /workspace/coverage/default/28.chip_sw_all_escalation_resets.3497418160 Jul 09 08:18:44 PM PDT 24 Jul 09 08:28:13 PM PDT 24 6152597136 ps
T985 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3943646399 Jul 09 07:50:36 PM PDT 24 Jul 09 08:03:10 PM PDT 24 7058351756 ps
T318 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1732564742 Jul 09 08:03:23 PM PDT 24 Jul 09 08:11:50 PM PDT 24 4006516424 ps
T763 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2052563863 Jul 09 08:24:07 PM PDT 24 Jul 09 08:31:57 PM PDT 24 3362262728 ps
T986 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3759940673 Jul 09 08:02:46 PM PDT 24 Jul 09 09:13:01 PM PDT 24 15022933576 ps
T987 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2106727458 Jul 09 07:58:55 PM PDT 24 Jul 09 08:02:52 PM PDT 24 2753995496 ps
T988 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2106952995 Jul 09 08:16:41 PM PDT 24 Jul 09 08:26:37 PM PDT 24 4401340998 ps
T250 /workspace/coverage/default/1.chip_sw_plic_sw_irq.2280100538 Jul 09 07:59:05 PM PDT 24 Jul 09 08:04:47 PM PDT 24 3102465510 ps
T716 /workspace/coverage/default/85.chip_sw_all_escalation_resets.2218497189 Jul 09 08:23:24 PM PDT 24 Jul 09 08:31:29 PM PDT 24 5428095000 ps
T766 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1679576947 Jul 09 08:24:49 PM PDT 24 Jul 09 08:32:27 PM PDT 24 3703299536 ps
T989 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3614026206 Jul 09 08:06:35 PM PDT 24 Jul 09 08:17:38 PM PDT 24 3855465004 ps
T990 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2550081157 Jul 09 08:17:46 PM PDT 24 Jul 09 09:09:05 PM PDT 24 16680821666 ps
T86 /workspace/coverage/default/1.chip_jtag_csr_rw.3785292061 Jul 09 07:52:27 PM PDT 24 Jul 09 08:35:45 PM PDT 24 21996555984 ps
T991 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2960533354 Jul 09 07:58:40 PM PDT 24 Jul 09 08:03:04 PM PDT 24 2799578990 ps
T693 /workspace/coverage/default/0.chip_sw_power_sleep_load.764671382 Jul 09 07:52:04 PM PDT 24 Jul 09 07:59:06 PM PDT 24 4935438056 ps
T992 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1332269441 Jul 09 07:54:53 PM PDT 24 Jul 09 08:53:30 PM PDT 24 20593613472 ps
T784 /workspace/coverage/default/78.chip_sw_all_escalation_resets.3140266539 Jul 09 08:23:39 PM PDT 24 Jul 09 08:33:19 PM PDT 24 5047384708 ps
T993 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.195841645 Jul 09 07:56:10 PM PDT 24 Jul 09 08:07:46 PM PDT 24 4250479436 ps
T205 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.533444429 Jul 09 07:56:38 PM PDT 24 Jul 09 11:06:24 PM PDT 24 64178099516 ps
T994 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3941963000 Jul 09 08:06:52 PM PDT 24 Jul 09 08:28:27 PM PDT 24 7047963106 ps
T133 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.868829426 Jul 09 07:58:47 PM PDT 24 Jul 09 08:14:51 PM PDT 24 6612045892 ps
T306 /workspace/coverage/default/2.chip_plic_all_irqs_20.4105132110 Jul 09 08:15:40 PM PDT 24 Jul 09 08:28:13 PM PDT 24 4695124344 ps
T154 /workspace/coverage/default/1.rom_raw_unlock.241625839 Jul 09 08:02:18 PM PDT 24 Jul 09 08:06:20 PM PDT 24 6050742225 ps
T678 /workspace/coverage/default/34.chip_sw_all_escalation_resets.2580651554 Jul 09 08:20:14 PM PDT 24 Jul 09 08:29:56 PM PDT 24 4432297418 ps
T799 /workspace/coverage/default/98.chip_sw_all_escalation_resets.924552334 Jul 09 08:23:23 PM PDT 24 Jul 09 08:29:28 PM PDT 24 5260488220 ps
T38 /workspace/coverage/default/0.chip_sw_gpio.204155795 Jul 09 07:50:54 PM PDT 24 Jul 09 07:59:01 PM PDT 24 3687845902 ps
T265 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2690793769 Jul 09 08:00:10 PM PDT 24 Jul 09 08:57:26 PM PDT 24 14410049000 ps
T995 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.4166829564 Jul 09 07:51:15 PM PDT 24 Jul 09 08:08:53 PM PDT 24 8887886639 ps
T996 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3763838722 Jul 09 08:16:32 PM PDT 24 Jul 09 08:30:07 PM PDT 24 5203782722 ps
T267 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.516058422 Jul 09 08:02:55 PM PDT 24 Jul 09 09:50:08 PM PDT 24 23885776677 ps
T997 /workspace/coverage/default/1.chip_sw_kmac_smoketest.410647802 Jul 09 08:03:06 PM PDT 24 Jul 09 08:07:57 PM PDT 24 2649351720 ps
T998 /workspace/coverage/default/2.chip_sw_power_sleep_load.727349878 Jul 09 08:17:08 PM PDT 24 Jul 09 08:25:43 PM PDT 24 9173113732 ps
T67 /workspace/coverage/default/1.chip_tap_straps_rma.1933360986 Jul 09 08:00:18 PM PDT 24 Jul 09 08:05:34 PM PDT 24 4131450720 ps
T211 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1652432200 Jul 09 07:56:38 PM PDT 24 Jul 09 08:02:20 PM PDT 24 3273886676 ps
T999 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3973589450 Jul 09 08:07:02 PM PDT 24 Jul 09 08:17:58 PM PDT 24 4669137012 ps
T1000 /workspace/coverage/default/31.chip_sw_all_escalation_resets.2477000584 Jul 09 08:27:13 PM PDT 24 Jul 09 08:37:13 PM PDT 24 6048384484 ps
T1001 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3472621646 Jul 09 08:13:47 PM PDT 24 Jul 09 09:11:58 PM PDT 24 20504253582 ps
T244 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1954206605 Jul 09 08:22:10 PM PDT 24 Jul 09 08:29:10 PM PDT 24 3347212880 ps
T285 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3855094961 Jul 09 08:22:37 PM PDT 24 Jul 09 08:29:36 PM PDT 24 3826796680 ps
T87 /workspace/coverage/default/1.chip_jtag_mem_access.3118768565 Jul 09 07:52:35 PM PDT 24 Jul 09 08:18:26 PM PDT 24 13695098250 ps
T286 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.833364677 Jul 09 08:04:53 PM PDT 24 Jul 09 08:10:45 PM PDT 24 3600289634 ps
T287 /workspace/coverage/default/1.chip_sw_csrng_kat_test.3071119676 Jul 09 07:59:32 PM PDT 24 Jul 09 08:04:13 PM PDT 24 3067907578 ps
T288 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3091335214 Jul 09 07:51:24 PM PDT 24 Jul 09 08:00:04 PM PDT 24 3596702120 ps
T289 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2603433244 Jul 09 08:02:15 PM PDT 24 Jul 09 08:20:37 PM PDT 24 5461271000 ps
T290 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.96851460 Jul 09 07:59:05 PM PDT 24 Jul 09 08:07:37 PM PDT 24 3516021840 ps
T120 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1561232642 Jul 09 08:02:43 PM PDT 24 Jul 09 08:49:52 PM PDT 24 19319043044 ps
T291 /workspace/coverage/default/44.chip_sw_all_escalation_resets.3394881124 Jul 09 08:21:07 PM PDT 24 Jul 09 08:32:09 PM PDT 24 4775162224 ps
T425 /workspace/coverage/default/2.chip_sw_aes_entropy.1268417602 Jul 09 08:13:10 PM PDT 24 Jul 09 08:17:06 PM PDT 24 2469274080 ps
T426 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3706433036 Jul 09 08:12:01 PM PDT 24 Jul 09 08:15:17 PM PDT 24 2601160731 ps
T427 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1397945791 Jul 09 07:59:33 PM PDT 24 Jul 09 08:50:51 PM PDT 24 11162929257 ps
T7 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2433160469 Jul 09 08:02:11 PM PDT 24 Jul 09 08:08:50 PM PDT 24 4329612286 ps
T412 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1284152304 Jul 09 08:22:12 PM PDT 24 Jul 09 08:29:31 PM PDT 24 4056962640 ps
T147 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.987456902 Jul 09 07:50:52 PM PDT 24 Jul 09 08:00:57 PM PDT 24 8445717942 ps
T231 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2960254051 Jul 09 08:13:12 PM PDT 24 Jul 09 09:44:29 PM PDT 24 47098888717 ps
T413 /workspace/coverage/default/87.chip_sw_all_escalation_resets.1979079952 Jul 09 08:24:33 PM PDT 24 Jul 09 08:35:50 PM PDT 24 5264098110 ps
T414 /workspace/coverage/default/0.chip_sw_otbn_randomness.2412468780 Jul 09 07:53:23 PM PDT 24 Jul 09 08:08:43 PM PDT 24 6215668632 ps
T415 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.105783179 Jul 09 07:49:14 PM PDT 24 Jul 09 08:12:27 PM PDT 24 8521837920 ps
T416 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.4119851574 Jul 09 07:51:25 PM PDT 24 Jul 09 07:58:02 PM PDT 24 3322740270 ps
T417 /workspace/coverage/default/88.chip_sw_all_escalation_resets.1505697534 Jul 09 08:27:42 PM PDT 24 Jul 09 08:39:06 PM PDT 24 5914191802 ps
T418 /workspace/coverage/default/1.chip_sw_edn_boot_mode.1541406305 Jul 09 07:57:02 PM PDT 24 Jul 09 08:06:14 PM PDT 24 3465993576 ps
T1002 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2828275678 Jul 09 07:59:57 PM PDT 24 Jul 09 08:12:28 PM PDT 24 4376793112 ps
T34 /workspace/coverage/default/0.chip_sw_usbdev_config_host.3221154437 Jul 09 07:49:03 PM PDT 24 Jul 09 08:16:20 PM PDT 24 7920690952 ps
T188 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3392534646 Jul 09 08:01:17 PM PDT 24 Jul 09 08:04:56 PM PDT 24 3480088560 ps
T381 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1320296296 Jul 09 08:20:22 PM PDT 24 Jul 09 08:27:50 PM PDT 24 3550203318 ps
T382 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.81411192 Jul 09 08:15:38 PM PDT 24 Jul 09 08:33:14 PM PDT 24 12439666577 ps
T27 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2980132167 Jul 09 07:55:30 PM PDT 24 Jul 09 08:07:26 PM PDT 24 6813459015 ps
T383 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1024277483 Jul 09 08:14:06 PM PDT 24 Jul 09 08:19:47 PM PDT 24 2370234188 ps
T384 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3970751980 Jul 09 07:59:33 PM PDT 24 Jul 09 09:08:34 PM PDT 24 14511112980 ps
T385 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4022228259 Jul 09 08:21:38 PM PDT 24 Jul 09 08:24:51 PM PDT 24 2620661260 ps
T14 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.4053781001 Jul 09 07:56:05 PM PDT 24 Jul 09 08:04:12 PM PDT 24 5655267868 ps
T52 /workspace/coverage/default/1.chip_sw_power_virus.1821527652 Jul 09 08:07:25 PM PDT 24 Jul 09 08:27:08 PM PDT 24 4846674960 ps
T386 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3068837646 Jul 09 08:16:35 PM PDT 24 Jul 09 08:25:11 PM PDT 24 3181138664 ps
T1003 /workspace/coverage/default/3.chip_tap_straps_dev.447344396 Jul 09 08:17:20 PM PDT 24 Jul 09 08:23:28 PM PDT 24 3850119467 ps
T1004 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3030276709 Jul 09 08:14:55 PM PDT 24 Jul 09 08:19:57 PM PDT 24 3033243080 ps
T796 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1194227988 Jul 09 08:25:14 PM PDT 24 Jul 09 08:32:42 PM PDT 24 3411071420 ps
T782 /workspace/coverage/default/82.chip_sw_all_escalation_resets.1167243753 Jul 09 08:23:59 PM PDT 24 Jul 09 08:32:29 PM PDT 24 4269441584 ps
T24 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3345821374 Jul 09 08:05:22 PM PDT 24 Jul 09 08:11:33 PM PDT 24 3960529002 ps
T773 /workspace/coverage/default/16.chip_sw_all_escalation_resets.2087220273 Jul 09 08:19:01 PM PDT 24 Jul 09 08:26:35 PM PDT 24 4623943992 ps
T337 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.478619421 Jul 09 08:16:54 PM PDT 24 Jul 09 08:22:42 PM PDT 24 3074913193 ps
T1005 /workspace/coverage/default/0.chip_sw_kmac_smoketest.233771459 Jul 09 07:54:53 PM PDT 24 Jul 09 08:00:29 PM PDT 24 3113248084 ps
T1006 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.997495439 Jul 09 08:19:47 PM PDT 24 Jul 09 08:44:16 PM PDT 24 7405393568 ps
T1007 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1273157272 Jul 09 07:58:26 PM PDT 24 Jul 09 08:14:26 PM PDT 24 6073529979 ps
T48 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1498130581 Jul 09 08:00:47 PM PDT 24 Jul 09 08:12:19 PM PDT 24 7479205400 ps
T1008 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2556446972 Jul 09 08:22:46 PM PDT 24 Jul 09 08:28:53 PM PDT 24 3127685280 ps
T365 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1660119899 Jul 09 08:11:57 PM PDT 24 Jul 09 08:15:47 PM PDT 24 2541909128 ps
T1009 /workspace/coverage/default/0.chip_sw_coremark.1714165742 Jul 09 07:52:12 PM PDT 24 Jul 10 12:04:51 AM PDT 24 71539019180 ps
T1010 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.345833978 Jul 09 08:20:30 PM PDT 24 Jul 09 08:28:46 PM PDT 24 7196201593 ps
T1011 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.777193301 Jul 09 08:15:11 PM PDT 24 Jul 09 08:25:13 PM PDT 24 10137502556 ps
T163 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1690154143 Jul 09 07:49:15 PM PDT 24 Jul 09 07:53:52 PM PDT 24 2770274909 ps
T1012 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2336057412 Jul 09 08:23:16 PM PDT 24 Jul 09 09:01:54 PM PDT 24 13245986600 ps
T422 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.202351278 Jul 09 08:23:07 PM PDT 24 Jul 09 08:31:41 PM PDT 24 4100626852 ps
T100 /workspace/coverage/default/4.chip_sw_all_escalation_resets.1084659853 Jul 09 08:13:11 PM PDT 24 Jul 09 08:27:52 PM PDT 24 6327752892 ps
T732 /workspace/coverage/default/95.chip_sw_all_escalation_resets.2740714426 Jul 09 08:25:08 PM PDT 24 Jul 09 08:36:03 PM PDT 24 6078378990 ps
T197 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.995273579 Jul 09 08:06:06 PM PDT 24 Jul 09 08:14:11 PM PDT 24 4363447959 ps
T1013 /workspace/coverage/default/1.chip_sw_otbn_smoketest.2186255386 Jul 09 08:04:29 PM PDT 24 Jul 09 08:36:45 PM PDT 24 7620586880 ps
T720 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1058655251 Jul 09 08:20:10 PM PDT 24 Jul 09 08:28:32 PM PDT 24 3696942696 ps
T166 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3443043979 Jul 09 07:51:16 PM PDT 24 Jul 09 08:01:54 PM PDT 24 5416938316 ps
T1014 /workspace/coverage/default/2.chip_sw_kmac_entropy.620835446 Jul 09 08:05:59 PM PDT 24 Jul 09 08:09:41 PM PDT 24 2941264216 ps
T1015 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3819401203 Jul 09 07:51:07 PM PDT 24 Jul 09 07:59:11 PM PDT 24 5397195198 ps
T1016 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3274546823 Jul 09 08:16:58 PM PDT 24 Jul 09 08:26:30 PM PDT 24 3651942890 ps
T1017 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.635923938 Jul 09 08:00:53 PM PDT 24 Jul 09 08:06:39 PM PDT 24 3603193768 ps
T1018 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1071753470 Jul 09 08:18:01 PM PDT 24 Jul 09 08:23:12 PM PDT 24 3083320500 ps
T74 /workspace/coverage/default/2.chip_tap_straps_rma.160882122 Jul 09 08:15:28 PM PDT 24 Jul 09 08:21:21 PM PDT 24 4193104763 ps
T1019 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.641245629 Jul 09 07:54:18 PM PDT 24 Jul 09 08:36:52 PM PDT 24 22282215282 ps
T161 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.669596796 Jul 09 08:06:57 PM PDT 24 Jul 09 08:08:38 PM PDT 24 1604882249 ps
T1020 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.765318115 Jul 09 08:03:17 PM PDT 24 Jul 09 08:06:16 PM PDT 24 2277919610 ps
T717 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1767826858 Jul 09 08:20:26 PM PDT 24 Jul 09 08:29:52 PM PDT 24 4106776876 ps
T277 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2210871714 Jul 09 08:02:22 PM PDT 24 Jul 09 08:10:24 PM PDT 24 4328396057 ps
T324 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3447391380 Jul 09 08:01:31 PM PDT 24 Jul 09 08:13:40 PM PDT 24 4650122364 ps
T771 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.522611380 Jul 09 08:24:17 PM PDT 24 Jul 09 08:31:37 PM PDT 24 4000814222 ps
T1021 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3758563821 Jul 09 08:15:53 PM PDT 24 Jul 09 08:27:48 PM PDT 24 4587136270 ps
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