| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.26 | 95.58 | 94.27 | 95.49 | 95.12 | 97.53 | 99.58 |
| T2764 | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.2170758752 | Jul 09 07:29:24 PM PDT 24 | Jul 09 07:50:48 PM PDT 24 | 66703550511 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.4218269185 | Jul 09 07:35:52 PM PDT 24 | Jul 09 07:36:19 PM PDT 24 | 86633793 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3673261897 | Jul 09 07:25:23 PM PDT 24 | Jul 09 07:25:42 PM PDT 24 | 57587956 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.1907384467 | Jul 09 07:38:39 PM PDT 24 | Jul 09 08:09:20 PM PDT 24 | 101861972434 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/29.xbar_stress_all.3004383312 | Jul 09 07:30:18 PM PDT 24 | Jul 09 07:34:32 PM PDT 24 | 3245806178 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.2833894540 | Jul 09 07:37:08 PM PDT 24 | Jul 09 07:39:54 PM PDT 24 | 598983675 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3841265773 | Jul 09 07:39:25 PM PDT 24 | Jul 09 07:42:32 PM PDT 24 | 598117641 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3203027502 | Jul 09 07:26:04 PM PDT 24 | Jul 09 07:34:39 PM PDT 24 | 27092729824 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.2492741558 | Jul 09 07:28:39 PM PDT 24 | Jul 09 07:30:06 PM PDT 24 | 8007874416 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/48.xbar_random.2199186550 | Jul 09 07:33:13 PM PDT 24 | Jul 09 07:33:20 PM PDT 24 | 34764856 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.3004380375 | Jul 09 07:31:55 PM PDT 24 | Jul 09 07:32:25 PM PDT 24 | 641219126 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.1974023794 | Jul 09 07:40:29 PM PDT 24 | Jul 09 07:41:23 PM PDT 24 | 1272500126 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.3763401696 | Jul 09 07:30:29 PM PDT 24 | Jul 09 07:31:29 PM PDT 24 | 1382386522 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1774544076 | Jul 09 07:30:51 PM PDT 24 | Jul 09 07:30:59 PM PDT 24 | 37904334 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/99.xbar_random.104558943 | Jul 09 07:41:41 PM PDT 24 | Jul 09 07:42:28 PM PDT 24 | 513351879 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.2548407181 | Jul 09 07:25:45 PM PDT 24 | Jul 09 07:26:07 PM PDT 24 | 26496211 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/56.xbar_random.524741836 | Jul 09 07:35:33 PM PDT 24 | Jul 09 07:36:24 PM PDT 24 | 1533015909 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.1647365240 | Jul 09 07:28:48 PM PDT 24 | Jul 09 07:30:36 PM PDT 24 | 2379054341 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.2862508506 | Jul 09 07:33:49 PM PDT 24 | Jul 09 07:34:55 PM PDT 24 | 836818149 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.567089299 | Jul 09 07:40:35 PM PDT 24 | Jul 09 07:40:59 PM PDT 24 | 199301141 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.3021012229 | Jul 09 07:35:47 PM PDT 24 | Jul 09 07:35:59 PM PDT 24 | 98191210 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.3967972133 | Jul 09 07:37:46 PM PDT 24 | Jul 09 08:16:59 PM PDT 24 | 138341984616 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/10.chip_csr_rw.1534957737 | Jul 09 07:26:04 PM PDT 24 | Jul 09 07:35:42 PM PDT 24 | 5577986354 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/71.xbar_error_random.3259372166 | Jul 09 07:37:22 PM PDT 24 | Jul 09 07:37:42 PM PDT 24 | 183296801 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.15356640 | Jul 09 07:27:20 PM PDT 24 | Jul 09 07:28:33 PM PDT 24 | 751315812 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/80.xbar_same_source.3136167370 | Jul 09 07:38:46 PM PDT 24 | Jul 09 07:39:00 PM PDT 24 | 120043603 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.2392355372 | Jul 09 07:41:42 PM PDT 24 | Jul 09 07:44:15 PM PDT 24 | 8138390410 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.3857677119 | Jul 09 07:37:51 PM PDT 24 | Jul 09 07:38:29 PM PDT 24 | 3455638613 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.790074322 | Jul 09 07:41:31 PM PDT 24 | Jul 09 07:42:46 PM PDT 24 | 4307123397 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2321975631 | Jul 09 07:26:52 PM PDT 24 | Jul 09 07:31:17 PM PDT 24 | 2369294450 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.3688662521 | Jul 09 07:41:47 PM PDT 24 | Jul 09 07:46:35 PM PDT 24 | 3315881901 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/3.xbar_error_random.3148522640 | Jul 09 07:25:36 PM PDT 24 | Jul 09 07:26:16 PM PDT 24 | 999389355 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.418200778 | Jul 09 07:39:18 PM PDT 24 | Jul 09 07:40:50 PM PDT 24 | 1927181528 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.3088344319 | Jul 09 07:40:30 PM PDT 24 | Jul 09 07:42:24 PM PDT 24 | 6263595730 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/42.xbar_error_random.1669965602 | Jul 09 07:32:29 PM PDT 24 | Jul 09 07:33:18 PM PDT 24 | 1514581237 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.3455245879 | Jul 09 07:30:32 PM PDT 24 | Jul 09 08:02:32 PM PDT 24 | 113724100174 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.1142601615 | Jul 09 07:41:11 PM PDT 24 | Jul 09 07:41:41 PM PDT 24 | 318599202 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.3704508172 | Jul 09 07:33:58 PM PDT 24 | Jul 09 07:40:45 PM PDT 24 | 38501274861 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/70.xbar_smoke.2160898252 | Jul 09 07:37:15 PM PDT 24 | Jul 09 07:37:24 PM PDT 24 | 163972913 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1951929822 | Jul 09 07:29:39 PM PDT 24 | Jul 09 07:29:47 PM PDT 24 | 45671116 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.855735343 | Jul 09 07:40:34 PM PDT 24 | Jul 09 07:51:20 PM PDT 24 | 65397161985 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/69.xbar_same_source.1832123600 | Jul 09 07:37:06 PM PDT 24 | Jul 09 07:37:23 PM PDT 24 | 164810835 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.3816083301 | Jul 09 07:30:03 PM PDT 24 | Jul 09 08:09:27 PM PDT 24 | 123293061278 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.2386875612 | Jul 09 07:33:00 PM PDT 24 | Jul 09 07:34:21 PM PDT 24 | 2197649840 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/91.xbar_stress_all.1495479703 | Jul 09 07:40:41 PM PDT 24 | Jul 09 07:43:58 PM PDT 24 | 2382218675 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/73.xbar_smoke.2100663489 | Jul 09 07:37:37 PM PDT 24 | Jul 09 07:37:48 PM PDT 24 | 256662899 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.2299961306 | Jul 09 07:39:30 PM PDT 24 | Jul 09 07:41:09 PM PDT 24 | 9344598188 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.618065636 | Jul 09 07:37:01 PM PDT 24 | Jul 09 07:42:19 PM PDT 24 | 4357816950 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.601354700 | Jul 09 07:38:58 PM PDT 24 | Jul 09 07:45:07 PM PDT 24 | 799138651 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2084739456 | Jul 09 07:25:27 PM PDT 24 | Jul 09 07:27:12 PM PDT 24 | 5224311379 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/91.xbar_error_random.335571136 | Jul 09 07:40:41 PM PDT 24 | Jul 09 07:42:03 PM PDT 24 | 2514693922 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.2948973878 | Jul 09 07:30:54 PM PDT 24 | Jul 09 07:32:22 PM PDT 24 | 4875021160 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/92.xbar_error_random.925956439 | Jul 09 07:40:49 PM PDT 24 | Jul 09 07:41:40 PM PDT 24 | 1560596024 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.791921481 | Jul 09 07:38:54 PM PDT 24 | Jul 09 07:39:41 PM PDT 24 | 4414287175 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.3478223553 | Jul 09 07:38:39 PM PDT 24 | Jul 09 07:38:47 PM PDT 24 | 54785841 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.1177353833 | Jul 09 07:40:48 PM PDT 24 | Jul 09 08:00:05 PM PDT 24 | 104602379820 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/81.xbar_error_random.848592213 | Jul 09 07:38:51 PM PDT 24 | Jul 09 07:39:06 PM PDT 24 | 305334250 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/96.xbar_error_random.488942582 | Jul 09 07:41:15 PM PDT 24 | Jul 09 07:41:52 PM PDT 24 | 932196017 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1370416551 | Jul 09 07:35:52 PM PDT 24 | Jul 09 07:37:30 PM PDT 24 | 5102276534 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.2312538275 | Jul 09 07:30:45 PM PDT 24 | Jul 09 07:31:43 PM PDT 24 | 1308779813 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.375538440 | Jul 09 07:29:31 PM PDT 24 | Jul 09 07:30:08 PM PDT 24 | 833786177 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3099481757 | Jul 09 07:26:41 PM PDT 24 | Jul 09 07:43:28 PM PDT 24 | 89272567470 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.786345198 | Jul 09 07:39:41 PM PDT 24 | Jul 09 07:40:03 PM PDT 24 | 158508898 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.1851387469 | Jul 09 07:39:43 PM PDT 24 | Jul 09 07:52:11 PM PDT 24 | 64723445321 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1250110962 | Jul 09 07:35:44 PM PDT 24 | Jul 09 07:35:55 PM PDT 24 | 47668828 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.4086052929 | Jul 09 07:26:02 PM PDT 24 | Jul 09 07:27:46 PM PDT 24 | 4888173459 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.4099034717 | Jul 09 07:29:23 PM PDT 24 | Jul 09 07:30:03 PM PDT 24 | 427326749 ps | ||
| T619 | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.3205908505 | Jul 09 07:41:03 PM PDT 24 | Jul 09 07:43:58 PM PDT 24 | 2504401951 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/77.xbar_stress_all.883003276 | Jul 09 07:38:22 PM PDT 24 | Jul 09 07:45:42 PM PDT 24 | 12448019003 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/46.xbar_smoke.3278432122 | Jul 09 07:32:45 PM PDT 24 | Jul 09 07:32:52 PM PDT 24 | 38318896 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.1416401664 | Jul 09 07:38:52 PM PDT 24 | Jul 09 07:40:35 PM PDT 24 | 2044162470 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/30.xbar_error_random.2388305904 | Jul 09 07:30:19 PM PDT 24 | Jul 09 07:30:56 PM PDT 24 | 384205433 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.2134550072 | Jul 09 07:30:29 PM PDT 24 | Jul 09 07:30:40 PM PDT 24 | 42863991 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/30.xbar_same_source.4090007758 | Jul 09 07:30:22 PM PDT 24 | Jul 09 07:31:05 PM PDT 24 | 523473601 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3370592565 | Jul 09 07:26:03 PM PDT 24 | Jul 09 08:05:00 PM PDT 24 | 136568293081 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.4234845318 | Jul 09 07:25:23 PM PDT 24 | Jul 09 07:42:07 PM PDT 24 | 95276076310 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/19.xbar_error_random.136448348 | Jul 09 07:28:09 PM PDT 24 | Jul 09 07:28:48 PM PDT 24 | 454394609 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/45.xbar_error_random.3065802360 | Jul 09 07:32:38 PM PDT 24 | Jul 09 07:33:10 PM PDT 24 | 388901446 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3444931119 | Jul 09 07:25:16 PM PDT 24 | Jul 09 07:30:51 PM PDT 24 | 2299547157 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.25888783 | Jul 09 07:40:05 PM PDT 24 | Jul 09 07:50:27 PM PDT 24 | 32960734663 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.894242441 | Jul 09 07:38:16 PM PDT 24 | Jul 09 07:45:24 PM PDT 24 | 5458756359 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.352240916 | Jul 09 07:30:45 PM PDT 24 | Jul 09 07:54:01 PM PDT 24 | 80746877524 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/34.xbar_smoke.2258349708 | Jul 09 07:30:43 PM PDT 24 | Jul 09 07:30:52 PM PDT 24 | 37342307 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.3703749514 | Jul 09 07:25:25 PM PDT 24 | Jul 09 09:42:07 PM PDT 24 | 57306895496 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3762305211 | Jul 09 07:35:55 PM PDT 24 | Jul 09 08:08:35 PM PDT 24 | 104409008798 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.196374479 | Jul 09 07:41:27 PM PDT 24 | Jul 09 08:01:06 PM PDT 24 | 64551422166 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/57.xbar_stress_all.1579760853 | Jul 09 07:35:44 PM PDT 24 | Jul 09 07:44:26 PM PDT 24 | 13922659558 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.2352923608 | Jul 09 07:38:41 PM PDT 24 | Jul 09 07:38:57 PM PDT 24 | 104321630 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.796393022 | Jul 09 07:40:57 PM PDT 24 | Jul 09 07:43:08 PM PDT 24 | 569814213 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/19.xbar_smoke.2509924434 | Jul 09 07:28:10 PM PDT 24 | Jul 09 07:28:17 PM PDT 24 | 36670975 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/0.chip_tl_errors.3045081387 | Jul 09 07:25:08 PM PDT 24 | Jul 09 07:29:01 PM PDT 24 | 3460749616 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3049186768 | Jul 09 07:31:51 PM PDT 24 | Jul 09 07:39:05 PM PDT 24 | 3595791214 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.1714872461 | Jul 09 07:36:08 PM PDT 24 | Jul 09 07:42:38 PM PDT 24 | 11734150304 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/17.xbar_stress_all.1129217073 | Jul 09 07:27:45 PM PDT 24 | Jul 09 07:31:38 PM PDT 24 | 3262757937 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.3148760548 | Jul 09 07:25:26 PM PDT 24 | Jul 09 07:31:57 PM PDT 24 | 12345565427 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.1503287540 | Jul 09 07:30:33 PM PDT 24 | Jul 09 07:34:08 PM PDT 24 | 2579415732 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.2511063933 | Jul 09 07:25:50 PM PDT 24 | Jul 09 07:32:38 PM PDT 24 | 21763920358 ps | ||
| T368 | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1369874350 | Jul 09 07:26:09 PM PDT 24 | Jul 09 07:55:48 PM PDT 24 | 13812937628 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1943870341 | Jul 09 07:25:22 PM PDT 24 | Jul 09 07:25:55 PM PDT 24 | 213185910 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/76.xbar_error_random.3922039038 | Jul 09 07:38:15 PM PDT 24 | Jul 09 07:38:25 PM PDT 24 | 154297589 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.1844013267 | Jul 09 07:25:46 PM PDT 24 | Jul 09 07:28:25 PM PDT 24 | 1615451540 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/68.xbar_random.1470051391 | Jul 09 07:36:59 PM PDT 24 | Jul 09 07:38:06 PM PDT 24 | 1714215507 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/25.xbar_same_source.3492646772 | Jul 09 07:29:09 PM PDT 24 | Jul 09 07:30:38 PM PDT 24 | 2770561411 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.160273392 | Jul 09 07:40:42 PM PDT 24 | Jul 09 07:43:41 PM PDT 24 | 4493059443 ps | ||
| T142 | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2321539853 | Jul 09 07:25:28 PM PDT 24 | Jul 09 07:31:55 PM PDT 24 | 6804617236 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.355215762 | Jul 09 07:35:48 PM PDT 24 | Jul 09 07:43:29 PM PDT 24 | 26409052282 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/26.chip_tl_errors.1174666607 | Jul 09 07:29:17 PM PDT 24 | Jul 09 07:31:01 PM PDT 24 | 2739678904 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.805279405 | Jul 09 07:35:48 PM PDT 24 | Jul 09 07:37:13 PM PDT 24 | 7653102596 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.2733514172 | Jul 09 07:40:51 PM PDT 24 | Jul 09 07:41:34 PM PDT 24 | 922521476 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/82.xbar_same_source.1014189416 | Jul 09 07:39:07 PM PDT 24 | Jul 09 07:39:48 PM PDT 24 | 1425353010 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/16.xbar_stress_all.1776338120 | Jul 09 07:27:28 PM PDT 24 | Jul 09 07:30:13 PM PDT 24 | 3510248478 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.2050359842 | Jul 09 07:28:48 PM PDT 24 | Jul 09 07:33:37 PM PDT 24 | 17371317401 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.6308300 | Jul 09 07:32:46 PM PDT 24 | Jul 09 07:33:41 PM PDT 24 | 592250470 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1130744098 | Jul 09 07:33:23 PM PDT 24 | Jul 09 07:34:11 PM PDT 24 | 1259686395 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/82.xbar_stress_all.2890251127 | Jul 09 07:39:11 PM PDT 24 | Jul 09 07:48:22 PM PDT 24 | 14586177998 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2599650442 | Jul 09 07:38:17 PM PDT 24 | Jul 09 07:39:09 PM PDT 24 | 365470685 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.1907704432 | Jul 09 07:35:31 PM PDT 24 | Jul 09 07:36:48 PM PDT 24 | 7466805706 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.1366099685 | Jul 09 07:41:05 PM PDT 24 | Jul 09 07:42:37 PM PDT 24 | 5404329732 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.4244491499 | Jul 09 07:33:36 PM PDT 24 | Jul 09 07:44:25 PM PDT 24 | 5672794858 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.3930236246 | Jul 09 07:41:08 PM PDT 24 | Jul 09 07:42:02 PM PDT 24 | 683487566 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.3123814438 | Jul 09 07:34:04 PM PDT 24 | Jul 09 07:35:58 PM PDT 24 | 6437293929 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.3822691727 | Jul 09 07:30:20 PM PDT 24 | Jul 09 07:30:52 PM PDT 24 | 755341038 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3133665301 | Jul 09 07:27:11 PM PDT 24 | Jul 09 07:55:17 PM PDT 24 | 16554100542 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/58.xbar_same_source.1511212485 | Jul 09 07:35:44 PM PDT 24 | Jul 09 07:36:28 PM PDT 24 | 1375591966 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.521378581 | Jul 09 07:35:49 PM PDT 24 | Jul 09 07:47:59 PM PDT 24 | 42544678893 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1301526768 | Jul 09 07:26:06 PM PDT 24 | Jul 09 07:27:51 PM PDT 24 | 4734068558 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.598155592 | Jul 09 07:39:56 PM PDT 24 | Jul 09 07:41:16 PM PDT 24 | 4652098799 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/43.xbar_same_source.322919481 | Jul 09 07:32:21 PM PDT 24 | Jul 09 07:32:45 PM PDT 24 | 289676226 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.3983536462 | Jul 09 07:30:04 PM PDT 24 | Jul 09 07:30:28 PM PDT 24 | 383137308 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.593877296 | Jul 09 07:33:11 PM PDT 24 | Jul 09 07:33:40 PM PDT 24 | 611294839 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.3081429414 | Jul 09 07:28:22 PM PDT 24 | Jul 09 07:28:56 PM PDT 24 | 135942494 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/96.xbar_smoke.2661162427 | Jul 09 07:41:11 PM PDT 24 | Jul 09 07:41:19 PM PDT 24 | 51337414 ps | ||
| T2893 | /workspace/coverage/cover_reg_top/3.xbar_random.3432686886 | Jul 09 07:25:25 PM PDT 24 | Jul 09 07:26:21 PM PDT 24 | 588952220 ps | ||
| T2894 | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.76881509 | Jul 09 07:36:54 PM PDT 24 | Jul 09 07:48:22 PM PDT 24 | 63284829889 ps | ||
| T2895 | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.3425587587 | Jul 09 07:29:26 PM PDT 24 | Jul 09 07:42:50 PM PDT 24 | 76107152556 ps | ||
| T2896 | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.1956313520 | Jul 09 07:25:45 PM PDT 24 | Jul 09 07:27:28 PM PDT 24 | 5365450868 ps | ||
| T2897 | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3725340940 | Jul 09 07:27:42 PM PDT 24 | Jul 09 08:00:25 PM PDT 24 | 113015197549 ps | ||
| T2898 | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3102848083 | Jul 09 07:27:04 PM PDT 24 | Jul 09 07:33:55 PM PDT 24 | 40348386463 ps | ||
| T2899 | /workspace/coverage/cover_reg_top/23.chip_tl_errors.2195718461 | Jul 09 07:28:40 PM PDT 24 | Jul 09 07:30:17 PM PDT 24 | 2340768088 ps | ||
| T2900 | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.445836775 | Jul 09 07:29:24 PM PDT 24 | Jul 09 07:31:23 PM PDT 24 | 320552077 ps | ||
| T40 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2446042993 | Jul 09 07:41:48 PM PDT 24 | Jul 09 07:45:16 PM PDT 24 | 5011526005 ps | ||
| T41 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.911279007 | Jul 09 07:41:49 PM PDT 24 | Jul 09 07:46:34 PM PDT 24 | 5046852050 ps | ||
| T42 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2771583277 | Jul 09 07:41:57 PM PDT 24 | Jul 09 07:45:46 PM PDT 24 | 4790248599 ps | ||
| T43 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4070666629 | Jul 09 07:41:53 PM PDT 24 | Jul 09 07:45:21 PM PDT 24 | 4017154203 ps | ||
| T191 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2214836179 | Jul 09 07:41:47 PM PDT 24 | Jul 09 07:45:07 PM PDT 24 | 4962523816 ps | ||
| T192 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2868297251 | Jul 09 07:41:52 PM PDT 24 | Jul 09 07:45:54 PM PDT 24 | 4999369648 ps | ||
| T193 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.66124641 | Jul 09 07:41:48 PM PDT 24 | Jul 09 07:45:28 PM PDT 24 | 5150251560 ps | ||
| T194 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.230005850 | Jul 09 07:41:49 PM PDT 24 | Jul 09 07:44:50 PM PDT 24 | 5439682464 ps | ||
| T195 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1500651540 | Jul 09 07:41:49 PM PDT 24 | Jul 09 07:46:33 PM PDT 24 | 5189463026 ps | ||
| T196 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3784800572 | Jul 09 07:41:46 PM PDT 24 | Jul 09 07:46:06 PM PDT 24 | 4450449259 ps |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1103440611 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 15458224914 ps |
| CPU time | 1493.59 seconds |
| Started | Jul 09 07:51:53 PM PDT 24 |
| Finished | Jul 09 08:16:48 PM PDT 24 |
| Peak memory | 611316 kb |
| Host | smart-dfb3c3ac-922e-40e1-8623-e9608c9447ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1103440611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1103440611 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.3062048370 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 13292341580 ps |
| CPU time | 1381.91 seconds |
| Started | Jul 09 08:06:15 PM PDT 24 |
| Finished | Jul 09 08:29:18 PM PDT 24 |
| Peak memory | 608408 kb |
| Host | smart-7763bbca-ba59-4096-9919-ac483e487160 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062048370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.3062048370 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1004886183 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2259288065 ps |
| CPU time | 191.51 seconds |
| Started | Jul 09 07:25:20 PM PDT 24 |
| Finished | Jul 09 07:28:40 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-13ccf76c-9932-4777-96ec-3be2c0222dd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004886183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1004886183 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.2565958833 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 3486248878 ps |
| CPU time | 643.18 seconds |
| Started | Jul 09 08:16:15 PM PDT 24 |
| Finished | Jul 09 08:26:59 PM PDT 24 |
| Peak memory | 608864 kb |
| Host | smart-bb3d972d-6bff-4ce4-bd46-e76900ec5bc8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565958833 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.2565958833 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3557304780 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 171374713637 ps |
| CPU time | 3310.3 seconds |
| Started | Jul 09 07:37:06 PM PDT 24 |
| Finished | Jul 09 08:32:18 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-7f044b1f-2cac-4584-b0c2-d34da1c9275a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557304780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.3557304780 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2446042993 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5011526005 ps |
| CPU time | 207.46 seconds |
| Started | Jul 09 07:41:48 PM PDT 24 |
| Finished | Jul 09 07:45:16 PM PDT 24 |
| Peak memory | 649496 kb |
| Host | smart-f6814161-d635-46d4-9756-7bca4bc813c6 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446042993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.2446042993 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.4140996485 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 100791325470 ps |
| CPU time | 1824.02 seconds |
| Started | Jul 09 07:30:20 PM PDT 24 |
| Finished | Jul 09 08:00:50 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-98f78aad-2950-4661-af46-32ca67b6d8f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140996485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.4140996485 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.346567614 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 8505506436 ps |
| CPU time | 1317.24 seconds |
| Started | Jul 09 08:13:42 PM PDT 24 |
| Finished | Jul 09 08:35:40 PM PDT 24 |
| Peak memory | 611412 kb |
| Host | smart-20ee23bf-c285-47de-a01c-4a22f589f78b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346567 614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.346567614 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2399100139 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 15996906050 ps |
| CPU time | 2101.54 seconds |
| Started | Jul 09 07:25:28 PM PDT 24 |
| Finished | Jul 09 08:00:41 PM PDT 24 |
| Peak memory | 593484 kb |
| Host | smart-df9abda3-e500-404e-8b92-1b061eff7f14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399100139 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.2399100139 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.2567638111 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 14670597624 ps |
| CPU time | 4172.01 seconds |
| Started | Jul 09 08:23:34 PM PDT 24 |
| Finished | Jul 09 09:33:07 PM PDT 24 |
| Peak memory | 610612 kb |
| Host | smart-98c362de-0d33-434f-bb50-7b9c26d39604 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=2567638111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.2567638111 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.1998306231 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 134883330513 ps |
| CPU time | 2195.23 seconds |
| Started | Jul 09 07:33:06 PM PDT 24 |
| Finished | Jul 09 08:09:42 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-491dbaab-61fe-49a7-b2ed-9cc447950a0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998306231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.1998306231 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_virus.1821527652 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 4846674960 ps |
| CPU time | 1181.78 seconds |
| Started | Jul 09 08:07:25 PM PDT 24 |
| Finished | Jul 09 08:27:08 PM PDT 24 |
| Peak memory | 625328 kb |
| Host | smart-125a46da-8f33-4021-a38c-b1fb63ec7e9a |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device= sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_ regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1821527652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.1821527652 |
| Directory | /workspace/1.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.4158483080 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 46352247240 ps |
| CPU time | 5795.42 seconds |
| Started | Jul 09 07:50:17 PM PDT 24 |
| Finished | Jul 09 09:26:55 PM PDT 24 |
| Peak memory | 619428 kb |
| Host | smart-1fa63a43-2482-41d9-a6e6-e00b6c792185 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158483080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.4158483080 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.831802112 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 125081706278 ps |
| CPU time | 2172.34 seconds |
| Started | Jul 09 07:27:59 PM PDT 24 |
| Finished | Jul 09 08:04:16 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-cbd18dc9-1bc5-45e3-915b-0a786cbb13ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831802112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_d evice_slow_rsp.831802112 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.1669532791 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 5702143266 ps |
| CPU time | 1355.19 seconds |
| Started | Jul 09 07:58:39 PM PDT 24 |
| Finished | Jul 09 08:21:15 PM PDT 24 |
| Peak memory | 610428 kb |
| Host | smart-007679a3-ebfa-43c0-a8af-48f2deb7159b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669532791 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.1669532791 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.318824349 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3419880493 ps |
| CPU time | 365.87 seconds |
| Started | Jul 09 07:49:12 PM PDT 24 |
| Finished | Jul 09 07:55:18 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-11abe141-06af-433b-8bda-ec0bd026f1be |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188 24349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.318824349 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4067723598 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 22114146060 ps |
| CPU time | 1817.97 seconds |
| Started | Jul 09 07:51:53 PM PDT 24 |
| Finished | Jul 09 08:22:12 PM PDT 24 |
| Peak memory | 611068 kb |
| Host | smart-3d00b46e-9dd8-4bc5-8183-00ebe091161d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4067723598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4067723598 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2323289016 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 3353427562 ps |
| CPU time | 282.01 seconds |
| Started | Jul 09 07:54:39 PM PDT 24 |
| Finished | Jul 09 07:59:22 PM PDT 24 |
| Peak memory | 609484 kb |
| Host | smart-d64e5439-3f81-4ef2-b176-409ca6a189e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2323289016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.2323289016 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.296446061 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6098681125 ps |
| CPU time | 533.53 seconds |
| Started | Jul 09 07:58:58 PM PDT 24 |
| Finished | Jul 09 08:07:53 PM PDT 24 |
| Peak memory | 611392 kb |
| Host | smart-a2d2f38f-cc78-4d3e-a7d2-ad284b54e6a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296446061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrn g_lc_hw_debug_en_test.296446061 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.913249733 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 135641896030 ps |
| CPU time | 2379.99 seconds |
| Started | Jul 09 07:30:37 PM PDT 24 |
| Finished | Jul 09 08:10:21 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-b8f86a1c-b860-4317-84e5-7d9140d801b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913249733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_d evice_slow_rsp.913249733 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.3066486090 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3021913720 ps |
| CPU time | 323.08 seconds |
| Started | Jul 09 08:14:25 PM PDT 24 |
| Finished | Jul 09 08:19:48 PM PDT 24 |
| Peak memory | 610020 kb |
| Host | smart-01d6d910-bc47-40a0-971e-98650cebeacb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066486090 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.3066486090 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3471866211 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 143050213266 ps |
| CPU time | 2740.84 seconds |
| Started | Jul 09 07:38:01 PM PDT 24 |
| Finished | Jul 09 08:23:43 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-b0e45014-8948-4d0a-abd7-48782d22b4d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471866211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.3471866211 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.4105132110 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 4695124344 ps |
| CPU time | 751.55 seconds |
| Started | Jul 09 08:15:40 PM PDT 24 |
| Finished | Jul 09 08:28:13 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-1bbf125d-ec35-476a-8c63-fa51c7ac4e3f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105132110 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.4105132110 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.2939035626 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 7545211216 ps |
| CPU time | 265.47 seconds |
| Started | Jul 09 07:31:42 PM PDT 24 |
| Finished | Jul 09 07:36:10 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-3ef1b8e1-4f6a-4c59-a6ad-b56bdd360f75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939035626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2939035626 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.673867628 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 4624926840 ps |
| CPU time | 370.66 seconds |
| Started | Jul 09 07:28:06 PM PDT 24 |
| Finished | Jul 09 07:34:19 PM PDT 24 |
| Peak memory | 604040 kb |
| Host | smart-60a10b2c-e3bf-4e5b-b10c-2ce62968ba1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673867628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.673867628 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.2009506209 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3513171807 ps |
| CPU time | 308.95 seconds |
| Started | Jul 09 07:57:11 PM PDT 24 |
| Finished | Jul 09 08:02:20 PM PDT 24 |
| Peak memory | 609020 kb |
| Host | smart-e1eca18d-8d05-4282-b4e8-4aa8d63b648c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009506209 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.2009506209 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1889699291 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 95172599026 ps |
| CPU time | 1794.18 seconds |
| Started | Jul 09 07:35:50 PM PDT 24 |
| Finished | Jul 09 08:05:51 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-dfe0ed43-a31b-4ae2-95c7-448680a2963e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889699291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.1889699291 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.776295744 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 21045938656 ps |
| CPU time | 4653.05 seconds |
| Started | Jul 09 07:57:59 PM PDT 24 |
| Finished | Jul 09 09:15:33 PM PDT 24 |
| Peak memory | 610888 kb |
| Host | smart-a09170c8-e067-4414-aa8d-6ef45eb97a23 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776295744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.776295744 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.3785292061 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 21996555984 ps |
| CPU time | 2597.13 seconds |
| Started | Jul 09 07:52:27 PM PDT 24 |
| Finished | Jul 09 08:35:45 PM PDT 24 |
| Peak memory | 608256 kb |
| Host | smart-8d971493-260e-4c83-95b9-e06c45849c40 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785292061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.3785292061 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3970394523 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 23246751880 ps |
| CPU time | 1290.45 seconds |
| Started | Jul 09 08:12:34 PM PDT 24 |
| Finished | Jul 09 08:34:06 PM PDT 24 |
| Peak memory | 615460 kb |
| Host | smart-4b8d1c44-b9bf-4068-abb5-cff431267ddb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39703945 23 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.3970394523 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3427145554 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 7327032686 ps |
| CPU time | 728.59 seconds |
| Started | Jul 09 08:19:22 PM PDT 24 |
| Finished | Jul 09 08:31:31 PM PDT 24 |
| Peak memory | 609928 kb |
| Host | smart-ebc5f9bf-f42f-40ee-96eb-e0601c30d3fa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34271455 54 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.3427145554 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.408961038 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 91213264425 ps |
| CPU time | 893.16 seconds |
| Started | Jul 09 07:32:32 PM PDT 24 |
| Finished | Jul 09 07:47:26 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-f821a369-6a80-4183-8019-18c4fd3f0c30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408961038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.408961038 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.1513379059 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 2939475148 ps |
| CPU time | 231.73 seconds |
| Started | Jul 09 07:37:32 PM PDT 24 |
| Finished | Jul 09 07:41:25 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-98dcbc76-ed30-479d-b3a9-b670d9e87971 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513379059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.1513379059 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.54760074 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 4946375059 ps |
| CPU time | 556.97 seconds |
| Started | Jul 09 07:51:35 PM PDT 24 |
| Finished | Jul 09 08:00:52 PM PDT 24 |
| Peak memory | 624008 kb |
| Host | smart-5014dadc-d0c9-4a00-8a98-2356c2902892 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54760074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.54760074 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.157421332 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 30704140584 ps |
| CPU time | 4028.01 seconds |
| Started | Jul 09 07:25:47 PM PDT 24 |
| Finished | Jul 09 08:33:13 PM PDT 24 |
| Peak memory | 593544 kb |
| Host | smart-1c2d0d47-c0dd-4be2-ab23-2c050b5003cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157421332 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.chip_same_csr_outstanding.157421332 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3345821374 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3960529002 ps |
| CPU time | 370 seconds |
| Started | Jul 09 08:05:22 PM PDT 24 |
| Finished | Jul 09 08:11:33 PM PDT 24 |
| Peak memory | 609424 kb |
| Host | smart-5fd0e966-c93f-4f1d-9155-4395d396d81b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345 821374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.3345821374 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3525493405 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4484203598 ps |
| CPU time | 481.05 seconds |
| Started | Jul 09 08:30:47 PM PDT 24 |
| Finished | Jul 09 08:38:48 PM PDT 24 |
| Peak memory | 649208 kb |
| Host | smart-a766648c-73fa-48c2-b174-477b35c6db5d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525493405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3525493405 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.512845155 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 5704104342 ps |
| CPU time | 432.61 seconds |
| Started | Jul 09 07:58:39 PM PDT 24 |
| Finished | Jul 09 08:05:53 PM PDT 24 |
| Peak memory | 609604 kb |
| Host | smart-17db089a-8a12-40f6-bcb5-9d808adbbf16 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51284515 5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.512845155 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2888406650 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 10850440256 ps |
| CPU time | 880.94 seconds |
| Started | Jul 09 07:50:49 PM PDT 24 |
| Finished | Jul 09 08:05:31 PM PDT 24 |
| Peak memory | 611036 kb |
| Host | smart-f0c68149-0932-4984-bd60-8396339562d2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888406650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.2888406650 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2881519118 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 5057419412 ps |
| CPU time | 783.52 seconds |
| Started | Jul 09 08:00:34 PM PDT 24 |
| Finished | Jul 09 08:13:39 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-fb8af8e0-0e3d-47e4-a54e-6cd0ac1871d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881519118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.2881519118 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.4188543942 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 42441063888 ps |
| CPU time | 4939.55 seconds |
| Started | Jul 09 08:00:19 PM PDT 24 |
| Finished | Jul 09 09:22:40 PM PDT 24 |
| Peak memory | 620844 kb |
| Host | smart-7c80bb6f-8f51-47fd-98f5-40c61b068f53 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4188543942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.4188543942 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.2854489159 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 4611776187 ps |
| CPU time | 463.32 seconds |
| Started | Jul 09 07:26:01 PM PDT 24 |
| Finished | Jul 09 07:34:06 PM PDT 24 |
| Peak memory | 604020 kb |
| Host | smart-4536dfd1-15ae-4677-8971-6949fcdd10ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854489159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.2854489159 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3443043979 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 5416938316 ps |
| CPU time | 635.88 seconds |
| Started | Jul 09 07:51:16 PM PDT 24 |
| Finished | Jul 09 08:01:54 PM PDT 24 |
| Peak memory | 611236 kb |
| Host | smart-6f9c3a94-fc60-4a4b-9ed3-22cb40fdadf6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3443043979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.3443043979 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.105834781 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2826368730 ps |
| CPU time | 284.09 seconds |
| Started | Jul 09 07:55:13 PM PDT 24 |
| Finished | Jul 09 07:59:57 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-f3a1f41b-af22-473b-8855-2c099b639c62 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058 34781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.105834781 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.2287153256 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 5847284756 ps |
| CPU time | 800.18 seconds |
| Started | Jul 09 08:23:41 PM PDT 24 |
| Finished | Jul 09 08:37:04 PM PDT 24 |
| Peak memory | 650744 kb |
| Host | smart-0c891ef3-6eb3-431a-92c4-822a7208c5e3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2287153256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.2287153256 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3719112025 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3397135560 ps |
| CPU time | 482.33 seconds |
| Started | Jul 09 08:18:23 PM PDT 24 |
| Finished | Jul 09 08:26:27 PM PDT 24 |
| Peak memory | 618820 kb |
| Host | smart-d09fc8ae-c20e-433b-b11e-4708a3660125 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3719112025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.3719112025 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.178117417 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 14228367145 ps |
| CPU time | 678.11 seconds |
| Started | Jul 09 07:26:29 PM PDT 24 |
| Finished | Jul 09 07:38:04 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-ef07f56c-4755-4e4b-8ec8-b98e02c72006 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178117417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_ with_rand_reset.178117417 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.3936534745 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2592472739 ps |
| CPU time | 82.14 seconds |
| Started | Jul 09 07:26:02 PM PDT 24 |
| Finished | Jul 09 07:27:46 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-408649e7-19d1-4bbf-8cde-3bacc1f87ebc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936534745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3936534745 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.2169043692 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 5732461514 ps |
| CPU time | 819.73 seconds |
| Started | Jul 09 08:17:52 PM PDT 24 |
| Finished | Jul 09 08:31:33 PM PDT 24 |
| Peak memory | 611172 kb |
| Host | smart-444656c6-ad0f-4701-8980-3767ea33a92b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2169043692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.2169043692 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2830766896 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 3822026020 ps |
| CPU time | 392.77 seconds |
| Started | Jul 09 07:51:35 PM PDT 24 |
| Finished | Jul 09 07:58:09 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-f892a723-b9f3-4c97-8538-24ee8c7587c1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28 30766896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.2830766896 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.3770390800 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 5643312608 ps |
| CPU time | 538.45 seconds |
| Started | Jul 09 08:23:52 PM PDT 24 |
| Finished | Jul 09 08:32:51 PM PDT 24 |
| Peak memory | 650452 kb |
| Host | smart-d81c01fe-156f-49af-9032-bca3ffc076bb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3770390800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.3770390800 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2771583277 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4790248599 ps |
| CPU time | 228.4 seconds |
| Started | Jul 09 07:41:57 PM PDT 24 |
| Finished | Jul 09 07:45:46 PM PDT 24 |
| Peak memory | 651056 kb |
| Host | smart-f6e2ee7a-f151-4944-9779-d457ccc5efb9 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771583277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.2771583277 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1612895260 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 9937348946 ps |
| CPU time | 1140.15 seconds |
| Started | Jul 09 08:12:11 PM PDT 24 |
| Finished | Jul 09 08:31:12 PM PDT 24 |
| Peak memory | 620296 kb |
| Host | smart-65f4d783-aeec-444d-a9db-8c3cd44346ea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612895260 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.1612895260 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.3573529971 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 4431141545 ps |
| CPU time | 463.77 seconds |
| Started | Jul 09 07:27:20 PM PDT 24 |
| Finished | Jul 09 07:35:11 PM PDT 24 |
| Peak memory | 603868 kb |
| Host | smart-6031c7a6-e144-44dc-a576-fa23f45a9ef1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573529971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.3573529971 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1020981775 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 4076465400 ps |
| CPU time | 419.11 seconds |
| Started | Jul 09 08:24:52 PM PDT 24 |
| Finished | Jul 09 08:31:52 PM PDT 24 |
| Peak memory | 648872 kb |
| Host | smart-aaa2a645-0d8a-4ce1-862a-7b371fe10fbf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020981775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1020981775 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2405834387 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 4288486743 ps |
| CPU time | 450.41 seconds |
| Started | Jul 09 07:25:28 PM PDT 24 |
| Finished | Jul 09 07:33:10 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-0b102be8-deb5-40a1-bfc3-87b978e3f39f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405834387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.2405834387 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1954206605 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 3347212880 ps |
| CPU time | 418.16 seconds |
| Started | Jul 09 08:22:10 PM PDT 24 |
| Finished | Jul 09 08:29:10 PM PDT 24 |
| Peak memory | 648904 kb |
| Host | smart-667a4197-88e8-449d-afc3-f8cbeb7ac866 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954206605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1954206605 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.96851460 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 3516021840 ps |
| CPU time | 510.8 seconds |
| Started | Jul 09 07:59:05 PM PDT 24 |
| Finished | Jul 09 08:07:37 PM PDT 24 |
| Peak memory | 649124 kb |
| Host | smart-bc5de3ca-a660-4844-8fc2-b634d7b301f2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96851460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ alert_handler_lpg_sleep_mode_alerts.96851460 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1454638160 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3995191730 ps |
| CPU time | 239.38 seconds |
| Started | Jul 09 07:48:38 PM PDT 24 |
| Finished | Jul 09 07:52:38 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-068fede7-69b5-404c-b890-5c2a157d63c0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454638160 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.1454638160 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1331989066 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 3814130689 ps |
| CPU time | 494.57 seconds |
| Started | Jul 09 08:18:29 PM PDT 24 |
| Finished | Jul 09 08:26:45 PM PDT 24 |
| Peak memory | 617852 kb |
| Host | smart-a9252e0c-ed31-4130-b106-4fef15da62d2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331989066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.1331989066 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2025375887 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 5176503025 ps |
| CPU time | 316.51 seconds |
| Started | Jul 09 07:32:29 PM PDT 24 |
| Finished | Jul 09 07:37:47 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-544e2c31-3d03-4ac8-ae0c-c58d40582c55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025375887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.2025375887 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.2104406855 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 928407901 ps |
| CPU time | 66.22 seconds |
| Started | Jul 09 07:32:13 PM PDT 24 |
| Finished | Jul 09 07:33:20 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-17378508-e947-45a7-b084-443bfb1286d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104406855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .2104406855 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.279301513 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 6062969994 ps |
| CPU time | 1275.85 seconds |
| Started | Jul 09 07:57:05 PM PDT 24 |
| Finished | Jul 09 08:18:22 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-3519c14a-3f32-4341-8edb-36ae289a3529 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279301513 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_plic_all_irqs_0.279301513 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.160882122 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 4193104763 ps |
| CPU time | 352.37 seconds |
| Started | Jul 09 08:15:28 PM PDT 24 |
| Finished | Jul 09 08:21:21 PM PDT 24 |
| Peak memory | 622924 kb |
| Host | smart-bff0cf9e-7662-4cdc-a170-e7f13c2262f1 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160882122 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.160882122 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2037989727 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 5283354297 ps |
| CPU time | 236.72 seconds |
| Started | Jul 09 07:25:32 PM PDT 24 |
| Finished | Jul 09 07:29:40 PM PDT 24 |
| Peak memory | 663088 kb |
| Host | smart-faec7714-10d5-4298-b5ff-56a3bf7eea09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037989727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.2037989727 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1795337075 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6218617452 ps |
| CPU time | 445.58 seconds |
| Started | Jul 09 08:05:01 PM PDT 24 |
| Finished | Jul 09 08:12:28 PM PDT 24 |
| Peak memory | 610900 kb |
| Host | smart-53813a5d-bc10-4314-a094-447ebbeef4ee |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795337075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.1795337075 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3130442868 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5527970072 ps |
| CPU time | 365.71 seconds |
| Started | Jul 09 07:50:31 PM PDT 24 |
| Finished | Jul 09 07:56:37 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-b19754b5-2238-4500-a167-a236376cc9a5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130442868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.3130442868 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2218223623 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2765037445 ps |
| CPU time | 144.9 seconds |
| Started | Jul 09 07:50:53 PM PDT 24 |
| Finished | Jul 09 07:53:19 PM PDT 24 |
| Peak memory | 621108 kb |
| Host | smart-766242d5-57ad-4d6b-8dbb-29d5df25a44a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22182236 23 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.2218223623 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1977871828 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 43644994621 ps |
| CPU time | 5927.88 seconds |
| Started | Jul 09 07:49:17 PM PDT 24 |
| Finished | Jul 09 09:28:07 PM PDT 24 |
| Peak memory | 619904 kb |
| Host | smart-0f71b46f-feec-402b-b74b-e5863e637ead |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1977871828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.1977871828 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.1219035043 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 3563158664 ps |
| CPU time | 291.71 seconds |
| Started | Jul 09 07:25:23 PM PDT 24 |
| Finished | Jul 09 07:30:25 PM PDT 24 |
| Peak memory | 604012 kb |
| Host | smart-391057bb-abd7-4c97-afeb-e83285682f56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219035043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.1219035043 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.1450843580 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 3913132849 ps |
| CPU time | 421.96 seconds |
| Started | Jul 09 07:29:04 PM PDT 24 |
| Finished | Jul 09 07:36:16 PM PDT 24 |
| Peak memory | 576172 kb |
| Host | smart-ef1238a9-cedc-4623-b656-100b378d967c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450843580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.1450843580 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3846991142 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 5394727291 ps |
| CPU time | 776.28 seconds |
| Started | Jul 09 07:55:47 PM PDT 24 |
| Finished | Jul 09 08:08:45 PM PDT 24 |
| Peak memory | 610612 kb |
| Host | smart-1ea373d3-bd0b-4d6d-b98d-287d5a51cf62 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3846991142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3846991142 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1343916525 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 3181209520 ps |
| CPU time | 470.03 seconds |
| Started | Jul 09 07:50:39 PM PDT 24 |
| Finished | Jul 09 07:58:30 PM PDT 24 |
| Peak memory | 608728 kb |
| Host | smart-daf2f022-2153-4457-a046-f2a497ea0eb6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134391 6525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.1343916525 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.1523223668 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 5392677162 ps |
| CPU time | 700.85 seconds |
| Started | Jul 09 08:22:51 PM PDT 24 |
| Finished | Jul 09 08:34:33 PM PDT 24 |
| Peak memory | 649852 kb |
| Host | smart-dfd50c1c-19bd-4a19-bcec-a5389b9ec2d4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1523223668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.1523223668 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3828586023 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 109574234408 ps |
| CPU time | 2024.73 seconds |
| Started | Jul 09 07:31:59 PM PDT 24 |
| Finished | Jul 09 08:05:46 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-4283889d-7e67-48a3-afad-78b5cbc677f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828586023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.3828586023 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.47382606 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 26402925920 ps |
| CPU time | 3042.7 seconds |
| Started | Jul 09 07:51:14 PM PDT 24 |
| Finished | Jul 09 08:41:59 PM PDT 24 |
| Peak memory | 611584 kb |
| Host | smart-7c10e563-0d5f-440f-9123-892cd52eafc7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47382606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitch _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sle ep_power_glitch_reset.47382606 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.2758261469 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 4866620974 ps |
| CPU time | 767.29 seconds |
| Started | Jul 09 07:58:57 PM PDT 24 |
| Finished | Jul 09 08:11:46 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-0aef25aa-82eb-4fb5-b5e1-eaaaa7f26909 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758261469 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.2758261469 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.1967375053 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 18134512315 ps |
| CPU time | 964.08 seconds |
| Started | Jul 09 07:37:17 PM PDT 24 |
| Finished | Jul 09 07:53:23 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-f93294fc-3364-43cb-9fd8-732343bd3882 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967375053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.1967375053 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.571203660 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 7027942360 ps |
| CPU time | 355.76 seconds |
| Started | Jul 09 07:25:41 PM PDT 24 |
| Finished | Jul 09 07:31:52 PM PDT 24 |
| Peak memory | 663304 kb |
| Host | smart-9cc71ea0-e679-499e-9a7c-488197c0eb53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571203660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_re set.571203660 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.443064100 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 522080309 ps |
| CPU time | 183.28 seconds |
| Started | Jul 09 07:31:33 PM PDT 24 |
| Finished | Jul 09 07:34:40 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-3908680c-bed1-421d-ad4f-2f1e0d1cd75d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443064100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_ with_rand_reset.443064100 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.2849061365 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3914438300 ps |
| CPU time | 519.54 seconds |
| Started | Jul 09 07:51:00 PM PDT 24 |
| Finished | Jul 09 07:59:41 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-184c0d92-c1be-4b62-83d2-7c339edbe13c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849061365 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.2849061365 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.3613210118 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 3890937219 ps |
| CPU time | 276.38 seconds |
| Started | Jul 09 07:25:44 PM PDT 24 |
| Finished | Jul 09 07:30:36 PM PDT 24 |
| Peak memory | 599260 kb |
| Host | smart-2a798267-e6d5-4b80-a3bd-0a68ee36ba6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613210118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.3613210118 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.2280664260 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 6626983680 ps |
| CPU time | 1025.94 seconds |
| Started | Jul 09 08:15:33 PM PDT 24 |
| Finished | Jul 09 08:32:40 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-beb16ae6-829b-460f-8f56-3f0a749c09a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280664260 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.2280664260 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.469910908 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 4942196809 ps |
| CPU time | 592.26 seconds |
| Started | Jul 09 07:30:33 PM PDT 24 |
| Finished | Jul 09 07:40:30 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-acf90326-ad19-4444-a16c-d757862d23d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469910908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_ with_rand_reset.469910908 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.868829426 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 6612045892 ps |
| CPU time | 963.31 seconds |
| Started | Jul 09 07:58:47 PM PDT 24 |
| Finished | Jul 09 08:14:51 PM PDT 24 |
| Peak memory | 610496 kb |
| Host | smart-89a774a7-b926-43eb-b5e7-597ba053d4ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86882942 6 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.868829426 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1022357113 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 4683014104 ps |
| CPU time | 591.7 seconds |
| Started | Jul 09 08:23:20 PM PDT 24 |
| Finished | Jul 09 08:33:12 PM PDT 24 |
| Peak memory | 609608 kb |
| Host | smart-33827ffa-3c11-4374-9805-61a0886e15d2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10223571 13 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.1022357113 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3366341620 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 30543253280 ps |
| CPU time | 3943.59 seconds |
| Started | Jul 09 07:25:59 PM PDT 24 |
| Finished | Jul 09 08:32:05 PM PDT 24 |
| Peak memory | 593904 kb |
| Host | smart-131f4df5-aedd-497d-aaf7-ab2654428575 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366341620 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.3366341620 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1561232642 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 19319043044 ps |
| CPU time | 2827.77 seconds |
| Started | Jul 09 08:02:43 PM PDT 24 |
| Finished | Jul 09 08:49:52 PM PDT 24 |
| Peak memory | 610820 kb |
| Host | smart-093d2fee-7a01-425d-8e36-efc44bb2914a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561232642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.1561232642 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.932787905 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2894248771 ps |
| CPU time | 299.49 seconds |
| Started | Jul 09 07:56:36 PM PDT 24 |
| Finished | Jul 09 08:01:36 PM PDT 24 |
| Peak memory | 622924 kb |
| Host | smart-51add0e0-55f0-4bcd-8ee8-2ecca7bd348a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932787905 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.932787905 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.3867921502 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 26942010000 ps |
| CPU time | 3755.2 seconds |
| Started | Jul 09 08:00:33 PM PDT 24 |
| Finished | Jul 09 09:03:10 PM PDT 24 |
| Peak memory | 611908 kb |
| Host | smart-aafc59ae-c6c9-42f1-8795-00ca0e8e13a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867921502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.3867921502 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.2428805707 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 10753495213 ps |
| CPU time | 620.43 seconds |
| Started | Jul 09 07:35:43 PM PDT 24 |
| Finished | Jul 09 07:46:07 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-eeaaf4a9-33ae-4519-be07-087ccc8133b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428805707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.2428805707 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3292587863 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 79519719882 ps |
| CPU time | 13603.2 seconds |
| Started | Jul 09 07:49:30 PM PDT 24 |
| Finished | Jul 09 11:36:16 PM PDT 24 |
| Peak memory | 634280 kb |
| Host | smart-c51fc072-dc40-41d5-b682-76a2e5e01722 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3292587863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.3292587863 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.3418564780 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 3390566352 ps |
| CPU time | 189.96 seconds |
| Started | Jul 09 07:25:45 PM PDT 24 |
| Finished | Jul 09 07:29:12 PM PDT 24 |
| Peak memory | 603960 kb |
| Host | smart-172d66a3-bbac-4087-b3d9-0aa0aba0e6ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418564780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.3418564780 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.2775452209 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 21353519138 ps |
| CPU time | 805.52 seconds |
| Started | Jul 09 07:37:36 PM PDT 24 |
| Finished | Jul 09 07:51:02 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-2fbe0424-d7c2-4fbb-814e-6a3ee2cda4ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775452209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.2775452209 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.775284991 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 5113812752 ps |
| CPU time | 890.87 seconds |
| Started | Jul 09 07:52:18 PM PDT 24 |
| Finished | Jul 09 08:07:10 PM PDT 24 |
| Peak memory | 609116 kb |
| Host | smart-c4c20978-fd81-4173-9b04-84522d4142fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775284991 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_20.775284991 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.2440069545 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 15630689506 ps |
| CPU time | 598 seconds |
| Started | Jul 09 07:38:32 PM PDT 24 |
| Finished | Jul 09 07:48:31 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-26ebcdf7-12bd-427a-9640-89ad43afbfed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440069545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.2440069545 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1956108050 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 3668556252 ps |
| CPU time | 731.36 seconds |
| Started | Jul 09 07:53:06 PM PDT 24 |
| Finished | Jul 09 08:05:18 PM PDT 24 |
| Peak memory | 613140 kb |
| Host | smart-b7c75b10-5867-4cc4-afc3-b89e06992fbd |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956108050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1956108050 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.4014923537 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 46807271725 ps |
| CPU time | 5828.18 seconds |
| Started | Jul 09 07:59:19 PM PDT 24 |
| Finished | Jul 09 09:36:29 PM PDT 24 |
| Peak memory | 620260 kb |
| Host | smart-b493d768-1871-4cfc-b785-12d35630081e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014923537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.4014923537 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3692852148 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 8000963062 ps |
| CPU time | 1464.73 seconds |
| Started | Jul 09 08:16:46 PM PDT 24 |
| Finished | Jul 09 08:41:13 PM PDT 24 |
| Peak memory | 618668 kb |
| Host | smart-59c974d8-4fd3-49b7-9922-268093870177 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3692852148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.3692852148 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3070275007 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 7878309096 ps |
| CPU time | 1496.16 seconds |
| Started | Jul 09 07:52:29 PM PDT 24 |
| Finished | Jul 09 08:17:26 PM PDT 24 |
| Peak memory | 617768 kb |
| Host | smart-de3224f2-41f3-4505-b859-4fcc08292ff4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3070275007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.3070275007 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1212678623 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 3823213573 ps |
| CPU time | 312.35 seconds |
| Started | Jul 09 07:26:02 PM PDT 24 |
| Finished | Jul 09 07:31:36 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-61607e3c-2049-40e4-9d28-736840e9e863 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212678623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.1212678623 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3652371977 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 44920320952 ps |
| CPU time | 5182.08 seconds |
| Started | Jul 09 08:05:07 PM PDT 24 |
| Finished | Jul 09 09:31:30 PM PDT 24 |
| Peak memory | 621524 kb |
| Host | smart-08d018d5-2c63-49d2-96b1-0b6d033d2597 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3652371977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.3652371977 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.1471954421 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 3730537050 ps |
| CPU time | 167.5 seconds |
| Started | Jul 09 07:25:53 PM PDT 24 |
| Finished | Jul 09 07:29:00 PM PDT 24 |
| Peak memory | 598824 kb |
| Host | smart-a2f5ce69-776a-4e3e-a85f-ae39be81f850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471954421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.1471954421 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3245249457 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 101685730372 ps |
| CPU time | 1904.93 seconds |
| Started | Jul 09 07:25:25 PM PDT 24 |
| Finished | Jul 09 07:57:21 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-aac8739e-6259-43d3-b78c-5ff1d53b6d54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245249457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.3245249457 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.4053781001 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5655267868 ps |
| CPU time | 485.56 seconds |
| Started | Jul 09 07:56:05 PM PDT 24 |
| Finished | Jul 09 08:04:12 PM PDT 24 |
| Peak memory | 610904 kb |
| Host | smart-4f731989-1673-4011-92cd-6c278d5fddb5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053781001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.4053781001 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.1368243572 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 15566154956 ps |
| CPU time | 525.84 seconds |
| Started | Jul 09 07:36:32 PM PDT 24 |
| Finished | Jul 09 07:45:18 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-693b1fc5-6f48-4f15-a7df-5712d7062668 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368243572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.1368243572 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3613206282 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 3466739224 ps |
| CPU time | 480.1 seconds |
| Started | Jul 09 07:55:32 PM PDT 24 |
| Finished | Jul 09 08:03:33 PM PDT 24 |
| Peak memory | 621328 kb |
| Host | smart-7a802656-f92b-4165-822a-b955db836c7c |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361320 6282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3613206282 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.3221154437 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 7920690952 ps |
| CPU time | 1634.89 seconds |
| Started | Jul 09 07:49:03 PM PDT 24 |
| Finished | Jul 09 08:16:20 PM PDT 24 |
| Peak memory | 609528 kb |
| Host | smart-bb9b1a2b-d964-4681-b986-f7a875eb108a |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32211 54437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.3221154437 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.3421169591 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 4416826016 ps |
| CPU time | 695 seconds |
| Started | Jul 09 08:16:34 PM PDT 24 |
| Finished | Jul 09 08:28:10 PM PDT 24 |
| Peak memory | 650204 kb |
| Host | smart-53fbe4cf-6ea3-475a-bb9f-7e743c6a14c7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3421169591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.3421169591 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.3693219903 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 5825999852 ps |
| CPU time | 589.73 seconds |
| Started | Jul 09 08:20:15 PM PDT 24 |
| Finished | Jul 09 08:30:06 PM PDT 24 |
| Peak memory | 650436 kb |
| Host | smart-72c3eeb0-d6f3-4420-bed6-a753c7c2f85b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3693219903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.3693219903 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2735529475 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 4894310689 ps |
| CPU time | 373.51 seconds |
| Started | Jul 09 07:31:30 PM PDT 24 |
| Finished | Jul 09 07:37:46 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-b33d08a4-e5f6-4f7d-9956-f88e6603358a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735529475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.2735529475 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3984956888 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 5151795576 ps |
| CPU time | 572.8 seconds |
| Started | Jul 09 07:25:42 PM PDT 24 |
| Finished | Jul 09 07:35:30 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-bca32b1e-243d-4ef9-8a7a-a2b81382e2ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984956888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.3984956888 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.817554342 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 5703068178 ps |
| CPU time | 643.26 seconds |
| Started | Jul 09 08:21:00 PM PDT 24 |
| Finished | Jul 09 08:31:44 PM PDT 24 |
| Peak memory | 650148 kb |
| Host | smart-6edddce9-237f-4bdb-ad1d-5cc6fc630fb5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 817554342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.817554342 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.2405780374 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 605060906 ps |
| CPU time | 43.37 seconds |
| Started | Jul 09 07:30:29 PM PDT 24 |
| Finished | Jul 09 07:31:17 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-3d95e76e-0152-4503-a997-6b8329a325d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405780374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2405780374 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.2205254229 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 1106779480 ps |
| CPU time | 85.63 seconds |
| Started | Jul 09 07:31:22 PM PDT 24 |
| Finished | Jul 09 07:32:49 PM PDT 24 |
| Peak memory | 576504 kb |
| Host | smart-4e2e18aa-8706-4328-a056-985a7944b9e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205254229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .2205254229 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2045574252 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 3389770424 ps |
| CPU time | 657.01 seconds |
| Started | Jul 09 07:50:46 PM PDT 24 |
| Finished | Jul 09 08:01:44 PM PDT 24 |
| Peak memory | 610428 kb |
| Host | smart-e009c527-b655-40ce-95e4-2dd175ed8677 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045574252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.2045574252 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.3708204917 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 4190234136 ps |
| CPU time | 690.57 seconds |
| Started | Jul 09 08:00:05 PM PDT 24 |
| Finished | Jul 09 08:11:37 PM PDT 24 |
| Peak memory | 608736 kb |
| Host | smart-6c74634f-9fae-4473-a0bc-17152583ebd4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708204917 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.3708204917 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1732564742 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 4006516424 ps |
| CPU time | 505.95 seconds |
| Started | Jul 09 08:03:23 PM PDT 24 |
| Finished | Jul 09 08:11:50 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-e97da5a3-db66-4169-a2b4-5745622b4954 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732564742 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.1732564742 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.669596796 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1604882249 ps |
| CPU time | 100.88 seconds |
| Started | Jul 09 08:06:57 PM PDT 24 |
| Finished | Jul 09 08:08:38 PM PDT 24 |
| Peak memory | 622160 kb |
| Host | smart-9062672c-cba6-47df-a409-83b05215f58a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669596796 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.669596796 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2530940132 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 4285012168 ps |
| CPU time | 938.43 seconds |
| Started | Jul 09 08:14:12 PM PDT 24 |
| Finished | Jul 09 08:29:51 PM PDT 24 |
| Peak memory | 608812 kb |
| Host | smart-d31d3aed-c985-4c07-afa9-356c50458c05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25309 40132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.2530940132 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3472553328 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 1559539580 ps |
| CPU time | 283.1 seconds |
| Started | Jul 09 07:25:20 PM PDT 24 |
| Finished | Jul 09 07:30:11 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-da3e5ce6-8391-4047-bd27-5c11648956c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472553328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.3472553328 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.3607044197 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 10770956844 ps |
| CPU time | 540.12 seconds |
| Started | Jul 09 07:29:50 PM PDT 24 |
| Finished | Jul 09 07:38:53 PM PDT 24 |
| Peak memory | 576896 kb |
| Host | smart-24cb538e-fd44-4155-a5cc-89ce5a4ed19d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607044197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.3607044197 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2498534914 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 4193787960 ps |
| CPU time | 439.19 seconds |
| Started | Jul 09 07:56:26 PM PDT 24 |
| Finished | Jul 09 08:03:46 PM PDT 24 |
| Peak memory | 649372 kb |
| Host | smart-f4ae3c26-92ac-48d7-b732-e0ac83537577 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498534914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.2498534914 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.26368941 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 5347932940 ps |
| CPU time | 660.71 seconds |
| Started | Jul 09 07:48:33 PM PDT 24 |
| Finished | Jul 09 07:59:35 PM PDT 24 |
| Peak memory | 650036 kb |
| Host | smart-c626b498-c882-4336-9ac5-ed43de8c74a6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 26368941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.26368941 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.3957595941 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 5324428856 ps |
| CPU time | 669.29 seconds |
| Started | Jul 09 07:56:01 PM PDT 24 |
| Finished | Jul 09 08:07:11 PM PDT 24 |
| Peak memory | 649844 kb |
| Host | smart-9abeaaf6-6c0b-4e1e-b216-994d5f3c2cf9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3957595941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.3957595941 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3457446402 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 3675182518 ps |
| CPU time | 353.53 seconds |
| Started | Jul 09 08:18:21 PM PDT 24 |
| Finished | Jul 09 08:24:15 PM PDT 24 |
| Peak memory | 648940 kb |
| Host | smart-0ab5f044-9b9e-4944-b4d5-75bded533c2d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457446402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3457446402 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.3069823040 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 6177948834 ps |
| CPU time | 759.49 seconds |
| Started | Jul 09 08:22:24 PM PDT 24 |
| Finished | Jul 09 08:35:06 PM PDT 24 |
| Peak memory | 650160 kb |
| Host | smart-a85b0f6c-1488-4209-9b4e-42456744a219 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3069823040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.3069823040 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2081628618 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3622770912 ps |
| CPU time | 502.71 seconds |
| Started | Jul 09 08:18:43 PM PDT 24 |
| Finished | Jul 09 08:27:06 PM PDT 24 |
| Peak memory | 649468 kb |
| Host | smart-02467600-7b4f-4f78-9362-147c3e0b3e85 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081628618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2081628618 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.3607129262 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 6035467008 ps |
| CPU time | 720.31 seconds |
| Started | Jul 09 08:19:45 PM PDT 24 |
| Finished | Jul 09 08:31:46 PM PDT 24 |
| Peak memory | 650248 kb |
| Host | smart-8a9a395b-1ee0-4c55-847d-a5f6ada22c9a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3607129262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.3607129262 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2636316720 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 3126877800 ps |
| CPU time | 390.18 seconds |
| Started | Jul 09 08:22:15 PM PDT 24 |
| Finished | Jul 09 08:28:46 PM PDT 24 |
| Peak memory | 649120 kb |
| Host | smart-9bfa100e-59ba-432e-aba4-7c0999f126a8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636316720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2636316720 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.1932696740 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 5700223974 ps |
| CPU time | 697.15 seconds |
| Started | Jul 09 08:19:03 PM PDT 24 |
| Finished | Jul 09 08:30:41 PM PDT 24 |
| Peak memory | 650460 kb |
| Host | smart-47b0f83d-b7a0-4b21-98ca-a2fd2f9a1445 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1932696740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.1932696740 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2535165693 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 4258647736 ps |
| CPU time | 412.92 seconds |
| Started | Jul 09 08:21:39 PM PDT 24 |
| Finished | Jul 09 08:28:33 PM PDT 24 |
| Peak memory | 648856 kb |
| Host | smart-fc0095b4-94f4-4ddb-8dab-976dbe6de807 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535165693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2535165693 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1320296296 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 3550203318 ps |
| CPU time | 447.05 seconds |
| Started | Jul 09 08:20:22 PM PDT 24 |
| Finished | Jul 09 08:27:50 PM PDT 24 |
| Peak memory | 648888 kb |
| Host | smart-99e6aa54-4d86-40de-8fca-5bd5e994d611 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320296296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1320296296 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.3008755752 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 5405689512 ps |
| CPU time | 713.54 seconds |
| Started | Jul 09 08:17:48 PM PDT 24 |
| Finished | Jul 09 08:29:43 PM PDT 24 |
| Peak memory | 649840 kb |
| Host | smart-d493b209-d9a2-4269-802c-6d02589df8aa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3008755752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.3008755752 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.4096851051 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 4428738402 ps |
| CPU time | 475.96 seconds |
| Started | Jul 09 08:19:59 PM PDT 24 |
| Finished | Jul 09 08:27:56 PM PDT 24 |
| Peak memory | 649168 kb |
| Host | smart-b2bc1f3a-079b-48a9-80b0-1c34786589d5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096851051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4096851051 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1060897894 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 4398313210 ps |
| CPU time | 332.46 seconds |
| Started | Jul 09 08:22:57 PM PDT 24 |
| Finished | Jul 09 08:28:30 PM PDT 24 |
| Peak memory | 649072 kb |
| Host | smart-080abcfd-c4cf-4601-ad2e-537798901315 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060897894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1060897894 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.3007629788 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 4820130940 ps |
| CPU time | 594.49 seconds |
| Started | Jul 09 08:19:08 PM PDT 24 |
| Finished | Jul 09 08:29:03 PM PDT 24 |
| Peak memory | 650212 kb |
| Host | smart-5cb89b97-c892-4790-9225-eaf8ec7b827e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3007629788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.3007629788 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.192511411 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 4193687788 ps |
| CPU time | 504.88 seconds |
| Started | Jul 09 08:13:28 PM PDT 24 |
| Finished | Jul 09 08:21:53 PM PDT 24 |
| Peak memory | 648900 kb |
| Host | smart-ae50f8eb-1446-4a4f-8272-5385bf969db6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192511411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _alert_handler_lpg_sleep_mode_alerts.192511411 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.2516970608 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 5122396420 ps |
| CPU time | 636.45 seconds |
| Started | Jul 09 08:24:05 PM PDT 24 |
| Finished | Jul 09 08:34:42 PM PDT 24 |
| Peak memory | 650476 kb |
| Host | smart-f07ae559-d0ee-4ba6-a67a-6e20d5071bf8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2516970608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.2516970608 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3952258524 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3590561530 ps |
| CPU time | 322.04 seconds |
| Started | Jul 09 08:18:39 PM PDT 24 |
| Finished | Jul 09 08:24:02 PM PDT 24 |
| Peak memory | 648748 kb |
| Host | smart-8ba40dcb-cae7-4a02-b809-1d5dc1586424 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952258524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3952258524 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.1125749361 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 5318340148 ps |
| CPU time | 678.91 seconds |
| Started | Jul 09 08:18:59 PM PDT 24 |
| Finished | Jul 09 08:30:18 PM PDT 24 |
| Peak memory | 649872 kb |
| Host | smart-5af2d48c-526f-443f-b4f2-870042a1b844 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1125749361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.1125749361 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.2180277148 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 4818722030 ps |
| CPU time | 807.66 seconds |
| Started | Jul 09 08:20:40 PM PDT 24 |
| Finished | Jul 09 08:34:08 PM PDT 24 |
| Peak memory | 650304 kb |
| Host | smart-541d86c7-f3cb-4ac8-a0d4-086da9aec402 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2180277148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.2180277148 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.522611380 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 4000814222 ps |
| CPU time | 439.65 seconds |
| Started | Jul 09 08:24:17 PM PDT 24 |
| Finished | Jul 09 08:31:37 PM PDT 24 |
| Peak memory | 648596 kb |
| Host | smart-0668a3da-9d9a-406f-bcb3-e3f25bafe9e0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522611380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_s w_alert_handler_lpg_sleep_mode_alerts.522611380 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.1416942882 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 4510707104 ps |
| CPU time | 646.96 seconds |
| Started | Jul 09 08:19:17 PM PDT 24 |
| Finished | Jul 09 08:30:04 PM PDT 24 |
| Peak memory | 650208 kb |
| Host | smart-2ab1b29d-e4b6-4850-9376-225f7e3ca78a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1416942882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.1416942882 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.3497418160 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 6152597136 ps |
| CPU time | 568.05 seconds |
| Started | Jul 09 08:18:44 PM PDT 24 |
| Finished | Jul 09 08:28:13 PM PDT 24 |
| Peak memory | 650344 kb |
| Host | smart-aecde8f6-bf7a-48eb-9a2b-9690de626186 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3497418160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.3497418160 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1294360449 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 3944379372 ps |
| CPU time | 335.59 seconds |
| Started | Jul 09 08:26:07 PM PDT 24 |
| Finished | Jul 09 08:31:43 PM PDT 24 |
| Peak memory | 648956 kb |
| Host | smart-27792f89-74b8-4f0a-b86d-9266c32e012c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294360449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1294360449 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2883335610 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 4201038108 ps |
| CPU time | 418.38 seconds |
| Started | Jul 09 08:21:20 PM PDT 24 |
| Finished | Jul 09 08:28:21 PM PDT 24 |
| Peak memory | 649252 kb |
| Host | smart-13dc5786-25a2-4309-b016-25feba99086b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883335610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.2883335610 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3834365928 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 3433419788 ps |
| CPU time | 411.35 seconds |
| Started | Jul 09 08:20:10 PM PDT 24 |
| Finished | Jul 09 08:27:03 PM PDT 24 |
| Peak memory | 648844 kb |
| Host | smart-8a777eda-3aea-4442-83a3-034bf34183e7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834365928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3834365928 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.2477000584 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 6048384484 ps |
| CPU time | 599.76 seconds |
| Started | Jul 09 08:27:13 PM PDT 24 |
| Finished | Jul 09 08:37:13 PM PDT 24 |
| Peak memory | 650176 kb |
| Host | smart-8733ad3c-4394-4e97-9171-ac6da485cbb1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2477000584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.2477000584 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.164275378 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3963430428 ps |
| CPU time | 397.21 seconds |
| Started | Jul 09 08:20:16 PM PDT 24 |
| Finished | Jul 09 08:26:54 PM PDT 24 |
| Peak memory | 648968 kb |
| Host | smart-3a537ea8-8777-4ccc-b46f-123385818871 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164275378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_s w_alert_handler_lpg_sleep_mode_alerts.164275378 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.2872766989 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 5521102472 ps |
| CPU time | 729.25 seconds |
| Started | Jul 09 08:21:29 PM PDT 24 |
| Finished | Jul 09 08:33:39 PM PDT 24 |
| Peak memory | 650068 kb |
| Host | smart-39f1beca-d711-419c-bee7-bf448f202f96 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2872766989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.2872766989 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2762266475 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 3876085544 ps |
| CPU time | 401.87 seconds |
| Started | Jul 09 08:18:58 PM PDT 24 |
| Finished | Jul 09 08:25:41 PM PDT 24 |
| Peak memory | 648636 kb |
| Host | smart-954c589a-842f-46b1-ad4c-30ffab1f837c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762266475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2762266475 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.1340428465 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 4700940350 ps |
| CPU time | 585.99 seconds |
| Started | Jul 09 08:21:33 PM PDT 24 |
| Finished | Jul 09 08:31:19 PM PDT 24 |
| Peak memory | 650416 kb |
| Host | smart-4bddb69e-a5dc-45f7-8690-6b76176548c6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1340428465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.1340428465 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.1286666935 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 5211005966 ps |
| CPU time | 696.67 seconds |
| Started | Jul 09 08:19:25 PM PDT 24 |
| Finished | Jul 09 08:31:02 PM PDT 24 |
| Peak memory | 650156 kb |
| Host | smart-8c5feb0f-caca-48d6-9d7a-64488ebb7d78 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1286666935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.1286666935 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3861741721 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 4097258152 ps |
| CPU time | 447.14 seconds |
| Started | Jul 09 08:20:55 PM PDT 24 |
| Finished | Jul 09 08:28:22 PM PDT 24 |
| Peak memory | 648928 kb |
| Host | smart-81ac084d-b2a9-49c5-8763-89ec35e01eb1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861741721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3861741721 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3283672950 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 3101500462 ps |
| CPU time | 337.47 seconds |
| Started | Jul 09 08:21:25 PM PDT 24 |
| Finished | Jul 09 08:27:03 PM PDT 24 |
| Peak memory | 649016 kb |
| Host | smart-9b99f9ed-9db6-41e9-b352-ae17cd979056 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283672950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3283672950 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.1776619512 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 5633166900 ps |
| CPU time | 702.86 seconds |
| Started | Jul 09 08:20:53 PM PDT 24 |
| Finished | Jul 09 08:32:37 PM PDT 24 |
| Peak memory | 649844 kb |
| Host | smart-7132dd06-68fb-452d-a389-500726548347 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1776619512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.1776619512 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1663435059 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 4285494676 ps |
| CPU time | 429.25 seconds |
| Started | Jul 09 08:21:22 PM PDT 24 |
| Finished | Jul 09 08:28:32 PM PDT 24 |
| Peak memory | 648644 kb |
| Host | smart-42990d79-1d6a-40c1-8a50-33bd3f722974 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663435059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1663435059 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2829461320 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 3673421016 ps |
| CPU time | 465.09 seconds |
| Started | Jul 09 08:21:05 PM PDT 24 |
| Finished | Jul 09 08:28:51 PM PDT 24 |
| Peak memory | 648636 kb |
| Host | smart-057cc226-0c72-41ec-9d90-fd19d2a0eac8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829461320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2829461320 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2792328158 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 3188776500 ps |
| CPU time | 400.17 seconds |
| Started | Jul 09 08:20:20 PM PDT 24 |
| Finished | Jul 09 08:27:01 PM PDT 24 |
| Peak memory | 648688 kb |
| Host | smart-1889624f-e4a4-474e-a2aa-fb64d35aed38 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792328158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2792328158 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.3328594002 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 5935034840 ps |
| CPU time | 679.46 seconds |
| Started | Jul 09 08:24:02 PM PDT 24 |
| Finished | Jul 09 08:35:23 PM PDT 24 |
| Peak memory | 650172 kb |
| Host | smart-7d7fc7ad-c2ec-4ea7-b979-1532c3ba19b0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3328594002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.3328594002 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.391611427 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3471465858 ps |
| CPU time | 414.89 seconds |
| Started | Jul 09 08:25:54 PM PDT 24 |
| Finished | Jul 09 08:32:50 PM PDT 24 |
| Peak memory | 648960 kb |
| Host | smart-c7c3424b-e4f3-4e2e-b43e-56a0d74b3898 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391611427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_s w_alert_handler_lpg_sleep_mode_alerts.391611427 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.257147462 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 3595941050 ps |
| CPU time | 388.83 seconds |
| Started | Jul 09 08:19:51 PM PDT 24 |
| Finished | Jul 09 08:26:21 PM PDT 24 |
| Peak memory | 649084 kb |
| Host | smart-1b7abe3e-aa55-468b-85bd-ecff5dab7295 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257147462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw _alert_handler_lpg_sleep_mode_alerts.257147462 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.1578010357 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 4557196680 ps |
| CPU time | 683.08 seconds |
| Started | Jul 09 08:13:29 PM PDT 24 |
| Finished | Jul 09 08:24:52 PM PDT 24 |
| Peak memory | 650180 kb |
| Host | smart-ee5704aa-5c98-4f17-a4d1-b362f714b44f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1578010357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.1578010357 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.4074007366 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 3528191422 ps |
| CPU time | 415.78 seconds |
| Started | Jul 09 08:26:07 PM PDT 24 |
| Finished | Jul 09 08:33:05 PM PDT 24 |
| Peak memory | 648840 kb |
| Host | smart-c523e83d-5d8c-40a4-be1c-d73725eb34fb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074007366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4074007366 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.2836746899 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 4842242136 ps |
| CPU time | 587.94 seconds |
| Started | Jul 09 08:20:48 PM PDT 24 |
| Finished | Jul 09 08:30:37 PM PDT 24 |
| Peak memory | 649872 kb |
| Host | smart-7562f8ce-b588-486a-80a2-c9a14f8109cc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2836746899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.2836746899 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2400068370 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 3877645956 ps |
| CPU time | 327.37 seconds |
| Started | Jul 09 08:21:57 PM PDT 24 |
| Finished | Jul 09 08:27:25 PM PDT 24 |
| Peak memory | 649032 kb |
| Host | smart-09d7c559-ec99-4b12-b462-207cb8f1e2fd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400068370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2400068370 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.1398093585 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 5628361032 ps |
| CPU time | 650.41 seconds |
| Started | Jul 09 08:20:00 PM PDT 24 |
| Finished | Jul 09 08:30:51 PM PDT 24 |
| Peak memory | 650384 kb |
| Host | smart-5fa41f53-2666-49c2-80a5-ac207656edd8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1398093585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.1398093585 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.122025592 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 4294704632 ps |
| CPU time | 491.26 seconds |
| Started | Jul 09 08:20:29 PM PDT 24 |
| Finished | Jul 09 08:28:40 PM PDT 24 |
| Peak memory | 649240 kb |
| Host | smart-5fbeb65e-7007-46e3-a7d8-02b331784261 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122025592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_s w_alert_handler_lpg_sleep_mode_alerts.122025592 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.779194377 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 3841198160 ps |
| CPU time | 355.97 seconds |
| Started | Jul 09 08:21:10 PM PDT 24 |
| Finished | Jul 09 08:27:07 PM PDT 24 |
| Peak memory | 648760 kb |
| Host | smart-55df0ffa-8994-4fcd-b1dd-de270856285d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779194377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_s w_alert_handler_lpg_sleep_mode_alerts.779194377 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.3420586300 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 4637380304 ps |
| CPU time | 596.21 seconds |
| Started | Jul 09 08:22:07 PM PDT 24 |
| Finished | Jul 09 08:32:04 PM PDT 24 |
| Peak memory | 649732 kb |
| Host | smart-302258d3-c5fa-4622-8478-8114b148ce46 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3420586300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.3420586300 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.2851532116 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 5248787376 ps |
| CPU time | 611.92 seconds |
| Started | Jul 09 08:21:25 PM PDT 24 |
| Finished | Jul 09 08:31:38 PM PDT 24 |
| Peak memory | 650156 kb |
| Host | smart-15f54f24-8d06-488f-ab1b-d60512556175 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2851532116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.2851532116 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1035304518 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3675746324 ps |
| CPU time | 415.51 seconds |
| Started | Jul 09 08:22:53 PM PDT 24 |
| Finished | Jul 09 08:29:49 PM PDT 24 |
| Peak memory | 648572 kb |
| Host | smart-fdf648b4-767f-48d4-bbdb-1cc0ff3d268e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035304518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1035304518 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1679576947 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 3703299536 ps |
| CPU time | 457.11 seconds |
| Started | Jul 09 08:24:49 PM PDT 24 |
| Finished | Jul 09 08:32:27 PM PDT 24 |
| Peak memory | 649120 kb |
| Host | smart-12983b14-dcf2-4e4f-88b8-1d6a53f613ac |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679576947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1679576947 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.8949208 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 4415080374 ps |
| CPU time | 559.53 seconds |
| Started | Jul 09 08:23:22 PM PDT 24 |
| Finished | Jul 09 08:32:43 PM PDT 24 |
| Peak memory | 649856 kb |
| Host | smart-89dd073a-103b-4330-9dc7-9449978e263d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 8949208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.8949208 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.3084134773 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 4609365078 ps |
| CPU time | 542.67 seconds |
| Started | Jul 09 08:23:20 PM PDT 24 |
| Finished | Jul 09 08:32:23 PM PDT 24 |
| Peak memory | 649884 kb |
| Host | smart-ef0169e9-f7ac-4a78-a1ef-99139f9882ee |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3084134773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.3084134773 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.2507724556 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 5084927552 ps |
| CPU time | 600.33 seconds |
| Started | Jul 09 08:23:57 PM PDT 24 |
| Finished | Jul 09 08:33:58 PM PDT 24 |
| Peak memory | 650232 kb |
| Host | smart-2fd03ac1-909d-4989-b549-1ee36a4ac2b2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2507724556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.2507724556 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.2715952626 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 4695313370 ps |
| CPU time | 550.09 seconds |
| Started | Jul 09 08:22:23 PM PDT 24 |
| Finished | Jul 09 08:31:34 PM PDT 24 |
| Peak memory | 649892 kb |
| Host | smart-c7801682-baeb-4ef5-9b5c-e316bec3824b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2715952626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.2715952626 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.3877227024 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 5567429904 ps |
| CPU time | 575.64 seconds |
| Started | Jul 09 08:25:59 PM PDT 24 |
| Finished | Jul 09 08:35:36 PM PDT 24 |
| Peak memory | 650084 kb |
| Host | smart-a3ba9d67-2230-4401-a32b-ce566a169ed3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3877227024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.3877227024 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.1228399906 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 5755988072 ps |
| CPU time | 528.53 seconds |
| Started | Jul 09 08:26:50 PM PDT 24 |
| Finished | Jul 09 08:35:40 PM PDT 24 |
| Peak memory | 650240 kb |
| Host | smart-6a0974d9-195e-4cb9-bc17-9419e02f5916 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1228399906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.1228399906 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.3140266539 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 5047384708 ps |
| CPU time | 579.67 seconds |
| Started | Jul 09 08:23:39 PM PDT 24 |
| Finished | Jul 09 08:33:19 PM PDT 24 |
| Peak memory | 649912 kb |
| Host | smart-ee64ce2e-67ca-43d9-ad5a-e30e6cda46ea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3140266539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.3140266539 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2860371819 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3838324568 ps |
| CPU time | 357.04 seconds |
| Started | Jul 09 08:23:32 PM PDT 24 |
| Finished | Jul 09 08:29:29 PM PDT 24 |
| Peak memory | 648988 kb |
| Host | smart-e6d36fc3-48e8-49da-b5ad-2c912abd66c9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860371819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2860371819 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.1400703558 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 6002683300 ps |
| CPU time | 537.33 seconds |
| Started | Jul 09 08:23:08 PM PDT 24 |
| Finished | Jul 09 08:32:06 PM PDT 24 |
| Peak memory | 650616 kb |
| Host | smart-043cf45a-2aaa-47a0-b097-e8ef9909964d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1400703558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.1400703558 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.3562752408 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 5801302532 ps |
| CPU time | 570.15 seconds |
| Started | Jul 09 08:23:33 PM PDT 24 |
| Finished | Jul 09 08:33:03 PM PDT 24 |
| Peak memory | 649796 kb |
| Host | smart-dbe9768f-1115-4b5c-a9de-554b393e0bad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3562752408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.3562752408 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.2740714426 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 6078378990 ps |
| CPU time | 653.15 seconds |
| Started | Jul 09 08:25:08 PM PDT 24 |
| Finished | Jul 09 08:36:03 PM PDT 24 |
| Peak memory | 650164 kb |
| Host | smart-95d9dff2-533a-444b-abfd-da78bc099e4c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2740714426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.2740714426 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.2820611436 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 3345900908 ps |
| CPU time | 183.11 seconds |
| Started | Jul 09 07:25:26 PM PDT 24 |
| Finished | Jul 09 07:28:41 PM PDT 24 |
| Peak memory | 599036 kb |
| Host | smart-eaf5485b-6037-4fd0-98ce-5c55e855eedf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820611436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.2820611436 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.815222182 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 3262395105 ps |
| CPU time | 177.67 seconds |
| Started | Jul 09 07:27:47 PM PDT 24 |
| Finished | Jul 09 07:30:52 PM PDT 24 |
| Peak memory | 598928 kb |
| Host | smart-35c4404f-b542-46a2-8abd-e573a04f0707 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815222182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.815222182 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2189987428 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 8523047240 ps |
| CPU time | 2125.8 seconds |
| Started | Jul 09 07:53:16 PM PDT 24 |
| Finished | Jul 09 08:28:43 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-5594feee-298b-4725-87a7-06b5644d97b7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2189987428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2189987428 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.167124308 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 5404986932 ps |
| CPU time | 469.84 seconds |
| Started | Jul 09 07:52:52 PM PDT 24 |
| Finished | Jul 09 08:00:43 PM PDT 24 |
| Peak memory | 611044 kb |
| Host | smart-377f3cb9-0cad-4829-8e8d-70566d6dad4d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=167124308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_sl eep_wake_up.167124308 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.970319957 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 3920588120 ps |
| CPU time | 676.87 seconds |
| Started | Jul 09 07:48:53 PM PDT 24 |
| Finished | Jul 09 08:00:11 PM PDT 24 |
| Peak memory | 622832 kb |
| Host | smart-c39b9da6-6628-4c0f-81d5-97d8b8ebbef4 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970319957 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.970319957 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2389087273 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 4845808072 ps |
| CPU time | 667.67 seconds |
| Started | Jul 09 07:49:21 PM PDT 24 |
| Finished | Jul 09 08:00:30 PM PDT 24 |
| Peak memory | 624292 kb |
| Host | smart-5ef21190-5e2b-4c6f-a044-8fcad66831b7 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389087273 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.2389087273 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.2585496211 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3737683892 ps |
| CPU time | 404.8 seconds |
| Started | Jul 09 07:54:56 PM PDT 24 |
| Finished | Jul 09 08:01:42 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-ab68cff8-7b70-427d-9748-244ce720818a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585496211 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.2585496211 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.2580651554 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 4432297418 ps |
| CPU time | 580.07 seconds |
| Started | Jul 09 08:20:14 PM PDT 24 |
| Finished | Jul 09 08:29:56 PM PDT 24 |
| Peak memory | 611032 kb |
| Host | smart-f11d5fd7-9cbb-424e-b1d2-9cc59f5f6af6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2580651554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.2580651554 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.987456902 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 8445717942 ps |
| CPU time | 604.31 seconds |
| Started | Jul 09 07:50:52 PM PDT 24 |
| Finished | Jul 09 08:00:57 PM PDT 24 |
| Peak memory | 609880 kb |
| Host | smart-fd3e19a3-f70f-4118-b83d-1efc6a6f34e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987456902 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.987456902 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3398752593 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 8640085258 ps |
| CPU time | 760.14 seconds |
| Started | Jul 09 07:51:00 PM PDT 24 |
| Finished | Jul 09 08:03:41 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-2a8b7b1f-207d-4092-8be9-148baa0551ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398752593 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.3398752593 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1573571879 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 50744211200 ps |
| CPU time | 5465.74 seconds |
| Started | Jul 09 07:54:12 PM PDT 24 |
| Finished | Jul 09 09:25:19 PM PDT 24 |
| Peak memory | 620504 kb |
| Host | smart-716938a4-6d58-4ced-abdf-b0f39bc91133 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573571879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_dev.1573571879 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.1909866997 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2871461686 ps |
| CPU time | 287.27 seconds |
| Started | Jul 09 08:14:24 PM PDT 24 |
| Finished | Jul 09 08:19:12 PM PDT 24 |
| Peak memory | 608776 kb |
| Host | smart-c864f4d4-2419-4c27-8f47-15c237115ad8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909866997 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.1909866997 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.3442570432 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1995366446 ps |
| CPU time | 148.77 seconds |
| Started | Jul 09 07:27:11 PM PDT 24 |
| Finished | Jul 09 07:29:43 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-ffdfe9fa-6a07-4d40-87c9-8223fe56c0a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442570432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3442570432 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.476509742 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 4279534963 ps |
| CPU time | 622.16 seconds |
| Started | Jul 09 07:48:49 PM PDT 24 |
| Finished | Jul 09 07:59:12 PM PDT 24 |
| Peak memory | 610480 kb |
| Host | smart-3f2d0439-d737-45b5-8784-1cf2ecab0f26 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=476509742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.476509742 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.700185334 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4164876096 ps |
| CPU time | 450.61 seconds |
| Started | Jul 09 08:05:30 PM PDT 24 |
| Finished | Jul 09 08:13:02 PM PDT 24 |
| Peak memory | 609016 kb |
| Host | smart-3fcb8960-0fd1-46d0-8cfb-5175bdb47945 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700185334 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.chip_sw_gpio.700185334 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1233481871 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 3661109680 ps |
| CPU time | 495.36 seconds |
| Started | Jul 09 08:15:19 PM PDT 24 |
| Finished | Jul 09 08:23:35 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-81b5b250-f0c2-46c1-b3a1-77834e90f153 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233481871 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.1233481871 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2464069166 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 7203541048 ps |
| CPU time | 359.36 seconds |
| Started | Jul 09 07:25:21 PM PDT 24 |
| Finished | Jul 09 07:31:30 PM PDT 24 |
| Peak memory | 661644 kb |
| Host | smart-f84a5425-ebb6-4ca3-8dea-96c0d2ff13bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464069166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.2464069166 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3211757773 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 17940154820 ps |
| CPU time | 581.22 seconds |
| Started | Jul 09 07:50:53 PM PDT 24 |
| Finished | Jul 09 08:00:35 PM PDT 24 |
| Peak memory | 619128 kb |
| Host | smart-0c6749fe-5283-4f90-bc52-01ccc0484217 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3211757773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3211757773 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1258061918 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3034258574 ps |
| CPU time | 289.86 seconds |
| Started | Jul 09 07:48:54 PM PDT 24 |
| Finished | Jul 09 07:53:46 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-0b5bf836-790f-45e0-bf15-8d4fd49ad4e7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258061918 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.1258061918 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.2559596932 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 2454782894 ps |
| CPU time | 227.88 seconds |
| Started | Jul 09 07:51:28 PM PDT 24 |
| Finished | Jul 09 07:55:17 PM PDT 24 |
| Peak memory | 609528 kb |
| Host | smart-77e03762-8fc2-425b-b2b0-fceb4c7bf283 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559596932 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.2559596932 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4138270095 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 121383914848 ps |
| CPU time | 16799.3 seconds |
| Started | Jul 09 07:51:15 PM PDT 24 |
| Finished | Jul 10 12:31:18 AM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-73e157de-8415-41ae-9b27-dc4fd7ebf61a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4138270095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.4138270095 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1895375088 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 5540077804 ps |
| CPU time | 474.69 seconds |
| Started | Jul 09 07:51:55 PM PDT 24 |
| Finished | Jul 09 07:59:50 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-d73a6733-8913-4add-9f30-698802c66811 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1895375088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.1895375088 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1038834828 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 36686477465 ps |
| CPU time | 7021.08 seconds |
| Started | Jul 09 07:25:05 PM PDT 24 |
| Finished | Jul 09 09:22:09 PM PDT 24 |
| Peak memory | 594340 kb |
| Host | smart-2d267fe0-be7e-48fd-a715-9d12da751bcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038834828 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.chip_csr_aliasing.1038834828 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.76194087 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 4453129560 ps |
| CPU time | 328.42 seconds |
| Started | Jul 09 07:25:21 PM PDT 24 |
| Finished | Jul 09 07:30:57 PM PDT 24 |
| Peak memory | 597096 kb |
| Host | smart-1a57a423-dc3e-4862-b6e9-f4e00e3c0a4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76194087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.76194087 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.612181643 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 1087807675 ps |
| CPU time | 249.9 seconds |
| Started | Jul 09 07:25:22 PM PDT 24 |
| Finished | Jul 09 07:29:42 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-fb683c3f-22f3-48ea-88e5-1f9bbe98b396 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612181643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_reset_error.612181643 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.4037966684 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 15789323230 ps |
| CPU time | 561.91 seconds |
| Started | Jul 09 07:29:02 PM PDT 24 |
| Finished | Jul 09 07:38:34 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-8fde9eba-c044-4d95-a6d7-49bca6988a78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037966684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.4037966684 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.821921012 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 10550462181 ps |
| CPU time | 341.8 seconds |
| Started | Jul 09 07:31:30 PM PDT 24 |
| Finished | Jul 09 07:37:14 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-755f37d6-2c9f-4c4e-b415-6c1b9587d2eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821921012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.821921012 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.834027933 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1885632791 ps |
| CPU time | 143.7 seconds |
| Started | Jul 09 07:35:30 PM PDT 24 |
| Finished | Jul 09 07:37:55 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-4e444288-61fd-43d8-9afc-a5edb7b31bda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834027933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.834027933 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.1250332163 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 5508212801 ps |
| CPU time | 189.76 seconds |
| Started | Jul 09 07:37:37 PM PDT 24 |
| Finished | Jul 09 07:40:48 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-6f71b612-0d4b-46b3-af3c-9692d75144f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250332163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.1250332163 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.3794379953 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 808850565 ps |
| CPU time | 30.84 seconds |
| Started | Jul 09 07:39:55 PM PDT 24 |
| Finished | Jul 09 07:40:27 PM PDT 24 |
| Peak memory | 576484 kb |
| Host | smart-fbca1066-2392-489f-8a0c-ee04bc816caf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794379953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.3794379953 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.3205908505 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2504401951 ps |
| CPU time | 173.78 seconds |
| Started | Jul 09 07:41:03 PM PDT 24 |
| Finished | Jul 09 07:43:58 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-4d9e5f40-5987-4457-b24e-4be9bf267ebc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205908505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.3205908505 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3615900740 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 7405334892 ps |
| CPU time | 528.27 seconds |
| Started | Jul 09 07:50:38 PM PDT 24 |
| Finished | Jul 09 07:59:27 PM PDT 24 |
| Peak memory | 610764 kb |
| Host | smart-b5aeb907-8d46-469c-a3f7-c1574582f5f5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615900740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3615900740 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.2032675233 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 2773200260 ps |
| CPU time | 342.2 seconds |
| Started | Jul 09 07:53:25 PM PDT 24 |
| Finished | Jul 09 07:59:09 PM PDT 24 |
| Peak memory | 610496 kb |
| Host | smart-34066061-157d-4235-8bd8-69ff0bc71d03 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032675233 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.2032675233 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.1933360986 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 4131450720 ps |
| CPU time | 314.67 seconds |
| Started | Jul 09 08:00:18 PM PDT 24 |
| Finished | Jul 09 08:05:34 PM PDT 24 |
| Peak memory | 621312 kb |
| Host | smart-48e8ce7c-08e6-40c0-9385-f8015f8019ce |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933360986 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.1933360986 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.344703005 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 1849695600 ps |
| CPU time | 131.95 seconds |
| Started | Jul 09 08:16:44 PM PDT 24 |
| Finished | Jul 09 08:18:57 PM PDT 24 |
| Peak memory | 642164 kb |
| Host | smart-5e96ab69-62a5-4f70-94b5-5ff537d6166f |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344703005 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.344703005 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.3073041584 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 3383926706 ps |
| CPU time | 199.27 seconds |
| Started | Jul 09 07:50:12 PM PDT 24 |
| Finished | Jul 09 07:53:32 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-8121c681-dffb-4fdb-a04a-a010d3c3e7fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073041584 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.3073041584 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.4095317804 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 4818551520 ps |
| CPU time | 226.62 seconds |
| Started | Jul 09 07:25:22 PM PDT 24 |
| Finished | Jul 09 07:29:18 PM PDT 24 |
| Peak memory | 664056 kb |
| Host | smart-8976b7d6-a6c0-443f-9576-ad26bc66d246 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095317804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.4095317804 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.734516801 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 2966309966 ps |
| CPU time | 565.09 seconds |
| Started | Jul 09 07:53:59 PM PDT 24 |
| Finished | Jul 09 08:03:24 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-5e131197-945f-4a2d-8f6c-b999b9fdbcef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734516801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_b oot_mode.734516801 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2087504505 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 6641614730 ps |
| CPU time | 1558.88 seconds |
| Started | Jul 09 07:53:22 PM PDT 24 |
| Finished | Jul 09 08:19:22 PM PDT 24 |
| Peak memory | 611028 kb |
| Host | smart-a67e0aa7-7bc1-49ef-bab5-a67a6eaec1e2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2087504505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.2087504505 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2050460524 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 17670098290 ps |
| CPU time | 4655 seconds |
| Started | Jul 09 07:54:21 PM PDT 24 |
| Finished | Jul 09 09:11:58 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-af9e1e63-15b2-4cd4-bc95-64bf78d30029 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20504 60524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2050460524 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1690154143 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 2770274909 ps |
| CPU time | 275.82 seconds |
| Started | Jul 09 07:49:15 PM PDT 24 |
| Finished | Jul 09 07:53:52 PM PDT 24 |
| Peak memory | 621668 kb |
| Host | smart-e21239b9-c529-4a70-a8e9-6688f62584ab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690154143 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.1690154143 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3887101476 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 23373119744 ps |
| CPU time | 7496.18 seconds |
| Started | Jul 09 07:58:22 PM PDT 24 |
| Finished | Jul 09 10:03:20 PM PDT 24 |
| Peak memory | 609716 kb |
| Host | smart-7181ee6d-17e9-4de1-8ecf-2c3e282da8c6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3887101476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3887101476 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2557314142 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 4239433222 ps |
| CPU time | 385.43 seconds |
| Started | Jul 09 07:25:15 PM PDT 24 |
| Finished | Jul 09 07:31:43 PM PDT 24 |
| Peak memory | 591288 kb |
| Host | smart-ba445a9f-c3f9-48b8-ac44-b58464d44a19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557314142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.2557314142 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.1021271236 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 4379829472 ps |
| CPU time | 357.05 seconds |
| Started | Jul 09 07:25:18 PM PDT 24 |
| Finished | Jul 09 07:31:20 PM PDT 24 |
| Peak memory | 599324 kb |
| Host | smart-6e364621-4018-4d26-958b-c2da7da8d0cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021271236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.1021271236 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3305212857 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 8409331032 ps |
| CPU time | 412.02 seconds |
| Started | Jul 09 07:25:17 PM PDT 24 |
| Finished | Jul 09 07:32:12 PM PDT 24 |
| Peak memory | 590644 kb |
| Host | smart-fbc9b07a-79db-4ab2-a3fb-786663df595c |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305212857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.3305212857 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2647226941 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 9865377552 ps |
| CPU time | 330.91 seconds |
| Started | Jul 09 07:25:14 PM PDT 24 |
| Finished | Jul 09 07:30:47 PM PDT 24 |
| Peak memory | 591552 kb |
| Host | smart-9d50ce71-d6a3-4696-be2b-5e515d188eb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647226941 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.2647226941 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3225409504 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 16121321491 ps |
| CPU time | 1692.02 seconds |
| Started | Jul 09 07:25:27 PM PDT 24 |
| Finished | Jul 09 07:53:51 PM PDT 24 |
| Peak memory | 593112 kb |
| Host | smart-92a6c8f1-b89e-4c21-8645-babd48d4b3b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225409504 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.3225409504 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.3045081387 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 3460749616 ps |
| CPU time | 232 seconds |
| Started | Jul 09 07:25:08 PM PDT 24 |
| Finished | Jul 09 07:29:01 PM PDT 24 |
| Peak memory | 598904 kb |
| Host | smart-1c51f959-539d-42b7-9486-dd27b7c90392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045081387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.3045081387 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.2106719754 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 1805163622 ps |
| CPU time | 76.32 seconds |
| Started | Jul 09 07:25:20 PM PDT 24 |
| Finished | Jul 09 07:26:42 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-90037f04-ed27-40b3-8369-80b9907f626c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106719754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 2106719754 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2815989580 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 15583828032 ps |
| CPU time | 273.64 seconds |
| Started | Jul 09 07:25:27 PM PDT 24 |
| Finished | Jul 09 07:30:12 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-d99a9a7b-40b1-4019-ad90-763bb5a89c61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815989580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.2815989580 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.703575127 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 1579765709 ps |
| CPU time | 68.96 seconds |
| Started | Jul 09 07:25:16 PM PDT 24 |
| Finished | Jul 09 07:26:29 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-8cdddd7d-2f8c-4f97-a310-52e842f5090c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703575127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr. 703575127 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.279705980 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 2088667911 ps |
| CPU time | 71.47 seconds |
| Started | Jul 09 07:25:21 PM PDT 24 |
| Finished | Jul 09 07:26:41 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-e386bc88-1d56-45d7-8a4a-4cc2334c7076 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279705980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.279705980 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.3756517362 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 519512637 ps |
| CPU time | 43.55 seconds |
| Started | Jul 09 07:25:20 PM PDT 24 |
| Finished | Jul 09 07:26:09 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-c4e97c5f-c364-4a75-ad66-83f67b6c6606 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756517362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.3756517362 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.484028859 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 10781352032 ps |
| CPU time | 110.91 seconds |
| Started | Jul 09 07:25:20 PM PDT 24 |
| Finished | Jul 09 07:27:16 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-86ba5a28-2326-499b-aab3-32d451418846 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484028859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.484028859 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.4103074381 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 64222704078 ps |
| CPU time | 1124.37 seconds |
| Started | Jul 09 07:25:22 PM PDT 24 |
| Finished | Jul 09 07:44:16 PM PDT 24 |
| Peak memory | 576464 kb |
| Host | smart-6dc6114b-070d-4f3c-a1c6-eccf8106aeb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103074381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.4103074381 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1084924606 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 377274408 ps |
| CPU time | 38.97 seconds |
| Started | Jul 09 07:25:15 PM PDT 24 |
| Finished | Jul 09 07:25:57 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-b221d876-509a-4604-9a65-ef00ae038333 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084924606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.1084924606 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.2299289923 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1298323156 ps |
| CPU time | 40.12 seconds |
| Started | Jul 09 07:25:25 PM PDT 24 |
| Finished | Jul 09 07:26:16 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-f966195b-3370-49bf-8e20-9f77db1b6234 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299289923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2299289923 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.3912309597 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 50214481 ps |
| CPU time | 6.46 seconds |
| Started | Jul 09 07:25:15 PM PDT 24 |
| Finished | Jul 09 07:25:24 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-d5892f10-4fb7-4bdb-8fd1-c20fa9591431 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912309597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3912309597 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.156558573 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 8141245127 ps |
| CPU time | 83.76 seconds |
| Started | Jul 09 07:25:11 PM PDT 24 |
| Finished | Jul 09 07:26:35 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-e5655ea1-4b85-4f65-aca0-d2edf42810e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156558573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.156558573 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1793765716 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 5153083601 ps |
| CPU time | 89.27 seconds |
| Started | Jul 09 07:25:19 PM PDT 24 |
| Finished | Jul 09 07:26:55 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-9d22f513-c083-4da1-9261-b40f3c7f0b4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793765716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1793765716 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1991138436 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 50182946 ps |
| CPU time | 6.48 seconds |
| Started | Jul 09 07:25:07 PM PDT 24 |
| Finished | Jul 09 07:25:15 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-2b551ca8-888c-41ee-aead-bb0a73cb5fae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991138436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .1991138436 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.1590838546 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 687255653 ps |
| CPU time | 58.45 seconds |
| Started | Jul 09 07:25:23 PM PDT 24 |
| Finished | Jul 09 07:26:32 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-5b97bb42-73dd-4a8d-93f5-cb4c3406d627 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590838546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1590838546 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1911842101 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 15942597719 ps |
| CPU time | 489.79 seconds |
| Started | Jul 09 07:25:17 PM PDT 24 |
| Finished | Jul 09 07:33:30 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-5657a188-59ad-4012-b9cc-a6cf9378499e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911842101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1911842101 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3444931119 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 2299547157 ps |
| CPU time | 330.7 seconds |
| Started | Jul 09 07:25:16 PM PDT 24 |
| Finished | Jul 09 07:30:51 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-0c4ee803-c37f-44b5-bb5a-086cc2cc3f7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444931119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.3444931119 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3457147247 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 3754769582 ps |
| CPU time | 306.91 seconds |
| Started | Jul 09 07:25:26 PM PDT 24 |
| Finished | Jul 09 07:30:44 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-5c301beb-8a47-4f6a-b14f-663c577daceb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457147247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.3457147247 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.808581556 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 739444197 ps |
| CPU time | 32.43 seconds |
| Started | Jul 09 07:25:18 PM PDT 24 |
| Finished | Jul 09 07:25:55 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-266518c2-1550-4808-ad2e-481e7a9ffb8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808581556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.808581556 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1664620789 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 51698793978 ps |
| CPU time | 9988.32 seconds |
| Started | Jul 09 07:25:17 PM PDT 24 |
| Finished | Jul 09 10:11:50 PM PDT 24 |
| Peak memory | 631984 kb |
| Host | smart-b89cd503-a884-4bdb-89bf-bb2cf716cf87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664620789 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.1664620789 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3425826112 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 45948275368 ps |
| CPU time | 5367.74 seconds |
| Started | Jul 09 07:25:22 PM PDT 24 |
| Finished | Jul 09 08:55:00 PM PDT 24 |
| Peak memory | 592828 kb |
| Host | smart-1e282de7-0561-4bd5-83b8-0471d6c52c88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425826112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.3425826112 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3900465649 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 7824874440 ps |
| CPU time | 295.12 seconds |
| Started | Jul 09 07:25:21 PM PDT 24 |
| Finished | Jul 09 07:30:25 PM PDT 24 |
| Peak memory | 589984 kb |
| Host | smart-f37d2451-bce8-482e-9f06-b53a4ed6c737 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900465649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.3900465649 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3012152847 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 17062681112 ps |
| CPU time | 761.47 seconds |
| Started | Jul 09 07:25:15 PM PDT 24 |
| Finished | Jul 09 07:38:00 PM PDT 24 |
| Peak memory | 592580 kb |
| Host | smart-b14b1cd4-dc85-4e25-b5ba-60c11c2052c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012152847 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.3012152847 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.1801916746 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 508879419 ps |
| CPU time | 36.89 seconds |
| Started | Jul 09 07:25:31 PM PDT 24 |
| Finished | Jul 09 07:26:20 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-7f72e030-c751-439c-a274-8dc2ea3b485c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801916746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 1801916746 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3586357438 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 36568069736 ps |
| CPU time | 605.62 seconds |
| Started | Jul 09 07:25:18 PM PDT 24 |
| Finished | Jul 09 07:35:27 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-11f05865-b79d-4be2-9a73-d426ae8c9055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586357438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.3586357438 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3673261897 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 57587956 ps |
| CPU time | 8.31 seconds |
| Started | Jul 09 07:25:23 PM PDT 24 |
| Finished | Jul 09 07:25:42 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-824b5d20-2b30-4e9d-a905-2b27bee9af0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673261897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .3673261897 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.2362835901 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 1528442439 ps |
| CPU time | 60.18 seconds |
| Started | Jul 09 07:25:19 PM PDT 24 |
| Finished | Jul 09 07:26:26 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-b9445286-7bfb-42bb-a8b2-5ce21561d851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362835901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2362835901 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.3477779880 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 115093636 ps |
| CPU time | 12.41 seconds |
| Started | Jul 09 07:25:16 PM PDT 24 |
| Finished | Jul 09 07:25:31 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-9d5c9211-02cd-453d-ad6f-eb91bda577b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477779880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.3477779880 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.4234845318 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 95276076310 ps |
| CPU time | 994.2 seconds |
| Started | Jul 09 07:25:23 PM PDT 24 |
| Finished | Jul 09 07:42:07 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-c10621b0-3088-4ad1-ad82-12b29f971e86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234845318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.4234845318 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3351465613 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 39854400938 ps |
| CPU time | 669.73 seconds |
| Started | Jul 09 07:25:27 PM PDT 24 |
| Finished | Jul 09 07:36:49 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-851ea43c-4d21-43d9-8b3d-63e5f43c4553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351465613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3351465613 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3270542924 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 86616564 ps |
| CPU time | 10.83 seconds |
| Started | Jul 09 07:25:20 PM PDT 24 |
| Finished | Jul 09 07:25:39 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-40916225-2d4e-48d0-bc51-333461329a7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270542924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.3270542924 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.4205648400 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 513423725 ps |
| CPU time | 36.46 seconds |
| Started | Jul 09 07:25:19 PM PDT 24 |
| Finished | Jul 09 07:26:02 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-bd598025-b577-48db-a451-959a72b4d871 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205648400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.4205648400 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.1837260342 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 42288032 ps |
| CPU time | 5.56 seconds |
| Started | Jul 09 07:25:19 PM PDT 24 |
| Finished | Jul 09 07:25:29 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-d2626e7a-1c44-4cef-bc8e-27a065960642 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837260342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1837260342 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3674177565 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 9951241361 ps |
| CPU time | 106.49 seconds |
| Started | Jul 09 07:25:28 PM PDT 24 |
| Finished | Jul 09 07:27:25 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-f1997225-ce95-4ae0-b235-2e20ca01e053 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674177565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3674177565 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2223088838 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 5266683845 ps |
| CPU time | 93.02 seconds |
| Started | Jul 09 07:25:19 PM PDT 24 |
| Finished | Jul 09 07:26:58 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-e0b55c54-c5a1-40e8-a82c-b0971898541f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223088838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2223088838 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.240634671 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 42886379 ps |
| CPU time | 5.66 seconds |
| Started | Jul 09 07:25:27 PM PDT 24 |
| Finished | Jul 09 07:25:44 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-ce438a2c-fc60-4fc5-926e-47ded9daf0aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240634671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays. 240634671 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.3445509840 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 3121798833 ps |
| CPU time | 137.43 seconds |
| Started | Jul 09 07:25:18 PM PDT 24 |
| Finished | Jul 09 07:27:40 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-a6762047-0654-4c8e-b2da-f0b1e7ce98cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445509840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3445509840 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1943870341 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 213185910 ps |
| CPU time | 23.63 seconds |
| Started | Jul 09 07:25:22 PM PDT 24 |
| Finished | Jul 09 07:25:55 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-4fbda4ff-9b8a-4f17-b5d4-7d97fbf4b07a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943870341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1943870341 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.1534957737 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 5577986354 ps |
| CPU time | 555.13 seconds |
| Started | Jul 09 07:26:04 PM PDT 24 |
| Finished | Jul 09 07:35:42 PM PDT 24 |
| Peak memory | 597688 kb |
| Host | smart-cf355e55-f6d8-4f6f-bc61-5cc1bb5bde9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534957737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.1534957737 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3851574534 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 28329155858 ps |
| CPU time | 5178.1 seconds |
| Started | Jul 09 07:25:53 PM PDT 24 |
| Finished | Jul 09 08:52:32 PM PDT 24 |
| Peak memory | 593416 kb |
| Host | smart-36987a6a-51cf-4e4f-8bfa-1e1d414d253e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851574534 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.3851574534 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.437413849 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 174015853 ps |
| CPU time | 15.87 seconds |
| Started | Jul 09 07:26:00 PM PDT 24 |
| Finished | Jul 09 07:26:36 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-e5374d11-efb1-49f2-ab2a-3e6d9bf59e76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437413849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device. 437413849 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.649411708 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 50555469974 ps |
| CPU time | 878.47 seconds |
| Started | Jul 09 07:26:09 PM PDT 24 |
| Finished | Jul 09 07:41:09 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-35358881-e402-47f8-9b55-eb8ded493c94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649411708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_d evice_slow_rsp.649411708 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3612260755 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 372391447 ps |
| CPU time | 17.71 seconds |
| Started | Jul 09 07:26:08 PM PDT 24 |
| Finished | Jul 09 07:26:49 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-298e27ce-9dba-46d5-ae14-960ae2392a15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612260755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.3612260755 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.2022916242 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 502477835 ps |
| CPU time | 38.7 seconds |
| Started | Jul 09 07:26:01 PM PDT 24 |
| Finished | Jul 09 07:27:00 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-2bbda779-53a7-4912-926a-7330bf4d2bd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022916242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2022916242 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.1717818378 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 1456961349 ps |
| CPU time | 48.42 seconds |
| Started | Jul 09 07:26:06 PM PDT 24 |
| Finished | Jul 09 07:27:18 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-1ffcd88b-17fe-448a-97e2-bcaa221f5792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717818378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.1717818378 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.695081673 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 77827303001 ps |
| CPU time | 791.48 seconds |
| Started | Jul 09 07:26:09 PM PDT 24 |
| Finished | Jul 09 07:39:42 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-f869379f-6a7e-4d68-9164-edc8b3400cc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695081673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.695081673 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2795223232 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 2873713001 ps |
| CPU time | 48.86 seconds |
| Started | Jul 09 07:26:00 PM PDT 24 |
| Finished | Jul 09 07:27:10 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-97fbe3d5-6f1c-4b87-a9e2-3ecaba38f2e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795223232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.2795223232 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.955955090 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 643921719 ps |
| CPU time | 58.47 seconds |
| Started | Jul 09 07:26:00 PM PDT 24 |
| Finished | Jul 09 07:27:19 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-7f85c4e4-c59c-4c48-8218-9e97ecdf4397 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955955090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_dela ys.955955090 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.2929560719 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 225862496 ps |
| CPU time | 9.16 seconds |
| Started | Jul 09 07:25:53 PM PDT 24 |
| Finished | Jul 09 07:26:22 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-9b0e0366-20df-481a-98d4-f9acaaee832c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929560719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2929560719 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1001052856 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 6064276433 ps |
| CPU time | 62.2 seconds |
| Started | Jul 09 07:25:53 PM PDT 24 |
| Finished | Jul 09 07:27:15 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-e10e5646-f70c-4999-8306-79137b45f573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001052856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1001052856 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1407846861 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 3594076908 ps |
| CPU time | 61 seconds |
| Started | Jul 09 07:26:09 PM PDT 24 |
| Finished | Jul 09 07:27:32 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-b6d039cb-898c-45ff-8f45-f1b19c138ad5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407846861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1407846861 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1141391073 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 39029137 ps |
| CPU time | 5.77 seconds |
| Started | Jul 09 07:25:51 PM PDT 24 |
| Finished | Jul 09 07:26:16 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-42f75d0f-7fc1-412b-83c5-dd0854348b17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141391073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.1141391073 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.2894457237 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 73665667 ps |
| CPU time | 8.87 seconds |
| Started | Jul 09 07:25:57 PM PDT 24 |
| Finished | Jul 09 07:26:28 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-19f87831-8a83-4d9f-8bc6-cd9008aec0d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894457237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2894457237 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3510573336 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 907318074 ps |
| CPU time | 89.52 seconds |
| Started | Jul 09 07:26:05 PM PDT 24 |
| Finished | Jul 09 07:27:56 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-6ff17229-fb71-46e2-ae95-defbe7c95b90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510573336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3510573336 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.645123758 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 93648803 ps |
| CPU time | 18.1 seconds |
| Started | Jul 09 07:26:10 PM PDT 24 |
| Finished | Jul 09 07:26:49 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-fc11fee8-3a92-4cad-82b7-18429514bff0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645123758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_ with_rand_reset.645123758 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3774358767 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 212078750 ps |
| CPU time | 22.39 seconds |
| Started | Jul 09 07:26:10 PM PDT 24 |
| Finished | Jul 09 07:26:54 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-a4772620-32d1-4398-9aeb-b4efacea2b30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774358767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3774358767 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.3040871568 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 4319068649 ps |
| CPU time | 315.92 seconds |
| Started | Jul 09 07:26:09 PM PDT 24 |
| Finished | Jul 09 07:31:47 PM PDT 24 |
| Peak memory | 597496 kb |
| Host | smart-93c7ee7f-d324-49e7-a0d8-e1387065bddb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040871568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.3040871568 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.2737860266 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 285640375 ps |
| CPU time | 11.41 seconds |
| Started | Jul 09 07:26:03 PM PDT 24 |
| Finished | Jul 09 07:26:37 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-9eded867-592f-493d-a177-df1f15e8912d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737860266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .2737860266 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3370592565 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 136568293081 ps |
| CPU time | 2314.67 seconds |
| Started | Jul 09 07:26:03 PM PDT 24 |
| Finished | Jul 09 08:05:00 PM PDT 24 |
| Peak memory | 576848 kb |
| Host | smart-9500575c-7dd6-43c2-bc83-0650bcec6690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370592565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.3370592565 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2782418277 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 1196539601 ps |
| CPU time | 49.3 seconds |
| Started | Jul 09 07:26:06 PM PDT 24 |
| Finished | Jul 09 07:27:18 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-48b9a3bf-5d98-428c-a915-d8d02ac63b87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782418277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.2782418277 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.2860971383 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 455047847 ps |
| CPU time | 38.86 seconds |
| Started | Jul 09 07:26:00 PM PDT 24 |
| Finished | Jul 09 07:26:59 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-6901d43d-2330-4051-93e1-847c27e7ad1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860971383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2860971383 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.674198890 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 127753549 ps |
| CPU time | 7.71 seconds |
| Started | Jul 09 07:26:05 PM PDT 24 |
| Finished | Jul 09 07:26:34 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-00d334a5-cf76-4562-82e5-ee70963eb82f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674198890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.674198890 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3907223881 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 6182986056 ps |
| CPU time | 66.74 seconds |
| Started | Jul 09 07:26:01 PM PDT 24 |
| Finished | Jul 09 07:27:30 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-6da7ba61-6c60-4f4c-8f43-fb96e8b49f3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907223881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3907223881 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3203027502 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 27092729824 ps |
| CPU time | 492.09 seconds |
| Started | Jul 09 07:26:04 PM PDT 24 |
| Finished | Jul 09 07:34:39 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-c385031d-78e7-444a-9b97-655a65e8d285 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203027502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3203027502 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3869184574 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 212561020 ps |
| CPU time | 18.03 seconds |
| Started | Jul 09 07:26:09 PM PDT 24 |
| Finished | Jul 09 07:26:49 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-6fe498cd-3fb0-4430-8461-086adb13c447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869184574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.3869184574 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.2940966398 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 238323332 ps |
| CPU time | 20 seconds |
| Started | Jul 09 07:26:04 PM PDT 24 |
| Finished | Jul 09 07:26:47 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-d7a4af07-a62d-4543-ab16-f065d6e251ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940966398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2940966398 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.1939730668 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 208666628 ps |
| CPU time | 9.68 seconds |
| Started | Jul 09 07:26:03 PM PDT 24 |
| Finished | Jul 09 07:26:34 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-a94e9548-c0b7-44ef-98d1-d5b025eb678b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939730668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1939730668 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1163460553 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 7539427599 ps |
| CPU time | 80.82 seconds |
| Started | Jul 09 07:26:02 PM PDT 24 |
| Finished | Jul 09 07:27:44 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-d9ab0f10-563a-4f94-be98-2ea3206d0691 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163460553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1163460553 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.4086052929 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 4888173459 ps |
| CPU time | 81.55 seconds |
| Started | Jul 09 07:26:02 PM PDT 24 |
| Finished | Jul 09 07:27:46 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-afe35cd5-8c90-4c8a-ab8d-aff0a26847cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086052929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.4086052929 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.4288264341 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 42807427 ps |
| CPU time | 6.25 seconds |
| Started | Jul 09 07:26:05 PM PDT 24 |
| Finished | Jul 09 07:26:33 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-ea9f3281-a7fe-4fa6-aa88-17e551882a7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288264341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.4288264341 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.74116858 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 2521443847 ps |
| CPU time | 95.76 seconds |
| Started | Jul 09 07:26:06 PM PDT 24 |
| Finished | Jul 09 07:28:05 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-b0695e07-33fa-4614-b887-42a0d75bf57f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74116858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.74116858 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3309659608 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 18710564428 ps |
| CPU time | 663.7 seconds |
| Started | Jul 09 07:26:03 PM PDT 24 |
| Finished | Jul 09 07:37:29 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-91eb059a-9b91-4f2c-999c-7842c807eb8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309659608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3309659608 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2733865836 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 2507087041 ps |
| CPU time | 389.78 seconds |
| Started | Jul 09 07:25:59 PM PDT 24 |
| Finished | Jul 09 07:32:50 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-75b6c13c-6e78-40d2-9501-5b025bdcda73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733865836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.2733865836 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.485689586 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 191531361 ps |
| CPU time | 84.98 seconds |
| Started | Jul 09 07:26:01 PM PDT 24 |
| Finished | Jul 09 07:27:48 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-37d2f80b-eeaf-48d5-bf02-ac865fa49224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485689586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_reset_error.485689586 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.785925736 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 594417964 ps |
| CPU time | 29.14 seconds |
| Started | Jul 09 07:26:04 PM PDT 24 |
| Finished | Jul 09 07:26:56 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-9ca8ad3e-7864-4a54-bf77-7c7ba6b7257c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785925736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.785925736 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.2706197060 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 6048115554 ps |
| CPU time | 744.88 seconds |
| Started | Jul 09 07:26:27 PM PDT 24 |
| Finished | Jul 09 07:39:09 PM PDT 24 |
| Peak memory | 598492 kb |
| Host | smart-66d59c15-7ccc-490f-b8a3-ac6e45d33ab9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706197060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.2706197060 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1369874350 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 13812937628 ps |
| CPU time | 1757.5 seconds |
| Started | Jul 09 07:26:09 PM PDT 24 |
| Finished | Jul 09 07:55:48 PM PDT 24 |
| Peak memory | 593568 kb |
| Host | smart-6ad43892-825c-4724-ab09-013c111e81d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369874350 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.1369874350 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.830626098 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 3474730950 ps |
| CPU time | 202.46 seconds |
| Started | Jul 09 07:26:06 PM PDT 24 |
| Finished | Jul 09 07:29:52 PM PDT 24 |
| Peak memory | 603932 kb |
| Host | smart-da58322d-1dd1-493c-abaa-a3951cf7fd59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830626098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.830626098 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.3510023345 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 1162548034 ps |
| CPU time | 55.06 seconds |
| Started | Jul 09 07:26:22 PM PDT 24 |
| Finished | Jul 09 07:27:36 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-2ea41d94-33d3-47b8-96e8-e63d5f782445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510023345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .3510023345 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1015361280 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 31089365408 ps |
| CPU time | 555.7 seconds |
| Started | Jul 09 07:26:20 PM PDT 24 |
| Finished | Jul 09 07:35:55 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-9db24116-37f8-4468-b6a9-9a48fcbc50e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015361280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.1015361280 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2136771032 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 1057156995 ps |
| CPU time | 40.68 seconds |
| Started | Jul 09 07:26:24 PM PDT 24 |
| Finished | Jul 09 07:27:22 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-1f180422-1698-4cb2-a262-9103a6ea753d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136771032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.2136771032 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.1365968343 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 116488892 ps |
| CPU time | 7.38 seconds |
| Started | Jul 09 07:26:19 PM PDT 24 |
| Finished | Jul 09 07:26:46 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-b43f1ff5-6139-4899-8491-aab26884f312 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365968343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1365968343 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.3910286099 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 77437111 ps |
| CPU time | 9.72 seconds |
| Started | Jul 09 07:26:08 PM PDT 24 |
| Finished | Jul 09 07:26:41 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-dbfaed80-c477-4804-975b-f86a0716cf90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910286099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.3910286099 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1506244480 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 7366594073 ps |
| CPU time | 72.79 seconds |
| Started | Jul 09 07:26:11 PM PDT 24 |
| Finished | Jul 09 07:27:45 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-96126fa0-9c7f-4e09-8813-01e8ab82d7db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506244480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1506244480 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.381441077 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 68797945573 ps |
| CPU time | 1116.31 seconds |
| Started | Jul 09 07:26:14 PM PDT 24 |
| Finished | Jul 09 07:45:11 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-ef3eb671-496b-4484-a4b3-0225788d6f67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381441077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.381441077 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1037724278 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 591310835 ps |
| CPU time | 49.63 seconds |
| Started | Jul 09 07:26:11 PM PDT 24 |
| Finished | Jul 09 07:27:22 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-2f169786-ff05-4665-bd09-8c3948b64409 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037724278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.1037724278 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.3216939211 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 352936759 ps |
| CPU time | 26.92 seconds |
| Started | Jul 09 07:26:24 PM PDT 24 |
| Finished | Jul 09 07:27:09 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-01667ca7-5ff5-40b7-9f6e-776e6fbe311c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216939211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3216939211 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.592441172 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 174128292 ps |
| CPU time | 8 seconds |
| Started | Jul 09 07:26:07 PM PDT 24 |
| Finished | Jul 09 07:26:37 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-13d4ba24-a7a9-46ed-afd6-564f0f2a0499 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592441172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.592441172 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1297217483 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 4661725812 ps |
| CPU time | 50.23 seconds |
| Started | Jul 09 07:26:10 PM PDT 24 |
| Finished | Jul 09 07:27:21 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-2f64e1ac-3515-492b-bc53-76e19a0bb1c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297217483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1297217483 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1301526768 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 4734068558 ps |
| CPU time | 82.44 seconds |
| Started | Jul 09 07:26:06 PM PDT 24 |
| Finished | Jul 09 07:27:51 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-c7fbc5fb-cda2-483b-9e1a-c977c5914895 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301526768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1301526768 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2706315763 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 46844355 ps |
| CPU time | 5.93 seconds |
| Started | Jul 09 07:26:06 PM PDT 24 |
| Finished | Jul 09 07:26:35 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-6dc756da-f9fa-47b1-bb18-bf8023103feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706315763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.2706315763 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.2830861012 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 2970784634 ps |
| CPU time | 102.64 seconds |
| Started | Jul 09 07:26:27 PM PDT 24 |
| Finished | Jul 09 07:28:27 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-44951381-449c-4581-b463-f4c73f43871a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830861012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2830861012 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.4202899826 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 16964960836 ps |
| CPU time | 596.57 seconds |
| Started | Jul 09 07:26:32 PM PDT 24 |
| Finished | Jul 09 07:36:43 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-248e0e7f-8683-4222-a807-c9e84b29edca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202899826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.4202899826 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3129584172 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 42164236 ps |
| CPU time | 20.54 seconds |
| Started | Jul 09 07:26:27 PM PDT 24 |
| Finished | Jul 09 07:27:04 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-cd6928b3-a627-4d54-99df-6cf2c2944003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129584172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.3129584172 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3902602120 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 52376085 ps |
| CPU time | 9.01 seconds |
| Started | Jul 09 07:26:22 PM PDT 24 |
| Finished | Jul 09 07:26:49 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-cdf39f58-c120-4410-aa25-97509c1bad44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902602120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3902602120 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.364939281 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 3433600450 ps |
| CPU time | 287.66 seconds |
| Started | Jul 09 07:26:52 PM PDT 24 |
| Finished | Jul 09 07:31:47 PM PDT 24 |
| Peak memory | 599040 kb |
| Host | smart-c9ac357e-bb70-4a44-9f51-98c7cfc1fa4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364939281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.364939281 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3625074959 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 16090203935 ps |
| CPU time | 2323.98 seconds |
| Started | Jul 09 07:26:34 PM PDT 24 |
| Finished | Jul 09 08:05:33 PM PDT 24 |
| Peak memory | 593404 kb |
| Host | smart-8d78f881-a4a5-4531-8af3-42e5cda7c46d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625074959 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.3625074959 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.3144695898 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 3141086760 ps |
| CPU time | 81.98 seconds |
| Started | Jul 09 07:26:37 PM PDT 24 |
| Finished | Jul 09 07:28:11 PM PDT 24 |
| Peak memory | 598988 kb |
| Host | smart-6e864403-a939-4d8b-b09c-7efa01221bd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144695898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.3144695898 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.3144284183 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 1019847808 ps |
| CPU time | 89.71 seconds |
| Started | Jul 09 07:26:46 PM PDT 24 |
| Finished | Jul 09 07:28:25 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-de77e369-cb4f-4eed-b5f3-37a82ad3edef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144284183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .3144284183 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.832477663 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 57056386279 ps |
| CPU time | 1002.87 seconds |
| Started | Jul 09 07:26:47 PM PDT 24 |
| Finished | Jul 09 07:43:39 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-e81aa043-8f93-4c8a-95a2-67df901566aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832477663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_d evice_slow_rsp.832477663 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.237050831 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 1270286466 ps |
| CPU time | 53.42 seconds |
| Started | Jul 09 07:26:47 PM PDT 24 |
| Finished | Jul 09 07:27:50 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-b6dfef46-f6c5-4cb9-a602-f6b9313efc12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237050831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr .237050831 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.4025992625 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 2097193289 ps |
| CPU time | 76.33 seconds |
| Started | Jul 09 07:26:46 PM PDT 24 |
| Finished | Jul 09 07:28:11 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-3faa1e0c-59f8-4f35-ba33-efa0c09a8512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025992625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.4025992625 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.3228012558 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 439331968 ps |
| CPU time | 38.18 seconds |
| Started | Jul 09 07:26:41 PM PDT 24 |
| Finished | Jul 09 07:27:31 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-573ce041-7d51-4565-a1ee-fa06a982710e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228012558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.3228012558 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3099481757 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 89272567470 ps |
| CPU time | 995.24 seconds |
| Started | Jul 09 07:26:41 PM PDT 24 |
| Finished | Jul 09 07:43:28 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-9595886a-7b01-43cc-ae39-7badc9ada20c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099481757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3099481757 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.4146963977 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 4339617595 ps |
| CPU time | 73.5 seconds |
| Started | Jul 09 07:26:47 PM PDT 24 |
| Finished | Jul 09 07:28:09 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-bad1ac58-7c6f-4c5f-8db4-1cd48da96aa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146963977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.4146963977 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.727217834 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 602448014 ps |
| CPU time | 54.69 seconds |
| Started | Jul 09 07:26:40 PM PDT 24 |
| Finished | Jul 09 07:27:47 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-03bf2f06-3eb4-4158-b235-b428c4a298d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727217834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_dela ys.727217834 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.3970269391 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 437413240 ps |
| CPU time | 16.55 seconds |
| Started | Jul 09 07:26:48 PM PDT 24 |
| Finished | Jul 09 07:27:13 PM PDT 24 |
| Peak memory | 576484 kb |
| Host | smart-86fd44f8-a1db-4737-8623-1eae43849055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970269391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3970269391 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.1007802686 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 48526315 ps |
| CPU time | 6.51 seconds |
| Started | Jul 09 07:26:34 PM PDT 24 |
| Finished | Jul 09 07:26:55 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-23fc421a-7684-4b6f-b681-49403d445b56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007802686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1007802686 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.1692993009 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 10093968838 ps |
| CPU time | 97.49 seconds |
| Started | Jul 09 07:26:34 PM PDT 24 |
| Finished | Jul 09 07:28:26 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-160c6c4c-98ab-462f-a976-cc16919cb7f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692993009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1692993009 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.289848444 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 4821614988 ps |
| CPU time | 81.45 seconds |
| Started | Jul 09 07:26:40 PM PDT 24 |
| Finished | Jul 09 07:28:13 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-78da33c2-d689-4110-9ce5-3ef6f9fc1e4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289848444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.289848444 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.103955010 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 54426065 ps |
| CPU time | 6.61 seconds |
| Started | Jul 09 07:26:33 PM PDT 24 |
| Finished | Jul 09 07:26:53 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-e573dd9f-07be-4519-be0f-a57368406bbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103955010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays .103955010 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.3341417510 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 245439587 ps |
| CPU time | 22.38 seconds |
| Started | Jul 09 07:26:47 PM PDT 24 |
| Finished | Jul 09 07:27:18 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-df261ed8-ade2-4f10-a6bd-d17395cf4025 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341417510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3341417510 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3152853936 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 8085318839 ps |
| CPU time | 269.81 seconds |
| Started | Jul 09 07:26:55 PM PDT 24 |
| Finished | Jul 09 07:31:30 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-90ee1449-4550-45f7-8383-d8fc83ab67a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152853936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3152853936 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.302694698 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 2109963727 ps |
| CPU time | 293.93 seconds |
| Started | Jul 09 07:26:47 PM PDT 24 |
| Finished | Jul 09 07:31:50 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-c0eaa82d-4796-40e6-b072-be74d7e1dd03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302694698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_ with_rand_reset.302694698 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2321975631 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 2369294450 ps |
| CPU time | 258.03 seconds |
| Started | Jul 09 07:26:52 PM PDT 24 |
| Finished | Jul 09 07:31:17 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-f5c22487-f0bd-487e-97c6-0a081c12b376 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321975631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.2321975631 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2163620647 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 279931814 ps |
| CPU time | 33.13 seconds |
| Started | Jul 09 07:26:47 PM PDT 24 |
| Finished | Jul 09 07:27:30 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-c6089463-09a1-4387-b698-9d7646e36c60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163620647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2163620647 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.2938658990 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 4382381291 ps |
| CPU time | 286.71 seconds |
| Started | Jul 09 07:27:06 PM PDT 24 |
| Finished | Jul 09 07:31:57 PM PDT 24 |
| Peak memory | 598952 kb |
| Host | smart-12379ae2-dde4-4217-9224-2b12b8f64ea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938658990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.2938658990 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2896324914 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 15953808506 ps |
| CPU time | 2035.67 seconds |
| Started | Jul 09 07:26:52 PM PDT 24 |
| Finished | Jul 09 08:00:55 PM PDT 24 |
| Peak memory | 593480 kb |
| Host | smart-38d8fce8-288d-424c-812d-52e6eecf6807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896324914 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.2896324914 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.3180225706 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 2733900466 ps |
| CPU time | 80.05 seconds |
| Started | Jul 09 07:26:55 PM PDT 24 |
| Finished | Jul 09 07:28:20 PM PDT 24 |
| Peak memory | 603936 kb |
| Host | smart-fc6063a1-cb22-47c3-b873-29a72605cd71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180225706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.3180225706 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.210191901 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 352786483 ps |
| CPU time | 27.63 seconds |
| Started | Jul 09 07:27:01 PM PDT 24 |
| Finished | Jul 09 07:27:32 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-9dbaf830-3897-4141-946d-c63718223d84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210191901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device. 210191901 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1032290288 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 12623178511 ps |
| CPU time | 225.61 seconds |
| Started | Jul 09 07:26:59 PM PDT 24 |
| Finished | Jul 09 07:30:49 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-75b5f2b2-9ec9-4c33-8048-30c84acd5b55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032290288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.1032290288 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2896267682 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 265519462 ps |
| CPU time | 27.56 seconds |
| Started | Jul 09 07:27:18 PM PDT 24 |
| Finished | Jul 09 07:27:53 PM PDT 24 |
| Peak memory | 576492 kb |
| Host | smart-f20925da-0d30-4b26-85b3-c10933189790 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896267682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.2896267682 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.3143474059 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 1611579759 ps |
| CPU time | 54.49 seconds |
| Started | Jul 09 07:27:01 PM PDT 24 |
| Finished | Jul 09 07:27:59 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-8df6c466-4314-418c-b859-2990b2f99fcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143474059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3143474059 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.4203779595 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 2240454395 ps |
| CPU time | 74.9 seconds |
| Started | Jul 09 07:27:02 PM PDT 24 |
| Finished | Jul 09 07:28:21 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-2fe15cb2-5ffe-42d2-a2d6-cc23ca196df8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203779595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.4203779595 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3102848083 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 40348386463 ps |
| CPU time | 406.02 seconds |
| Started | Jul 09 07:27:04 PM PDT 24 |
| Finished | Jul 09 07:33:55 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-257e03af-d1ed-49f6-90cc-26c9b186c279 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102848083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3102848083 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.338820572 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 68685258655 ps |
| CPU time | 1145.91 seconds |
| Started | Jul 09 07:27:01 PM PDT 24 |
| Finished | Jul 09 07:46:11 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-053eda66-38dd-4ed7-b76e-ac7489b127d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338820572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.338820572 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.16879882 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 280785204 ps |
| CPU time | 24.34 seconds |
| Started | Jul 09 07:27:05 PM PDT 24 |
| Finished | Jul 09 07:27:34 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-318e11e0-0b73-40c3-9c2f-78ff3ea389d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16879882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delay s.16879882 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.3799126041 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 2101278737 ps |
| CPU time | 64.47 seconds |
| Started | Jul 09 07:27:01 PM PDT 24 |
| Finished | Jul 09 07:28:09 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-ad27ba72-b02e-48d2-8c57-5610fd0bd8a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799126041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3799126041 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.3213247104 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 239149890 ps |
| CPU time | 10.04 seconds |
| Started | Jul 09 07:26:53 PM PDT 24 |
| Finished | Jul 09 07:27:09 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-2639fb6b-b395-41cd-aa94-f62409e198f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213247104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3213247104 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3341852052 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 8452059693 ps |
| CPU time | 89.45 seconds |
| Started | Jul 09 07:26:54 PM PDT 24 |
| Finished | Jul 09 07:28:29 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-150b2763-23cd-4e49-9a8f-785dbefba6f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341852052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3341852052 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.845627515 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 4421621067 ps |
| CPU time | 69.46 seconds |
| Started | Jul 09 07:26:53 PM PDT 24 |
| Finished | Jul 09 07:28:08 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-b588da6e-9530-4ba6-8996-63fb3da46d8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845627515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.845627515 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.956837424 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 48444545 ps |
| CPU time | 5.82 seconds |
| Started | Jul 09 07:26:56 PM PDT 24 |
| Finished | Jul 09 07:27:07 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-ffdd078d-4d74-45a9-b69c-3e01f992b43e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956837424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays .956837424 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.3460070248 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 9753568740 ps |
| CPU time | 348.92 seconds |
| Started | Jul 09 07:27:06 PM PDT 24 |
| Finished | Jul 09 07:32:59 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-85511879-05c5-4bc5-8ce0-9fc45abb657a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460070248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3460070248 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1891732726 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 3390932673 ps |
| CPU time | 249.35 seconds |
| Started | Jul 09 07:27:06 PM PDT 24 |
| Finished | Jul 09 07:31:19 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-18a49ec2-d36b-4379-9609-754611b029a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891732726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.1891732726 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2847286502 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 4040210313 ps |
| CPU time | 238.02 seconds |
| Started | Jul 09 07:27:07 PM PDT 24 |
| Finished | Jul 09 07:31:09 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-e3fdc2f4-f952-409d-97c3-9c25dcbc09b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847286502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.2847286502 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.3469124782 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 499351935 ps |
| CPU time | 24.04 seconds |
| Started | Jul 09 07:27:19 PM PDT 24 |
| Finished | Jul 09 07:27:49 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-6f35b53e-748d-453f-a22b-e990351cc02e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469124782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3469124782 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.4127466202 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 5186250941 ps |
| CPU time | 554.22 seconds |
| Started | Jul 09 07:27:20 PM PDT 24 |
| Finished | Jul 09 07:36:41 PM PDT 24 |
| Peak memory | 598792 kb |
| Host | smart-1fd97632-cd05-4acd-ac7f-e59b1ab2d68e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127466202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.4127466202 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3133665301 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 16554100542 ps |
| CPU time | 1681.04 seconds |
| Started | Jul 09 07:27:11 PM PDT 24 |
| Finished | Jul 09 07:55:17 PM PDT 24 |
| Peak memory | 593408 kb |
| Host | smart-f74e4f05-5ec3-452b-b3d3-da0e719221d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133665301 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.3133665301 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.3543881909 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4642751128 ps |
| CPU time | 317.99 seconds |
| Started | Jul 09 07:27:07 PM PDT 24 |
| Finished | Jul 09 07:32:29 PM PDT 24 |
| Peak memory | 603908 kb |
| Host | smart-58739d14-62a4-4b79-8ccb-2bc7394a78a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543881909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.3543881909 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.405516112 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 1686553543 ps |
| CPU time | 62.26 seconds |
| Started | Jul 09 07:27:14 PM PDT 24 |
| Finished | Jul 09 07:28:20 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-62011744-c70a-4249-a204-dda8e403bba4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405516112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device. 405516112 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3230671835 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 77434064996 ps |
| CPU time | 1372.78 seconds |
| Started | Jul 09 07:27:14 PM PDT 24 |
| Finished | Jul 09 07:50:11 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-c0569d9d-a46b-4d8f-8fd6-231031dc0a04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230671835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.3230671835 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3392462745 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 101092853 ps |
| CPU time | 15.03 seconds |
| Started | Jul 09 07:27:18 PM PDT 24 |
| Finished | Jul 09 07:27:40 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-dc0de9e8-884c-4602-8b45-b89436c95849 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392462745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.3392462745 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.546978622 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 222684838 ps |
| CPU time | 22.66 seconds |
| Started | Jul 09 07:27:15 PM PDT 24 |
| Finished | Jul 09 07:27:42 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-3bc8a522-3fe9-484e-986b-272771192de0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546978622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.546978622 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.59477323 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 449027308 ps |
| CPU time | 38.77 seconds |
| Started | Jul 09 07:27:23 PM PDT 24 |
| Finished | Jul 09 07:28:09 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-84b86aa9-8542-431c-891f-66e23208084c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59477323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.59477323 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.862541079 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 72853516802 ps |
| CPU time | 810.86 seconds |
| Started | Jul 09 07:27:13 PM PDT 24 |
| Finished | Jul 09 07:40:48 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-6c43ff6f-6716-4642-845e-75520dfbad64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862541079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.862541079 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.85238750 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 61165178542 ps |
| CPU time | 1082.68 seconds |
| Started | Jul 09 07:27:24 PM PDT 24 |
| Finished | Jul 09 07:45:33 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-b1b93bc7-c31b-42da-bb03-18be781f5920 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85238750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.85238750 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.2821010825 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 554730840 ps |
| CPU time | 52.07 seconds |
| Started | Jul 09 07:27:15 PM PDT 24 |
| Finished | Jul 09 07:28:12 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-b414755e-f3b4-4377-bfa0-a718625985a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821010825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.2821010825 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.1880914335 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 328229302 ps |
| CPU time | 24.11 seconds |
| Started | Jul 09 07:27:24 PM PDT 24 |
| Finished | Jul 09 07:27:54 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-786bba69-2835-4468-868f-d93ede8d0b1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880914335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1880914335 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.3478624084 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 282970231 ps |
| CPU time | 11.88 seconds |
| Started | Jul 09 07:27:07 PM PDT 24 |
| Finished | Jul 09 07:27:23 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-19bfa467-80bb-4fea-87a7-648926720c56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478624084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3478624084 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.3041992858 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 8968224638 ps |
| CPU time | 86.47 seconds |
| Started | Jul 09 07:27:06 PM PDT 24 |
| Finished | Jul 09 07:28:37 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-2b7d27ce-b301-4e6c-b6c5-9e28ca26523b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041992858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3041992858 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.1608347802 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 5748478747 ps |
| CPU time | 101.63 seconds |
| Started | Jul 09 07:27:13 PM PDT 24 |
| Finished | Jul 09 07:28:59 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-cb7c771b-6f7f-4c5f-9c23-34d60039ef5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608347802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1608347802 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3078630808 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 40381518 ps |
| CPU time | 5.94 seconds |
| Started | Jul 09 07:27:07 PM PDT 24 |
| Finished | Jul 09 07:27:17 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-bfd424ef-bbb8-40a0-9125-409d394cb9aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078630808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.3078630808 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.2630011348 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 2459112697 ps |
| CPU time | 228.84 seconds |
| Started | Jul 09 07:27:19 PM PDT 24 |
| Finished | Jul 09 07:31:14 PM PDT 24 |
| Peak memory | 576884 kb |
| Host | smart-a9748b07-c2e6-4343-a92d-4a7f3b9b6d15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630011348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2630011348 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.342569126 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 4581511828 ps |
| CPU time | 174.87 seconds |
| Started | Jul 09 07:27:20 PM PDT 24 |
| Finished | Jul 09 07:30:22 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-b6ba00ae-f635-40ea-bdfa-4a25d62a7342 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342569126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.342569126 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.738962475 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 163123253 ps |
| CPU time | 43.35 seconds |
| Started | Jul 09 07:27:20 PM PDT 24 |
| Finished | Jul 09 07:28:10 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-54da15e8-9b3d-42a9-a0a3-c61a9821647a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738962475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_ with_rand_reset.738962475 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.453860590 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 5876555254 ps |
| CPU time | 256.39 seconds |
| Started | Jul 09 07:27:24 PM PDT 24 |
| Finished | Jul 09 07:31:47 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-14acb427-d4bd-4a35-925c-41128dbeec62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453860590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_reset_error.453860590 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.1717722792 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 1078198044 ps |
| CPU time | 41.66 seconds |
| Started | Jul 09 07:27:22 PM PDT 24 |
| Finished | Jul 09 07:28:11 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-91c40119-4b7b-482f-8ffb-4b536fae0c37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717722792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1717722792 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.3133767325 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 6754566028 ps |
| CPU time | 720.92 seconds |
| Started | Jul 09 07:27:26 PM PDT 24 |
| Finished | Jul 09 07:39:33 PM PDT 24 |
| Peak memory | 598104 kb |
| Host | smart-fb7e4049-1210-4981-8ba0-ed0fc73c76fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133767325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.3133767325 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.1058542314 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 29120451723 ps |
| CPU time | 4167.68 seconds |
| Started | Jul 09 07:27:20 PM PDT 24 |
| Finished | Jul 09 08:36:55 PM PDT 24 |
| Peak memory | 593488 kb |
| Host | smart-6c709644-e731-47e0-80e1-a5e267768c61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058542314 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.1058542314 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.15356640 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 751315812 ps |
| CPU time | 65.83 seconds |
| Started | Jul 09 07:27:20 PM PDT 24 |
| Finished | Jul 09 07:28:33 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-dcf1a0ba-a54b-4f37-8f8e-b9d47d0a0dad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15356640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.15356640 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3174820857 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 53772200391 ps |
| CPU time | 978.62 seconds |
| Started | Jul 09 07:27:28 PM PDT 24 |
| Finished | Jul 09 07:43:52 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-55312667-1b25-4be8-aac0-0c655ff099b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174820857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.3174820857 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.726909966 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 591025004 ps |
| CPU time | 24.1 seconds |
| Started | Jul 09 07:27:26 PM PDT 24 |
| Finished | Jul 09 07:27:56 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-af5a1e17-8bd4-47dc-846b-c3a2db4ed029 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726909966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr .726909966 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.831994659 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 376412784 ps |
| CPU time | 16.74 seconds |
| Started | Jul 09 07:27:29 PM PDT 24 |
| Finished | Jul 09 07:27:51 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-ff7db279-ed57-4e9a-9e36-d79979a40f06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831994659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.831994659 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.3787647594 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 2501847796 ps |
| CPU time | 103.42 seconds |
| Started | Jul 09 07:27:20 PM PDT 24 |
| Finished | Jul 09 07:29:10 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-6c0d6777-b8a0-48a7-bc7c-b0cdaba2f89a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787647594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.3787647594 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2706956395 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 36575584376 ps |
| CPU time | 377.87 seconds |
| Started | Jul 09 07:27:21 PM PDT 24 |
| Finished | Jul 09 07:33:46 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-63bf839f-a63d-4484-a7dd-4a5442ed98be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706956395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2706956395 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.4107731569 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 53589704998 ps |
| CPU time | 887.16 seconds |
| Started | Jul 09 07:27:18 PM PDT 24 |
| Finished | Jul 09 07:42:12 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-8ec119fb-a43f-4f05-a7d5-800301bb195e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107731569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.4107731569 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.3763150611 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 394551723 ps |
| CPU time | 33.01 seconds |
| Started | Jul 09 07:27:20 PM PDT 24 |
| Finished | Jul 09 07:28:00 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-5d14156d-cd6f-4f16-b75e-2d2985401749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763150611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.3763150611 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.451786836 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 2440625163 ps |
| CPU time | 69.66 seconds |
| Started | Jul 09 07:27:29 PM PDT 24 |
| Finished | Jul 09 07:28:44 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-947e4c6e-89b2-4b37-8db7-6ec3f0260400 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451786836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.451786836 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.3752602715 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 201918638 ps |
| CPU time | 9.2 seconds |
| Started | Jul 09 07:27:19 PM PDT 24 |
| Finished | Jul 09 07:27:35 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-87d3614c-3793-4116-939c-398903868a52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752602715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3752602715 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.454222835 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 7266197923 ps |
| CPU time | 78.8 seconds |
| Started | Jul 09 07:27:23 PM PDT 24 |
| Finished | Jul 09 07:28:49 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-a933cf74-8326-4168-b4ec-e18d717f03b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454222835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.454222835 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.2166037823 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 5845605646 ps |
| CPU time | 100.67 seconds |
| Started | Jul 09 07:27:19 PM PDT 24 |
| Finished | Jul 09 07:29:06 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-30e23eff-d1af-47df-9549-dff4ec2aa0bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166037823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2166037823 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.4281097622 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 45107933 ps |
| CPU time | 6.8 seconds |
| Started | Jul 09 07:27:17 PM PDT 24 |
| Finished | Jul 09 07:27:29 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-7f7247e0-0361-44fa-8cbb-51f0901efe12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281097622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.4281097622 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.1776338120 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 3510248478 ps |
| CPU time | 159.23 seconds |
| Started | Jul 09 07:27:28 PM PDT 24 |
| Finished | Jul 09 07:30:13 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-d5d2c397-ae86-48fe-91c6-0922c8b22b6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776338120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1776338120 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.2915391569 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 2329471061 ps |
| CPU time | 171.93 seconds |
| Started | Jul 09 07:27:29 PM PDT 24 |
| Finished | Jul 09 07:30:26 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-54a7c722-698d-4719-ac72-09a1e900bfdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915391569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2915391569 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.1600711408 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 2166182097 ps |
| CPU time | 93.62 seconds |
| Started | Jul 09 07:27:28 PM PDT 24 |
| Finished | Jul 09 07:29:07 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-39dd149e-61e6-4798-9bcf-9a9a2927d267 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600711408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.1600711408 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.3413686957 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 255845283 ps |
| CPU time | 77.95 seconds |
| Started | Jul 09 07:27:28 PM PDT 24 |
| Finished | Jul 09 07:28:52 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-5be5ce97-0f64-4157-bc65-863cc6c5e5c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413686957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.3413686957 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.922305736 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 298203173 ps |
| CPU time | 35.18 seconds |
| Started | Jul 09 07:27:27 PM PDT 24 |
| Finished | Jul 09 07:28:07 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-85cb4bb6-5c57-46c3-baae-3a343a0d1690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922305736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.922305736 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.4282073023 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 6059359800 ps |
| CPU time | 588.16 seconds |
| Started | Jul 09 07:27:47 PM PDT 24 |
| Finished | Jul 09 07:37:43 PM PDT 24 |
| Peak memory | 598696 kb |
| Host | smart-95be942f-18d6-46d4-bfbb-0d8c03ba9a90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282073023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.4282073023 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.1457709617 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 15080886937 ps |
| CPU time | 1763.1 seconds |
| Started | Jul 09 07:27:27 PM PDT 24 |
| Finished | Jul 09 07:56:55 PM PDT 24 |
| Peak memory | 593580 kb |
| Host | smart-0b3d6234-aa14-4886-8879-c88e464e5b04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457709617 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.1457709617 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.3082469010 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 4057625768 ps |
| CPU time | 207.75 seconds |
| Started | Jul 09 07:27:34 PM PDT 24 |
| Finished | Jul 09 07:31:06 PM PDT 24 |
| Peak memory | 603952 kb |
| Host | smart-581dee9b-a723-44ed-8472-30cc6a359d6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082469010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.3082469010 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.482749991 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 732413753 ps |
| CPU time | 56.23 seconds |
| Started | Jul 09 07:27:42 PM PDT 24 |
| Finished | Jul 09 07:28:44 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-4d9e4c7c-0f7f-413a-bd9a-c231db29121c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482749991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device. 482749991 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3725340940 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 113015197549 ps |
| CPU time | 1957.09 seconds |
| Started | Jul 09 07:27:42 PM PDT 24 |
| Finished | Jul 09 08:00:25 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-d9722366-34cc-4385-bcff-3d45af014bda |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725340940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.3725340940 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3934746288 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 63464265 ps |
| CPU time | 5.62 seconds |
| Started | Jul 09 07:27:44 PM PDT 24 |
| Finished | Jul 09 07:27:56 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-393342cc-5e11-4c01-b865-a036a154e2ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934746288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.3934746288 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.2439366457 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 1676628298 ps |
| CPU time | 54.26 seconds |
| Started | Jul 09 07:27:41 PM PDT 24 |
| Finished | Jul 09 07:28:41 PM PDT 24 |
| Peak memory | 576428 kb |
| Host | smart-dc565131-0561-4310-93fa-d507379a775b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439366457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2439366457 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.2459650440 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 137310418 ps |
| CPU time | 15.48 seconds |
| Started | Jul 09 07:27:35 PM PDT 24 |
| Finished | Jul 09 07:27:54 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-3b8d163e-0e2a-4e86-b55c-7b94563299ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459650440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.2459650440 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.387196410 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 68741978702 ps |
| CPU time | 773.58 seconds |
| Started | Jul 09 07:27:37 PM PDT 24 |
| Finished | Jul 09 07:40:35 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-b4f5d560-30de-4688-9c12-9f8745c87e7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387196410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.387196410 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.898864445 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 29054577567 ps |
| CPU time | 500.22 seconds |
| Started | Jul 09 07:27:33 PM PDT 24 |
| Finished | Jul 09 07:35:57 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-fefa375d-dc53-437c-8557-21efe78afa05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898864445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.898864445 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.272119860 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 485688469 ps |
| CPU time | 44.03 seconds |
| Started | Jul 09 07:27:36 PM PDT 24 |
| Finished | Jul 09 07:28:25 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-4487fb67-c19b-40eb-afa1-e41d9e0748ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272119860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_dela ys.272119860 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.2265781633 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 359022383 ps |
| CPU time | 29.91 seconds |
| Started | Jul 09 07:27:40 PM PDT 24 |
| Finished | Jul 09 07:28:15 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-85367e92-08e4-474f-82ef-7f3331260bdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265781633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2265781633 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.2770979223 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 44604817 ps |
| CPU time | 5.42 seconds |
| Started | Jul 09 07:30:01 PM PDT 24 |
| Finished | Jul 09 07:30:10 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-a212e9a8-5cf9-430d-a5c2-6a6652ded0e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770979223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2770979223 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.132544139 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 8898933800 ps |
| CPU time | 96.92 seconds |
| Started | Jul 09 07:27:34 PM PDT 24 |
| Finished | Jul 09 07:29:15 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-f46bba0d-bd60-4f55-b188-f73a7380b706 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132544139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.132544139 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2640066782 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 4151213449 ps |
| CPU time | 71.94 seconds |
| Started | Jul 09 07:27:36 PM PDT 24 |
| Finished | Jul 09 07:28:52 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-b515dd44-ef59-48c6-bf1f-06a8ec3bab9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640066782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2640066782 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.693405834 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 49587137 ps |
| CPU time | 7.08 seconds |
| Started | Jul 09 07:27:43 PM PDT 24 |
| Finished | Jul 09 07:27:56 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-5cde4869-ad7a-48b6-a88f-5a8627c3e51b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693405834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays .693405834 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.1129217073 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 3262757937 ps |
| CPU time | 226.04 seconds |
| Started | Jul 09 07:27:45 PM PDT 24 |
| Finished | Jul 09 07:31:38 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-2c88795e-aeed-49e6-89f6-c1458db15734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129217073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1129217073 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.2198911028 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 4393971825 ps |
| CPU time | 153.7 seconds |
| Started | Jul 09 07:27:41 PM PDT 24 |
| Finished | Jul 09 07:30:21 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-64477b59-0093-4e4b-99ea-ca4c8b28d6b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198911028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2198911028 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.35456156 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 10484420211 ps |
| CPU time | 609.23 seconds |
| Started | Jul 09 07:27:41 PM PDT 24 |
| Finished | Jul 09 07:37:55 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-467f08cf-600c-476e-87b5-5afc2e456c80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35456156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_w ith_rand_reset.35456156 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.2357347274 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 2558157208 ps |
| CPU time | 369.6 seconds |
| Started | Jul 09 07:27:41 PM PDT 24 |
| Finished | Jul 09 07:33:57 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-86ba7ca1-b2a3-4da5-b38d-cd0a63fc2bdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357347274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al l_with_reset_error.2357347274 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.2891773379 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 134429233 ps |
| CPU time | 18.71 seconds |
| Started | Jul 09 07:27:41 PM PDT 24 |
| Finished | Jul 09 07:28:04 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-2554b048-6020-49f7-b36d-86f617221447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891773379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2891773379 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.3411923094 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 5890359672 ps |
| CPU time | 529.93 seconds |
| Started | Jul 09 07:28:01 PM PDT 24 |
| Finished | Jul 09 07:36:55 PM PDT 24 |
| Peak memory | 599024 kb |
| Host | smart-8453c5e3-49f9-4e18-bddd-77523c9b6171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411923094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.3411923094 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.893633462 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 30859465330 ps |
| CPU time | 4402.04 seconds |
| Started | Jul 09 07:27:47 PM PDT 24 |
| Finished | Jul 09 08:41:16 PM PDT 24 |
| Peak memory | 593796 kb |
| Host | smart-e6484778-c7ba-4aee-8c65-41206fef5d00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893633462 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 18.chip_same_csr_outstanding.893633462 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.2460589789 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 916531076 ps |
| CPU time | 65.51 seconds |
| Started | Jul 09 07:27:57 PM PDT 24 |
| Finished | Jul 09 07:29:07 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-18c8ea9d-2ffa-403f-a7a2-c0776cfa3ac2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460589789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .2460589789 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.3467419566 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 292361340 ps |
| CPU time | 30.07 seconds |
| Started | Jul 09 07:27:58 PM PDT 24 |
| Finished | Jul 09 07:28:32 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-71c0558d-e04f-4eaa-a963-436084650708 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467419566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.3467419566 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.280840695 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 105187459 ps |
| CPU time | 11.67 seconds |
| Started | Jul 09 07:27:58 PM PDT 24 |
| Finished | Jul 09 07:28:14 PM PDT 24 |
| Peak memory | 576484 kb |
| Host | smart-29d01c19-b988-4970-af97-7f3151e27bf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280840695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.280840695 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.2455251702 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 521244617 ps |
| CPU time | 46.26 seconds |
| Started | Jul 09 07:27:46 PM PDT 24 |
| Finished | Jul 09 07:28:40 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-9258a59c-2b85-443d-9cb5-f902be20de7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455251702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.2455251702 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.4170697155 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 76156144446 ps |
| CPU time | 727.76 seconds |
| Started | Jul 09 07:27:53 PM PDT 24 |
| Finished | Jul 09 07:40:08 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-6b76bad3-7ded-4845-a5c1-52e4eadd63ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170697155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.4170697155 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1896931052 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 62964463851 ps |
| CPU time | 1057.23 seconds |
| Started | Jul 09 07:27:59 PM PDT 24 |
| Finished | Jul 09 07:45:40 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-cdd8e59e-e13a-434e-aba7-c4121027582a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896931052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1896931052 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.2438757566 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 614654578 ps |
| CPU time | 56.87 seconds |
| Started | Jul 09 07:27:53 PM PDT 24 |
| Finished | Jul 09 07:28:56 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-55593d05-243a-4d74-a95f-818de0191577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438757566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.2438757566 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.263309287 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 212421728 ps |
| CPU time | 17.55 seconds |
| Started | Jul 09 07:28:02 PM PDT 24 |
| Finished | Jul 09 07:28:23 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-554195b6-c2ac-423d-a7e8-c3fc3f70b744 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263309287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.263309287 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.367617894 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 49238819 ps |
| CPU time | 6.92 seconds |
| Started | Jul 09 07:27:48 PM PDT 24 |
| Finished | Jul 09 07:28:03 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-ddfea574-c952-44c0-8954-c11c7b402dd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367617894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.367617894 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.1495689243 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 9896627969 ps |
| CPU time | 108.88 seconds |
| Started | Jul 09 07:27:48 PM PDT 24 |
| Finished | Jul 09 07:29:44 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-83552664-4989-4e5a-b5fd-8ff029f6e7ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495689243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1495689243 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2754267131 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 4338674036 ps |
| CPU time | 71.49 seconds |
| Started | Jul 09 07:27:49 PM PDT 24 |
| Finished | Jul 09 07:29:09 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-f28df3d4-78fc-4382-b8f5-b3c04cbc6373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754267131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2754267131 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.4293146472 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 41977892 ps |
| CPU time | 6.33 seconds |
| Started | Jul 09 07:27:49 PM PDT 24 |
| Finished | Jul 09 07:28:03 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-b1ceb70d-254a-4292-b5ba-6cadf27b8584 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293146472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.4293146472 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.635982985 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 20079227103 ps |
| CPU time | 713.27 seconds |
| Started | Jul 09 07:27:57 PM PDT 24 |
| Finished | Jul 09 07:39:55 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-7301c126-1339-42c9-950b-aa5a40f586b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635982985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.635982985 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.474113241 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 1623626061 ps |
| CPU time | 117.08 seconds |
| Started | Jul 09 07:28:03 PM PDT 24 |
| Finished | Jul 09 07:30:03 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-a1a80597-c1d7-4144-a715-5a0079c4732d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474113241 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.474113241 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.2321867279 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 3145056561 ps |
| CPU time | 188.79 seconds |
| Started | Jul 09 07:28:03 PM PDT 24 |
| Finished | Jul 09 07:31:15 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-6b2ee0fe-ba42-4c1f-b7d0-77e91fbd1ef7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321867279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.2321867279 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.638634157 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 972704797 ps |
| CPU time | 142.48 seconds |
| Started | Jul 09 07:28:00 PM PDT 24 |
| Finished | Jul 09 07:30:26 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-67cbb10c-d10f-456b-81b2-c86f96efab77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638634157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_reset_error.638634157 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.183891818 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 274658506 ps |
| CPU time | 33.37 seconds |
| Started | Jul 09 07:27:58 PM PDT 24 |
| Finished | Jul 09 07:28:36 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-346aacdf-da15-40a0-bad5-799062ef8a88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183891818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.183891818 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.789862932 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 4291836230 ps |
| CPU time | 388.11 seconds |
| Started | Jul 09 07:28:12 PM PDT 24 |
| Finished | Jul 09 07:34:41 PM PDT 24 |
| Peak memory | 597392 kb |
| Host | smart-1361eb75-5dbb-4fa4-8ff0-729b165565e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789862932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.789862932 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.4231390858 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 28375975476 ps |
| CPU time | 4264.94 seconds |
| Started | Jul 09 07:28:04 PM PDT 24 |
| Finished | Jul 09 08:39:12 PM PDT 24 |
| Peak memory | 593756 kb |
| Host | smart-ec10e3ed-7440-4fa4-8dec-aa6353629e25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231390858 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.4231390858 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.239374973 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 2636599386 ps |
| CPU time | 118.65 seconds |
| Started | Jul 09 07:28:06 PM PDT 24 |
| Finished | Jul 09 07:30:07 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-2e632532-51d3-479f-88ce-55294ce1db09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239374973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device. 239374973 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.3572839308 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 69327910300 ps |
| CPU time | 1188.24 seconds |
| Started | Jul 09 07:28:05 PM PDT 24 |
| Finished | Jul 09 07:47:56 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-cd211683-34bf-4dcf-a2d9-756d09327874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572839308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.3572839308 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.540079071 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 313267666 ps |
| CPU time | 36.3 seconds |
| Started | Jul 09 07:28:04 PM PDT 24 |
| Finished | Jul 09 07:28:43 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-45280a59-f10f-40ec-a697-f3a7b57f5b27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540079071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr .540079071 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.136448348 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 454394609 ps |
| CPU time | 36.97 seconds |
| Started | Jul 09 07:28:09 PM PDT 24 |
| Finished | Jul 09 07:28:48 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-6bcc8380-a7cc-445b-aef5-157267012dad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136448348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.136448348 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.3138579384 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 1222724332 ps |
| CPU time | 44.6 seconds |
| Started | Jul 09 07:28:06 PM PDT 24 |
| Finished | Jul 09 07:28:53 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-c3e77667-3811-49ed-a339-20a6edf43be1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138579384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.3138579384 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.4038071224 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 50309356056 ps |
| CPU time | 525.71 seconds |
| Started | Jul 09 07:28:09 PM PDT 24 |
| Finished | Jul 09 07:36:57 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-f3b4b012-656d-4dcf-aa74-a57d66964617 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038071224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.4038071224 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.2560173551 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 38517075861 ps |
| CPU time | 649.64 seconds |
| Started | Jul 09 07:28:06 PM PDT 24 |
| Finished | Jul 09 07:38:58 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-b03bfd04-61e5-48ac-b5a6-ae9d3eb2114a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560173551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2560173551 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.2568033871 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 337250048 ps |
| CPU time | 31.85 seconds |
| Started | Jul 09 07:28:07 PM PDT 24 |
| Finished | Jul 09 07:28:42 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-cfb2b4a8-bc7b-4d30-9335-6de630d8b4bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568033871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.2568033871 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.3204547226 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 219884332 ps |
| CPU time | 16.43 seconds |
| Started | Jul 09 07:28:05 PM PDT 24 |
| Finished | Jul 09 07:28:24 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-b13b33ee-f768-4e0b-a34e-43a4ed1320ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204547226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3204547226 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.2509924434 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 36670975 ps |
| CPU time | 5.49 seconds |
| Started | Jul 09 07:28:10 PM PDT 24 |
| Finished | Jul 09 07:28:17 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-28cbc029-395b-4a83-ab31-41cf0fdfec1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509924434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2509924434 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.742478181 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 7744867369 ps |
| CPU time | 81.36 seconds |
| Started | Jul 09 07:28:09 PM PDT 24 |
| Finished | Jul 09 07:29:32 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-0cc13770-17f0-46c6-8032-161dec7dc48a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742478181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.742478181 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3561883890 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 5689340987 ps |
| CPU time | 90.93 seconds |
| Started | Jul 09 07:28:05 PM PDT 24 |
| Finished | Jul 09 07:29:38 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-9ba1f92a-67c9-44c6-b1a8-efecb8eb703e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561883890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3561883890 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.3849581669 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 41557402 ps |
| CPU time | 5.43 seconds |
| Started | Jul 09 07:28:07 PM PDT 24 |
| Finished | Jul 09 07:28:15 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-33a3d298-008e-44e8-a0d9-2279a021bddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849581669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.3849581669 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.2335168958 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 2729125067 ps |
| CPU time | 211.73 seconds |
| Started | Jul 09 07:28:07 PM PDT 24 |
| Finished | Jul 09 07:31:41 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-6ef4316c-412b-49c5-8c89-ff11e196bc3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335168958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2335168958 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.3649978855 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 529776545 ps |
| CPU time | 53.13 seconds |
| Started | Jul 09 07:28:14 PM PDT 24 |
| Finished | Jul 09 07:29:09 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-acd120ce-b8a3-4e0a-b043-aeed64f318e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649978855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3649978855 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2614875183 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 707256113 ps |
| CPU time | 149.72 seconds |
| Started | Jul 09 07:28:09 PM PDT 24 |
| Finished | Jul 09 07:30:41 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-01ce3905-7eae-4757-b0ff-87e05b5d10f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614875183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.2614875183 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.1292750012 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 4564077361 ps |
| CPU time | 386.68 seconds |
| Started | Jul 09 07:28:16 PM PDT 24 |
| Finished | Jul 09 07:34:44 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-ec9b035a-027e-40cc-8e4a-ce888bf7fc7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292750012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.1292750012 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.3024304087 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 1104144951 ps |
| CPU time | 51.27 seconds |
| Started | Jul 09 07:28:05 PM PDT 24 |
| Finished | Jul 09 07:28:59 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-c79d727e-7a43-4a55-8aa8-d47303362f37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024304087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3024304087 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.2653726422 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 46884830620 ps |
| CPU time | 4775.33 seconds |
| Started | Jul 09 07:25:18 PM PDT 24 |
| Finished | Jul 09 08:44:57 PM PDT 24 |
| Peak memory | 592904 kb |
| Host | smart-48f8a6ff-62fe-43df-a546-0e21e1f0a80d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653726422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.2653726422 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.3658404749 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 6072298635 ps |
| CPU time | 488.79 seconds |
| Started | Jul 09 07:25:40 PM PDT 24 |
| Finished | Jul 09 07:34:03 PM PDT 24 |
| Peak memory | 599364 kb |
| Host | smart-b96015d5-d8c9-4323-b4ef-ad9a17544c97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658404749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.3658404749 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.3698365741 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 6354081243 ps |
| CPU time | 191.2 seconds |
| Started | Jul 09 07:25:20 PM PDT 24 |
| Finished | Jul 09 07:28:37 PM PDT 24 |
| Peak memory | 590680 kb |
| Host | smart-6b8f699e-6694-46f1-9c2a-f0334248949b |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698365741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.3698365741 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3840628709 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 12610670866 ps |
| CPU time | 491.99 seconds |
| Started | Jul 09 07:25:26 PM PDT 24 |
| Finished | Jul 09 07:33:49 PM PDT 24 |
| Peak memory | 592692 kb |
| Host | smart-390a3419-2786-4165-ad26-2268d34a031c |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840628709 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.3840628709 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.2886035777 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 15217144896 ps |
| CPU time | 2072.71 seconds |
| Started | Jul 09 07:25:23 PM PDT 24 |
| Finished | Jul 09 08:00:06 PM PDT 24 |
| Peak memory | 592516 kb |
| Host | smart-ad3295d5-6f45-428b-9f86-95e8de2c127c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886035777 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.2886035777 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.3234396593 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 3922669348 ps |
| CPU time | 185.95 seconds |
| Started | Jul 09 07:25:27 PM PDT 24 |
| Finished | Jul 09 07:28:44 PM PDT 24 |
| Peak memory | 604028 kb |
| Host | smart-56fce931-5d14-482c-80a7-3a59f6ef5909 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234396593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.3234396593 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.2777910405 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 1290901318 ps |
| CPU time | 81 seconds |
| Started | Jul 09 07:25:29 PM PDT 24 |
| Finished | Jul 09 07:27:01 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-e51eabb7-e50a-4eae-aade-8a9c19c5773e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777910405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 2777910405 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.3339630208 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 99533011182 ps |
| CPU time | 1788.2 seconds |
| Started | Jul 09 07:25:21 PM PDT 24 |
| Finished | Jul 09 07:55:17 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-932d1ce2-6a4a-4732-a867-99a15af1f79f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339630208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.3339630208 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.425194000 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 307452253 ps |
| CPU time | 14.58 seconds |
| Started | Jul 09 07:25:37 PM PDT 24 |
| Finished | Jul 09 07:26:03 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-5ddd955d-907a-48f1-8eb4-b7f807e9f80e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425194000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr. 425194000 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.3113459954 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 72976063 ps |
| CPU time | 8.83 seconds |
| Started | Jul 09 07:25:26 PM PDT 24 |
| Finished | Jul 09 07:25:46 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-b330c4f3-cea1-4b84-8bce-59e64ed8c33a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113459954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3113459954 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.1176077396 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 2342464244 ps |
| CPU time | 94.46 seconds |
| Started | Jul 09 07:25:29 PM PDT 24 |
| Finished | Jul 09 07:27:15 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-39764464-d705-4633-8211-b5dc8b22bead |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176077396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.1176077396 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.1426984048 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 67415722126 ps |
| CPU time | 695.95 seconds |
| Started | Jul 09 07:25:27 PM PDT 24 |
| Finished | Jul 09 07:37:15 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-4c372dfd-8883-4399-b605-e3a25e7a6537 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426984048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1426984048 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.1826763942 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 9251616863 ps |
| CPU time | 151.72 seconds |
| Started | Jul 09 07:25:29 PM PDT 24 |
| Finished | Jul 09 07:28:12 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-acb70ba3-28a6-4383-ac0e-1b83490a13fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826763942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1826763942 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.2817713375 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 29461246 ps |
| CPU time | 5.81 seconds |
| Started | Jul 09 07:25:28 PM PDT 24 |
| Finished | Jul 09 07:25:45 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-f2aa80f9-d07d-4eb7-806f-c4401fa80c54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817713375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.2817713375 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.3569386166 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 454910525 ps |
| CPU time | 14.44 seconds |
| Started | Jul 09 07:25:28 PM PDT 24 |
| Finished | Jul 09 07:25:54 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-08a87761-b336-478f-b4f4-0c30cecb78ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569386166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3569386166 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.2788861456 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 54048516 ps |
| CPU time | 6.84 seconds |
| Started | Jul 09 07:25:20 PM PDT 24 |
| Finished | Jul 09 07:25:35 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-3dfc0087-c8b8-47bc-8537-21bbb4fcc0fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788861456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2788861456 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.3811068896 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 8444135261 ps |
| CPU time | 89.95 seconds |
| Started | Jul 09 07:25:20 PM PDT 24 |
| Finished | Jul 09 07:26:58 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-7b07f522-1fa5-4bc0-b2df-30eed554e6f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811068896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3811068896 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.1030529001 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 5497233490 ps |
| CPU time | 89.35 seconds |
| Started | Jul 09 07:25:19 PM PDT 24 |
| Finished | Jul 09 07:26:53 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-b06c7e0e-acf1-4852-872f-891b5afe9b10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030529001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1030529001 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.3980516450 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 49711957 ps |
| CPU time | 6.17 seconds |
| Started | Jul 09 07:25:21 PM PDT 24 |
| Finished | Jul 09 07:25:34 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-31a6e636-24e7-4f62-a317-bfa5c49db5ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980516450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .3980516450 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.1312562379 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 307732429 ps |
| CPU time | 23.78 seconds |
| Started | Jul 09 07:25:37 PM PDT 24 |
| Finished | Jul 09 07:26:14 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-38920068-01e9-47a4-bdd9-6003e59a5ab8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312562379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1312562379 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.3148760548 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 12345565427 ps |
| CPU time | 380.37 seconds |
| Started | Jul 09 07:25:26 PM PDT 24 |
| Finished | Jul 09 07:31:57 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-f11fe388-93cf-4aef-8415-27777069da21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148760548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3148760548 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.1644739451 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 8077942967 ps |
| CPU time | 514.53 seconds |
| Started | Jul 09 07:25:24 PM PDT 24 |
| Finished | Jul 09 07:34:10 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-976a8ae2-7f04-4edf-96cf-3bf4f4f92883 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644739451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.1644739451 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.3025268239 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 14720427112 ps |
| CPU time | 659.58 seconds |
| Started | Jul 09 07:25:26 PM PDT 24 |
| Finished | Jul 09 07:36:36 PM PDT 24 |
| Peak memory | 576956 kb |
| Host | smart-b5474c36-d903-4bd5-a2d7-c73ef5c521fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025268239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.3025268239 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.952883570 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 323174134 ps |
| CPU time | 40.65 seconds |
| Started | Jul 09 07:25:25 PM PDT 24 |
| Finished | Jul 09 07:26:15 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-0938a9f1-df81-4759-b853-f54100a519dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952883570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.952883570 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.75579013 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 3247339400 ps |
| CPU time | 140.71 seconds |
| Started | Jul 09 07:28:12 PM PDT 24 |
| Finished | Jul 09 07:30:34 PM PDT 24 |
| Peak memory | 603980 kb |
| Host | smart-edcc0f6c-4b76-4259-9a4c-e1dc28c2fc5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75579013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.75579013 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.1980644507 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 1029835678 ps |
| CPU time | 73.71 seconds |
| Started | Jul 09 07:28:20 PM PDT 24 |
| Finished | Jul 09 07:29:36 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-84609877-5635-4fda-8343-dc8788131632 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980644507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .1980644507 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.483291933 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 65126416034 ps |
| CPU time | 1095.11 seconds |
| Started | Jul 09 07:28:20 PM PDT 24 |
| Finished | Jul 09 07:46:38 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-139dbfe9-9547-494a-af50-741fc15f1361 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483291933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_d evice_slow_rsp.483291933 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3562519014 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 1250117531 ps |
| CPU time | 39.71 seconds |
| Started | Jul 09 07:28:36 PM PDT 24 |
| Finished | Jul 09 07:29:18 PM PDT 24 |
| Peak memory | 576464 kb |
| Host | smart-6bd866da-7f0a-44af-a971-1ac8af667733 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562519014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.3562519014 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.1170802554 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 117288773 ps |
| CPU time | 12.61 seconds |
| Started | Jul 09 07:28:20 PM PDT 24 |
| Finished | Jul 09 07:28:35 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-74b18e1f-8ddc-4613-b110-4189438f0af4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170802554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1170802554 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.2916153735 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 2488099796 ps |
| CPU time | 89.36 seconds |
| Started | Jul 09 07:28:16 PM PDT 24 |
| Finished | Jul 09 07:29:46 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-6a9a45d2-51d1-4e18-907e-8c59b22ef47d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916153735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.2916153735 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.3120145607 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 60688315773 ps |
| CPU time | 627.78 seconds |
| Started | Jul 09 07:28:18 PM PDT 24 |
| Finished | Jul 09 07:38:48 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-e7dc0474-0228-4402-a9c0-c6ae35769a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120145607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3120145607 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.1209428672 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 62779788628 ps |
| CPU time | 1102.75 seconds |
| Started | Jul 09 07:28:18 PM PDT 24 |
| Finished | Jul 09 07:46:43 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-21360d93-da61-4e9f-9a97-dfaae5051c71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209428672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1209428672 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.611564639 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 331898040 ps |
| CPU time | 31.7 seconds |
| Started | Jul 09 07:28:13 PM PDT 24 |
| Finished | Jul 09 07:28:46 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-e4625410-0dc9-456f-a97f-ae456bff9e9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611564639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_dela ys.611564639 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.3412240529 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 2055500302 ps |
| CPU time | 59.66 seconds |
| Started | Jul 09 07:28:20 PM PDT 24 |
| Finished | Jul 09 07:29:22 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-b7727900-7b0f-41d1-84ae-2f065f601b44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412240529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3412240529 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.384471546 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 185408970 ps |
| CPU time | 8 seconds |
| Started | Jul 09 07:28:13 PM PDT 24 |
| Finished | Jul 09 07:28:23 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-5c70d836-58d6-49ff-87eb-dc384bd99974 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384471546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.384471546 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.1622214521 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 9987680116 ps |
| CPU time | 101.66 seconds |
| Started | Jul 09 07:28:12 PM PDT 24 |
| Finished | Jul 09 07:29:55 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-222aebb7-719a-4e9c-9ed2-fa7b4e433a5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622214521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1622214521 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.3962123229 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 4360370892 ps |
| CPU time | 74.08 seconds |
| Started | Jul 09 07:28:12 PM PDT 24 |
| Finished | Jul 09 07:29:27 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-a0bb2413-0cc3-44a7-878e-2b3517343f33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962123229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3962123229 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.2184695280 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 45827237 ps |
| CPU time | 7.01 seconds |
| Started | Jul 09 07:28:12 PM PDT 24 |
| Finished | Jul 09 07:28:20 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-bf4b6cc6-7bc9-47cc-af6c-ad0c6b7c1739 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184695280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.2184695280 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.3460390947 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 19907803325 ps |
| CPU time | 718.01 seconds |
| Started | Jul 09 07:28:19 PM PDT 24 |
| Finished | Jul 09 07:40:19 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-cf2304fe-ba6f-47ac-a606-aa175f629160 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460390947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3460390947 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.2402479456 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 1222067507 ps |
| CPU time | 83.71 seconds |
| Started | Jul 09 07:28:19 PM PDT 24 |
| Finished | Jul 09 07:29:45 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-43765dab-1501-4628-8afd-7d41a9829242 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402479456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2402479456 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.3081429414 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 135942494 ps |
| CPU time | 30.96 seconds |
| Started | Jul 09 07:28:22 PM PDT 24 |
| Finished | Jul 09 07:28:56 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-3d1847fd-bf4b-4259-90f5-15589b139576 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081429414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.3081429414 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.130531697 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 1701485216 ps |
| CPU time | 215.17 seconds |
| Started | Jul 09 07:28:34 PM PDT 24 |
| Finished | Jul 09 07:32:12 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-6aeb264a-2156-4b7a-b000-80f07dc80124 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130531697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_reset_error.130531697 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.936008798 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 295495230 ps |
| CPU time | 30.54 seconds |
| Started | Jul 09 07:28:34 PM PDT 24 |
| Finished | Jul 09 07:29:07 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-09093457-85e1-4159-9340-f8463d7de3bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936008798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.936008798 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.1579115212 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 4377050024 ps |
| CPU time | 363.13 seconds |
| Started | Jul 09 07:28:19 PM PDT 24 |
| Finished | Jul 09 07:34:25 PM PDT 24 |
| Peak memory | 597772 kb |
| Host | smart-ebba4176-6bca-4378-ae77-ad611a078b71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579115212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.1579115212 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.728635052 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 542984875 ps |
| CPU time | 54.38 seconds |
| Started | Jul 09 07:28:19 PM PDT 24 |
| Finished | Jul 09 07:29:16 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-615dc96f-b4dc-45c2-9e5b-edf42ca36b8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728635052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device. 728635052 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1586756973 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 15018592610 ps |
| CPU time | 235.91 seconds |
| Started | Jul 09 07:28:34 PM PDT 24 |
| Finished | Jul 09 07:32:33 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-542bc084-d17e-4db6-92d2-49ad4f2c0abe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586756973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.1586756973 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.4224377948 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 1109199125 ps |
| CPU time | 47.99 seconds |
| Started | Jul 09 07:28:26 PM PDT 24 |
| Finished | Jul 09 07:29:16 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-ea49bdf8-8847-4e91-8357-75c88a589ccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224377948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.4224377948 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.3123336776 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 2149259993 ps |
| CPU time | 70.61 seconds |
| Started | Jul 09 07:28:27 PM PDT 24 |
| Finished | Jul 09 07:29:39 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-a3c6c986-c14b-4e10-afda-5dfd3304b8b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123336776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3123336776 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.2842023519 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 529697775 ps |
| CPU time | 51.98 seconds |
| Started | Jul 09 07:28:18 PM PDT 24 |
| Finished | Jul 09 07:29:12 PM PDT 24 |
| Peak memory | 576472 kb |
| Host | smart-4a26e537-c789-490d-a620-8e493f089762 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842023519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.2842023519 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.2937488729 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 86484822041 ps |
| CPU time | 870.19 seconds |
| Started | Jul 09 07:28:19 PM PDT 24 |
| Finished | Jul 09 07:42:51 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-808b64ca-8f23-474d-b4e4-9be8c74ad4eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937488729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2937488729 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.4051526313 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 30170215887 ps |
| CPU time | 499.7 seconds |
| Started | Jul 09 07:28:22 PM PDT 24 |
| Finished | Jul 09 07:36:45 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-3abd3d40-5a03-4632-a210-da8ff90b31ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051526313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.4051526313 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.3816341749 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 72177198 ps |
| CPU time | 9.03 seconds |
| Started | Jul 09 07:28:18 PM PDT 24 |
| Finished | Jul 09 07:28:29 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-4e7c770a-f33f-40ae-a48e-b1321c261bcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816341749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.3816341749 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.373712340 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 2211122712 ps |
| CPU time | 70.38 seconds |
| Started | Jul 09 07:28:29 PM PDT 24 |
| Finished | Jul 09 07:29:41 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-e2ee8722-084e-4db0-8fc2-a64d5cd1eb60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373712340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.373712340 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.1090820441 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 227452708 ps |
| CPU time | 10.28 seconds |
| Started | Jul 09 07:28:18 PM PDT 24 |
| Finished | Jul 09 07:28:30 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-69c1a3cb-9015-40ce-9c20-5253bd57550a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090820441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1090820441 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.3409523424 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 8185873743 ps |
| CPU time | 86.58 seconds |
| Started | Jul 09 07:28:20 PM PDT 24 |
| Finished | Jul 09 07:29:49 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-87cba809-850a-4263-b412-723197fe8fa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409523424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3409523424 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.2618700526 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 6389537489 ps |
| CPU time | 112.69 seconds |
| Started | Jul 09 07:28:19 PM PDT 24 |
| Finished | Jul 09 07:30:14 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-0b1e5b8a-c685-4805-a436-97a04a70c0ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618700526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2618700526 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3321816202 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 52157894 ps |
| CPU time | 7.26 seconds |
| Started | Jul 09 07:28:18 PM PDT 24 |
| Finished | Jul 09 07:28:27 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-ee5f2bdf-c654-49da-a649-24e960041d77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321816202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.3321816202 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.3053554074 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1815825139 ps |
| CPU time | 169.7 seconds |
| Started | Jul 09 07:28:25 PM PDT 24 |
| Finished | Jul 09 07:31:17 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-30bdd71c-8bf1-4605-a5f6-c1965940095e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053554074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3053554074 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.1488059496 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 4010561993 ps |
| CPU time | 155.75 seconds |
| Started | Jul 09 07:28:27 PM PDT 24 |
| Finished | Jul 09 07:31:05 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-69da158a-050a-4baf-939c-6efcfd94b40a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488059496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1488059496 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1583075750 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 186939852 ps |
| CPU time | 47.48 seconds |
| Started | Jul 09 07:28:27 PM PDT 24 |
| Finished | Jul 09 07:29:17 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-4729d004-0eb3-4179-b05b-8870ffab00df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583075750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.1583075750 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.1331855038 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 365757580 ps |
| CPU time | 154.87 seconds |
| Started | Jul 09 07:28:25 PM PDT 24 |
| Finished | Jul 09 07:31:02 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-63639ac7-2d4f-484d-a15b-a2bcac685ef3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331855038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.1331855038 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.2440763269 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 327466115 ps |
| CPU time | 40.16 seconds |
| Started | Jul 09 07:28:25 PM PDT 24 |
| Finished | Jul 09 07:29:07 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-df9e3c4b-324a-4024-b621-354e16f87488 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440763269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2440763269 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.4135641690 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 3388449974 ps |
| CPU time | 193.56 seconds |
| Started | Jul 09 07:28:25 PM PDT 24 |
| Finished | Jul 09 07:31:41 PM PDT 24 |
| Peak memory | 599068 kb |
| Host | smart-beb01966-99cf-422d-999f-9aa6bdbc55c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135641690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.4135641690 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.715808316 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2991231912 ps |
| CPU time | 124.3 seconds |
| Started | Jul 09 07:28:34 PM PDT 24 |
| Finished | Jul 09 07:30:41 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-2cba16d6-3dff-424f-8ef4-6b5494057832 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715808316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device. 715808316 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.860201063 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 72146306785 ps |
| CPU time | 1348.3 seconds |
| Started | Jul 09 07:28:30 PM PDT 24 |
| Finished | Jul 09 07:51:01 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-7778d737-13ce-4d61-aace-80993fc07eb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860201063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_d evice_slow_rsp.860201063 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.2045804375 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 516526507 ps |
| CPU time | 18.27 seconds |
| Started | Jul 09 07:28:40 PM PDT 24 |
| Finished | Jul 09 07:29:02 PM PDT 24 |
| Peak memory | 576464 kb |
| Host | smart-5c73aead-f060-4fcb-8535-239537e34abf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045804375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.2045804375 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.2586157306 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 358017986 ps |
| CPU time | 14.46 seconds |
| Started | Jul 09 07:28:33 PM PDT 24 |
| Finished | Jul 09 07:28:50 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-dc6473fd-906c-4a9d-9d92-c03ace34bfa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586157306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2586157306 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.4100365249 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 499025699 ps |
| CPU time | 41.11 seconds |
| Started | Jul 09 07:28:32 PM PDT 24 |
| Finished | Jul 09 07:29:15 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-b85bfc96-2dff-4432-8e92-309658ab34c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100365249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.4100365249 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.572006819 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 6988266939 ps |
| CPU time | 72.64 seconds |
| Started | Jul 09 07:28:32 PM PDT 24 |
| Finished | Jul 09 07:29:47 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-aca2a4d0-aec5-4a65-a61c-0b3fbb56d4c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572006819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.572006819 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.3097496209 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 18066398313 ps |
| CPU time | 280.42 seconds |
| Started | Jul 09 07:28:41 PM PDT 24 |
| Finished | Jul 09 07:33:26 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-a6623607-edd1-4e71-9bd6-c7752b675cac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097496209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3097496209 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.3427607969 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 203956225 ps |
| CPU time | 22.52 seconds |
| Started | Jul 09 07:28:32 PM PDT 24 |
| Finished | Jul 09 07:28:56 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-d61031bf-9caa-44e2-8a4d-5639ed7de714 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427607969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.3427607969 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.3481720848 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1937550129 ps |
| CPU time | 57.63 seconds |
| Started | Jul 09 07:28:32 PM PDT 24 |
| Finished | Jul 09 07:29:31 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-ecd0e799-09ee-42f7-b679-8907a9fef9ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481720848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3481720848 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.560610808 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 131977932 ps |
| CPU time | 8 seconds |
| Started | Jul 09 07:28:28 PM PDT 24 |
| Finished | Jul 09 07:28:38 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-24c6d01a-e1bb-4cdd-b6a2-4f180fc8e867 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560610808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.560610808 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.2024873194 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 6568526708 ps |
| CPU time | 63.14 seconds |
| Started | Jul 09 07:28:40 PM PDT 24 |
| Finished | Jul 09 07:29:47 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-8b16bcd8-2fe5-4cb2-805c-4d3a905b97d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024873194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2024873194 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.247385685 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 4918511654 ps |
| CPU time | 81.84 seconds |
| Started | Jul 09 07:28:33 PM PDT 24 |
| Finished | Jul 09 07:29:57 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-18040ee4-53d6-4362-bda3-5a345b7d0a05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247385685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.247385685 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.4271020710 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 48652538 ps |
| CPU time | 6.53 seconds |
| Started | Jul 09 07:28:25 PM PDT 24 |
| Finished | Jul 09 07:28:34 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-2777a15b-f2a4-4869-b994-5bff23f5c8e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271020710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.4271020710 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.801608984 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 3746778141 ps |
| CPU time | 278.13 seconds |
| Started | Jul 09 07:28:36 PM PDT 24 |
| Finished | Jul 09 07:33:16 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-b615287d-ab53-4f9a-be4d-e3a15c1364a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801608984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.801608984 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.227974890 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 2742745530 ps |
| CPU time | 204.99 seconds |
| Started | Jul 09 07:28:43 PM PDT 24 |
| Finished | Jul 09 07:32:13 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-34979832-3971-46a4-a7c7-e8fd152ab07c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227974890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.227974890 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.814909479 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 126377140 ps |
| CPU time | 55.99 seconds |
| Started | Jul 09 07:28:42 PM PDT 24 |
| Finished | Jul 09 07:29:43 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-1fcd936f-0070-4efd-a70c-e0bf62255ecd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814909479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_ with_rand_reset.814909479 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.2896893932 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 3213232475 ps |
| CPU time | 236.84 seconds |
| Started | Jul 09 07:28:40 PM PDT 24 |
| Finished | Jul 09 07:32:41 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-8edc5ba8-f9a4-4037-8652-a65ccec5f37a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896893932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.2896893932 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.163543075 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 577882256 ps |
| CPU time | 24.8 seconds |
| Started | Jul 09 07:28:36 PM PDT 24 |
| Finished | Jul 09 07:29:02 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-c2ebb088-bb7e-4943-8d0c-9c3289afa82b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163543075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.163543075 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.2195718461 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 2340768088 ps |
| CPU time | 93.39 seconds |
| Started | Jul 09 07:28:40 PM PDT 24 |
| Finished | Jul 09 07:30:17 PM PDT 24 |
| Peak memory | 604020 kb |
| Host | smart-d57b5dc3-e37f-40c2-a44e-6f685468d944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195718461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.2195718461 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.1647365240 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 2379054341 ps |
| CPU time | 101.9 seconds |
| Started | Jul 09 07:28:48 PM PDT 24 |
| Finished | Jul 09 07:30:36 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-10f33bd6-d62a-4308-b4b4-5d91fed73627 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647365240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .1647365240 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.435486007 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 94362613627 ps |
| CPU time | 1713.09 seconds |
| Started | Jul 09 07:28:48 PM PDT 24 |
| Finished | Jul 09 07:57:28 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-168f2e83-ed0e-4440-8bb7-02d650c8646d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435486007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_d evice_slow_rsp.435486007 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.1752958470 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 191887473 ps |
| CPU time | 19.22 seconds |
| Started | Jul 09 07:28:55 PM PDT 24 |
| Finished | Jul 09 07:29:21 PM PDT 24 |
| Peak memory | 576464 kb |
| Host | smart-23237277-3782-4b05-be9a-e126b8014fb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752958470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.1752958470 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.1171022727 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 595784834 ps |
| CPU time | 47.06 seconds |
| Started | Jul 09 07:28:46 PM PDT 24 |
| Finished | Jul 09 07:29:39 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-b1f872f7-db51-4e47-8f50-f1f4f6f462e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171022727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1171022727 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.1850474925 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 201532069 ps |
| CPU time | 11.19 seconds |
| Started | Jul 09 07:28:47 PM PDT 24 |
| Finished | Jul 09 07:29:04 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-219243bd-a2d8-4f4d-8107-0f87f551ba4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850474925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.1850474925 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.3806784510 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 58495584972 ps |
| CPU time | 618.4 seconds |
| Started | Jul 09 07:28:47 PM PDT 24 |
| Finished | Jul 09 07:39:11 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-6b8b5f82-9326-4db9-8224-ca01212303e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806784510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3806784510 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.2050359842 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 17371317401 ps |
| CPU time | 282.41 seconds |
| Started | Jul 09 07:28:48 PM PDT 24 |
| Finished | Jul 09 07:33:37 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-9f9cb125-1d73-4eec-9745-f399618ac58b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050359842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2050359842 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.2237581152 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 615364634 ps |
| CPU time | 53.48 seconds |
| Started | Jul 09 07:28:48 PM PDT 24 |
| Finished | Jul 09 07:29:47 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-49ac281a-b5f8-4bfc-8e2d-1e31b6861235 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237581152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.2237581152 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.3597748474 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 267838457 ps |
| CPU time | 19.88 seconds |
| Started | Jul 09 07:28:47 PM PDT 24 |
| Finished | Jul 09 07:29:13 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-bf6af4fc-cd58-49a6-b6a4-831e4026af3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597748474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3597748474 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.3743573176 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 177331730 ps |
| CPU time | 8.54 seconds |
| Started | Jul 09 07:28:39 PM PDT 24 |
| Finished | Jul 09 07:28:51 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-188196ce-ffb6-4f07-8b8a-a991a9287718 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743573176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3743573176 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.2492741558 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 8007874416 ps |
| CPU time | 83.29 seconds |
| Started | Jul 09 07:28:39 PM PDT 24 |
| Finished | Jul 09 07:30:06 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-1ccf703f-c631-4555-a81e-1d557d8d88a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492741558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2492741558 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.3793733105 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 3969858958 ps |
| CPU time | 74.02 seconds |
| Started | Jul 09 07:28:40 PM PDT 24 |
| Finished | Jul 09 07:29:59 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-92af18cb-0117-49f4-9261-f229a1d94582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793733105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3793733105 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.4264394653 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 52497391 ps |
| CPU time | 6.81 seconds |
| Started | Jul 09 07:28:42 PM PDT 24 |
| Finished | Jul 09 07:28:54 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-42e643f3-40ec-4040-9bc1-a4ac883fcc63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264394653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.4264394653 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.1142433612 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 16694947602 ps |
| CPU time | 692.79 seconds |
| Started | Jul 09 07:28:54 PM PDT 24 |
| Finished | Jul 09 07:40:34 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-0025f6ed-d8bb-43e8-9091-45c6d82e9977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142433612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1142433612 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.356359684 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 1585508923 ps |
| CPU time | 127.02 seconds |
| Started | Jul 09 07:28:55 PM PDT 24 |
| Finished | Jul 09 07:31:09 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-bcc6ec3f-5683-4c33-912d-b3ce7e5d8973 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356359684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.356359684 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3863478886 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 1042863616 ps |
| CPU time | 293.06 seconds |
| Started | Jul 09 07:28:54 PM PDT 24 |
| Finished | Jul 09 07:33:55 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-11443927-5a61-4201-9029-d6bcce135c86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863478886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.3863478886 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.730725816 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 18461684682 ps |
| CPU time | 723.3 seconds |
| Started | Jul 09 07:28:55 PM PDT 24 |
| Finished | Jul 09 07:41:06 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-afa6000c-f3eb-4255-a585-b85a575b7c57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730725816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_reset_error.730725816 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.1537171807 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 133151629 ps |
| CPU time | 15.94 seconds |
| Started | Jul 09 07:28:52 PM PDT 24 |
| Finished | Jul 09 07:29:14 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-7cc86d07-7fa1-4099-9e6a-96144889d334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537171807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1537171807 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.3181030963 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 3337457189 ps |
| CPU time | 186.67 seconds |
| Started | Jul 09 07:28:53 PM PDT 24 |
| Finished | Jul 09 07:32:07 PM PDT 24 |
| Peak memory | 601868 kb |
| Host | smart-b26441c7-3451-4c4d-8e45-03c60c5c39b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181030963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.3181030963 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.1151201819 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 376484813 ps |
| CPU time | 32.52 seconds |
| Started | Jul 09 07:29:04 PM PDT 24 |
| Finished | Jul 09 07:29:47 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-151689ce-0529-4905-b8ce-68990c620fee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151201819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .1151201819 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1124051406 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 59054368470 ps |
| CPU time | 952.24 seconds |
| Started | Jul 09 07:29:02 PM PDT 24 |
| Finished | Jul 09 07:45:04 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-53845fbe-5573-4b3f-a9b0-d0346a4761b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124051406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.1124051406 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.2773212725 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 619533322 ps |
| CPU time | 22.9 seconds |
| Started | Jul 09 07:29:07 PM PDT 24 |
| Finished | Jul 09 07:29:41 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-4ae8ab37-7b5e-4cdd-9645-b51b3f172b28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773212725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.2773212725 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.503498166 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 1634868600 ps |
| CPU time | 63.36 seconds |
| Started | Jul 09 07:29:02 PM PDT 24 |
| Finished | Jul 09 07:30:14 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-146809bb-dfd2-4299-94c0-9d7ac95e06c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503498166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.503498166 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.2775785119 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 158907734 ps |
| CPU time | 9.11 seconds |
| Started | Jul 09 07:28:53 PM PDT 24 |
| Finished | Jul 09 07:29:10 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-4d2a8664-d649-4177-9f74-aa9b368c0078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775785119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.2775785119 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.3687390883 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 89979135735 ps |
| CPU time | 871.38 seconds |
| Started | Jul 09 07:28:54 PM PDT 24 |
| Finished | Jul 09 07:43:32 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-6d4555b2-5c01-4189-abbc-7c6116a78cb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687390883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3687390883 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.246010799 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 29495420378 ps |
| CPU time | 525.38 seconds |
| Started | Jul 09 07:28:55 PM PDT 24 |
| Finished | Jul 09 07:37:48 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-73acf284-2fd8-4862-96f1-ed5d7c11b96a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246010799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.246010799 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.2245657924 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 98173332 ps |
| CPU time | 10.88 seconds |
| Started | Jul 09 07:28:54 PM PDT 24 |
| Finished | Jul 09 07:29:12 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-0e67b509-cb1a-425f-9dc7-76c3db98a6f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245657924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.2245657924 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.1083847075 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 412565040 ps |
| CPU time | 31.46 seconds |
| Started | Jul 09 07:29:03 PM PDT 24 |
| Finished | Jul 09 07:29:44 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-672c2622-3e55-48da-938a-de9a6b08f45a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083847075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1083847075 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.1367363572 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 222705724 ps |
| CPU time | 9.6 seconds |
| Started | Jul 09 07:28:53 PM PDT 24 |
| Finished | Jul 09 07:29:10 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-40378c14-25c9-48cc-9137-bb76b272f74c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367363572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1367363572 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.3763398382 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 8678947308 ps |
| CPU time | 87.7 seconds |
| Started | Jul 09 07:28:57 PM PDT 24 |
| Finished | Jul 09 07:30:33 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-0e4321d9-012d-4c73-8f11-c74628ef3340 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763398382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3763398382 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1062201205 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 5469590954 ps |
| CPU time | 94.71 seconds |
| Started | Jul 09 07:28:54 PM PDT 24 |
| Finished | Jul 09 07:30:36 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-edac5e86-2598-492d-9204-e38e6f7cb059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062201205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1062201205 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.362519301 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 53447791 ps |
| CPU time | 6.42 seconds |
| Started | Jul 09 07:29:36 PM PDT 24 |
| Finished | Jul 09 07:29:44 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-648cfa35-a46a-4d70-ab24-4359db427b3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362519301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays .362519301 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.3727519931 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 1810522952 ps |
| CPU time | 133.28 seconds |
| Started | Jul 09 07:29:02 PM PDT 24 |
| Finished | Jul 09 07:31:25 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-f68a8135-6d5d-44d1-a29d-1bb7ac0dc6d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727519931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3727519931 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.1843330338 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 8616699130 ps |
| CPU time | 501.17 seconds |
| Started | Jul 09 07:29:08 PM PDT 24 |
| Finished | Jul 09 07:37:40 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-b302fc44-bd4d-4f1e-8f24-c4407d9faccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843330338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.1843330338 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.467734792 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 1166519772 ps |
| CPU time | 51.25 seconds |
| Started | Jul 09 07:29:03 PM PDT 24 |
| Finished | Jul 09 07:30:04 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-6c986fcb-bf1c-4dad-8d25-3f553eb149d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467734792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.467734792 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.2609950127 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 3297429880 ps |
| CPU time | 212.43 seconds |
| Started | Jul 09 07:29:02 PM PDT 24 |
| Finished | Jul 09 07:32:43 PM PDT 24 |
| Peak memory | 603976 kb |
| Host | smart-a7cf3168-ee8e-4dfc-81fe-6f391bc5cf46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609950127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.2609950127 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.2823763435 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 1328517591 ps |
| CPU time | 58.95 seconds |
| Started | Jul 09 07:29:09 PM PDT 24 |
| Finished | Jul 09 07:30:20 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-df16768e-2c32-4023-9b99-20646627d649 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823763435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .2823763435 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1541472408 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 64839173758 ps |
| CPU time | 1229.08 seconds |
| Started | Jul 09 07:29:09 PM PDT 24 |
| Finished | Jul 09 07:49:51 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-9bc1c648-79d9-41ac-9e51-d489640f0ea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541472408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_ device_slow_rsp.1541472408 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2239880165 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 259554381 ps |
| CPU time | 13.04 seconds |
| Started | Jul 09 07:29:09 PM PDT 24 |
| Finished | Jul 09 07:29:34 PM PDT 24 |
| Peak memory | 576504 kb |
| Host | smart-b4a0509a-e012-4794-9795-3de01c591b98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239880165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.2239880165 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.107202245 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 790825093 ps |
| CPU time | 26 seconds |
| Started | Jul 09 07:29:12 PM PDT 24 |
| Finished | Jul 09 07:29:49 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-25642d69-c09a-437d-83f2-fee472ef001c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107202245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.107202245 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.3892129529 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 253345191 ps |
| CPU time | 23.49 seconds |
| Started | Jul 09 07:29:08 PM PDT 24 |
| Finished | Jul 09 07:29:43 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-5ee2b3d4-2a36-4400-9624-8267d18c8c3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892129529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.3892129529 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.1523814071 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 11597498948 ps |
| CPU time | 118.37 seconds |
| Started | Jul 09 07:29:08 PM PDT 24 |
| Finished | Jul 09 07:31:17 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-ede9c64e-f550-4d04-95cf-a89ba0921977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523814071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1523814071 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.74304798 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 67087946076 ps |
| CPU time | 1206.11 seconds |
| Started | Jul 09 07:29:07 PM PDT 24 |
| Finished | Jul 09 07:49:24 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-fd844b3a-bc2e-48c7-bb16-c9aa503ccb81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74304798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.74304798 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.837042894 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 362053194 ps |
| CPU time | 32.51 seconds |
| Started | Jul 09 07:29:09 PM PDT 24 |
| Finished | Jul 09 07:29:53 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-47f7bfe4-5dfa-40e3-aced-c4c8a1663cae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837042894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_dela ys.837042894 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.3492646772 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 2770561411 ps |
| CPU time | 77.52 seconds |
| Started | Jul 09 07:29:09 PM PDT 24 |
| Finished | Jul 09 07:30:38 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-f87332e0-ed3a-466b-b4dc-4e80125981dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492646772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3492646772 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.704085413 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 52459254 ps |
| CPU time | 6.95 seconds |
| Started | Jul 09 07:29:05 PM PDT 24 |
| Finished | Jul 09 07:29:22 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-162cea9c-da1f-451c-91f3-47155c2a9870 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704085413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.704085413 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.1031990621 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 9196299302 ps |
| CPU time | 98.2 seconds |
| Started | Jul 09 07:29:03 PM PDT 24 |
| Finished | Jul 09 07:30:50 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-c315dc9e-1f68-40e2-89e3-cd590a2fc33f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031990621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1031990621 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.2307423236 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 4637661981 ps |
| CPU time | 77.79 seconds |
| Started | Jul 09 07:29:08 PM PDT 24 |
| Finished | Jul 09 07:30:37 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-d90071e8-a7cb-4bcc-afc3-c545d3fea0fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307423236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2307423236 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.3613515464 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 53813474 ps |
| CPU time | 6.46 seconds |
| Started | Jul 09 07:29:03 PM PDT 24 |
| Finished | Jul 09 07:29:19 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-968ae031-883d-416f-aeb7-2d9a7ffbaa7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613515464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.3613515464 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.3309588987 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 1400867255 ps |
| CPU time | 113.75 seconds |
| Started | Jul 09 07:29:20 PM PDT 24 |
| Finished | Jul 09 07:31:23 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-840145af-c6d8-49bd-b5c1-a2e342666a7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309588987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3309588987 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.1866316880 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 2673970169 ps |
| CPU time | 222.07 seconds |
| Started | Jul 09 07:29:19 PM PDT 24 |
| Finished | Jul 09 07:33:11 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-e27f0e3d-bdef-443e-8b57-7869db7a3915 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866316880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1866316880 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2568839465 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 5126463472 ps |
| CPU time | 399.07 seconds |
| Started | Jul 09 07:29:19 PM PDT 24 |
| Finished | Jul 09 07:36:08 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-dc6a2c35-428c-415c-ba81-2e37e4e49158 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568839465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.2568839465 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.4167404313 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 9365479303 ps |
| CPU time | 546.31 seconds |
| Started | Jul 09 07:29:18 PM PDT 24 |
| Finished | Jul 09 07:38:35 PM PDT 24 |
| Peak memory | 577792 kb |
| Host | smart-3ba3e39e-aa88-4352-96f7-c8b90a66969b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167404313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.4167404313 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.1254573280 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 169633430 ps |
| CPU time | 22.32 seconds |
| Started | Jul 09 07:29:10 PM PDT 24 |
| Finished | Jul 09 07:29:44 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-60d4188f-fa43-4ab3-bbf5-57549e535d51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254573280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1254573280 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.1174666607 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 2739678904 ps |
| CPU time | 93.05 seconds |
| Started | Jul 09 07:29:17 PM PDT 24 |
| Finished | Jul 09 07:31:01 PM PDT 24 |
| Peak memory | 598936 kb |
| Host | smart-6a9c9841-df28-4eda-9041-4496275b8ab7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174666607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.1174666607 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.3908354746 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 1944710371 ps |
| CPU time | 74.68 seconds |
| Started | Jul 09 07:29:16 PM PDT 24 |
| Finished | Jul 09 07:30:42 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-f44b3ead-f510-4a64-b82a-1a148c8bb606 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908354746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .3908354746 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2394955812 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 130389714413 ps |
| CPU time | 2559.15 seconds |
| Started | Jul 09 07:29:17 PM PDT 24 |
| Finished | Jul 09 08:12:07 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-a634b0cd-8748-45f0-bc4f-02e238ba3089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394955812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.2394955812 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1113758237 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 313528892 ps |
| CPU time | 33.33 seconds |
| Started | Jul 09 07:29:17 PM PDT 24 |
| Finished | Jul 09 07:30:01 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-a6222bcf-0022-4358-95be-889127f29983 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113758237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.1113758237 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.2234845496 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 507814012 ps |
| CPU time | 47.4 seconds |
| Started | Jul 09 07:29:18 PM PDT 24 |
| Finished | Jul 09 07:30:16 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-cc3797b1-2357-4cd5-9779-543934142328 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234845496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2234845496 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.950834834 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 366409896 ps |
| CPU time | 32.91 seconds |
| Started | Jul 09 07:29:17 PM PDT 24 |
| Finished | Jul 09 07:30:01 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-bac35ee4-4b90-4711-a593-bf8bfbcc4aff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950834834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.950834834 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.2902423625 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 106203299704 ps |
| CPU time | 1159.56 seconds |
| Started | Jul 09 07:29:16 PM PDT 24 |
| Finished | Jul 09 07:48:48 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-86fdbbca-13e8-4ff3-a00e-840b4cae72f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902423625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.2902423625 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.2376678612 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 35114470189 ps |
| CPU time | 584 seconds |
| Started | Jul 09 07:29:17 PM PDT 24 |
| Finished | Jul 09 07:39:12 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-5a3463fa-4755-476a-a5d6-1c6d97a70162 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376678612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2376678612 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.209675400 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 595336338 ps |
| CPU time | 54.38 seconds |
| Started | Jul 09 07:29:16 PM PDT 24 |
| Finished | Jul 09 07:30:22 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-7de54b37-f19d-446e-b3dd-a9cd6775d78c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209675400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_dela ys.209675400 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.2272749663 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 424265871 ps |
| CPU time | 32.76 seconds |
| Started | Jul 09 07:29:21 PM PDT 24 |
| Finished | Jul 09 07:30:02 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-e4ba00f6-996e-4278-b760-b6621176a8d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272749663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2272749663 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.2200999659 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 50452455 ps |
| CPU time | 6.18 seconds |
| Started | Jul 09 07:29:16 PM PDT 24 |
| Finished | Jul 09 07:29:33 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-620acd4f-c230-4ff4-99aa-fab92dced6b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200999659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2200999659 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.3656627072 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 10065592437 ps |
| CPU time | 106.74 seconds |
| Started | Jul 09 07:29:16 PM PDT 24 |
| Finished | Jul 09 07:31:14 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-e8f4a1b9-5888-42ed-b075-0a743406ebcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656627072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3656627072 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1147588269 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 5382407881 ps |
| CPU time | 86.99 seconds |
| Started | Jul 09 07:29:17 PM PDT 24 |
| Finished | Jul 09 07:30:55 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-bad325f8-b259-411e-93a1-f70dd7d66834 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147588269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1147588269 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.1604694129 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 46756170 ps |
| CPU time | 6.65 seconds |
| Started | Jul 09 07:29:17 PM PDT 24 |
| Finished | Jul 09 07:29:34 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-d62b162e-6d90-434f-8405-088035e4fa72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604694129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.1604694129 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.2726695770 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 7735821371 ps |
| CPU time | 332.58 seconds |
| Started | Jul 09 07:29:16 PM PDT 24 |
| Finished | Jul 09 07:35:00 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-4ab7a6ce-63ae-4756-8f22-094498e0b1a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726695770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2726695770 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.2585492837 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 1738733780 ps |
| CPU time | 147.32 seconds |
| Started | Jul 09 07:29:26 PM PDT 24 |
| Finished | Jul 09 07:31:58 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-363ea59c-790c-4f33-94dc-be87ec1a930e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585492837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2585492837 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.445836775 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 320552077 ps |
| CPU time | 113.18 seconds |
| Started | Jul 09 07:29:24 PM PDT 24 |
| Finished | Jul 09 07:31:23 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-49feebdb-2310-4423-b288-e3fe8fde52cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445836775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_ with_rand_reset.445836775 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.71176076 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 3019855843 ps |
| CPU time | 384.09 seconds |
| Started | Jul 09 07:29:25 PM PDT 24 |
| Finished | Jul 09 07:35:55 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-6ecb6510-3383-4a7a-9e81-491169125966 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71176076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_ with_reset_error.71176076 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.1960404889 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 96521924 ps |
| CPU time | 7.7 seconds |
| Started | Jul 09 07:29:16 PM PDT 24 |
| Finished | Jul 09 07:29:35 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-45696135-26f7-46e5-9145-ca60477d21f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960404889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1960404889 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.2285245406 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 3124351090 ps |
| CPU time | 291.99 seconds |
| Started | Jul 09 07:29:24 PM PDT 24 |
| Finished | Jul 09 07:34:22 PM PDT 24 |
| Peak memory | 598892 kb |
| Host | smart-0ec66b04-7016-4522-a72c-75940dcaeff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285245406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.2285245406 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.991011378 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 1492461628 ps |
| CPU time | 74.72 seconds |
| Started | Jul 09 07:29:33 PM PDT 24 |
| Finished | Jul 09 07:30:50 PM PDT 24 |
| Peak memory | 576460 kb |
| Host | smart-3c1e2f1c-66fc-4791-8aba-33376e764fb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991011378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device. 991011378 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.4045252591 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 104034630149 ps |
| CPU time | 1857.61 seconds |
| Started | Jul 09 07:29:32 PM PDT 24 |
| Finished | Jul 09 08:00:32 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-56fb83a8-ff63-4b0b-8bfb-9fbe9a50966c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045252591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.4045252591 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.425115491 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 422447259 ps |
| CPU time | 20.73 seconds |
| Started | Jul 09 07:29:34 PM PDT 24 |
| Finished | Jul 09 07:29:56 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-f203840e-cd0d-4424-90f1-11d98ee63d1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425115491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr .425115491 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.2453256207 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 253045469 ps |
| CPU time | 11.93 seconds |
| Started | Jul 09 07:29:32 PM PDT 24 |
| Finished | Jul 09 07:29:46 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-5495e7aa-6a0f-412f-8c43-51a1a2146dbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453256207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2453256207 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.2100132949 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1649749968 ps |
| CPU time | 69.01 seconds |
| Started | Jul 09 07:29:25 PM PDT 24 |
| Finished | Jul 09 07:30:39 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-e1b5e242-b80a-4e19-aaaa-67d92b35f949 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100132949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.2100132949 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.3425587587 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 76107152556 ps |
| CPU time | 799.3 seconds |
| Started | Jul 09 07:29:26 PM PDT 24 |
| Finished | Jul 09 07:42:50 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-19d6ff5a-beb6-4595-8bc6-399415159c16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425587587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.3425587587 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.2170758752 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 66703550511 ps |
| CPU time | 1277.25 seconds |
| Started | Jul 09 07:29:24 PM PDT 24 |
| Finished | Jul 09 07:50:48 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-f352cf03-41d5-4210-8c6a-c1373512b348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170758752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2170758752 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.4099034717 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 427326749 ps |
| CPU time | 33.44 seconds |
| Started | Jul 09 07:29:23 PM PDT 24 |
| Finished | Jul 09 07:30:03 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-298ad97e-d8ad-4adf-9a47-d44b02faec7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099034717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.4099034717 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.1043368069 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 751406399 ps |
| CPU time | 24.04 seconds |
| Started | Jul 09 07:29:34 PM PDT 24 |
| Finished | Jul 09 07:29:59 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-abe8127e-b910-46db-a985-6e026c19b5ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043368069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1043368069 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.1017722836 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 226597441 ps |
| CPU time | 9.68 seconds |
| Started | Jul 09 07:29:27 PM PDT 24 |
| Finished | Jul 09 07:29:41 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-c260e3dc-d8d0-4af8-8c4e-d5ece8911131 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017722836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1017722836 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.1166947750 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 8635443723 ps |
| CPU time | 96.63 seconds |
| Started | Jul 09 07:29:23 PM PDT 24 |
| Finished | Jul 09 07:31:07 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-3132b2c6-a8da-4751-9d9a-a8baf7858532 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166947750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1166947750 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.1078794543 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 4322091609 ps |
| CPU time | 72.85 seconds |
| Started | Jul 09 07:29:22 PM PDT 24 |
| Finished | Jul 09 07:30:43 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-624f2862-a913-43d3-a54a-ee8d3bcaa4f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078794543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1078794543 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.516360607 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 49082992 ps |
| CPU time | 7.28 seconds |
| Started | Jul 09 07:29:24 PM PDT 24 |
| Finished | Jul 09 07:29:37 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-4fb2abfd-1ee9-4605-86fd-1e5e5dabd0e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516360607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays .516360607 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.1423341944 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 1221790805 ps |
| CPU time | 44.5 seconds |
| Started | Jul 09 07:29:32 PM PDT 24 |
| Finished | Jul 09 07:30:18 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-f8a42800-200a-45df-9b4a-661d79fec685 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423341944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1423341944 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3142906426 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 16324587129 ps |
| CPU time | 578.52 seconds |
| Started | Jul 09 07:29:32 PM PDT 24 |
| Finished | Jul 09 07:39:13 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-060ec272-f92f-49a9-aaa6-4ebfe6968eb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142906426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3142906426 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.3885502172 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 22469703736 ps |
| CPU time | 1077.83 seconds |
| Started | Jul 09 07:29:33 PM PDT 24 |
| Finished | Jul 09 07:47:34 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-e46a285b-40c1-42b9-950e-94e215b8131f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885502172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.3885502172 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.843205327 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 361667478 ps |
| CPU time | 125.34 seconds |
| Started | Jul 09 07:29:34 PM PDT 24 |
| Finished | Jul 09 07:31:41 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-f6da6975-bfef-4794-8eaf-cf20bd8ecd73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843205327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_reset_error.843205327 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.375538440 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 833786177 ps |
| CPU time | 35.07 seconds |
| Started | Jul 09 07:29:31 PM PDT 24 |
| Finished | Jul 09 07:30:08 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-1abde1d2-8b58-470f-bef4-f71388d86165 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375538440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.375538440 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.2279156109 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 2753796000 ps |
| CPU time | 85.49 seconds |
| Started | Jul 09 07:29:32 PM PDT 24 |
| Finished | Jul 09 07:30:59 PM PDT 24 |
| Peak memory | 598904 kb |
| Host | smart-c582d59a-ba00-4f05-ae30-7e90a99ff490 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279156109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.2279156109 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.4012766958 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 1862643296 ps |
| CPU time | 80.74 seconds |
| Started | Jul 09 07:29:40 PM PDT 24 |
| Finished | Jul 09 07:31:03 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-eb515540-66ac-4405-b230-a5767c79e94c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012766958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .4012766958 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.1139160559 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 61525108950 ps |
| CPU time | 1060.75 seconds |
| Started | Jul 09 07:29:39 PM PDT 24 |
| Finished | Jul 09 07:47:22 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-44bd9373-2147-4266-9901-f19da8f57a2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139160559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.1139160559 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.789791033 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 1328884422 ps |
| CPU time | 54.74 seconds |
| Started | Jul 09 07:29:53 PM PDT 24 |
| Finished | Jul 09 07:30:50 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-c0c01df0-7b38-458c-b375-d1dd52c4b375 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789791033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr .789791033 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.1905972706 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 2012189232 ps |
| CPU time | 74.62 seconds |
| Started | Jul 09 07:29:48 PM PDT 24 |
| Finished | Jul 09 07:31:06 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-19789536-a6f6-4363-9cb9-ce10822554f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905972706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1905972706 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.1130869795 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 1255657530 ps |
| CPU time | 44.53 seconds |
| Started | Jul 09 07:29:41 PM PDT 24 |
| Finished | Jul 09 07:30:28 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-27e25be9-4a9f-4029-bc2d-e961ec268142 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130869795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.1130869795 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.2413941153 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 71020766101 ps |
| CPU time | 722.96 seconds |
| Started | Jul 09 07:29:39 PM PDT 24 |
| Finished | Jul 09 07:41:44 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-6013caf0-37a1-48f2-bbe7-c9cbb312731a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413941153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2413941153 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.3595692249 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 33527430727 ps |
| CPU time | 579.88 seconds |
| Started | Jul 09 07:29:39 PM PDT 24 |
| Finished | Jul 09 07:39:21 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-ca43a99d-9275-47a6-b343-3dfc0b452ff5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595692249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3595692249 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.1668641240 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 45413517 ps |
| CPU time | 6.67 seconds |
| Started | Jul 09 07:29:41 PM PDT 24 |
| Finished | Jul 09 07:29:50 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-cfe07cbc-7f9e-4cad-b2ca-747fb88dad12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668641240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.1668641240 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.2774717201 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 2107937521 ps |
| CPU time | 64.34 seconds |
| Started | Jul 09 07:29:39 PM PDT 24 |
| Finished | Jul 09 07:30:45 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-39e23493-7dd3-4d96-ba80-226c67a0dc50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774717201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2774717201 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.364927773 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 165314024 ps |
| CPU time | 8.6 seconds |
| Started | Jul 09 07:29:38 PM PDT 24 |
| Finished | Jul 09 07:29:49 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-8baea921-6b04-4673-912d-2ef0e6df9dc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364927773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.364927773 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.1721784122 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 8382523278 ps |
| CPU time | 89.6 seconds |
| Started | Jul 09 07:29:40 PM PDT 24 |
| Finished | Jul 09 07:31:12 PM PDT 24 |
| Peak memory | 574576 kb |
| Host | smart-bd741338-9630-4cdf-a1d5-2ee760209d7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721784122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1721784122 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.2738604020 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 5731474877 ps |
| CPU time | 99.28 seconds |
| Started | Jul 09 07:29:39 PM PDT 24 |
| Finished | Jul 09 07:31:20 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-31ce0f1c-73d3-4bc6-af38-72ee12372e54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738604020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2738604020 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1951929822 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 45671116 ps |
| CPU time | 5.85 seconds |
| Started | Jul 09 07:29:39 PM PDT 24 |
| Finished | Jul 09 07:29:47 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-b77f815c-6daf-4872-89cb-944dfa24c845 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951929822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.1951929822 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.2881836369 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 2247003008 ps |
| CPU time | 82.82 seconds |
| Started | Jul 09 07:29:49 PM PDT 24 |
| Finished | Jul 09 07:31:15 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-93ef8ad3-d43e-4745-a7c5-9fca18ddaaf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881836369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2881836369 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.49700242 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 14726099167 ps |
| CPU time | 580.32 seconds |
| Started | Jul 09 07:29:51 PM PDT 24 |
| Finished | Jul 09 07:39:34 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-865921da-4de5-4ea9-97ff-1a06a2620a9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49700242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.49700242 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1338741167 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 2121972434 ps |
| CPU time | 258.18 seconds |
| Started | Jul 09 07:29:51 PM PDT 24 |
| Finished | Jul 09 07:34:12 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-2901caa4-aceb-400a-94f4-d865e6aebc44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338741167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.1338741167 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.2197285742 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 1092196639 ps |
| CPU time | 50.34 seconds |
| Started | Jul 09 07:29:55 PM PDT 24 |
| Finished | Jul 09 07:30:47 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-14730499-d3ff-46ff-9ad4-e4e70f39f990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197285742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2197285742 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.3908298318 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 3170371850 ps |
| CPU time | 157.05 seconds |
| Started | Jul 09 07:29:49 PM PDT 24 |
| Finished | Jul 09 07:32:29 PM PDT 24 |
| Peak memory | 604036 kb |
| Host | smart-75fd407f-3bfc-49e3-8fe6-fe05c5d3cf0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908298318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.3908298318 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.3983536462 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 383137308 ps |
| CPU time | 19.13 seconds |
| Started | Jul 09 07:30:04 PM PDT 24 |
| Finished | Jul 09 07:30:28 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-107393e3-640d-4c2a-ab1c-624ee5c9d16c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983536462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .3983536462 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.3816083301 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 123293061278 ps |
| CPU time | 2359.46 seconds |
| Started | Jul 09 07:30:03 PM PDT 24 |
| Finished | Jul 09 08:09:27 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-0d963d82-eff4-4da3-9d5e-a4318e9af16e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816083301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.3816083301 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.124767688 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 1005088695 ps |
| CPU time | 40.41 seconds |
| Started | Jul 09 07:30:00 PM PDT 24 |
| Finished | Jul 09 07:30:43 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-dd1c8661-8b54-4b1c-bf29-8df564e65513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124767688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr .124767688 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.2373555959 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2116431628 ps |
| CPU time | 63.99 seconds |
| Started | Jul 09 07:30:04 PM PDT 24 |
| Finished | Jul 09 07:31:12 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-8fef121b-085f-40f7-bd51-deb3773e4712 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373555959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2373555959 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.507397786 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 150658745 ps |
| CPU time | 15.4 seconds |
| Started | Jul 09 07:30:04 PM PDT 24 |
| Finished | Jul 09 07:30:25 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-c1d83f72-e0a7-4e55-a1f2-57ed0d636ef3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507397786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.507397786 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.1926472335 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 66857439413 ps |
| CPU time | 635.34 seconds |
| Started | Jul 09 07:30:03 PM PDT 24 |
| Finished | Jul 09 07:40:43 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-63f2cab8-d4ff-492f-b54e-f520e2e91ffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926472335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1926472335 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.3706180493 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 61587219067 ps |
| CPU time | 1098.27 seconds |
| Started | Jul 09 07:30:02 PM PDT 24 |
| Finished | Jul 09 07:48:24 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-cdf59070-1c58-4bd8-b71e-28decbfb7580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706180493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3706180493 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.4040544278 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 630897814 ps |
| CPU time | 52.87 seconds |
| Started | Jul 09 07:30:04 PM PDT 24 |
| Finished | Jul 09 07:31:01 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-cf3528dd-ddd5-40c2-856d-f50d6758f09b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040544278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.4040544278 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.1229506810 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 569736423 ps |
| CPU time | 21 seconds |
| Started | Jul 09 07:30:04 PM PDT 24 |
| Finished | Jul 09 07:30:31 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-c4264adb-f59a-4a47-b139-d702872b5a54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229506810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1229506810 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.245105166 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 194964573 ps |
| CPU time | 9.41 seconds |
| Started | Jul 09 07:29:49 PM PDT 24 |
| Finished | Jul 09 07:30:01 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-2e64d817-e3cf-456c-9b16-754ae8554dd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245105166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.245105166 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.721219371 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 6042282535 ps |
| CPU time | 65.2 seconds |
| Started | Jul 09 07:30:04 PM PDT 24 |
| Finished | Jul 09 07:31:14 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-6f8c6940-1f76-429d-8b4a-f6325614c6be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721219371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.721219371 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.3119932413 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 5919317694 ps |
| CPU time | 98.68 seconds |
| Started | Jul 09 07:30:03 PM PDT 24 |
| Finished | Jul 09 07:31:45 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-9fedb3a3-d842-441a-8d47-85c9e4672f82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119932413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3119932413 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.893357116 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 52908611 ps |
| CPU time | 6.67 seconds |
| Started | Jul 09 07:29:49 PM PDT 24 |
| Finished | Jul 09 07:29:59 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-61f9e691-cc83-4aa0-aa2e-b9a2e3accd80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893357116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays .893357116 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.3004383312 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 3245806178 ps |
| CPU time | 247.26 seconds |
| Started | Jul 09 07:30:18 PM PDT 24 |
| Finished | Jul 09 07:34:32 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-22a41cae-1348-4e53-b4c2-365ee9c28fbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004383312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3004383312 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.2083509547 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 3891078050 ps |
| CPU time | 275.04 seconds |
| Started | Jul 09 07:30:22 PM PDT 24 |
| Finished | Jul 09 07:35:03 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-5708a853-951c-48f0-86f5-90ca1b5f1ce4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083509547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2083509547 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.4103912097 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 3789460975 ps |
| CPU time | 406.67 seconds |
| Started | Jul 09 07:30:17 PM PDT 24 |
| Finished | Jul 09 07:37:10 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-c45940a9-6ae9-4ff9-952e-aacc25a7c503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103912097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.4103912097 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2295788434 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 2041238754 ps |
| CPU time | 226.6 seconds |
| Started | Jul 09 07:30:18 PM PDT 24 |
| Finished | Jul 09 07:34:11 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-bb220d81-35a7-4076-9a88-41153d4d8896 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295788434 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.2295788434 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.1401210962 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 235769916 ps |
| CPU time | 28.88 seconds |
| Started | Jul 09 07:30:04 PM PDT 24 |
| Finished | Jul 09 07:30:38 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-d1ef84f4-64b5-41dd-a98b-dd46704bd1cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401210962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1401210962 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.2720722425 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 40470363880 ps |
| CPU time | 6576.25 seconds |
| Started | Jul 09 07:25:36 PM PDT 24 |
| Finished | Jul 09 09:15:26 PM PDT 24 |
| Peak memory | 593888 kb |
| Host | smart-5e30d202-c84e-4899-ba75-cb41a5bf6644 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720722425 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.2720722425 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.2617231132 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 62417586450 ps |
| CPU time | 6532.84 seconds |
| Started | Jul 09 07:25:22 PM PDT 24 |
| Finished | Jul 09 09:14:25 PM PDT 24 |
| Peak memory | 591600 kb |
| Host | smart-2d527be5-5195-41ae-aabd-37e50e29aeb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617231132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.2617231132 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.2223890325 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 3722120449 ps |
| CPU time | 227.47 seconds |
| Started | Jul 09 07:25:36 PM PDT 24 |
| Finished | Jul 09 07:29:36 PM PDT 24 |
| Peak memory | 597452 kb |
| Host | smart-62d63439-b3d4-452c-ab5a-37dc0c2a9e93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223890325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.2223890325 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.3376745127 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 27958076602 ps |
| CPU time | 2979.62 seconds |
| Started | Jul 09 07:25:37 PM PDT 24 |
| Finished | Jul 09 08:15:31 PM PDT 24 |
| Peak memory | 593748 kb |
| Host | smart-2d3bfffa-e799-4f3e-a9ff-e3ed39e89d32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376745127 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.3376745127 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.2379470280 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 3706687610 ps |
| CPU time | 261.09 seconds |
| Started | Jul 09 07:25:28 PM PDT 24 |
| Finished | Jul 09 07:30:01 PM PDT 24 |
| Peak memory | 604028 kb |
| Host | smart-f751aea4-63d0-4ba6-9b1c-c6773947f344 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379470280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.2379470280 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.257566471 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 1124596924 ps |
| CPU time | 74.22 seconds |
| Started | Jul 09 07:25:24 PM PDT 24 |
| Finished | Jul 09 07:26:49 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-81763158-948d-4966-8af3-7dfcc89be52d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257566471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.257566471 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.3262319116 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 21465069 ps |
| CPU time | 5.35 seconds |
| Started | Jul 09 07:25:32 PM PDT 24 |
| Finished | Jul 09 07:25:49 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-40efbdf7-97f0-4e3b-a9bf-c6830af5f2f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262319116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .3262319116 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.3148522640 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 999389355 ps |
| CPU time | 28.61 seconds |
| Started | Jul 09 07:25:36 PM PDT 24 |
| Finished | Jul 09 07:26:16 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-6ac06914-84c2-4346-855f-db4f92816666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148522640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3148522640 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.3432686886 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 588952220 ps |
| CPU time | 44.83 seconds |
| Started | Jul 09 07:25:25 PM PDT 24 |
| Finished | Jul 09 07:26:21 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-7593f423-802b-4f0d-abf2-159fdf97a0d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432686886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.3432686886 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.2838024950 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 107675699018 ps |
| CPU time | 1156.29 seconds |
| Started | Jul 09 07:25:24 PM PDT 24 |
| Finished | Jul 09 07:44:51 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-3d0a339d-12ee-4c32-a48b-fb101a231354 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838024950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2838024950 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.1560784505 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 55636332878 ps |
| CPU time | 891.94 seconds |
| Started | Jul 09 07:25:34 PM PDT 24 |
| Finished | Jul 09 07:40:38 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-7a2baaf3-5a5f-4703-9fab-5d72a381394a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560784505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1560784505 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.1523324206 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 282605939 ps |
| CPU time | 25.03 seconds |
| Started | Jul 09 07:25:23 PM PDT 24 |
| Finished | Jul 09 07:25:58 PM PDT 24 |
| Peak memory | 576504 kb |
| Host | smart-def5c151-205e-4c23-af80-8ffda2ebdee9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523324206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.1523324206 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.3415957562 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 2384195237 ps |
| CPU time | 66.69 seconds |
| Started | Jul 09 07:25:37 PM PDT 24 |
| Finished | Jul 09 07:26:57 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-9585efe9-b673-4edb-9a8b-d0653cdc0a50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415957562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.3415957562 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.2344129999 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 167943429 ps |
| CPU time | 7.75 seconds |
| Started | Jul 09 07:25:37 PM PDT 24 |
| Finished | Jul 09 07:25:57 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-ba4e76d2-c64c-4a1d-a259-50106c28d41d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344129999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2344129999 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.3154053427 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 9071358599 ps |
| CPU time | 99.71 seconds |
| Started | Jul 09 07:25:37 PM PDT 24 |
| Finished | Jul 09 07:27:29 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-f691d9f8-c3b7-4e56-83c4-a8c6b8e2a01b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154053427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3154053427 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2084739456 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 5224311379 ps |
| CPU time | 94.02 seconds |
| Started | Jul 09 07:25:27 PM PDT 24 |
| Finished | Jul 09 07:27:12 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-76a8e035-f300-4ccb-8863-845fd52474fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084739456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2084739456 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.3478241416 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 35333249 ps |
| CPU time | 5.34 seconds |
| Started | Jul 09 07:25:24 PM PDT 24 |
| Finished | Jul 09 07:25:40 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-28f22179-1963-43f5-9f73-8d83828753f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478241416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .3478241416 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.3134806480 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 3226499629 ps |
| CPU time | 130.81 seconds |
| Started | Jul 09 07:25:40 PM PDT 24 |
| Finished | Jul 09 07:28:05 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-5e3f4a66-40cb-45eb-bd62-f1562a723ac1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134806480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3134806480 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.3753452126 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 2409210172 ps |
| CPU time | 86.59 seconds |
| Started | Jul 09 07:25:40 PM PDT 24 |
| Finished | Jul 09 07:27:21 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-a4f3aec6-535f-4215-af8f-cd183f7958cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753452126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3753452126 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.1208601787 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 367150184 ps |
| CPU time | 129.55 seconds |
| Started | Jul 09 07:25:25 PM PDT 24 |
| Finished | Jul 09 07:27:46 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-48d49257-cde5-44c2-96fa-cf3ec82f0ea5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208601787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.1208601787 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.4042712086 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 609204953 ps |
| CPU time | 251.6 seconds |
| Started | Jul 09 07:25:41 PM PDT 24 |
| Finished | Jul 09 07:30:07 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-4cbbecb4-a6f5-47eb-85a2-6f74b0e881e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042712086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.4042712086 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.3866339194 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 227343407 ps |
| CPU time | 12.47 seconds |
| Started | Jul 09 07:25:27 PM PDT 24 |
| Finished | Jul 09 07:25:51 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-c1828e6c-44de-49c4-b4da-310534f23a11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866339194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3866339194 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.3822691727 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 755341038 ps |
| CPU time | 26.64 seconds |
| Started | Jul 09 07:30:20 PM PDT 24 |
| Finished | Jul 09 07:30:52 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-38e25bee-352c-444e-bb98-224814a05206 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822691727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .3822691727 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.977586848 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 297782880 ps |
| CPU time | 34.25 seconds |
| Started | Jul 09 07:30:19 PM PDT 24 |
| Finished | Jul 09 07:30:59 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-450e7a7d-8bfb-4d8d-97f2-dc5acbcb139b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977586848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr .977586848 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.2388305904 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 384205433 ps |
| CPU time | 30.7 seconds |
| Started | Jul 09 07:30:19 PM PDT 24 |
| Finished | Jul 09 07:30:56 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-d855f615-0dbe-48a3-ae51-58b8eb1b4e46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388305904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2388305904 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.2577641890 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 593955894 ps |
| CPU time | 59.98 seconds |
| Started | Jul 09 07:30:19 PM PDT 24 |
| Finished | Jul 09 07:31:25 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-3c28ef20-9ae8-4cc4-b9df-c6b47476251c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577641890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.2577641890 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.1655625713 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 39652637872 ps |
| CPU time | 416.07 seconds |
| Started | Jul 09 07:30:17 PM PDT 24 |
| Finished | Jul 09 07:37:19 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-7d681d76-c28b-471a-9b84-7f20f6590fe3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655625713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1655625713 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.273877285 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 34667130001 ps |
| CPU time | 599.9 seconds |
| Started | Jul 09 07:30:20 PM PDT 24 |
| Finished | Jul 09 07:40:26 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-861f6f51-880a-485d-b6ad-df08e754ddec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273877285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.273877285 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.2931811111 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 305127007 ps |
| CPU time | 26.73 seconds |
| Started | Jul 09 07:30:18 PM PDT 24 |
| Finished | Jul 09 07:30:52 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-de1d9d6a-1fcb-4eb8-84bf-865d802fa720 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931811111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.2931811111 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.4090007758 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 523473601 ps |
| CPU time | 37.09 seconds |
| Started | Jul 09 07:30:22 PM PDT 24 |
| Finished | Jul 09 07:31:05 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-24b126ce-d8ee-4a13-be49-dfca6cb5e816 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090007758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.4090007758 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.3708410508 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 51321328 ps |
| CPU time | 6.66 seconds |
| Started | Jul 09 07:30:17 PM PDT 24 |
| Finished | Jul 09 07:30:30 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-7489f12c-45d1-438e-84b6-673ea04b14a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708410508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3708410508 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.2647988778 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 7936879987 ps |
| CPU time | 81.79 seconds |
| Started | Jul 09 07:30:18 PM PDT 24 |
| Finished | Jul 09 07:31:46 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-325ae068-f9f6-4f4b-9c63-75eec92d8dd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647988778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2647988778 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.4220043118 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 4740522616 ps |
| CPU time | 72.18 seconds |
| Started | Jul 09 07:30:22 PM PDT 24 |
| Finished | Jul 09 07:31:40 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-5dd5bfdf-5784-4392-860d-5f5beae68b63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220043118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.4220043118 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.3692553809 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 46253942 ps |
| CPU time | 6.45 seconds |
| Started | Jul 09 07:30:21 PM PDT 24 |
| Finished | Jul 09 07:30:33 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-b435f70d-0bd7-40fc-81e1-3dfdff8ff2cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692553809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.3692553809 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.3148361873 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 14675843163 ps |
| CPU time | 564.3 seconds |
| Started | Jul 09 07:30:28 PM PDT 24 |
| Finished | Jul 09 07:39:56 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-76bc4d02-caac-4deb-a1db-9da62c8196b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148361873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3148361873 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1765890383 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2676061926 ps |
| CPU time | 329.75 seconds |
| Started | Jul 09 07:30:31 PM PDT 24 |
| Finished | Jul 09 07:36:06 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-65e56e76-0f43-4086-9ead-573e4bd5f3ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765890383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.1765890383 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1526947063 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 11150106328 ps |
| CPU time | 612.3 seconds |
| Started | Jul 09 07:30:29 PM PDT 24 |
| Finished | Jul 09 07:40:46 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-b3fb5671-21d2-4996-86d7-da03a7635c97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526947063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.1526947063 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.484424420 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 1138587812 ps |
| CPU time | 47.04 seconds |
| Started | Jul 09 07:30:19 PM PDT 24 |
| Finished | Jul 09 07:31:12 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-f0cd6f91-f76d-4228-8b82-7bc2558498e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484424420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.484424420 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.3512377270 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 182099399 ps |
| CPU time | 19.73 seconds |
| Started | Jul 09 07:30:29 PM PDT 24 |
| Finished | Jul 09 07:30:54 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-96cc86a8-408f-40b9-8ff1-a36fa30b437b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512377270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .3512377270 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.3455245879 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 113724100174 ps |
| CPU time | 1914.43 seconds |
| Started | Jul 09 07:30:32 PM PDT 24 |
| Finished | Jul 09 08:02:32 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-7d26f233-d194-49ac-9f0e-4d781364a826 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455245879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_ device_slow_rsp.3455245879 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3883417991 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 33955921 ps |
| CPU time | 6.65 seconds |
| Started | Jul 09 07:30:30 PM PDT 24 |
| Finished | Jul 09 07:30:42 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-820b0622-e5d2-4f10-b9ce-fe1acfd6211a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883417991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.3883417991 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.822130109 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 1883580268 ps |
| CPU time | 63.78 seconds |
| Started | Jul 09 07:30:30 PM PDT 24 |
| Finished | Jul 09 07:31:39 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-05a0bf24-56fa-4b17-9d14-d5deab744608 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822130109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.822130109 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.908356083 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 865935839 ps |
| CPU time | 29.28 seconds |
| Started | Jul 09 07:30:32 PM PDT 24 |
| Finished | Jul 09 07:31:06 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-dcfb7c48-a3d5-420a-a781-6de8570c8f3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908356083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.908356083 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.2935124896 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 74779538394 ps |
| CPU time | 740.67 seconds |
| Started | Jul 09 07:30:32 PM PDT 24 |
| Finished | Jul 09 07:42:58 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-eedbebab-f5ce-453c-a73f-41f3d5f7700e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935124896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2935124896 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.3001302350 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 52620731923 ps |
| CPU time | 876.52 seconds |
| Started | Jul 09 07:30:30 PM PDT 24 |
| Finished | Jul 09 07:45:12 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-7974fd43-0b24-4bca-af85-b9b559733bc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001302350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3001302350 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.2384356936 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 577475911 ps |
| CPU time | 52.65 seconds |
| Started | Jul 09 07:30:32 PM PDT 24 |
| Finished | Jul 09 07:31:29 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-a1beae8d-2237-47a0-8818-4746dc05584f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384356936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.2384356936 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.3427742699 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 195510833 ps |
| CPU time | 16.6 seconds |
| Started | Jul 09 07:30:29 PM PDT 24 |
| Finished | Jul 09 07:30:51 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-e576e274-ee35-4172-b410-987ea426bea1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427742699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3427742699 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.4060878865 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 46229845 ps |
| CPU time | 6.47 seconds |
| Started | Jul 09 07:30:33 PM PDT 24 |
| Finished | Jul 09 07:30:44 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-ea2b223f-27f9-41de-81da-2982bd50cb03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060878865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.4060878865 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.2348427977 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 10065106187 ps |
| CPU time | 107.22 seconds |
| Started | Jul 09 07:30:29 PM PDT 24 |
| Finished | Jul 09 07:32:20 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-6bc3a3b2-5a4a-4723-aea0-90489316ea48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348427977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2348427977 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2797205699 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 6221922354 ps |
| CPU time | 108.22 seconds |
| Started | Jul 09 07:30:31 PM PDT 24 |
| Finished | Jul 09 07:32:25 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-1d6baaf0-4df3-4e76-bc5d-2c24133c0e9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797205699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2797205699 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.2134550072 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 42863991 ps |
| CPU time | 6.27 seconds |
| Started | Jul 09 07:30:29 PM PDT 24 |
| Finished | Jul 09 07:30:40 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-fc59233f-7581-4978-8b46-487f312f770c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134550072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.2134550072 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.3717376957 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 21656858734 ps |
| CPU time | 857.69 seconds |
| Started | Jul 09 07:30:29 PM PDT 24 |
| Finished | Jul 09 07:44:51 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-f8056341-e372-445a-b623-d9ca19b96e05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717376957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3717376957 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.1503287540 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 2579415732 ps |
| CPU time | 210.23 seconds |
| Started | Jul 09 07:30:33 PM PDT 24 |
| Finished | Jul 09 07:34:08 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-c243d4c3-4596-434c-959f-36cf93c24e7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503287540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1503287540 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3514108887 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 2046213103 ps |
| CPU time | 139.89 seconds |
| Started | Jul 09 07:30:30 PM PDT 24 |
| Finished | Jul 09 07:32:55 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-0e924408-8d60-42d2-a248-da55b6655ae8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514108887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.3514108887 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.1506216404 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 204171676 ps |
| CPU time | 22.73 seconds |
| Started | Jul 09 07:30:32 PM PDT 24 |
| Finished | Jul 09 07:30:59 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-7657906c-d2bc-4586-a9e5-a67486e47b77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506216404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1506216404 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.3763401696 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 1382386522 ps |
| CPU time | 54.77 seconds |
| Started | Jul 09 07:30:29 PM PDT 24 |
| Finished | Jul 09 07:31:29 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-e6462c39-a577-4966-b0ce-84a7326eccfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763401696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .3763401696 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.2551416898 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 177970593 ps |
| CPU time | 21.73 seconds |
| Started | Jul 09 07:30:38 PM PDT 24 |
| Finished | Jul 09 07:31:02 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-729c167b-ad05-4d71-a21c-fff1d4ac6693 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551416898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.2551416898 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.1448165124 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 2227438103 ps |
| CPU time | 87.15 seconds |
| Started | Jul 09 07:30:35 PM PDT 24 |
| Finished | Jul 09 07:32:06 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-b3b3ae6a-0ed7-48b3-bfd8-d2da1b68af89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448165124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1448165124 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.2461394639 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 2462048267 ps |
| CPU time | 94.54 seconds |
| Started | Jul 09 07:30:26 PM PDT 24 |
| Finished | Jul 09 07:32:05 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-ff43ca13-ebb9-47ec-b93e-8ce10c88fad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461394639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.2461394639 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.993891074 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 29568405111 ps |
| CPU time | 328.33 seconds |
| Started | Jul 09 07:30:29 PM PDT 24 |
| Finished | Jul 09 07:36:03 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-3ea95fb8-9e87-4bf9-a7c9-f14fa6986b46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993891074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.993891074 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.3281054093 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 18871704331 ps |
| CPU time | 315.63 seconds |
| Started | Jul 09 07:30:29 PM PDT 24 |
| Finished | Jul 09 07:35:48 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-8e101f0f-3f7f-49c0-8deb-e32f599f3c5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281054093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3281054093 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.1525945968 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 464541485 ps |
| CPU time | 40.89 seconds |
| Started | Jul 09 07:30:30 PM PDT 24 |
| Finished | Jul 09 07:31:16 PM PDT 24 |
| Peak memory | 576484 kb |
| Host | smart-dd7cca72-fe03-47c2-8fe1-07f351859ba9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525945968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.1525945968 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.3845422941 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 398486084 ps |
| CPU time | 31.83 seconds |
| Started | Jul 09 07:30:36 PM PDT 24 |
| Finished | Jul 09 07:31:11 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-695545cf-5ff0-4873-aa45-306287299b87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845422941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3845422941 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.3135958495 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 100707693 ps |
| CPU time | 6.88 seconds |
| Started | Jul 09 07:30:28 PM PDT 24 |
| Finished | Jul 09 07:30:40 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-b1d6b710-745e-468c-bd38-bf2a8eadad57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135958495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3135958495 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.3115285111 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 7786323009 ps |
| CPU time | 84.93 seconds |
| Started | Jul 09 07:30:32 PM PDT 24 |
| Finished | Jul 09 07:32:02 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-8fc5cccc-9e23-424d-a08d-6dbc71cb16ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115285111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3115285111 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.2372280031 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 5562821693 ps |
| CPU time | 92.15 seconds |
| Started | Jul 09 07:30:30 PM PDT 24 |
| Finished | Jul 09 07:32:07 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-274607a2-c084-438b-acf3-da0bbb545066 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372280031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2372280031 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3103720903 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 44057714 ps |
| CPU time | 5.99 seconds |
| Started | Jul 09 07:30:31 PM PDT 24 |
| Finished | Jul 09 07:30:43 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-f43c3c85-60f0-4282-975b-cb63151f0f63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103720903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.3103720903 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.893685405 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 2140791856 ps |
| CPU time | 175.82 seconds |
| Started | Jul 09 07:30:38 PM PDT 24 |
| Finished | Jul 09 07:33:36 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-d100d15f-8aa1-4a9f-bd3f-d04d96ab5da5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893685405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.893685405 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.4186172549 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 4291413929 ps |
| CPU time | 320.01 seconds |
| Started | Jul 09 07:30:41 PM PDT 24 |
| Finished | Jul 09 07:36:03 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-15d4aebc-5a9c-4127-bcc6-5de09009e828 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186172549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.4186172549 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.2088855183 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 12800494 ps |
| CPU time | 18.89 seconds |
| Started | Jul 09 07:30:37 PM PDT 24 |
| Finished | Jul 09 07:30:59 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-781b3d31-224b-473f-83b0-723447e620bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088855183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.2088855183 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.848149590 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 194645517 ps |
| CPU time | 82 seconds |
| Started | Jul 09 07:30:41 PM PDT 24 |
| Finished | Jul 09 07:32:06 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-6cd73946-f93c-403e-a513-969b8a996ada |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848149590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_reset_error.848149590 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.1534120426 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 189089937 ps |
| CPU time | 23.59 seconds |
| Started | Jul 09 07:30:37 PM PDT 24 |
| Finished | Jul 09 07:31:03 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-3547de81-b151-42d1-a4ed-1b8e1a148183 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534120426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1534120426 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.2807438390 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 613115413 ps |
| CPU time | 44.91 seconds |
| Started | Jul 09 07:30:48 PM PDT 24 |
| Finished | Jul 09 07:31:36 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-bcab7e62-2054-4284-b424-b743dbd5b15c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807438390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .2807438390 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.352240916 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 80746877524 ps |
| CPU time | 1393.34 seconds |
| Started | Jul 09 07:30:45 PM PDT 24 |
| Finished | Jul 09 07:54:01 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-cbd185ff-a455-4e44-8b87-f67c5617ef7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352240916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_d evice_slow_rsp.352240916 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.2312538275 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 1308779813 ps |
| CPU time | 56.14 seconds |
| Started | Jul 09 07:30:45 PM PDT 24 |
| Finished | Jul 09 07:31:43 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-a8859d05-62c3-4aa6-9a8d-0f183d4da3ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312538275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.2312538275 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.3713830913 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 164615400 ps |
| CPU time | 8.23 seconds |
| Started | Jul 09 07:30:43 PM PDT 24 |
| Finished | Jul 09 07:30:54 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-c6343ac3-0a1b-451d-af2b-6b24974577af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713830913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3713830913 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.1835798861 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 195994713 ps |
| CPU time | 16.12 seconds |
| Started | Jul 09 07:30:44 PM PDT 24 |
| Finished | Jul 09 07:31:02 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-dc1e5126-c8c3-42ba-8d54-cdc3e40a7fc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835798861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.1835798861 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.2109188197 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 11993858630 ps |
| CPU time | 125.58 seconds |
| Started | Jul 09 07:30:46 PM PDT 24 |
| Finished | Jul 09 07:32:53 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-bff9bb34-7df1-430d-90c6-15c7009929bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109188197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2109188197 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.3289389430 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 63112124068 ps |
| CPU time | 1183.56 seconds |
| Started | Jul 09 07:30:48 PM PDT 24 |
| Finished | Jul 09 07:50:34 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-09d183a7-a0f1-4d4a-a13f-fc7ca1f5a51e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289389430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3289389430 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.3162112383 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 231081788 ps |
| CPU time | 25.59 seconds |
| Started | Jul 09 07:30:48 PM PDT 24 |
| Finished | Jul 09 07:31:16 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-de203013-b3a7-4e8a-a58e-6d3999f6665e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162112383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.3162112383 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.4122399527 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 91480486 ps |
| CPU time | 10.1 seconds |
| Started | Jul 09 07:30:49 PM PDT 24 |
| Finished | Jul 09 07:31:01 PM PDT 24 |
| Peak memory | 576464 kb |
| Host | smart-19ce277e-502a-466e-98f8-32d90f01b716 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122399527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.4122399527 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.1822433303 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 141450726 ps |
| CPU time | 8.08 seconds |
| Started | Jul 09 07:30:37 PM PDT 24 |
| Finished | Jul 09 07:30:48 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-cf9750e9-4331-4b03-a59c-aebe29e04d70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822433303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1822433303 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.3688227050 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 6754528802 ps |
| CPU time | 69.76 seconds |
| Started | Jul 09 07:31:55 PM PDT 24 |
| Finished | Jul 09 07:33:07 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-cc048c79-1d53-4a84-b9a3-797f11896751 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688227050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3688227050 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.385387026 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 5662019297 ps |
| CPU time | 93.87 seconds |
| Started | Jul 09 07:30:46 PM PDT 24 |
| Finished | Jul 09 07:32:21 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-3437c88a-f368-4831-b0d9-28f543d49c73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385387026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.385387026 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.2241954351 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 52107267 ps |
| CPU time | 6.89 seconds |
| Started | Jul 09 07:30:36 PM PDT 24 |
| Finished | Jul 09 07:30:47 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-5e18567e-614c-4bd2-b38c-346e0962100d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241954351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.2241954351 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.3741485845 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 9487438183 ps |
| CPU time | 312.12 seconds |
| Started | Jul 09 07:30:44 PM PDT 24 |
| Finished | Jul 09 07:35:59 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-69704a91-9d69-40e8-a6ff-c8d671ee0487 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741485845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3741485845 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.932231233 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 9524531126 ps |
| CPU time | 341.84 seconds |
| Started | Jul 09 07:30:48 PM PDT 24 |
| Finished | Jul 09 07:36:33 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-dae1d066-329f-400b-b8aa-9fc6aa23d275 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932231233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.932231233 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.297845519 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1316848168 ps |
| CPU time | 117.48 seconds |
| Started | Jul 09 07:30:45 PM PDT 24 |
| Finished | Jul 09 07:32:44 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-c8c2f848-d15d-4d73-b0e3-d3bcc7caf615 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297845519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_ with_rand_reset.297845519 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.3791757449 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 14596858 ps |
| CPU time | 17.65 seconds |
| Started | Jul 09 07:30:44 PM PDT 24 |
| Finished | Jul 09 07:31:04 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-dafd3e78-3c70-4189-8a4b-760047f01cbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791757449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.3791757449 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.978839604 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 94762371 ps |
| CPU time | 7.3 seconds |
| Started | Jul 09 07:30:42 PM PDT 24 |
| Finished | Jul 09 07:30:52 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-9a6a20f5-cfb5-436d-98fc-b11f6202cae3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978839604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.978839604 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1719308597 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 1774371339 ps |
| CPU time | 65.57 seconds |
| Started | Jul 09 07:30:54 PM PDT 24 |
| Finished | Jul 09 07:32:02 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-82258146-8800-4810-9fce-63d7698d61f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719308597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .1719308597 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.2018150062 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 100526895476 ps |
| CPU time | 1900.22 seconds |
| Started | Jul 09 07:30:52 PM PDT 24 |
| Finished | Jul 09 08:02:34 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-38de7533-0530-4391-b447-5f7b78105ff8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018150062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.2018150062 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.1440938647 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 307172734 ps |
| CPU time | 14.35 seconds |
| Started | Jul 09 07:30:53 PM PDT 24 |
| Finished | Jul 09 07:31:09 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-b8be154e-c9a8-4517-ab45-38d3391532b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440938647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.1440938647 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.3583027920 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 430289880 ps |
| CPU time | 37.39 seconds |
| Started | Jul 09 07:30:53 PM PDT 24 |
| Finished | Jul 09 07:31:32 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-dba696dc-92e0-4967-b0b2-fd5946cb0305 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583027920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3583027920 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.903358196 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 395738000 ps |
| CPU time | 31.59 seconds |
| Started | Jul 09 07:30:58 PM PDT 24 |
| Finished | Jul 09 07:31:32 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-871dee98-04a8-4927-8550-f64b21742a7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903358196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.903358196 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.2621370580 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 100977487027 ps |
| CPU time | 1092.36 seconds |
| Started | Jul 09 07:30:56 PM PDT 24 |
| Finished | Jul 09 07:49:11 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-53537a3b-359a-4909-b25c-a2c6099d9c8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621370580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2621370580 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.2091392499 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 55073263110 ps |
| CPU time | 936.98 seconds |
| Started | Jul 09 07:30:54 PM PDT 24 |
| Finished | Jul 09 07:46:33 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-35dde3c2-a8df-45a8-8012-b00f191b14b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091392499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2091392499 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.3123396441 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 60630825 ps |
| CPU time | 8.05 seconds |
| Started | Jul 09 07:30:58 PM PDT 24 |
| Finished | Jul 09 07:31:09 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-f24c2a3c-b977-469b-8ef2-69c9e5fff110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123396441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.3123396441 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.2797050938 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 570571936 ps |
| CPU time | 41.01 seconds |
| Started | Jul 09 07:30:50 PM PDT 24 |
| Finished | Jul 09 07:31:33 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-184c7434-8e41-4002-9100-af9c5b9ef128 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797050938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2797050938 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.2258349708 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 37342307 ps |
| CPU time | 6.19 seconds |
| Started | Jul 09 07:30:43 PM PDT 24 |
| Finished | Jul 09 07:30:52 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-cc1653a7-b895-4274-9f16-781c9d81a22f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258349708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2258349708 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.2700889156 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 8741125745 ps |
| CPU time | 93.18 seconds |
| Started | Jul 09 07:30:47 PM PDT 24 |
| Finished | Jul 09 07:32:21 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-b0a646b6-f212-4bb5-9767-cdd4b9e87dc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700889156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2700889156 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.3964581647 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 5061403808 ps |
| CPU time | 89.47 seconds |
| Started | Jul 09 07:30:51 PM PDT 24 |
| Finished | Jul 09 07:32:23 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-afe1a45a-f691-4367-b24b-c4b4f2102f37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964581647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3964581647 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.2075450543 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 45168619 ps |
| CPU time | 6.62 seconds |
| Started | Jul 09 07:30:42 PM PDT 24 |
| Finished | Jul 09 07:30:52 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-b877c68f-7412-4558-9caf-64197ec00058 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075450543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.2075450543 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.175041416 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 3040488753 ps |
| CPU time | 284.64 seconds |
| Started | Jul 09 07:30:52 PM PDT 24 |
| Finished | Jul 09 07:35:39 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-5958abfb-de3e-4325-97aa-c19960756fe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175041416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.175041416 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.3882741688 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 11240540697 ps |
| CPU time | 357.63 seconds |
| Started | Jul 09 07:30:52 PM PDT 24 |
| Finished | Jul 09 07:36:52 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-fa926ed2-27a3-481f-803c-887ae51d8051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882741688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3882741688 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.501484923 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 3524643919 ps |
| CPU time | 452.86 seconds |
| Started | Jul 09 07:30:50 PM PDT 24 |
| Finished | Jul 09 07:38:25 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-defba171-81c0-4599-ad68-efe30f1ff65d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501484923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_ with_rand_reset.501484923 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2858511816 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 237929526 ps |
| CPU time | 61.58 seconds |
| Started | Jul 09 07:30:51 PM PDT 24 |
| Finished | Jul 09 07:31:55 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-9cc890cd-991f-4bd1-af78-6181c7ef3069 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858511816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.2858511816 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.413294932 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 1021737649 ps |
| CPU time | 44.32 seconds |
| Started | Jul 09 07:30:55 PM PDT 24 |
| Finished | Jul 09 07:31:42 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-aba04476-26e3-420a-93aa-9f78c73401bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413294932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.413294932 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.1596611731 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 638124406 ps |
| CPU time | 27.77 seconds |
| Started | Jul 09 07:30:56 PM PDT 24 |
| Finished | Jul 09 07:31:27 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-edc0182f-b2a3-4322-8ccd-af0f7f88a3cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596611731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .1596611731 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3904290253 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 127806829449 ps |
| CPU time | 2341.74 seconds |
| Started | Jul 09 07:30:58 PM PDT 24 |
| Finished | Jul 09 08:10:03 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-f7943f33-331f-475d-8dcc-27c7b9a3c2d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904290253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.3904290253 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3757270780 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 201482254 ps |
| CPU time | 19.34 seconds |
| Started | Jul 09 07:31:11 PM PDT 24 |
| Finished | Jul 09 07:31:33 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-4acdb422-24d2-4b69-8ed3-4d96b33067f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757270780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.3757270780 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.2773308768 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 1017079663 ps |
| CPU time | 39.1 seconds |
| Started | Jul 09 07:30:58 PM PDT 24 |
| Finished | Jul 09 07:31:40 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-2a26bfc3-376b-4a14-8006-1025652e45b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773308768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2773308768 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.511458473 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 644875294 ps |
| CPU time | 59.87 seconds |
| Started | Jul 09 07:30:52 PM PDT 24 |
| Finished | Jul 09 07:31:54 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-9bf01236-beb2-451b-86cb-e58211c3a3ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511458473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.511458473 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.447308096 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 80328745096 ps |
| CPU time | 866.76 seconds |
| Started | Jul 09 07:30:57 PM PDT 24 |
| Finished | Jul 09 07:45:27 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-17f4353b-3bcc-42cb-8620-c5a31bc4cabc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447308096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.447308096 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.3296450216 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 18758358615 ps |
| CPU time | 305.86 seconds |
| Started | Jul 09 07:30:59 PM PDT 24 |
| Finished | Jul 09 07:36:07 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-fd9f7d48-d88e-400a-aa5b-123c3af3fcca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296450216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3296450216 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.3142640921 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 542506475 ps |
| CPU time | 42.01 seconds |
| Started | Jul 09 07:30:58 PM PDT 24 |
| Finished | Jul 09 07:31:43 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-6bb0ac4b-3955-4905-943a-4bf9a9664767 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142640921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del ays.3142640921 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.1854353846 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 236326542 ps |
| CPU time | 9.88 seconds |
| Started | Jul 09 07:30:59 PM PDT 24 |
| Finished | Jul 09 07:31:12 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-4b435f9e-cdb6-4094-b052-f382d611cdf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854353846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1854353846 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.2703701363 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 196888970 ps |
| CPU time | 8.52 seconds |
| Started | Jul 09 07:30:58 PM PDT 24 |
| Finished | Jul 09 07:31:09 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-d83d7ecb-21d1-49a3-8ffe-1025822eb869 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703701363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2703701363 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.393856337 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 9394138625 ps |
| CPU time | 101.76 seconds |
| Started | Jul 09 07:30:53 PM PDT 24 |
| Finished | Jul 09 07:32:36 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-bf8f5791-cb7f-496a-ac5a-e71dba190efa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393856337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.393856337 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.2948973878 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 4875021160 ps |
| CPU time | 86.45 seconds |
| Started | Jul 09 07:30:54 PM PDT 24 |
| Finished | Jul 09 07:32:22 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-5eb38142-8f6a-4bc4-b559-359a9127773a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948973878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2948973878 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1774544076 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 37904334 ps |
| CPU time | 6.26 seconds |
| Started | Jul 09 07:30:51 PM PDT 24 |
| Finished | Jul 09 07:30:59 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-271ca445-c688-4105-ae10-4ea6189e0b30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774544076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.1774544076 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.1099449846 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 3265962991 ps |
| CPU time | 253.73 seconds |
| Started | Jul 09 07:31:08 PM PDT 24 |
| Finished | Jul 09 07:35:24 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-ac49dddd-df7a-4f11-a62d-d0d226b973b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099449846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1099449846 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.3770004946 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 3940100132 ps |
| CPU time | 119.36 seconds |
| Started | Jul 09 07:31:06 PM PDT 24 |
| Finished | Jul 09 07:33:07 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-20bdff9e-0c51-439a-8ed8-a0d8a3d85e57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770004946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3770004946 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1101334921 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 278245424 ps |
| CPU time | 87.09 seconds |
| Started | Jul 09 07:31:06 PM PDT 24 |
| Finished | Jul 09 07:32:35 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-be8edab6-a3c2-4845-9176-7f0fdd82cfa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101334921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.1101334921 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.4072069342 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 1890170709 ps |
| CPU time | 206.46 seconds |
| Started | Jul 09 07:31:06 PM PDT 24 |
| Finished | Jul 09 07:34:35 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-5a2f2932-b621-437f-b154-414f20acd80b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072069342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.4072069342 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.2796080548 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 745026884 ps |
| CPU time | 32.37 seconds |
| Started | Jul 09 07:31:09 PM PDT 24 |
| Finished | Jul 09 07:31:44 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-4da8caa0-f7ab-448b-a6ab-502eb46dab78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796080548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2796080548 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.3320164626 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 360944795 ps |
| CPU time | 41.7 seconds |
| Started | Jul 09 07:31:12 PM PDT 24 |
| Finished | Jul 09 07:31:57 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-a5c2d9b7-545c-45c4-a008-6dd53836b30c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320164626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .3320164626 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.29638689 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 90261537026 ps |
| CPU time | 1645.23 seconds |
| Started | Jul 09 07:31:13 PM PDT 24 |
| Finished | Jul 09 07:58:42 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-9eb4f984-599a-4d36-96a6-1adbf61bf6fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29638689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_de vice_slow_rsp.29638689 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3100241483 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 782234337 ps |
| CPU time | 33.37 seconds |
| Started | Jul 09 07:31:16 PM PDT 24 |
| Finished | Jul 09 07:31:51 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-27a16eb8-9160-4f2b-8304-d391166905e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100241483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.3100241483 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.165239429 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 948240079 ps |
| CPU time | 32.38 seconds |
| Started | Jul 09 07:31:12 PM PDT 24 |
| Finished | Jul 09 07:31:47 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-0194ed04-db01-4a02-bd72-be924270a107 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165239429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.165239429 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.1198184561 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1501322979 ps |
| CPU time | 51.75 seconds |
| Started | Jul 09 07:31:12 PM PDT 24 |
| Finished | Jul 09 07:32:06 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-3f5b4b3e-e7c5-43f1-a599-56194cccd9b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198184561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.1198184561 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.2458512743 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 106547090850 ps |
| CPU time | 1144.98 seconds |
| Started | Jul 09 07:31:15 PM PDT 24 |
| Finished | Jul 09 07:50:23 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-0622af3a-b88d-478a-9070-bf8995a542c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458512743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2458512743 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.4216140053 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 28667930863 ps |
| CPU time | 472.53 seconds |
| Started | Jul 09 07:31:13 PM PDT 24 |
| Finished | Jul 09 07:39:08 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-33b9605c-1275-4f15-aea7-8160527e506a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216140053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.4216140053 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.2823357021 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 217011054 ps |
| CPU time | 20.37 seconds |
| Started | Jul 09 07:31:06 PM PDT 24 |
| Finished | Jul 09 07:31:29 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-05a19abb-075d-4ceb-8d45-eace53aaa9aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823357021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.2823357021 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.4022114394 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 2282970824 ps |
| CPU time | 66.46 seconds |
| Started | Jul 09 07:31:12 PM PDT 24 |
| Finished | Jul 09 07:32:22 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-272dda3d-f29c-4f28-8417-dfd60fa60365 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022114394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.4022114394 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.4134314817 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 41265236 ps |
| CPU time | 5.84 seconds |
| Started | Jul 09 07:31:08 PM PDT 24 |
| Finished | Jul 09 07:31:16 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-db996366-d7ff-4ced-9eb3-a066fcbc5cd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134314817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.4134314817 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.701743426 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 10738750787 ps |
| CPU time | 109.52 seconds |
| Started | Jul 09 07:31:08 PM PDT 24 |
| Finished | Jul 09 07:33:00 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-540da0d8-a2b4-4a88-b878-02a00948fec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701743426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.701743426 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.645994416 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 5613653616 ps |
| CPU time | 93.76 seconds |
| Started | Jul 09 07:31:11 PM PDT 24 |
| Finished | Jul 09 07:32:47 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-5c815d41-d5c8-4385-81a1-171911fa3fd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645994416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.645994416 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.3846844747 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 37745892 ps |
| CPU time | 6.34 seconds |
| Started | Jul 09 07:31:06 PM PDT 24 |
| Finished | Jul 09 07:31:14 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-f32c2340-f0ff-470e-a31a-c78e6fca2e58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846844747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.3846844747 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.4183256468 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 2236241209 ps |
| CPU time | 85.85 seconds |
| Started | Jul 09 07:31:13 PM PDT 24 |
| Finished | Jul 09 07:32:42 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-eb7ae68a-daaf-4df3-999d-2c69b1898ee6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183256468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.4183256468 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.3166065833 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 2557972894 ps |
| CPU time | 210.35 seconds |
| Started | Jul 09 07:31:12 PM PDT 24 |
| Finished | Jul 09 07:34:45 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-7da71105-8b82-445e-bd00-56fb23d4acca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166065833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3166065833 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2382725058 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 798245354 ps |
| CPU time | 169.85 seconds |
| Started | Jul 09 07:31:14 PM PDT 24 |
| Finished | Jul 09 07:34:07 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-a0132383-7789-4d6a-8acd-8d49bf5e9b96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382725058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.2382725058 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.2220912499 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 436700535 ps |
| CPU time | 128.17 seconds |
| Started | Jul 09 07:31:13 PM PDT 24 |
| Finished | Jul 09 07:33:23 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-90d28b65-9e60-4f3d-b072-7e2d61596fe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220912499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.2220912499 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.2216274509 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 634022827 ps |
| CPU time | 28.67 seconds |
| Started | Jul 09 07:31:14 PM PDT 24 |
| Finished | Jul 09 07:31:46 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-23a78920-6f90-4879-a66f-4fc34056b42f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216274509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2216274509 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.1185029257 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 87883185347 ps |
| CPU time | 1594.17 seconds |
| Started | Jul 09 07:31:22 PM PDT 24 |
| Finished | Jul 09 07:57:59 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-a6fb3f40-f5e5-4508-a95a-be7e3a424317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185029257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.1185029257 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.1909472081 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 83783945 ps |
| CPU time | 6.49 seconds |
| Started | Jul 09 07:31:29 PM PDT 24 |
| Finished | Jul 09 07:31:37 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-8ab01652-08f7-4c5e-afc1-e180c26af070 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909472081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.1909472081 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.2126786726 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 135049063 ps |
| CPU time | 8.52 seconds |
| Started | Jul 09 07:31:22 PM PDT 24 |
| Finished | Jul 09 07:31:32 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-42b44d3e-5899-4210-90ee-86c3f0df2fbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126786726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2126786726 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.1638584705 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 458422986 ps |
| CPU time | 45.19 seconds |
| Started | Jul 09 07:31:22 PM PDT 24 |
| Finished | Jul 09 07:32:09 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-a1418b69-68cd-4526-973f-2c637b48f8d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638584705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.1638584705 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.3612842567 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 16098739392 ps |
| CPU time | 151.05 seconds |
| Started | Jul 09 07:31:21 PM PDT 24 |
| Finished | Jul 09 07:33:54 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-3d7ad06f-6d5e-4567-8232-1d09ab6ce1e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612842567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3612842567 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.2793371521 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 67575011882 ps |
| CPU time | 1188.96 seconds |
| Started | Jul 09 07:31:21 PM PDT 24 |
| Finished | Jul 09 07:51:12 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-1ef5c377-061f-41fe-b24c-7ff71fdcbd11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793371521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2793371521 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.2381665012 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 124317169 ps |
| CPU time | 13.74 seconds |
| Started | Jul 09 07:31:21 PM PDT 24 |
| Finished | Jul 09 07:31:36 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-f045ec78-67a4-41a1-8494-c293ef182955 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381665012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.2381665012 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.2613343508 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 250849539 ps |
| CPU time | 21.17 seconds |
| Started | Jul 09 07:31:20 PM PDT 24 |
| Finished | Jul 09 07:31:43 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-d33ab05b-925f-47cd-a5b8-62b423ab9487 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613343508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2613343508 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.843436522 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 170335105 ps |
| CPU time | 8.29 seconds |
| Started | Jul 09 07:31:12 PM PDT 24 |
| Finished | Jul 09 07:31:23 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-3c1e630c-dd93-462d-bb64-ac1f66260364 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843436522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.843436522 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.1976663279 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 7359704525 ps |
| CPU time | 74.31 seconds |
| Started | Jul 09 07:31:19 PM PDT 24 |
| Finished | Jul 09 07:32:35 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-bc5c9d8b-43f6-49fb-87d2-39119bc244d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976663279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1976663279 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.4281731741 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 6127048450 ps |
| CPU time | 102.41 seconds |
| Started | Jul 09 07:31:20 PM PDT 24 |
| Finished | Jul 09 07:33:04 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-4e49c22f-d499-4417-85d6-f46e87d9241e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281731741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.4281731741 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1850216765 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 37380271 ps |
| CPU time | 5.88 seconds |
| Started | Jul 09 07:31:22 PM PDT 24 |
| Finished | Jul 09 07:31:30 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-6d5528b4-21e2-4544-97b4-a321f1c30586 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850216765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.1850216765 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.4153581928 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 11129066455 ps |
| CPU time | 451.68 seconds |
| Started | Jul 09 07:31:30 PM PDT 24 |
| Finished | Jul 09 07:39:04 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-af0c5d09-a4df-4101-9c59-9929a47dae03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153581928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.4153581928 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.1517030415 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 1150734408 ps |
| CPU time | 48.81 seconds |
| Started | Jul 09 07:31:30 PM PDT 24 |
| Finished | Jul 09 07:32:22 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-f20f99f2-efd1-467e-aa01-174c6e86828a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517030415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1517030415 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.2759342099 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 2561751596 ps |
| CPU time | 118.41 seconds |
| Started | Jul 09 07:31:36 PM PDT 24 |
| Finished | Jul 09 07:33:38 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-01fc729b-8b72-4067-bf4c-48ffa071e4d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759342099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .2759342099 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2757150049 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 126634703602 ps |
| CPU time | 2306.59 seconds |
| Started | Jul 09 07:31:45 PM PDT 24 |
| Finished | Jul 09 08:10:16 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-61752b26-361a-464e-bc5b-5d9ef83e376e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757150049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.2757150049 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.4068029060 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 242270942 ps |
| CPU time | 13.05 seconds |
| Started | Jul 09 07:31:44 PM PDT 24 |
| Finished | Jul 09 07:32:01 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-216c44cb-8b1d-42ae-801d-3038a7b1388d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068029060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.4068029060 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.1285360880 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 1294848621 ps |
| CPU time | 43.97 seconds |
| Started | Jul 09 07:31:42 PM PDT 24 |
| Finished | Jul 09 07:32:29 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-1b6d66e6-e12b-40e0-bfce-fc41987d396c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285360880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1285360880 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.2408835630 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 1144339848 ps |
| CPU time | 42.59 seconds |
| Started | Jul 09 07:31:40 PM PDT 24 |
| Finished | Jul 09 07:32:26 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-eb6ddcf3-d1ff-4708-b1fc-877ed71e1dbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408835630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.2408835630 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.3439716836 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 46627320812 ps |
| CPU time | 520.33 seconds |
| Started | Jul 09 07:31:36 PM PDT 24 |
| Finished | Jul 09 07:40:19 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-989f8220-6e8d-4c80-949d-5e60806c5ece |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439716836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3439716836 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.613692775 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 46832550929 ps |
| CPU time | 813.02 seconds |
| Started | Jul 09 07:31:35 PM PDT 24 |
| Finished | Jul 09 07:45:11 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-3f5a9cba-9334-49f3-bf30-5fd5be85b6cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613692775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.613692775 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.2901721062 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 391856329 ps |
| CPU time | 32.61 seconds |
| Started | Jul 09 07:31:45 PM PDT 24 |
| Finished | Jul 09 07:32:21 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-365538ce-2b83-4a46-854f-dae488f6c255 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901721062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.2901721062 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.3002366282 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 700324423 ps |
| CPU time | 22.26 seconds |
| Started | Jul 09 07:31:35 PM PDT 24 |
| Finished | Jul 09 07:32:01 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-1c1868f7-d1aa-4859-ad3a-80f58228f966 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002366282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3002366282 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.3889697603 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 206287071 ps |
| CPU time | 9.58 seconds |
| Started | Jul 09 07:31:34 PM PDT 24 |
| Finished | Jul 09 07:31:47 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-0fcd596a-b66e-4717-b5de-c94e7dbab287 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889697603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3889697603 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.1702126090 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 6193443427 ps |
| CPU time | 67.3 seconds |
| Started | Jul 09 07:31:29 PM PDT 24 |
| Finished | Jul 09 07:32:38 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-b34c52d8-7bd7-4233-a7df-afad76017835 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702126090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1702126090 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.1094056146 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 4298397864 ps |
| CPU time | 69.03 seconds |
| Started | Jul 09 07:31:31 PM PDT 24 |
| Finished | Jul 09 07:32:43 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-4b606733-c8ed-4705-9b5a-9a1044fb1535 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094056146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1094056146 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.492768240 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 55775793 ps |
| CPU time | 6.79 seconds |
| Started | Jul 09 07:31:29 PM PDT 24 |
| Finished | Jul 09 07:31:38 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-19415b90-c9ab-4cd6-a682-7c5a8e42453a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492768240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays .492768240 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.157104769 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 1721935762 ps |
| CPU time | 124.39 seconds |
| Started | Jul 09 07:31:42 PM PDT 24 |
| Finished | Jul 09 07:33:50 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-722dcad7-c0e2-4b85-808f-9a81641b57a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157104769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.157104769 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1117056528 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 1756494750 ps |
| CPU time | 148.28 seconds |
| Started | Jul 09 07:31:45 PM PDT 24 |
| Finished | Jul 09 07:34:16 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-2ac242cf-7080-4d7e-a48c-c632edae9d78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117056528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.1117056528 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2864131995 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 95964573 ps |
| CPU time | 34.18 seconds |
| Started | Jul 09 07:31:46 PM PDT 24 |
| Finished | Jul 09 07:32:23 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-8b25d129-1bcf-4480-bc2a-a4e9ea082caa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864131995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.2864131995 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.4110677986 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 749134746 ps |
| CPU time | 29.55 seconds |
| Started | Jul 09 07:31:44 PM PDT 24 |
| Finished | Jul 09 07:32:17 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-d84206d4-f526-4977-8414-e03e6b00d5a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110677986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.4110677986 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.3447381114 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 4082851646 ps |
| CPU time | 151.75 seconds |
| Started | Jul 09 07:31:53 PM PDT 24 |
| Finished | Jul 09 07:34:27 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-0f8795ed-25c4-42bd-a332-ec2c42b2ebd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447381114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .3447381114 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.1652101621 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 4551916549 ps |
| CPU time | 79.2 seconds |
| Started | Jul 09 07:31:55 PM PDT 24 |
| Finished | Jul 09 07:33:16 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-402a5cee-b4e8-44fa-a70d-00f75b6fd9a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652101621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.1652101621 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.3004380375 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 641219126 ps |
| CPU time | 28 seconds |
| Started | Jul 09 07:31:55 PM PDT 24 |
| Finished | Jul 09 07:32:25 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-b0953b44-d00a-4e2b-8942-b93fcd5a24b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004380375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.3004380375 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.1348345065 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 203408959 ps |
| CPU time | 18.18 seconds |
| Started | Jul 09 07:31:55 PM PDT 24 |
| Finished | Jul 09 07:32:16 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-8cd45bc2-e8d1-4618-9db4-6efbe85e40bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348345065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1348345065 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.3296170327 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 359554520 ps |
| CPU time | 32.9 seconds |
| Started | Jul 09 07:31:44 PM PDT 24 |
| Finished | Jul 09 07:32:20 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-8e019c27-226f-461b-9ea7-83c12398f6d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296170327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.3296170327 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.2118497919 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 99988608377 ps |
| CPU time | 1024.11 seconds |
| Started | Jul 09 07:31:46 PM PDT 24 |
| Finished | Jul 09 07:48:53 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-12b85741-125a-4410-a7f8-dfd873615029 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118497919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2118497919 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.1285743370 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 5315062027 ps |
| CPU time | 91.55 seconds |
| Started | Jul 09 07:31:47 PM PDT 24 |
| Finished | Jul 09 07:33:21 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-fa4390e3-7f14-42ab-850c-978b80ce145e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285743370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1285743370 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.884798949 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 556231096 ps |
| CPU time | 45.3 seconds |
| Started | Jul 09 07:31:47 PM PDT 24 |
| Finished | Jul 09 07:32:35 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-e32860db-5f31-4172-a97a-a605c69530f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884798949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_dela ys.884798949 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.2160202268 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 2280109919 ps |
| CPU time | 70.96 seconds |
| Started | Jul 09 07:31:50 PM PDT 24 |
| Finished | Jul 09 07:33:03 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-62c6d686-47e5-4f4a-9df9-e93b6504d096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160202268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2160202268 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.4157412988 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 45563244 ps |
| CPU time | 6.17 seconds |
| Started | Jul 09 07:31:43 PM PDT 24 |
| Finished | Jul 09 07:31:52 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-f8bf72ef-73e4-4ac2-ba5a-312af880628e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157412988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.4157412988 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.2427132419 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 9999224902 ps |
| CPU time | 106.72 seconds |
| Started | Jul 09 07:31:42 PM PDT 24 |
| Finished | Jul 09 07:33:32 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-d01a2fc5-8749-4b65-914a-f1a5f44cf5be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427132419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2427132419 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.2451484461 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 4622474125 ps |
| CPU time | 79.65 seconds |
| Started | Jul 09 07:31:43 PM PDT 24 |
| Finished | Jul 09 07:33:06 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-351b3290-6e08-46ef-a30d-1477f08b3161 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451484461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2451484461 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3248806656 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 46028111 ps |
| CPU time | 6 seconds |
| Started | Jul 09 07:31:46 PM PDT 24 |
| Finished | Jul 09 07:31:55 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-dfa96b8b-f4ae-4151-b55f-15e152a26c37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248806656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.3248806656 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.176978694 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 17034868985 ps |
| CPU time | 602.94 seconds |
| Started | Jul 09 07:31:55 PM PDT 24 |
| Finished | Jul 09 07:42:01 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-183ad792-5d31-4004-bf2e-e6e35fceaf52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176978694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.176978694 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.980780008 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 2489999830 ps |
| CPU time | 196.02 seconds |
| Started | Jul 09 07:31:54 PM PDT 24 |
| Finished | Jul 09 07:35:12 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-42276c8b-3893-4697-a1ef-2ec20af64aa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980780008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.980780008 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3049186768 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 3595791214 ps |
| CPU time | 431.25 seconds |
| Started | Jul 09 07:31:51 PM PDT 24 |
| Finished | Jul 09 07:39:05 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-a4846358-2aab-41f7-b8e5-ef2e40f3c8b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049186768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.3049186768 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3098848750 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 827972393 ps |
| CPU time | 241.61 seconds |
| Started | Jul 09 07:31:51 PM PDT 24 |
| Finished | Jul 09 07:35:55 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-3082a7f4-658a-4d40-8646-e63270e79ea0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098848750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.3098848750 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.1821421062 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 1011625484 ps |
| CPU time | 42.59 seconds |
| Started | Jul 09 07:31:51 PM PDT 24 |
| Finished | Jul 09 07:32:36 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-f25df5b1-7a38-4dee-971e-a3e98f9694b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821421062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1821421062 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.3703749514 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 57306895496 ps |
| CPU time | 8189.51 seconds |
| Started | Jul 09 07:25:25 PM PDT 24 |
| Finished | Jul 09 09:42:07 PM PDT 24 |
| Peak memory | 644980 kb |
| Host | smart-903b1055-66c2-455d-9b26-e0f28a42121e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703749514 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.3703749514 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.1861557853 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 10530767535 ps |
| CPU time | 840.6 seconds |
| Started | Jul 09 07:25:34 PM PDT 24 |
| Finished | Jul 09 07:39:46 PM PDT 24 |
| Peak memory | 592608 kb |
| Host | smart-540f476e-3fc6-4312-82cc-1dcc565a886a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861557853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.1861557853 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2321539853 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 6804617236 ps |
| CPU time | 374.73 seconds |
| Started | Jul 09 07:25:28 PM PDT 24 |
| Finished | Jul 09 07:31:55 PM PDT 24 |
| Peak memory | 660120 kb |
| Host | smart-711a5292-685f-4821-af90-0938673b6cfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321539853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.2321539853 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.4188299834 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 5841775160 ps |
| CPU time | 482.01 seconds |
| Started | Jul 09 07:25:42 PM PDT 24 |
| Finished | Jul 09 07:33:59 PM PDT 24 |
| Peak memory | 599168 kb |
| Host | smart-8079243a-a5f5-47ab-ac7e-bc9bff6d12b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188299834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.4188299834 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.1194052508 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 15713989960 ps |
| CPU time | 2141.62 seconds |
| Started | Jul 09 07:25:30 PM PDT 24 |
| Finished | Jul 09 08:01:24 PM PDT 24 |
| Peak memory | 593532 kb |
| Host | smart-ece57aa2-d9e3-40f5-96ed-414559d57080 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194052508 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.1194052508 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.796628804 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 1060040051 ps |
| CPU time | 70.54 seconds |
| Started | Jul 09 07:25:31 PM PDT 24 |
| Finished | Jul 09 07:26:54 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-fd968dd3-0b45-41ce-870e-800bc4ef1636 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796628804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.796628804 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.1587594237 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 25037033287 ps |
| CPU time | 428.2 seconds |
| Started | Jul 09 07:25:29 PM PDT 24 |
| Finished | Jul 09 07:32:48 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-95454e37-7607-4cd9-97b8-75985fdc07ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587594237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.1587594237 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.3040308664 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 282213461 ps |
| CPU time | 13.63 seconds |
| Started | Jul 09 07:25:41 PM PDT 24 |
| Finished | Jul 09 07:26:09 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-d0493424-a784-48bf-a4a7-d860f772cba5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040308664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .3040308664 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.2277405355 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 434507842 ps |
| CPU time | 17.09 seconds |
| Started | Jul 09 07:25:35 PM PDT 24 |
| Finished | Jul 09 07:26:04 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-330cac1b-5a84-491a-b076-294ae627809f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277405355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2277405355 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.3099080631 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 1824274271 ps |
| CPU time | 67.76 seconds |
| Started | Jul 09 07:25:36 PM PDT 24 |
| Finished | Jul 09 07:26:55 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-c3e251c0-1446-43a7-bc0b-29289d4bd810 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099080631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.3099080631 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.3581510383 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 4427814912 ps |
| CPU time | 44.6 seconds |
| Started | Jul 09 07:25:25 PM PDT 24 |
| Finished | Jul 09 07:26:21 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-80784bdf-515d-423e-ae02-c0a9538d9518 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581510383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3581510383 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.3777213426 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 53638433093 ps |
| CPU time | 840.28 seconds |
| Started | Jul 09 07:25:37 PM PDT 24 |
| Finished | Jul 09 07:39:51 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-174faba2-5663-4418-8d00-ad7a5aa6519b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777213426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3777213426 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.735225665 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 381542437 ps |
| CPU time | 29.8 seconds |
| Started | Jul 09 07:25:37 PM PDT 24 |
| Finished | Jul 09 07:26:20 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-3a3e4881-156b-45aa-9182-dbbf52e4162f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735225665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delay s.735225665 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.4171152694 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 214034968 ps |
| CPU time | 18.22 seconds |
| Started | Jul 09 07:25:27 PM PDT 24 |
| Finished | Jul 09 07:25:57 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-7e08f8f7-2fab-41ef-a23e-93dd0f47902f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171152694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.4171152694 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.4229595784 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 179549238 ps |
| CPU time | 8.75 seconds |
| Started | Jul 09 07:25:25 PM PDT 24 |
| Finished | Jul 09 07:25:45 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-d1472680-176c-4c22-996a-c0e85838d390 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229595784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.4229595784 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.3464097354 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 9459901749 ps |
| CPU time | 92.46 seconds |
| Started | Jul 09 07:25:41 PM PDT 24 |
| Finished | Jul 09 07:27:28 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-e812df98-77d8-4f1d-a86e-31a992c8c886 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464097354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3464097354 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.866970061 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 4436117728 ps |
| CPU time | 72.39 seconds |
| Started | Jul 09 07:25:28 PM PDT 24 |
| Finished | Jul 09 07:26:52 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-20458c34-ed51-40df-9cbb-dbd06e88d480 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866970061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.866970061 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.2359958742 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 44200032 ps |
| CPU time | 6.2 seconds |
| Started | Jul 09 07:25:27 PM PDT 24 |
| Finished | Jul 09 07:25:45 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-4bd8796f-eb4b-4432-a231-34b0c062f3fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359958742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .2359958742 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.2886281801 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 479583184 ps |
| CPU time | 28.22 seconds |
| Started | Jul 09 07:25:36 PM PDT 24 |
| Finished | Jul 09 07:26:16 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-d2b796aa-4b26-4dc6-8ee0-0cf02b96d7ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886281801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2886281801 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.3601193982 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 10865488215 ps |
| CPU time | 374.78 seconds |
| Started | Jul 09 07:25:38 PM PDT 24 |
| Finished | Jul 09 07:32:05 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-5da82164-1c8a-45da-8c7c-a4ff94cc3c6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601193982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3601193982 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.619085964 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 3143916695 ps |
| CPU time | 443.4 seconds |
| Started | Jul 09 07:25:33 PM PDT 24 |
| Finished | Jul 09 07:33:08 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-5f64e9c7-72ab-4a4a-a0b8-33ca71c63dfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619085964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_reset_error.619085964 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.627255928 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 184760440 ps |
| CPU time | 21.64 seconds |
| Started | Jul 09 07:25:37 PM PDT 24 |
| Finished | Jul 09 07:26:12 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-44b7f88e-de74-465a-b997-ae09be1d5ea8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627255928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.627255928 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.160019730 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 618625546 ps |
| CPU time | 25.41 seconds |
| Started | Jul 09 07:31:55 PM PDT 24 |
| Finished | Jul 09 07:32:23 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-38be470d-ce58-46ab-a833-8fa402753a02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160019730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device. 160019730 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.4208570747 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 221123642 ps |
| CPU time | 11.37 seconds |
| Started | Jul 09 07:32:04 PM PDT 24 |
| Finished | Jul 09 07:32:17 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-1b0a8dcd-3079-46ab-9c95-fed64e6f1266 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208570747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.4208570747 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.1747335382 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 518443738 ps |
| CPU time | 37.68 seconds |
| Started | Jul 09 07:32:04 PM PDT 24 |
| Finished | Jul 09 07:32:43 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-733e617a-3ac8-48c5-b6c5-4120a70a7be9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747335382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1747335382 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.3737815427 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 1221230629 ps |
| CPU time | 46.98 seconds |
| Started | Jul 09 07:31:50 PM PDT 24 |
| Finished | Jul 09 07:32:39 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-0fa0512e-93c5-4bb9-adf2-7c43f204b7a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737815427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.3737815427 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.3646292091 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 45407290040 ps |
| CPU time | 473.36 seconds |
| Started | Jul 09 07:31:57 PM PDT 24 |
| Finished | Jul 09 07:39:53 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-49683984-f439-45b9-a7af-6adf359ade4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646292091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3646292091 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.1908031226 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 17307192530 ps |
| CPU time | 283.2 seconds |
| Started | Jul 09 07:32:04 PM PDT 24 |
| Finished | Jul 09 07:36:49 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-96e2c928-a5f7-41cb-9c3d-a6f0fdf9d94b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908031226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1908031226 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.4290012398 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 305484802 ps |
| CPU time | 29.26 seconds |
| Started | Jul 09 07:31:52 PM PDT 24 |
| Finished | Jul 09 07:32:23 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-49201992-54d0-419a-87c1-d0e60c1a3f4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290012398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.4290012398 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.2005423680 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 448034456 ps |
| CPU time | 35.3 seconds |
| Started | Jul 09 07:31:58 PM PDT 24 |
| Finished | Jul 09 07:32:36 PM PDT 24 |
| Peak memory | 576452 kb |
| Host | smart-d3a99cd8-877b-41e3-80a2-f5c60d7239d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005423680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2005423680 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.2759469498 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 240172000 ps |
| CPU time | 10.02 seconds |
| Started | Jul 09 07:31:51 PM PDT 24 |
| Finished | Jul 09 07:32:03 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-8349bf23-3bee-4166-a229-fc5e8aeeb584 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759469498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2759469498 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.2962737666 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 7982801116 ps |
| CPU time | 82.45 seconds |
| Started | Jul 09 07:31:50 PM PDT 24 |
| Finished | Jul 09 07:33:14 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-38166213-5f00-4062-a59a-0202ad9d639c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962737666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2962737666 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.2297652414 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 5532730884 ps |
| CPU time | 102.45 seconds |
| Started | Jul 09 07:31:51 PM PDT 24 |
| Finished | Jul 09 07:33:36 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-c344104a-b58c-4fdc-a568-501d81b35d49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297652414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2297652414 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.2558622347 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 57234785 ps |
| CPU time | 7.43 seconds |
| Started | Jul 09 07:31:54 PM PDT 24 |
| Finished | Jul 09 07:32:04 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-a163c378-7a4a-4ee5-8061-4a08f49e590e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558622347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.2558622347 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.2093518963 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 2618968841 ps |
| CPU time | 93.79 seconds |
| Started | Jul 09 07:32:03 PM PDT 24 |
| Finished | Jul 09 07:33:38 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-0fd763cb-4b19-49f9-924f-22a649d5dce1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093518963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2093518963 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.4139921223 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 13947843145 ps |
| CPU time | 476.83 seconds |
| Started | Jul 09 07:32:02 PM PDT 24 |
| Finished | Jul 09 07:40:00 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-d615b2c1-4be7-4239-acf5-8423fb4a012b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139921223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.4139921223 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.4196969836 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 5961763477 ps |
| CPU time | 307.73 seconds |
| Started | Jul 09 07:32:02 PM PDT 24 |
| Finished | Jul 09 07:37:11 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-f8951233-54bd-4776-9556-f5425c342c9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196969836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.4196969836 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3834485839 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 1986002184 ps |
| CPU time | 219.39 seconds |
| Started | Jul 09 07:31:58 PM PDT 24 |
| Finished | Jul 09 07:35:39 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-e1262158-abd0-4156-83a7-675348b12b88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834485839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.3834485839 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.338040467 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 134286118 ps |
| CPU time | 16.36 seconds |
| Started | Jul 09 07:32:03 PM PDT 24 |
| Finished | Jul 09 07:32:21 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-6df92d4e-8ff4-4b54-920c-601768d36d3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338040467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.338040467 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.3444890859 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 563324195 ps |
| CPU time | 41.17 seconds |
| Started | Jul 09 07:32:08 PM PDT 24 |
| Finished | Jul 09 07:32:51 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-50c2f2e0-a153-4849-be2c-c82dfd69cae2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444890859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .3444890859 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2796772687 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 86711042864 ps |
| CPU time | 1606.32 seconds |
| Started | Jul 09 07:32:08 PM PDT 24 |
| Finished | Jul 09 07:58:56 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-029970a7-6501-46a7-96a5-c1c8a4f4db06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796772687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.2796772687 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.959209737 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 1228523479 ps |
| CPU time | 40.93 seconds |
| Started | Jul 09 07:32:10 PM PDT 24 |
| Finished | Jul 09 07:32:52 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-ad7b6e4d-7416-4913-b351-f29531fc8105 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959209737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr .959209737 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.3745515940 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 300990621 ps |
| CPU time | 23.07 seconds |
| Started | Jul 09 07:32:13 PM PDT 24 |
| Finished | Jul 09 07:32:37 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-60416cbc-b6c8-4a13-8cd7-10bc97301b74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745515940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3745515940 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.509215827 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 961942261 ps |
| CPU time | 34.44 seconds |
| Started | Jul 09 07:32:13 PM PDT 24 |
| Finished | Jul 09 07:32:49 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-d5c1956b-3964-4e40-9e35-2bf9582fc106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509215827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.509215827 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.1514006539 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 36228270106 ps |
| CPU time | 396.23 seconds |
| Started | Jul 09 07:32:06 PM PDT 24 |
| Finished | Jul 09 07:38:44 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-ae0783b8-fa34-48fa-899e-e4b67048bcb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514006539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1514006539 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.2139421824 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 10250353291 ps |
| CPU time | 183.45 seconds |
| Started | Jul 09 07:32:07 PM PDT 24 |
| Finished | Jul 09 07:35:12 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-904547de-62b5-4a4b-ad45-89b49b0f793e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139421824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2139421824 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.648343941 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 192207174 ps |
| CPU time | 19.5 seconds |
| Started | Jul 09 07:32:08 PM PDT 24 |
| Finished | Jul 09 07:32:29 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-c373fe8a-74d8-4e60-af86-cfe2e3b3509e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648343941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_dela ys.648343941 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.4195211441 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 505809138 ps |
| CPU time | 17.54 seconds |
| Started | Jul 09 07:32:09 PM PDT 24 |
| Finished | Jul 09 07:32:28 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-1d289d67-36d5-4478-bd96-bcf424f45402 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195211441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.4195211441 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.3776173481 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 175755011 ps |
| CPU time | 8.43 seconds |
| Started | Jul 09 07:31:58 PM PDT 24 |
| Finished | Jul 09 07:32:08 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-980ae625-8e44-4cb3-bf0d-bc300dbe8e05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776173481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3776173481 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.1120649656 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 9805177722 ps |
| CPU time | 98.57 seconds |
| Started | Jul 09 07:31:59 PM PDT 24 |
| Finished | Jul 09 07:33:40 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-2571770b-0c9c-4d70-b8ee-ca92758e5bd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120649656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1120649656 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.3713572063 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 4224351638 ps |
| CPU time | 72.26 seconds |
| Started | Jul 09 07:32:08 PM PDT 24 |
| Finished | Jul 09 07:33:22 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-57813ae1-d1cd-43df-aa23-59c486b7a602 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713572063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3713572063 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.3384553778 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 43856949 ps |
| CPU time | 5.89 seconds |
| Started | Jul 09 07:32:03 PM PDT 24 |
| Finished | Jul 09 07:32:10 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-8be57009-806b-47f2-ba3c-dc02895424bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384553778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.3384553778 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.528591404 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 3715472830 ps |
| CPU time | 151.28 seconds |
| Started | Jul 09 07:32:07 PM PDT 24 |
| Finished | Jul 09 07:34:41 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-f5bcea28-ff70-439f-876a-1da7f5e0c505 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528591404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.528591404 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.1109390373 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 2146118429 ps |
| CPU time | 166.66 seconds |
| Started | Jul 09 07:32:08 PM PDT 24 |
| Finished | Jul 09 07:34:56 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-6f3baf40-a7ab-4337-8d0b-e561346e4b06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109390373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1109390373 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.1777992226 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 661269560 ps |
| CPU time | 174.35 seconds |
| Started | Jul 09 07:32:07 PM PDT 24 |
| Finished | Jul 09 07:35:03 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-dc55f553-968b-4b85-8577-9ffdfbc7f689 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777992226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.1777992226 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.1877314201 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 10938296083 ps |
| CPU time | 501.44 seconds |
| Started | Jul 09 07:32:08 PM PDT 24 |
| Finished | Jul 09 07:40:31 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-ea782eff-c3df-40c3-b30e-265078739885 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877314201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.1877314201 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.3584317475 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 226994317 ps |
| CPU time | 12.23 seconds |
| Started | Jul 09 07:32:06 PM PDT 24 |
| Finished | Jul 09 07:32:20 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-88bd48d8-cad8-42d7-9108-62c77b954547 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584317475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3584317475 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.731439891 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 81167042840 ps |
| CPU time | 1470.82 seconds |
| Started | Jul 09 07:32:16 PM PDT 24 |
| Finished | Jul 09 07:56:48 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-9bcc40c3-2c0f-4413-b506-712be0b4f548 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731439891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_d evice_slow_rsp.731439891 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.1152956562 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 263817435 ps |
| CPU time | 29.54 seconds |
| Started | Jul 09 07:32:14 PM PDT 24 |
| Finished | Jul 09 07:32:45 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-071f670d-2855-41de-b0cb-b3dffdb0633b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152956562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.1152956562 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.1669965602 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 1514581237 ps |
| CPU time | 47.78 seconds |
| Started | Jul 09 07:32:29 PM PDT 24 |
| Finished | Jul 09 07:33:18 PM PDT 24 |
| Peak memory | 576456 kb |
| Host | smart-eee9eba1-24e5-46cf-afdb-dd1436171596 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669965602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1669965602 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.3338148743 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 354309134 ps |
| CPU time | 29.86 seconds |
| Started | Jul 09 07:32:15 PM PDT 24 |
| Finished | Jul 09 07:32:46 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-6fcee968-2c4a-447c-88fd-779736085646 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338148743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.3338148743 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.3293421102 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 100407156804 ps |
| CPU time | 1046.71 seconds |
| Started | Jul 09 07:32:17 PM PDT 24 |
| Finished | Jul 09 07:49:45 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-3ef3b73d-60fc-4940-a8dd-df464896814e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293421102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3293421102 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.152341064 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 24866358405 ps |
| CPU time | 440.63 seconds |
| Started | Jul 09 07:32:16 PM PDT 24 |
| Finished | Jul 09 07:39:38 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-a065c1f9-1a0e-4ef1-916e-9642cf9cde0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152341064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.152341064 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.628226727 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 499564009 ps |
| CPU time | 44.2 seconds |
| Started | Jul 09 07:32:15 PM PDT 24 |
| Finished | Jul 09 07:33:00 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-d308e3d6-acae-43e0-bf7b-ced4cb8d0073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628226727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_dela ys.628226727 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.4110798577 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 485060104 ps |
| CPU time | 33.05 seconds |
| Started | Jul 09 07:32:17 PM PDT 24 |
| Finished | Jul 09 07:32:51 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-5c067f92-db92-4edf-babe-5b7316ed85cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110798577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.4110798577 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.1402219197 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 47437212 ps |
| CPU time | 6.54 seconds |
| Started | Jul 09 07:32:19 PM PDT 24 |
| Finished | Jul 09 07:32:27 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-f442d78e-93c3-4414-a17d-056e03d57a5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402219197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1402219197 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.2848352868 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 8442068337 ps |
| CPU time | 85.98 seconds |
| Started | Jul 09 07:32:28 PM PDT 24 |
| Finished | Jul 09 07:33:56 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-766bc0fc-8c32-4c13-a680-40b1af976881 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848352868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2848352868 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.4233628272 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 4949617889 ps |
| CPU time | 83.03 seconds |
| Started | Jul 09 07:32:15 PM PDT 24 |
| Finished | Jul 09 07:33:39 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-79b0069f-5dfd-4ea0-bd91-d12657634b03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233628272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.4233628272 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.1171600450 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 45699458 ps |
| CPU time | 6.32 seconds |
| Started | Jul 09 07:32:13 PM PDT 24 |
| Finished | Jul 09 07:32:21 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-9d164e44-ee7e-4693-99dc-e85cbc7b63a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171600450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.1171600450 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.1293634278 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 3363238213 ps |
| CPU time | 290.38 seconds |
| Started | Jul 09 07:32:18 PM PDT 24 |
| Finished | Jul 09 07:37:09 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-d55f7a62-3e31-47dc-b1d9-ed55faddee56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293634278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1293634278 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.1942399568 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 204145474 ps |
| CPU time | 23.07 seconds |
| Started | Jul 09 07:32:30 PM PDT 24 |
| Finished | Jul 09 07:32:55 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-ab51aa4d-30cf-4a1b-bb2e-569d3edde3fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942399568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1942399568 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.3234807500 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 28649827535 ps |
| CPU time | 1283.72 seconds |
| Started | Jul 09 07:32:14 PM PDT 24 |
| Finished | Jul 09 07:53:39 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-1f8a8917-247f-4ad3-b4f2-10a9278cd193 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234807500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.3234807500 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.916435725 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 1098857001 ps |
| CPU time | 44.32 seconds |
| Started | Jul 09 07:32:29 PM PDT 24 |
| Finished | Jul 09 07:33:15 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-d3a0dd08-51bc-4de5-8473-ddc1c7773eba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916435725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.916435725 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.3687499924 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 2614961655 ps |
| CPU time | 90.26 seconds |
| Started | Jul 09 07:32:26 PM PDT 24 |
| Finished | Jul 09 07:33:58 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-33437a1c-d761-4a47-91bb-9feff8f587ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687499924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device .3687499924 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1702363197 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 8218489903 ps |
| CPU time | 149.88 seconds |
| Started | Jul 09 07:32:25 PM PDT 24 |
| Finished | Jul 09 07:34:56 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-803a32ad-4143-4ee0-a20c-926774f62e88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702363197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.1702363197 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.553857926 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 1163411510 ps |
| CPU time | 51.15 seconds |
| Started | Jul 09 07:32:23 PM PDT 24 |
| Finished | Jul 09 07:33:15 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-c9a2302e-a6cb-4beb-b7a0-6e768af0d98d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553857926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr .553857926 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.3202526503 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 622255970 ps |
| CPU time | 49.29 seconds |
| Started | Jul 09 07:32:23 PM PDT 24 |
| Finished | Jul 09 07:33:14 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-93c904ec-3f83-44c4-83d2-c28cba055520 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202526503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3202526503 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.3360234177 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 1606494023 ps |
| CPU time | 57.96 seconds |
| Started | Jul 09 07:32:23 PM PDT 24 |
| Finished | Jul 09 07:33:23 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-562dbd7a-c67a-4382-b15c-3868b495c327 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360234177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.3360234177 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.3830370585 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 4152925923 ps |
| CPU time | 42.72 seconds |
| Started | Jul 09 07:32:30 PM PDT 24 |
| Finished | Jul 09 07:33:14 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-bbe89ed9-7c59-40a6-8d32-ea7ffd66d29a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830370585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3830370585 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.2759243100 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 17126127727 ps |
| CPU time | 315.79 seconds |
| Started | Jul 09 07:32:24 PM PDT 24 |
| Finished | Jul 09 07:37:41 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-a6371c41-5d61-4884-94a9-71522988e8ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759243100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2759243100 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.1089086179 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 580244330 ps |
| CPU time | 49.37 seconds |
| Started | Jul 09 07:32:22 PM PDT 24 |
| Finished | Jul 09 07:33:13 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-0a343d1e-d4af-4a28-8a39-89aeb51188e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089086179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.1089086179 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.322919481 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 289676226 ps |
| CPU time | 22.2 seconds |
| Started | Jul 09 07:32:21 PM PDT 24 |
| Finished | Jul 09 07:32:45 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-f5a0aa41-cc62-45eb-a4b8-7c91e1b343db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322919481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.322919481 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.212034068 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 37558595 ps |
| CPU time | 5.55 seconds |
| Started | Jul 09 07:32:23 PM PDT 24 |
| Finished | Jul 09 07:32:30 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-59962047-c2e6-44de-944c-c31e85f0bd7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212034068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.212034068 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.763586620 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 7463453600 ps |
| CPU time | 78.86 seconds |
| Started | Jul 09 07:32:25 PM PDT 24 |
| Finished | Jul 09 07:33:46 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-63ad977a-3046-435b-b2b6-fd352f3faf95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763586620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.763586620 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2808432265 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 5900490343 ps |
| CPU time | 99.97 seconds |
| Started | Jul 09 07:32:27 PM PDT 24 |
| Finished | Jul 09 07:34:08 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-745b76eb-95dd-442a-9604-cb3a32a7a218 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808432265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2808432265 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.1277336688 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 38580675 ps |
| CPU time | 6.2 seconds |
| Started | Jul 09 07:32:21 PM PDT 24 |
| Finished | Jul 09 07:32:29 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-663b7c81-4a3b-4997-b845-5583e088873b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277336688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.1277336688 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.2430947688 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 14239915505 ps |
| CPU time | 529.21 seconds |
| Started | Jul 09 07:32:24 PM PDT 24 |
| Finished | Jul 09 07:41:15 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-3bb684db-e5ed-4031-98a8-450d01dfe6e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430947688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2430947688 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.2396322030 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 5298728246 ps |
| CPU time | 208.32 seconds |
| Started | Jul 09 07:32:26 PM PDT 24 |
| Finished | Jul 09 07:35:56 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-bef53c8e-57cd-4c84-a976-645a86cf2a05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396322030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2396322030 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.3064461547 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 5548645384 ps |
| CPU time | 511.51 seconds |
| Started | Jul 09 07:32:21 PM PDT 24 |
| Finished | Jul 09 07:40:54 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-177621b2-44bb-4e0e-a114-9630c0211f53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064461547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.3064461547 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.2846237779 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 108083123 ps |
| CPU time | 53.96 seconds |
| Started | Jul 09 07:32:26 PM PDT 24 |
| Finished | Jul 09 07:33:21 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-5ebc7cf5-4564-4127-86f2-2eaf23f1b442 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846237779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.2846237779 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.1796119957 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 289402937 ps |
| CPU time | 32.01 seconds |
| Started | Jul 09 07:32:24 PM PDT 24 |
| Finished | Jul 09 07:32:58 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-69fd52da-d158-4a8c-a635-b962663626ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796119957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1796119957 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.635661450 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 2559327946 ps |
| CPU time | 92.13 seconds |
| Started | Jul 09 07:32:32 PM PDT 24 |
| Finished | Jul 09 07:34:05 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-95740b3e-e93d-4947-987d-50be74102954 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635661450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device. 635661450 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3582179148 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 11048964238 ps |
| CPU time | 187.6 seconds |
| Started | Jul 09 07:32:30 PM PDT 24 |
| Finished | Jul 09 07:35:39 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-b71a5552-af55-4522-b891-e21dfdc3e548 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582179148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.3582179148 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.2741905936 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 316781332 ps |
| CPU time | 32.13 seconds |
| Started | Jul 09 07:32:35 PM PDT 24 |
| Finished | Jul 09 07:33:09 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-7e7b6a34-cc74-4d15-956b-4e7a7d810625 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741905936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.2741905936 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.3602536884 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 1481178257 ps |
| CPU time | 53.01 seconds |
| Started | Jul 09 07:32:33 PM PDT 24 |
| Finished | Jul 09 07:33:27 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-05173d9a-e63b-4438-a5de-6fb52c7d885a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602536884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3602536884 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.467827297 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 573080190 ps |
| CPU time | 22.49 seconds |
| Started | Jul 09 07:32:36 PM PDT 24 |
| Finished | Jul 09 07:33:00 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-c3c0ee63-e64a-46e3-be41-e1133578fa73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467827297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.467827297 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.2782485424 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 35418622551 ps |
| CPU time | 626.46 seconds |
| Started | Jul 09 07:32:30 PM PDT 24 |
| Finished | Jul 09 07:42:58 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-634c0d6f-da81-443a-ba11-e4aa67926155 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782485424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2782485424 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.2567322208 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 320772036 ps |
| CPU time | 27.75 seconds |
| Started | Jul 09 07:32:32 PM PDT 24 |
| Finished | Jul 09 07:33:01 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-ff49eabf-ee4c-4bb3-b6a2-d8e754b75b7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567322208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.2567322208 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.1815317524 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 2513637403 ps |
| CPU time | 74.45 seconds |
| Started | Jul 09 07:32:30 PM PDT 24 |
| Finished | Jul 09 07:33:46 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-324d4bfb-2b4e-45b7-865d-0372a9f081e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815317524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1815317524 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.3151767047 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 34562914 ps |
| CPU time | 5.68 seconds |
| Started | Jul 09 07:32:23 PM PDT 24 |
| Finished | Jul 09 07:32:30 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-77dfb3e1-e86d-4d21-b75e-b90fcff77b0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151767047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3151767047 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.611578642 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 4579568335 ps |
| CPU time | 48.33 seconds |
| Started | Jul 09 07:32:22 PM PDT 24 |
| Finished | Jul 09 07:33:12 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-51c97dd6-9d27-4913-9795-fe789fcb615b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611578642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.611578642 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.4286795778 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 3161234090 ps |
| CPU time | 51.77 seconds |
| Started | Jul 09 07:32:38 PM PDT 24 |
| Finished | Jul 09 07:33:31 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-c4435d71-19d2-40d2-b3c5-b841dc40a6de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286795778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.4286795778 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.3735674469 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 40979539 ps |
| CPU time | 6.11 seconds |
| Started | Jul 09 07:32:24 PM PDT 24 |
| Finished | Jul 09 07:32:32 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-a791bc00-4011-4497-b9b5-508e6cf566d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735674469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.3735674469 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.3531414736 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 3373579909 ps |
| CPU time | 246.86 seconds |
| Started | Jul 09 07:32:33 PM PDT 24 |
| Finished | Jul 09 07:36:41 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-a41c11cd-2970-4149-85d9-bbecddae7b5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531414736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3531414736 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.2660548930 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 2730771682 ps |
| CPU time | 202.36 seconds |
| Started | Jul 09 07:32:39 PM PDT 24 |
| Finished | Jul 09 07:36:03 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-e70aecf6-9c14-49e3-b036-36c23b5dc243 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660548930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2660548930 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.1293466906 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 9286188396 ps |
| CPU time | 555.87 seconds |
| Started | Jul 09 07:32:29 PM PDT 24 |
| Finished | Jul 09 07:41:47 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-f45a357e-fbf3-45ea-9047-df1aa91a098c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293466906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.1293466906 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.1556363900 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 43447576 ps |
| CPU time | 18.28 seconds |
| Started | Jul 09 07:32:52 PM PDT 24 |
| Finished | Jul 09 07:33:12 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-0f414ef3-e503-4777-8287-0a892a348523 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556363900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.1556363900 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.3623521200 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 279950634 ps |
| CPU time | 33.53 seconds |
| Started | Jul 09 07:32:30 PM PDT 24 |
| Finished | Jul 09 07:33:05 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-0e9fea39-867d-40b2-97e3-72a38c19b231 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623521200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3623521200 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.846001329 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 1389255592 ps |
| CPU time | 57.17 seconds |
| Started | Jul 09 07:32:37 PM PDT 24 |
| Finished | Jul 09 07:33:35 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-912e48c3-75e5-4c0c-9d22-b14953cb2d34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846001329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device. 846001329 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.4091884557 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 63753456543 ps |
| CPU time | 1080.09 seconds |
| Started | Jul 09 07:32:38 PM PDT 24 |
| Finished | Jul 09 07:50:40 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-dd54025b-7303-4fea-93eb-e25919f772d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091884557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.4091884557 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.1217037912 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 469398636 ps |
| CPU time | 22.65 seconds |
| Started | Jul 09 07:32:45 PM PDT 24 |
| Finished | Jul 09 07:33:10 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-7ab3d772-d97a-4952-a2a8-e009634ec1fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217037912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.1217037912 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.3065802360 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 388901446 ps |
| CPU time | 30.84 seconds |
| Started | Jul 09 07:32:38 PM PDT 24 |
| Finished | Jul 09 07:33:10 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-e866a6c2-96de-4691-95e2-262466d99a19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065802360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3065802360 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.3009032470 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 2359107765 ps |
| CPU time | 72.71 seconds |
| Started | Jul 09 07:32:37 PM PDT 24 |
| Finished | Jul 09 07:33:51 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-d4283e1f-a878-4321-ab13-1fe0dac7b4ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009032470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.3009032470 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.3864709095 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 103232396693 ps |
| CPU time | 1059.1 seconds |
| Started | Jul 09 07:32:39 PM PDT 24 |
| Finished | Jul 09 07:50:20 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-c5455368-2177-4707-84e5-0e5db8918099 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864709095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3864709095 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.2800330559 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 15407604562 ps |
| CPU time | 253.47 seconds |
| Started | Jul 09 07:32:40 PM PDT 24 |
| Finished | Jul 09 07:36:54 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-10acb607-95e6-47c8-b386-141cd851bf2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800330559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2800330559 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.2333251332 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 303247925 ps |
| CPU time | 27.64 seconds |
| Started | Jul 09 07:32:37 PM PDT 24 |
| Finished | Jul 09 07:33:06 PM PDT 24 |
| Peak memory | 576468 kb |
| Host | smart-d58571c7-124d-4066-a037-b6bafa8345f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333251332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.2333251332 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.3034727676 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 1543101713 ps |
| CPU time | 46.54 seconds |
| Started | Jul 09 07:32:38 PM PDT 24 |
| Finished | Jul 09 07:33:26 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-25407041-f696-470f-be6d-06cd46053714 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034727676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3034727676 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.2553699420 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 200651025 ps |
| CPU time | 8.18 seconds |
| Started | Jul 09 07:32:38 PM PDT 24 |
| Finished | Jul 09 07:32:48 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-3b1b91c6-7876-49bb-8186-5b81dac9906e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553699420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2553699420 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.2302959008 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 8074797598 ps |
| CPU time | 85.37 seconds |
| Started | Jul 09 07:32:44 PM PDT 24 |
| Finished | Jul 09 07:34:10 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-7285f95b-8773-47b6-8a21-1394bf3601a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302959008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2302959008 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.3084954138 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 4736462780 ps |
| CPU time | 78.24 seconds |
| Started | Jul 09 07:32:38 PM PDT 24 |
| Finished | Jul 09 07:33:58 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-cae4c72c-7275-4fa3-bec7-eed80faf3a4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084954138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3084954138 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.703652121 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 38588897 ps |
| CPU time | 5.97 seconds |
| Started | Jul 09 07:32:38 PM PDT 24 |
| Finished | Jul 09 07:32:45 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-3a693769-7024-4cde-ba91-40dd103b96ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703652121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays .703652121 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.3155843066 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 2132544585 ps |
| CPU time | 99.84 seconds |
| Started | Jul 09 07:32:44 PM PDT 24 |
| Finished | Jul 09 07:34:26 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-04d20212-dea6-4506-a16e-24fc363c9986 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155843066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3155843066 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.1520287616 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 4359673682 ps |
| CPU time | 304.99 seconds |
| Started | Jul 09 07:32:47 PM PDT 24 |
| Finished | Jul 09 07:37:54 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-1f549d71-aab6-4758-9531-fdeb0a17530a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520287616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1520287616 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.1159329589 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 94793275 ps |
| CPU time | 48.01 seconds |
| Started | Jul 09 07:32:45 PM PDT 24 |
| Finished | Jul 09 07:33:34 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-a03a166a-62e4-416e-80e9-44634c18d76d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159329589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.1159329589 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.1762428137 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 3231740541 ps |
| CPU time | 173.7 seconds |
| Started | Jul 09 07:32:45 PM PDT 24 |
| Finished | Jul 09 07:35:41 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-0683a527-c52f-42c5-9fe5-ed48f5cb0140 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762428137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.1762428137 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.382087505 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 231376315 ps |
| CPU time | 29.53 seconds |
| Started | Jul 09 07:32:48 PM PDT 24 |
| Finished | Jul 09 07:33:19 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-fe60849d-f9fb-4d37-9ac4-16b956942d2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382087505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.382087505 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.3804906889 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 263851624 ps |
| CPU time | 11.71 seconds |
| Started | Jul 09 07:32:48 PM PDT 24 |
| Finished | Jul 09 07:33:01 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-efc97a86-fed9-4117-9a19-2907b5f74b78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804906889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .3804906889 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.2447716602 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 21102072812 ps |
| CPU time | 350.64 seconds |
| Started | Jul 09 07:32:44 PM PDT 24 |
| Finished | Jul 09 07:38:36 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-ac7d375a-be96-44cd-ae3b-37931d4242fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447716602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.2447716602 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.831482689 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 1010725652 ps |
| CPU time | 37.42 seconds |
| Started | Jul 09 07:32:52 PM PDT 24 |
| Finished | Jul 09 07:33:31 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-6173f384-40ac-4e76-8fea-907acff5bbc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831482689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr .831482689 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.2511502158 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 458293257 ps |
| CPU time | 16.56 seconds |
| Started | Jul 09 07:32:52 PM PDT 24 |
| Finished | Jul 09 07:33:11 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-dcbc3597-03b3-4f2e-84c7-08ba25b8bee7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511502158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2511502158 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.575083998 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 2133279862 ps |
| CPU time | 76.76 seconds |
| Started | Jul 09 07:32:50 PM PDT 24 |
| Finished | Jul 09 07:34:07 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-3e756e31-b3f5-4659-8c8d-484c281b6095 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575083998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.575083998 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.1977804839 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 46911937796 ps |
| CPU time | 464.89 seconds |
| Started | Jul 09 07:32:45 PM PDT 24 |
| Finished | Jul 09 07:40:31 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-33c05c30-9471-4c34-b55e-ed9208bd6b0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977804839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1977804839 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.2530074232 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 38606010188 ps |
| CPU time | 638.46 seconds |
| Started | Jul 09 07:32:50 PM PDT 24 |
| Finished | Jul 09 07:43:29 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-d5589672-b18c-4660-b35d-867b6ba04db3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530074232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2530074232 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.6308300 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 592250470 ps |
| CPU time | 53.31 seconds |
| Started | Jul 09 07:32:46 PM PDT 24 |
| Finished | Jul 09 07:33:41 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-cda7814d-7bf1-4280-99b3-655ab6a50531 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6308300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.6308300 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.1098796566 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 2292030391 ps |
| CPU time | 60.76 seconds |
| Started | Jul 09 07:32:47 PM PDT 24 |
| Finished | Jul 09 07:33:50 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-01fc7b8f-1d20-467b-b86d-806392772d9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098796566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1098796566 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.3278432122 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 38318896 ps |
| CPU time | 5.6 seconds |
| Started | Jul 09 07:32:45 PM PDT 24 |
| Finished | Jul 09 07:32:52 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-cb5568cc-bc96-46aa-8c06-df1956ace223 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278432122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3278432122 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.925419091 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 7805667167 ps |
| CPU time | 86 seconds |
| Started | Jul 09 07:32:45 PM PDT 24 |
| Finished | Jul 09 07:34:13 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-ce61e97c-c7f6-4dfe-9337-bca391ad4d30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925419091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.925419091 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.1524455647 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 4796508302 ps |
| CPU time | 81.91 seconds |
| Started | Jul 09 07:32:47 PM PDT 24 |
| Finished | Jul 09 07:34:10 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-d52be684-3509-442c-9088-4da42e4c1fb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524455647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1524455647 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.1947775027 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 46097368 ps |
| CPU time | 5.63 seconds |
| Started | Jul 09 07:32:46 PM PDT 24 |
| Finished | Jul 09 07:32:54 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-b5ff372d-8568-4054-a228-7e779edc8eaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947775027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.1947775027 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.1021599882 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 8702244547 ps |
| CPU time | 322.72 seconds |
| Started | Jul 09 07:32:52 PM PDT 24 |
| Finished | Jul 09 07:38:16 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-0204a3a5-cfec-46c9-92f6-060ddf6c2e59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021599882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1021599882 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.2131740355 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 10179070458 ps |
| CPU time | 366.85 seconds |
| Started | Jul 09 07:32:53 PM PDT 24 |
| Finished | Jul 09 07:39:02 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-8cca8989-e27c-4296-9f85-e262164bd351 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131740355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2131740355 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3252242453 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 18851774719 ps |
| CPU time | 872.32 seconds |
| Started | Jul 09 07:33:00 PM PDT 24 |
| Finished | Jul 09 07:47:33 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-34d6bcbf-0ddb-408e-a689-51bc7c35d740 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252242453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.3252242453 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.295917953 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 7512161 ps |
| CPU time | 4.98 seconds |
| Started | Jul 09 07:32:51 PM PDT 24 |
| Finished | Jul 09 07:32:58 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-744e84fd-d5b2-4acb-a45f-46cc641ac186 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295917953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_reset_error.295917953 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.720157891 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 1016313801 ps |
| CPU time | 47.39 seconds |
| Started | Jul 09 07:32:51 PM PDT 24 |
| Finished | Jul 09 07:33:40 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-7fcf12cd-19a4-42e0-99b1-bf69da8c6f69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720157891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.720157891 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.3552840553 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 1528577913 ps |
| CPU time | 77.11 seconds |
| Started | Jul 09 07:33:02 PM PDT 24 |
| Finished | Jul 09 07:34:20 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-9e7572e9-e992-4962-bff8-227d2e9d270a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552840553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .3552840553 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.288434021 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 510362813 ps |
| CPU time | 22.36 seconds |
| Started | Jul 09 07:32:59 PM PDT 24 |
| Finished | Jul 09 07:33:23 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-5c3fd8d4-cddc-4d67-9aa2-c4148c32f444 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288434021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr .288434021 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.1349562652 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 862365559 ps |
| CPU time | 30.31 seconds |
| Started | Jul 09 07:32:59 PM PDT 24 |
| Finished | Jul 09 07:33:31 PM PDT 24 |
| Peak memory | 576492 kb |
| Host | smart-fe6b91e9-daf3-49d6-8c77-75dd7456bd11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349562652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1349562652 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.2099944707 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 1582655347 ps |
| CPU time | 62.22 seconds |
| Started | Jul 09 07:32:54 PM PDT 24 |
| Finished | Jul 09 07:33:57 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-775770d2-bf78-412b-af12-fa8aaa3b5632 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099944707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.2099944707 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.205893999 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 15942724573 ps |
| CPU time | 164.15 seconds |
| Started | Jul 09 07:33:00 PM PDT 24 |
| Finished | Jul 09 07:35:45 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-49870c6b-dbb4-433b-a3b4-717f45ac722d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205893999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.205893999 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.3955909613 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 48592845021 ps |
| CPU time | 871.52 seconds |
| Started | Jul 09 07:33:01 PM PDT 24 |
| Finished | Jul 09 07:47:34 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-ec633654-96e4-4200-b0d8-6b25f067dd58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955909613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3955909613 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.513101003 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 116031942 ps |
| CPU time | 11.86 seconds |
| Started | Jul 09 07:33:05 PM PDT 24 |
| Finished | Jul 09 07:33:18 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-45b28ca5-a47c-42f7-bfba-f7dc7f5fd75a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513101003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_dela ys.513101003 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.2806619690 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 278235809 ps |
| CPU time | 12.01 seconds |
| Started | Jul 09 07:33:03 PM PDT 24 |
| Finished | Jul 09 07:33:15 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-6a8dfb60-6730-4d66-b10c-e4e41bbc6443 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806619690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2806619690 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.2067462204 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 45114108 ps |
| CPU time | 5.93 seconds |
| Started | Jul 09 07:32:53 PM PDT 24 |
| Finished | Jul 09 07:33:00 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-836fbb89-ca80-4be7-8b35-7eb257c9ca97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067462204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2067462204 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.3378052194 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 9054720510 ps |
| CPU time | 92.6 seconds |
| Started | Jul 09 07:32:59 PM PDT 24 |
| Finished | Jul 09 07:34:33 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-f7f74206-3556-4ff8-a75e-854ee06ac3ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378052194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3378052194 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.550951600 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 4912563785 ps |
| CPU time | 80.17 seconds |
| Started | Jul 09 07:32:56 PM PDT 24 |
| Finished | Jul 09 07:34:17 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-0516fadc-2195-4ada-ba0a-a7f41d0dbd67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550951600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.550951600 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.1399085372 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 45396498 ps |
| CPU time | 6.47 seconds |
| Started | Jul 09 07:32:52 PM PDT 24 |
| Finished | Jul 09 07:33:01 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-a21d7abf-999e-48a3-9bd7-8c672fd26ec5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399085372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.1399085372 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.2555694296 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 4122220388 ps |
| CPU time | 346.85 seconds |
| Started | Jul 09 07:33:02 PM PDT 24 |
| Finished | Jul 09 07:38:50 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-5cc9982a-9d50-487c-9ffd-bd364f973263 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555694296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2555694296 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.2386875612 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 2197649840 ps |
| CPU time | 79.77 seconds |
| Started | Jul 09 07:33:00 PM PDT 24 |
| Finished | Jul 09 07:34:21 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-95f565e6-0f6b-4148-b2e4-c1bb1f9fca83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386875612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2386875612 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2899868773 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 535120658 ps |
| CPU time | 221.99 seconds |
| Started | Jul 09 07:33:01 PM PDT 24 |
| Finished | Jul 09 07:36:44 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-d4e8e767-4425-41cc-b5fd-feb99ecc951a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899868773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.2899868773 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.1503020976 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 497260742 ps |
| CPU time | 172.65 seconds |
| Started | Jul 09 07:33:05 PM PDT 24 |
| Finished | Jul 09 07:35:58 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-63a7ff02-fe96-45ab-8e02-4683ff839bcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503020976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.1503020976 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.987337329 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 727057494 ps |
| CPU time | 27.43 seconds |
| Started | Jul 09 07:33:00 PM PDT 24 |
| Finished | Jul 09 07:33:29 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-f38d0ca2-1fe5-4549-b3e9-cd51f33a2e41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987337329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.987337329 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.3356517796 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 1700361693 ps |
| CPU time | 68.26 seconds |
| Started | Jul 09 07:33:09 PM PDT 24 |
| Finished | Jul 09 07:34:19 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-2487e7b3-9acf-4309-a8e0-15dd315db28e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356517796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .3356517796 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.2659697056 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 53933507642 ps |
| CPU time | 995.73 seconds |
| Started | Jul 09 07:33:07 PM PDT 24 |
| Finished | Jul 09 07:49:44 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-ef693ac1-2c34-402a-9e04-04ef184ca048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659697056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.2659697056 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.39089002 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 429163242 ps |
| CPU time | 20.48 seconds |
| Started | Jul 09 07:33:15 PM PDT 24 |
| Finished | Jul 09 07:33:37 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-5da45aff-f33e-4069-a316-8c2afabdb9d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39089002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.39089002 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.990971660 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 421051506 ps |
| CPU time | 16.16 seconds |
| Started | Jul 09 07:33:08 PM PDT 24 |
| Finished | Jul 09 07:33:25 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-9f7372b2-6870-4982-bccd-5a26ff31e965 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990971660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.990971660 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.2199186550 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 34764856 ps |
| CPU time | 5.93 seconds |
| Started | Jul 09 07:33:13 PM PDT 24 |
| Finished | Jul 09 07:33:20 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-c3d0ca59-a434-4227-b573-966e83992b61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199186550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.2199186550 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.2011775915 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 30787921601 ps |
| CPU time | 331.23 seconds |
| Started | Jul 09 07:33:08 PM PDT 24 |
| Finished | Jul 09 07:38:40 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-e33781a4-1b49-4aad-9b10-7cce2ae98faf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011775915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2011775915 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.2939270437 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 51283087281 ps |
| CPU time | 932.56 seconds |
| Started | Jul 09 07:33:08 PM PDT 24 |
| Finished | Jul 09 07:48:42 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-8bc3f8bc-42f2-4523-88ce-580056d50efb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939270437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2939270437 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.1862042725 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 552325965 ps |
| CPU time | 45.89 seconds |
| Started | Jul 09 07:33:11 PM PDT 24 |
| Finished | Jul 09 07:33:58 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-a6d85b23-e45b-4dbe-b408-78382026cfd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862042725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.1862042725 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.4198648495 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 2440419796 ps |
| CPU time | 78.59 seconds |
| Started | Jul 09 07:33:09 PM PDT 24 |
| Finished | Jul 09 07:34:29 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-464a4573-5b9e-4c67-b7c0-99a49ae14cc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198648495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.4198648495 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.658101228 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 47917141 ps |
| CPU time | 6.23 seconds |
| Started | Jul 09 07:33:05 PM PDT 24 |
| Finished | Jul 09 07:33:12 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-83ab1c77-3640-47f7-bb58-cdcbb56e883b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658101228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.658101228 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.3529147404 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 10230125869 ps |
| CPU time | 106.21 seconds |
| Started | Jul 09 07:33:11 PM PDT 24 |
| Finished | Jul 09 07:34:58 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-4893e7f5-2345-4507-8cb6-333698746918 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529147404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3529147404 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1815881509 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 4279075193 ps |
| CPU time | 74.94 seconds |
| Started | Jul 09 07:33:11 PM PDT 24 |
| Finished | Jul 09 07:34:27 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-ac64abe6-e72c-497c-a137-8dc4f985385d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815881509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1815881509 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.1450769530 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 46938717 ps |
| CPU time | 6.03 seconds |
| Started | Jul 09 07:33:06 PM PDT 24 |
| Finished | Jul 09 07:33:13 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-aea7a721-1cb5-4934-8989-c77a4679003a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450769530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay s.1450769530 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.2828484927 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 2729559061 ps |
| CPU time | 268.81 seconds |
| Started | Jul 09 07:33:16 PM PDT 24 |
| Finished | Jul 09 07:37:46 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-37a8cdc4-50ef-4f81-bdbe-ddc2d3267b8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828484927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2828484927 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.4148461981 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 4991626356 ps |
| CPU time | 182.52 seconds |
| Started | Jul 09 07:33:17 PM PDT 24 |
| Finished | Jul 09 07:36:22 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-4bb9954c-11b2-454b-bc96-37d7bbb9265c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148461981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.4148461981 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2346501746 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1084501021 ps |
| CPU time | 40.34 seconds |
| Started | Jul 09 07:33:16 PM PDT 24 |
| Finished | Jul 09 07:33:58 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-d516a690-1b8d-46cd-b0db-18197ec3013d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346501746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.2346501746 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.391349588 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 18258871667 ps |
| CPU time | 753.38 seconds |
| Started | Jul 09 07:33:16 PM PDT 24 |
| Finished | Jul 09 07:45:51 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-a8709868-e11b-4928-a2e8-edb0957f9114 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391349588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_reset_error.391349588 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.593877296 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 611294839 ps |
| CPU time | 28.77 seconds |
| Started | Jul 09 07:33:11 PM PDT 24 |
| Finished | Jul 09 07:33:40 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-e0871a7f-a465-4bb9-8775-6eaec8ec2605 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593877296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.593877296 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.558699595 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 494874929 ps |
| CPU time | 38.83 seconds |
| Started | Jul 09 07:33:23 PM PDT 24 |
| Finished | Jul 09 07:34:05 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-ffe5034b-0dd9-4fc9-8a0c-21efef20f102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558699595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device. 558699595 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.3139012858 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 112551577509 ps |
| CPU time | 2034.53 seconds |
| Started | Jul 09 07:33:21 PM PDT 24 |
| Finished | Jul 09 08:07:18 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-01c8013b-04e8-41b8-a4d4-4df40ab92551 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139012858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.3139012858 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1130744098 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 1259686395 ps |
| CPU time | 46.36 seconds |
| Started | Jul 09 07:33:23 PM PDT 24 |
| Finished | Jul 09 07:34:11 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-73f3d952-e4d9-4e27-9ca9-8ca1fc54653d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130744098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.1130744098 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.4171511093 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 192496633 ps |
| CPU time | 18.3 seconds |
| Started | Jul 09 07:33:22 PM PDT 24 |
| Finished | Jul 09 07:33:42 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-475447da-392c-44d9-ac1f-65af7247078a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171511093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.4171511093 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.1426480612 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 622827155 ps |
| CPU time | 22.03 seconds |
| Started | Jul 09 07:33:16 PM PDT 24 |
| Finished | Jul 09 07:33:40 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-f6d90d0d-c846-4e39-af35-c40c3b98c601 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426480612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.1426480612 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.3513682537 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 85397180318 ps |
| CPU time | 896.71 seconds |
| Started | Jul 09 07:33:17 PM PDT 24 |
| Finished | Jul 09 07:48:15 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-8cf9f6c0-3c92-4ac6-8dd4-4ff40de719ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513682537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3513682537 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.2327578947 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 35546054634 ps |
| CPU time | 607.81 seconds |
| Started | Jul 09 07:33:15 PM PDT 24 |
| Finished | Jul 09 07:43:25 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-22a271b0-62db-479c-97be-de5096b4e970 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327578947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2327578947 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.2127810742 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 572764916 ps |
| CPU time | 45.58 seconds |
| Started | Jul 09 07:33:19 PM PDT 24 |
| Finished | Jul 09 07:34:07 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-cfd9c8ab-7a7d-4807-9f95-a176abceaafe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127810742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.2127810742 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.1548782781 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 2407792874 ps |
| CPU time | 66.2 seconds |
| Started | Jul 09 07:33:23 PM PDT 24 |
| Finished | Jul 09 07:34:31 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-d1d2559c-d555-4cc8-bc75-4c2db8ac6263 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548782781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1548782781 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.3086828254 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 40537614 ps |
| CPU time | 6.44 seconds |
| Started | Jul 09 07:33:14 PM PDT 24 |
| Finished | Jul 09 07:33:22 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-a6c30154-3f5f-42bf-b2da-8c02b254d0b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086828254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3086828254 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1692182888 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 7263793228 ps |
| CPU time | 75.1 seconds |
| Started | Jul 09 07:33:19 PM PDT 24 |
| Finished | Jul 09 07:34:36 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-c8eb4366-b9d1-4630-a004-03a83c41b027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692182888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1692182888 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.1696116049 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 5630118756 ps |
| CPU time | 92.96 seconds |
| Started | Jul 09 07:33:19 PM PDT 24 |
| Finished | Jul 09 07:34:54 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-98fe1cbe-afe2-49ab-91d8-cd5944f206ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696116049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1696116049 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.2401339879 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 46212315 ps |
| CPU time | 6.21 seconds |
| Started | Jul 09 07:33:18 PM PDT 24 |
| Finished | Jul 09 07:33:27 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-a15259a2-0f66-44ff-97e4-75d7e6f88ce4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401339879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.2401339879 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.1172015367 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 14627123593 ps |
| CPU time | 461.15 seconds |
| Started | Jul 09 07:33:20 PM PDT 24 |
| Finished | Jul 09 07:41:03 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-598329ce-bea9-4d6a-b4fe-ddafa2856f37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172015367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1172015367 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.1367020827 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 2128169823 ps |
| CPU time | 161.63 seconds |
| Started | Jul 09 07:33:21 PM PDT 24 |
| Finished | Jul 09 07:36:05 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-95de9984-beea-4d7b-b9f0-078fa3ed62e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367020827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1367020827 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.1023623911 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 101418343 ps |
| CPU time | 29.89 seconds |
| Started | Jul 09 07:33:23 PM PDT 24 |
| Finished | Jul 09 07:33:55 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-8b764de1-fe08-4d7a-a4e4-81886ef63712 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023623911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.1023623911 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.3697376539 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 450404511 ps |
| CPU time | 135.05 seconds |
| Started | Jul 09 07:33:31 PM PDT 24 |
| Finished | Jul 09 07:35:48 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-4779d6ae-27a3-4abd-b2a2-db9aff3eebb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697376539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.3697376539 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.636752593 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 1451037203 ps |
| CPU time | 54.68 seconds |
| Started | Jul 09 07:33:23 PM PDT 24 |
| Finished | Jul 09 07:34:20 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-71f4a90f-4372-49f0-85d6-1a413b794af7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636752593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.636752593 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.3725258380 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 4834874358 ps |
| CPU time | 308.88 seconds |
| Started | Jul 09 07:25:51 PM PDT 24 |
| Finished | Jul 09 07:31:19 PM PDT 24 |
| Peak memory | 596812 kb |
| Host | smart-2541e579-a1e4-4ae0-9290-c6bfdfccc377 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725258380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.3725258380 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.2037628208 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 31841149460 ps |
| CPU time | 4514.53 seconds |
| Started | Jul 09 07:25:30 PM PDT 24 |
| Finished | Jul 09 08:40:57 PM PDT 24 |
| Peak memory | 593752 kb |
| Host | smart-f2e81cff-c5b5-4ce7-9f2c-2ef997812990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037628208 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.2037628208 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.3129625334 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 4747888296 ps |
| CPU time | 352.71 seconds |
| Started | Jul 09 07:25:33 PM PDT 24 |
| Finished | Jul 09 07:31:38 PM PDT 24 |
| Peak memory | 603948 kb |
| Host | smart-e9e778f7-2687-4534-be00-ff4eecf3d3b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129625334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.3129625334 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.974067338 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 868152657 ps |
| CPU time | 75.23 seconds |
| Started | Jul 09 07:25:31 PM PDT 24 |
| Finished | Jul 09 07:26:58 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-84ca737e-05f7-4c1d-bf6d-9ebe62017387 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974067338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.974067338 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.483378180 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 77920497482 ps |
| CPU time | 1402.35 seconds |
| Started | Jul 09 07:25:33 PM PDT 24 |
| Finished | Jul 09 07:49:08 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-0362fab9-d38a-4b9e-92e6-abd859a1cdb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483378180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_de vice_slow_rsp.483378180 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.3575801116 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 582899076 ps |
| CPU time | 24.83 seconds |
| Started | Jul 09 07:25:43 PM PDT 24 |
| Finished | Jul 09 07:26:24 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-176aa7c0-5eab-453b-a892-af62789e1f2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575801116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .3575801116 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.1917391114 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 1256157534 ps |
| CPU time | 43.17 seconds |
| Started | Jul 09 07:25:32 PM PDT 24 |
| Finished | Jul 09 07:26:27 PM PDT 24 |
| Peak memory | 576464 kb |
| Host | smart-a94a4164-f438-4deb-b214-192eb68f3c6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917391114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1917391114 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.1779820581 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 320694201 ps |
| CPU time | 29.18 seconds |
| Started | Jul 09 07:25:32 PM PDT 24 |
| Finished | Jul 09 07:26:13 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-188d8861-cd62-4d18-abfe-f30a889db221 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779820581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.1779820581 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.2304679169 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 102360967361 ps |
| CPU time | 995.61 seconds |
| Started | Jul 09 07:25:31 PM PDT 24 |
| Finished | Jul 09 07:42:19 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-67b9b8f5-ca5c-456e-99e4-dcf12f3ae33a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304679169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2304679169 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.4184391149 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 54106054952 ps |
| CPU time | 862.4 seconds |
| Started | Jul 09 07:25:35 PM PDT 24 |
| Finished | Jul 09 07:40:09 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-1cdc2ca2-68b3-486c-8729-142a6d9ebcc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184391149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.4184391149 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.3976364641 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 66492407 ps |
| CPU time | 8.56 seconds |
| Started | Jul 09 07:25:31 PM PDT 24 |
| Finished | Jul 09 07:25:52 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-10c536ee-0b80-4269-bc37-36239c715a8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976364641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.3976364641 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.1704543183 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 241313866 ps |
| CPU time | 19.74 seconds |
| Started | Jul 09 07:25:31 PM PDT 24 |
| Finished | Jul 09 07:26:03 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-306c6288-b3b4-41c8-9018-aae6e90fe174 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704543183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1704543183 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.4167234049 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 43862306 ps |
| CPU time | 5.82 seconds |
| Started | Jul 09 07:25:33 PM PDT 24 |
| Finished | Jul 09 07:25:51 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-135d8d0d-32a3-4401-b8b6-8928465c0401 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167234049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.4167234049 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.2496477555 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 7568751073 ps |
| CPU time | 75.68 seconds |
| Started | Jul 09 07:25:43 PM PDT 24 |
| Finished | Jul 09 07:27:14 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-8c958c56-f526-4a8a-93e5-8c41aceb4fbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496477555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2496477555 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1178935353 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 5690047010 ps |
| CPU time | 91.21 seconds |
| Started | Jul 09 07:25:33 PM PDT 24 |
| Finished | Jul 09 07:27:16 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-e3e9bc47-7e48-492f-b32d-39b8eb10b89b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178935353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1178935353 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.781062384 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 54129513 ps |
| CPU time | 6.65 seconds |
| Started | Jul 09 07:25:30 PM PDT 24 |
| Finished | Jul 09 07:25:48 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-170f7227-66bc-4859-b214-51e1c19edc13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781062384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays. 781062384 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.2162193401 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 198659832 ps |
| CPU time | 8.25 seconds |
| Started | Jul 09 07:25:44 PM PDT 24 |
| Finished | Jul 09 07:26:08 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-c2fb7d05-8d84-41d9-ba22-d475169eaf4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162193401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2162193401 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.1779071203 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 6201162009 ps |
| CPU time | 196.43 seconds |
| Started | Jul 09 07:25:38 PM PDT 24 |
| Finished | Jul 09 07:29:08 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-2dc57194-7bad-408f-96b3-6226343fe4ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779071203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1779071203 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.296812839 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 4657994822 ps |
| CPU time | 247.84 seconds |
| Started | Jul 09 07:25:44 PM PDT 24 |
| Finished | Jul 09 07:30:08 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-13ba892f-4bcd-47a2-ac1e-6f777f0ab8a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296812839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_reset_error.296812839 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.2205784786 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 1012825018 ps |
| CPU time | 41.8 seconds |
| Started | Jul 09 07:25:43 PM PDT 24 |
| Finished | Jul 09 07:26:41 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-f0ac89ff-279a-4e10-9734-a83becdaaaf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205784786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2205784786 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.1790591516 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 2126298575 ps |
| CPU time | 86.42 seconds |
| Started | Jul 09 07:33:30 PM PDT 24 |
| Finished | Jul 09 07:34:58 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-9e539915-8820-440f-93fc-26bcc6c08255 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790591516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .1790591516 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1496295482 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 114142663365 ps |
| CPU time | 2230.72 seconds |
| Started | Jul 09 07:33:29 PM PDT 24 |
| Finished | Jul 09 08:10:42 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-ca0380af-195e-478a-9e87-73f2c176e570 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496295482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.1496295482 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.1475873347 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 564731040 ps |
| CPU time | 23.17 seconds |
| Started | Jul 09 07:33:32 PM PDT 24 |
| Finished | Jul 09 07:33:57 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-a2d619f8-00f4-4d9e-8542-bc445193b0c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475873347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.1475873347 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.3512475696 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 477927587 ps |
| CPU time | 35.68 seconds |
| Started | Jul 09 07:33:28 PM PDT 24 |
| Finished | Jul 09 07:34:05 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-a6eaac21-d5f6-407f-9781-b13b7c6fe58c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512475696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.3512475696 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.279569620 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 231030260 ps |
| CPU time | 21.35 seconds |
| Started | Jul 09 07:33:30 PM PDT 24 |
| Finished | Jul 09 07:33:53 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-a1e5e201-54f5-4e4a-b584-ab832d8dc1f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279569620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.279569620 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.3365539657 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 58511927834 ps |
| CPU time | 588.63 seconds |
| Started | Jul 09 07:33:30 PM PDT 24 |
| Finished | Jul 09 07:43:20 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-546d1ad3-a777-4567-a1ec-8a429f7a0989 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365539657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.3365539657 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.1399093226 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 13418165548 ps |
| CPU time | 220.77 seconds |
| Started | Jul 09 07:33:32 PM PDT 24 |
| Finished | Jul 09 07:37:16 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-0c7f734e-a8e3-4751-be4c-6d47de78056b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399093226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.1399093226 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.3058575671 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 155647836 ps |
| CPU time | 18.02 seconds |
| Started | Jul 09 07:33:28 PM PDT 24 |
| Finished | Jul 09 07:33:47 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-6c838baf-1479-4193-9b9d-c53870f3214c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058575671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.3058575671 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.1161751303 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 1978783701 ps |
| CPU time | 54.77 seconds |
| Started | Jul 09 07:33:30 PM PDT 24 |
| Finished | Jul 09 07:34:26 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-4f31e23e-582e-424d-91c6-2f2e3eed7038 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161751303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.1161751303 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.580167154 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 246398745 ps |
| CPU time | 10.61 seconds |
| Started | Jul 09 07:33:30 PM PDT 24 |
| Finished | Jul 09 07:33:43 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-cd41d821-8663-4ca7-92cc-134c0ec4dfcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580167154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.580167154 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.388130459 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 6726272956 ps |
| CPU time | 67.87 seconds |
| Started | Jul 09 07:33:33 PM PDT 24 |
| Finished | Jul 09 07:34:43 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-e9db1397-8740-42bb-9dba-8166213edd72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388130459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.388130459 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.3042186077 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 4081975356 ps |
| CPU time | 68.03 seconds |
| Started | Jul 09 07:33:30 PM PDT 24 |
| Finished | Jul 09 07:34:39 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-8bdacc0c-140f-4ec8-83c0-f6a0e4408a49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042186077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.3042186077 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.2494923364 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 53223309 ps |
| CPU time | 6.66 seconds |
| Started | Jul 09 07:33:30 PM PDT 24 |
| Finished | Jul 09 07:33:38 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-eeee0169-0037-4d4d-be64-4ad59aac4ed3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494923364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.2494923364 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.3572676502 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 9949725768 ps |
| CPU time | 395.24 seconds |
| Started | Jul 09 07:33:31 PM PDT 24 |
| Finished | Jul 09 07:40:09 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-9a852b6e-777b-4698-b671-302be7139c04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572676502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.3572676502 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.372726386 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 14299294862 ps |
| CPU time | 504.43 seconds |
| Started | Jul 09 07:33:35 PM PDT 24 |
| Finished | Jul 09 07:42:02 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-e5d86d56-7b70-470f-983b-79b9e7cabe8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372726386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.372726386 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.4244491499 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 5672794858 ps |
| CPU time | 645.9 seconds |
| Started | Jul 09 07:33:36 PM PDT 24 |
| Finished | Jul 09 07:44:25 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-28554c7b-613b-4eba-be3c-485cf9e52b95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244491499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.4244491499 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.1333691112 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 509878473 ps |
| CPU time | 166.78 seconds |
| Started | Jul 09 07:33:34 PM PDT 24 |
| Finished | Jul 09 07:36:24 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-4d07ea66-456c-4e4f-84e6-6d9552556e25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333691112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.1333691112 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.475754871 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 37616067 ps |
| CPU time | 7.07 seconds |
| Started | Jul 09 07:33:27 PM PDT 24 |
| Finished | Jul 09 07:33:36 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-5b00c38d-9782-4a74-a4c6-ae65d3cc3681 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475754871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.475754871 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.1635212022 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 3221324341 ps |
| CPU time | 126.93 seconds |
| Started | Jul 09 07:33:33 PM PDT 24 |
| Finished | Jul 09 07:35:43 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-f77de03c-0b8d-4b30-959b-a1c3d158baad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635212022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .1635212022 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.3458098569 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 89499730189 ps |
| CPU time | 1642.32 seconds |
| Started | Jul 09 07:33:43 PM PDT 24 |
| Finished | Jul 09 08:01:08 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-2453edf5-6ca8-4f08-980b-bbd1602eaf33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458098569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.3458098569 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.2760285458 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 142775690 ps |
| CPU time | 16.06 seconds |
| Started | Jul 09 07:33:43 PM PDT 24 |
| Finished | Jul 09 07:34:01 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-12c05289-4637-4dad-b559-a591a485e99a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760285458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.2760285458 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.4236909919 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 1129119892 ps |
| CPU time | 38.77 seconds |
| Started | Jul 09 07:33:46 PM PDT 24 |
| Finished | Jul 09 07:34:26 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-7d282a0c-ffe2-48ac-8ddb-e2cc9eb07962 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236909919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.4236909919 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.3774416745 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 1226841813 ps |
| CPU time | 43.72 seconds |
| Started | Jul 09 07:33:34 PM PDT 24 |
| Finished | Jul 09 07:34:20 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-eab8e817-5a00-4824-aa0c-01f2fb79aa81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774416745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.3774416745 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.3667540544 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 17357294116 ps |
| CPU time | 171.7 seconds |
| Started | Jul 09 07:33:36 PM PDT 24 |
| Finished | Jul 09 07:36:31 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-ede0e723-b033-4f99-a1eb-1537a5b5c36a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667540544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.3667540544 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.3898319384 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 3665123271 ps |
| CPU time | 60.1 seconds |
| Started | Jul 09 07:33:36 PM PDT 24 |
| Finished | Jul 09 07:34:39 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-d91db87e-a4cf-4258-8616-86a83d478508 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898319384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.3898319384 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.414382879 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 532557302 ps |
| CPU time | 43.36 seconds |
| Started | Jul 09 07:33:34 PM PDT 24 |
| Finished | Jul 09 07:34:21 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-ccf16b2a-b132-45d9-aefb-49bae75d8ff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414382879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_dela ys.414382879 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.3681786880 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 2158478330 ps |
| CPU time | 72.17 seconds |
| Started | Jul 09 07:33:42 PM PDT 24 |
| Finished | Jul 09 07:34:56 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-97f8e1ae-9afa-4264-b6ca-5497822661b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681786880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.3681786880 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.4043356293 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 43265703 ps |
| CPU time | 5.95 seconds |
| Started | Jul 09 07:33:34 PM PDT 24 |
| Finished | Jul 09 07:33:43 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-966a4ebb-da87-48e7-ba0f-fbbb95615990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043356293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.4043356293 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.57348265 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 7967615944 ps |
| CPU time | 75.06 seconds |
| Started | Jul 09 07:33:35 PM PDT 24 |
| Finished | Jul 09 07:34:54 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-57f4c5cc-4b4e-43bd-b086-87ae896c7178 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57348265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.57348265 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.2499042674 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 5117942530 ps |
| CPU time | 84.87 seconds |
| Started | Jul 09 07:33:35 PM PDT 24 |
| Finished | Jul 09 07:35:04 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-6461a8be-14af-450d-9b5a-69d07d4cc6d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499042674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.2499042674 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.2650637978 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 44813140 ps |
| CPU time | 5.76 seconds |
| Started | Jul 09 07:33:36 PM PDT 24 |
| Finished | Jul 09 07:33:45 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-16a9324f-7d40-4ab6-97e1-1b502756bfad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650637978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.2650637978 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.3774105172 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 5338973945 ps |
| CPU time | 212.35 seconds |
| Started | Jul 09 07:33:42 PM PDT 24 |
| Finished | Jul 09 07:37:17 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-72feda69-22ec-4865-8aa4-5561f667feed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774105172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.3774105172 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.1906665648 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 1369329104 ps |
| CPU time | 46.61 seconds |
| Started | Jul 09 07:33:43 PM PDT 24 |
| Finished | Jul 09 07:34:31 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-afc6aa87-ad4a-42f2-8df2-1aee7fed6e61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906665648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.1906665648 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.3263368797 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 551703695 ps |
| CPU time | 238.07 seconds |
| Started | Jul 09 07:33:43 PM PDT 24 |
| Finished | Jul 09 07:37:43 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-48bbde4c-1390-45d9-a1eb-fb9f91e92798 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263368797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.3263368797 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.4095516382 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 572804270 ps |
| CPU time | 157.74 seconds |
| Started | Jul 09 07:33:42 PM PDT 24 |
| Finished | Jul 09 07:36:21 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-dcf79bff-93bc-44d0-82e4-8151083567ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095516382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.4095516382 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.3735173078 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 110580556 ps |
| CPU time | 16.28 seconds |
| Started | Jul 09 07:33:43 PM PDT 24 |
| Finished | Jul 09 07:34:01 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-41676106-9e00-4b35-bae1-2b9af514f3f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735173078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.3735173078 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.2862508506 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 836818149 ps |
| CPU time | 65.04 seconds |
| Started | Jul 09 07:33:49 PM PDT 24 |
| Finished | Jul 09 07:34:55 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-7a7883a8-31a9-4efe-b127-2649ba9127d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862508506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .2862508506 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.187529801 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 97042196755 ps |
| CPU time | 1841.09 seconds |
| Started | Jul 09 07:33:48 PM PDT 24 |
| Finished | Jul 09 08:04:30 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-e979c80f-7f4c-41bd-bfca-029104575dce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187529801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_d evice_slow_rsp.187529801 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.1542073451 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 315047216 ps |
| CPU time | 29.71 seconds |
| Started | Jul 09 07:33:51 PM PDT 24 |
| Finished | Jul 09 07:34:22 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-783f0e30-7797-4229-9223-4ed752ddf481 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542073451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.1542073451 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.4206014334 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 92527810 ps |
| CPU time | 9.66 seconds |
| Started | Jul 09 07:33:52 PM PDT 24 |
| Finished | Jul 09 07:34:02 PM PDT 24 |
| Peak memory | 576484 kb |
| Host | smart-35e21403-a100-4b9d-b79d-709185c789b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206014334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.4206014334 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.2102068554 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 138632255 ps |
| CPU time | 13.76 seconds |
| Started | Jul 09 07:33:55 PM PDT 24 |
| Finished | Jul 09 07:34:10 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-565edd68-8718-4203-bc1f-774b48d2caf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102068554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.2102068554 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.61008422 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 54777298519 ps |
| CPU time | 580.21 seconds |
| Started | Jul 09 07:33:53 PM PDT 24 |
| Finished | Jul 09 07:43:35 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-c0909631-b72e-40ce-9dd3-7f928d4dd2bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61008422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.61008422 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.261003161 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 21245524400 ps |
| CPU time | 352.31 seconds |
| Started | Jul 09 07:33:55 PM PDT 24 |
| Finished | Jul 09 07:39:49 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-ec99b585-bbf8-485d-9bf0-fbac67f8bc63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261003161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.261003161 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.2352322280 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 488769102 ps |
| CPU time | 36.8 seconds |
| Started | Jul 09 07:33:50 PM PDT 24 |
| Finished | Jul 09 07:34:28 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-0e452025-4d23-4344-9624-f9b36f65b40d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352322280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.2352322280 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.341331800 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 1610835089 ps |
| CPU time | 46.82 seconds |
| Started | Jul 09 07:33:55 PM PDT 24 |
| Finished | Jul 09 07:34:43 PM PDT 24 |
| Peak memory | 576456 kb |
| Host | smart-74e875a7-2807-4587-bc47-d3bc943c2446 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341331800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.341331800 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.489554786 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 219477866 ps |
| CPU time | 9.51 seconds |
| Started | Jul 09 07:33:47 PM PDT 24 |
| Finished | Jul 09 07:33:57 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-4a42c39f-cc35-479d-a22e-bb227a31ea35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489554786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.489554786 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.2864895044 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 7356508723 ps |
| CPU time | 76.62 seconds |
| Started | Jul 09 07:33:50 PM PDT 24 |
| Finished | Jul 09 07:35:07 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-781f3b36-effb-4934-9eeb-35e2b6807ae2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864895044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.2864895044 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.4125117299 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 6304249526 ps |
| CPU time | 115.39 seconds |
| Started | Jul 09 07:33:50 PM PDT 24 |
| Finished | Jul 09 07:35:47 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-dff2911f-05b8-43f5-a5ed-b9efc87df3cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125117299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.4125117299 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.796112997 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 41448500 ps |
| CPU time | 5.8 seconds |
| Started | Jul 09 07:33:45 PM PDT 24 |
| Finished | Jul 09 07:33:52 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-1a401e69-0ceb-41f3-a5fd-627c335f9f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796112997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delays .796112997 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.3118315923 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 1114953651 ps |
| CPU time | 46.99 seconds |
| Started | Jul 09 07:33:50 PM PDT 24 |
| Finished | Jul 09 07:34:38 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-58b16c0c-0157-4116-b8fa-c868d02a449b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118315923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.3118315923 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.552047205 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 824315055 ps |
| CPU time | 72.15 seconds |
| Started | Jul 09 07:33:52 PM PDT 24 |
| Finished | Jul 09 07:35:05 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-184cb0ee-70e9-4dea-90e2-bc19dfa80ca7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552047205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.552047205 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2058071881 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 4607983938 ps |
| CPU time | 278.22 seconds |
| Started | Jul 09 07:33:51 PM PDT 24 |
| Finished | Jul 09 07:38:30 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-40ee0acc-859c-4144-be14-d6cf87135b47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058071881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.2058071881 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.3087880309 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 28313330 ps |
| CPU time | 13.43 seconds |
| Started | Jul 09 07:33:51 PM PDT 24 |
| Finished | Jul 09 07:34:05 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-e844790a-bbed-46f9-92eb-c136f174c6bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087880309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.3087880309 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.1916197228 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 234104024 ps |
| CPU time | 12.85 seconds |
| Started | Jul 09 07:33:49 PM PDT 24 |
| Finished | Jul 09 07:34:03 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-71b23477-302e-4f19-8868-66ecc744f06f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916197228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.1916197228 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.401655124 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 65603804 ps |
| CPU time | 7.19 seconds |
| Started | Jul 09 07:33:57 PM PDT 24 |
| Finished | Jul 09 07:34:05 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-2004498e-0f1b-44ed-8bc9-307d9c653bbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401655124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device. 401655124 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.2637290864 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 14956625235 ps |
| CPU time | 259.32 seconds |
| Started | Jul 09 07:33:58 PM PDT 24 |
| Finished | Jul 09 07:38:18 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-90d4d5b0-d06c-4538-a3de-996affc78498 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637290864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.2637290864 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.1713913792 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 224795949 ps |
| CPU time | 25.3 seconds |
| Started | Jul 09 07:35:33 PM PDT 24 |
| Finished | Jul 09 07:35:59 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-1af53c70-9929-4e79-837e-0318b6846af4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713913792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.1713913792 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.357672776 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 948713970 ps |
| CPU time | 31.16 seconds |
| Started | Jul 09 07:35:32 PM PDT 24 |
| Finished | Jul 09 07:36:04 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-cfa7e403-99f0-468f-b1e0-eb0c4ad5532e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357672776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.357672776 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.1771739238 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 592630469 ps |
| CPU time | 49.76 seconds |
| Started | Jul 09 07:33:58 PM PDT 24 |
| Finished | Jul 09 07:34:50 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-70c1a5a5-96f2-4ac5-ba0c-286ca5547551 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771739238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.1771739238 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.3704508172 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 38501274861 ps |
| CPU time | 405.09 seconds |
| Started | Jul 09 07:33:58 PM PDT 24 |
| Finished | Jul 09 07:40:45 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-8951a0e6-4a1d-46fa-8fe7-44bcc8acf3ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704508172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.3704508172 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.1774330670 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 27833026941 ps |
| CPU time | 462.71 seconds |
| Started | Jul 09 07:33:54 PM PDT 24 |
| Finished | Jul 09 07:41:39 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-7ad09236-f43f-4a74-baef-3b64bff7b230 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774330670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.1774330670 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.373709171 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 294060733 ps |
| CPU time | 28.24 seconds |
| Started | Jul 09 07:33:57 PM PDT 24 |
| Finished | Jul 09 07:34:26 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-d98b526e-ca96-4e24-a6ac-d49380eb7231 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373709171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_dela ys.373709171 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.2158926707 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 898752748 ps |
| CPU time | 28.46 seconds |
| Started | Jul 09 07:33:55 PM PDT 24 |
| Finished | Jul 09 07:34:25 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-5cd12eab-40fd-4a5c-a13d-07f677e2b239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158926707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.2158926707 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.1987731318 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 44318007 ps |
| CPU time | 6.36 seconds |
| Started | Jul 09 07:34:00 PM PDT 24 |
| Finished | Jul 09 07:34:08 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-3ad8bf9b-66ed-401a-81ce-7b0f3bac0f70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987731318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.1987731318 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.2385994955 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 9231672833 ps |
| CPU time | 100.18 seconds |
| Started | Jul 09 07:33:57 PM PDT 24 |
| Finished | Jul 09 07:35:38 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-761a1f0d-5c2e-4265-bf8a-c1998d34f0c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385994955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.2385994955 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.3123814438 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 6437293929 ps |
| CPU time | 112.29 seconds |
| Started | Jul 09 07:34:04 PM PDT 24 |
| Finished | Jul 09 07:35:58 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-ad91ebd3-5f9a-4344-9d1e-8a8d09646138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123814438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.3123814438 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.916857968 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 57288161 ps |
| CPU time | 6.82 seconds |
| Started | Jul 09 07:34:03 PM PDT 24 |
| Finished | Jul 09 07:34:12 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-0aeba811-d647-4c5d-8352-878f112322d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916857968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays .916857968 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.1273704718 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 11223190939 ps |
| CPU time | 422.15 seconds |
| Started | Jul 09 07:35:32 PM PDT 24 |
| Finished | Jul 09 07:42:36 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-2ed74f07-f6ef-4fa0-b126-01ec944cbf3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273704718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.1273704718 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.3228245080 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 617835393 ps |
| CPU time | 264.61 seconds |
| Started | Jul 09 07:35:33 PM PDT 24 |
| Finished | Jul 09 07:39:59 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-27187893-95e9-45fa-937a-d429a74e1692 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228245080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.3228245080 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.1978237318 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 7574544264 ps |
| CPU time | 417.91 seconds |
| Started | Jul 09 07:35:33 PM PDT 24 |
| Finished | Jul 09 07:42:33 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-e9ee0554-4fe8-4f67-bd93-bde3fcf800d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978237318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.1978237318 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.1220752944 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 1087630014 ps |
| CPU time | 49.75 seconds |
| Started | Jul 09 07:35:33 PM PDT 24 |
| Finished | Jul 09 07:36:25 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-38fa1837-a853-4bae-ac86-07bd397c4e28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220752944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.1220752944 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.3531799140 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 493061949 ps |
| CPU time | 23.11 seconds |
| Started | Jul 09 07:35:32 PM PDT 24 |
| Finished | Jul 09 07:35:57 PM PDT 24 |
| Peak memory | 576428 kb |
| Host | smart-891a4c25-9dbe-4e02-bd32-066f55a0df06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531799140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .3531799140 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.3436680428 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 30501689471 ps |
| CPU time | 542.96 seconds |
| Started | Jul 09 07:35:31 PM PDT 24 |
| Finished | Jul 09 07:44:35 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-d38feef9-fdf7-4e0d-bc3d-11241b2dbc0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436680428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.3436680428 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1711413868 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 770471121 ps |
| CPU time | 31.52 seconds |
| Started | Jul 09 07:35:34 PM PDT 24 |
| Finished | Jul 09 07:36:08 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-f6a02ec2-a021-4eb7-86c7-f161b55c36bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711413868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.1711413868 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.1491273096 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 1554486403 ps |
| CPU time | 46.99 seconds |
| Started | Jul 09 07:35:31 PM PDT 24 |
| Finished | Jul 09 07:36:19 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-8b1c406e-a2c7-4301-bc13-5127c280bd22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491273096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.1491273096 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.2075704136 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 1962077442 ps |
| CPU time | 72.48 seconds |
| Started | Jul 09 07:35:35 PM PDT 24 |
| Finished | Jul 09 07:36:49 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-08294b02-2f87-4555-bbff-f5c6037b9412 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075704136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.2075704136 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.999622753 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 86843942485 ps |
| CPU time | 1010.19 seconds |
| Started | Jul 09 07:35:36 PM PDT 24 |
| Finished | Jul 09 07:52:28 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-55cc6371-1f4b-4061-afa0-49ab6851ee52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999622753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.999622753 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.223185505 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 45050161407 ps |
| CPU time | 729.17 seconds |
| Started | Jul 09 07:35:35 PM PDT 24 |
| Finished | Jul 09 07:47:47 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-ec7864d5-b812-47d3-85ab-99f092ee2c41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223185505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.223185505 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.3770203069 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 489173991 ps |
| CPU time | 44.68 seconds |
| Started | Jul 09 07:35:33 PM PDT 24 |
| Finished | Jul 09 07:36:19 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-4f64023c-81e5-4b2f-a86a-57487fdb1cd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770203069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.3770203069 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.2685920588 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 2078367254 ps |
| CPU time | 65.99 seconds |
| Started | Jul 09 07:35:36 PM PDT 24 |
| Finished | Jul 09 07:36:44 PM PDT 24 |
| Peak memory | 576504 kb |
| Host | smart-48b77716-4983-4c5d-a0e6-9223c409ed1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685920588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.2685920588 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.4175259213 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 213485776 ps |
| CPU time | 9.05 seconds |
| Started | Jul 09 07:35:32 PM PDT 24 |
| Finished | Jul 09 07:35:42 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-8c695543-9622-4631-a5a1-a7057aee3be3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175259213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.4175259213 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.2163948900 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 8219492426 ps |
| CPU time | 81.36 seconds |
| Started | Jul 09 07:35:35 PM PDT 24 |
| Finished | Jul 09 07:36:59 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-ada7b922-e464-4a3b-b65b-dcc6614aaceb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163948900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.2163948900 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.2607420887 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 4689161513 ps |
| CPU time | 79.34 seconds |
| Started | Jul 09 07:35:33 PM PDT 24 |
| Finished | Jul 09 07:36:54 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-8551089c-f429-48e5-80be-685604c268db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607420887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.2607420887 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.3153210257 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 49855350 ps |
| CPU time | 5.9 seconds |
| Started | Jul 09 07:35:36 PM PDT 24 |
| Finished | Jul 09 07:35:44 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-2bbf246b-debf-463c-9331-faf0768989d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153210257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.3153210257 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.1350953199 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 7496303618 ps |
| CPU time | 268.02 seconds |
| Started | Jul 09 07:35:36 PM PDT 24 |
| Finished | Jul 09 07:40:07 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-4e8b44ea-04df-478f-a9e1-a39663f40839 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350953199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.1350953199 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.2086928608 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 12929313756 ps |
| CPU time | 491.24 seconds |
| Started | Jul 09 07:35:32 PM PDT 24 |
| Finished | Jul 09 07:43:45 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-68f1ddf3-e5e3-4fc4-a5d9-928af8067001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086928608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.2086928608 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.4135631051 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 243113937 ps |
| CPU time | 73.09 seconds |
| Started | Jul 09 07:35:29 PM PDT 24 |
| Finished | Jul 09 07:36:43 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-1dfe2813-2551-46b9-9db5-7c11dc5012db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135631051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.4135631051 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.2094616361 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 897763882 ps |
| CPU time | 304.73 seconds |
| Started | Jul 09 07:35:28 PM PDT 24 |
| Finished | Jul 09 07:40:33 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-63980a6c-11fe-4591-97ee-132043da241b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094616361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.2094616361 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.1943549696 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 149931704 ps |
| CPU time | 17.64 seconds |
| Started | Jul 09 07:35:35 PM PDT 24 |
| Finished | Jul 09 07:35:54 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-31fd5333-f4b6-43c4-ba10-c4cd76ccf6cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943549696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.1943549696 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.1968366602 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 99054704 ps |
| CPU time | 7.91 seconds |
| Started | Jul 09 07:35:32 PM PDT 24 |
| Finished | Jul 09 07:35:41 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-12496a1a-b664-4ab8-8cc3-cd9ce97f312e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968366602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .1968366602 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.70996524 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 71685687563 ps |
| CPU time | 1408.72 seconds |
| Started | Jul 09 07:35:36 PM PDT 24 |
| Finished | Jul 09 07:59:08 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-0b418b33-12ef-4f05-ac22-cffa6710fe7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70996524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_de vice_slow_rsp.70996524 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.2019456311 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 657002245 ps |
| CPU time | 31.94 seconds |
| Started | Jul 09 07:35:36 PM PDT 24 |
| Finished | Jul 09 07:36:11 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-73a0056c-a84e-46fa-aa59-9008a03e0072 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019456311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add r.2019456311 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.1938312050 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 450124203 ps |
| CPU time | 36.42 seconds |
| Started | Jul 09 07:35:33 PM PDT 24 |
| Finished | Jul 09 07:36:11 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-821c3add-6883-4083-b704-0c0a6e273ed2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938312050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.1938312050 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.1935854765 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 226479979 ps |
| CPU time | 18.86 seconds |
| Started | Jul 09 07:35:34 PM PDT 24 |
| Finished | Jul 09 07:35:55 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-da84baf5-4153-4e6a-9b33-06ebfb93b520 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935854765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.1935854765 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.2460996298 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 26271303918 ps |
| CPU time | 255.11 seconds |
| Started | Jul 09 07:35:36 PM PDT 24 |
| Finished | Jul 09 07:39:55 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-c4a31f2b-6fef-4920-9d6e-499e24f4c2ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460996298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.2460996298 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.1516102555 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 40609339584 ps |
| CPU time | 704.36 seconds |
| Started | Jul 09 07:35:32 PM PDT 24 |
| Finished | Jul 09 07:47:17 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-71bfe695-5699-4649-853a-e503a4999e6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516102555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.1516102555 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.3669972406 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 63253792 ps |
| CPU time | 8.17 seconds |
| Started | Jul 09 07:35:35 PM PDT 24 |
| Finished | Jul 09 07:35:46 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-59b2109e-dec2-48eb-a71a-7a138b7bc853 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669972406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.3669972406 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.4187616917 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 411561148 ps |
| CPU time | 31.17 seconds |
| Started | Jul 09 07:35:35 PM PDT 24 |
| Finished | Jul 09 07:36:09 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-d0e4e744-660a-4705-8191-a21f5aee7224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187616917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.4187616917 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.1918430682 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 45159514 ps |
| CPU time | 6.58 seconds |
| Started | Jul 09 07:35:30 PM PDT 24 |
| Finished | Jul 09 07:35:37 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-28275398-d3cf-4822-ab14-bdd088b7503c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918430682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.1918430682 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.3485774358 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 6396548183 ps |
| CPU time | 60.89 seconds |
| Started | Jul 09 07:35:32 PM PDT 24 |
| Finished | Jul 09 07:36:34 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-0af6ecae-9727-4c71-bae3-d9cdb9ff015e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485774358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.3485774358 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.194080785 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 3844445222 ps |
| CPU time | 67.04 seconds |
| Started | Jul 09 07:35:30 PM PDT 24 |
| Finished | Jul 09 07:36:38 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-7426c2d3-39f0-4bbe-a631-cfe0753232d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194080785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.194080785 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.2283080873 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 45238596 ps |
| CPU time | 6.05 seconds |
| Started | Jul 09 07:35:36 PM PDT 24 |
| Finished | Jul 09 07:35:45 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-05ab2762-0a5a-4ded-851b-b322c6d8a3a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283080873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.2283080873 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.4176886757 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2165704768 ps |
| CPU time | 198.49 seconds |
| Started | Jul 09 07:35:36 PM PDT 24 |
| Finished | Jul 09 07:38:57 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-88c5bcfb-e018-4787-9d18-296881cc93dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176886757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.4176886757 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.589167358 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 1450587955 ps |
| CPU time | 95.19 seconds |
| Started | Jul 09 07:35:36 PM PDT 24 |
| Finished | Jul 09 07:37:14 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-e5da6554-6a97-4c55-9538-592b09091daf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589167358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.589167358 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.4076105130 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 6856047472 ps |
| CPU time | 470.77 seconds |
| Started | Jul 09 07:35:33 PM PDT 24 |
| Finished | Jul 09 07:43:26 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-11242d08-f8cf-4f5c-b5c9-0c4f42d49dc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076105130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.4076105130 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2048696059 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 485951734 ps |
| CPU time | 53.7 seconds |
| Started | Jul 09 07:35:27 PM PDT 24 |
| Finished | Jul 09 07:36:21 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-249a860d-3877-450d-89dc-f7f2638a8634 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048696059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.2048696059 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.3497787642 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 985527659 ps |
| CPU time | 37.94 seconds |
| Started | Jul 09 07:35:35 PM PDT 24 |
| Finished | Jul 09 07:36:16 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-ae987413-cfdc-4ccb-b0ed-95db7ba0a62a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497787642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.3497787642 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.216116989 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 3166374941 ps |
| CPU time | 137.71 seconds |
| Started | Jul 09 07:35:33 PM PDT 24 |
| Finished | Jul 09 07:37:53 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-8dd3b56f-ca4b-432c-9f92-44d3237b14c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216116989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device. 216116989 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2182165241 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 36021268507 ps |
| CPU time | 639.04 seconds |
| Started | Jul 09 07:35:30 PM PDT 24 |
| Finished | Jul 09 07:46:10 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-6a374df8-edd7-4b70-9653-d290b59a9cd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182165241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.2182165241 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.3872426707 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 741955944 ps |
| CPU time | 32.25 seconds |
| Started | Jul 09 07:35:23 PM PDT 24 |
| Finished | Jul 09 07:35:57 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-1a9562a2-d6cf-4f37-bd16-609ebca59ee4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872426707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.3872426707 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.4147538283 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 1681368522 ps |
| CPU time | 56.5 seconds |
| Started | Jul 09 07:35:33 PM PDT 24 |
| Finished | Jul 09 07:36:31 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-e797e195-c3d9-4a05-b8c4-c156891de4cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147538283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.4147538283 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.524741836 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 1533015909 ps |
| CPU time | 49.6 seconds |
| Started | Jul 09 07:35:33 PM PDT 24 |
| Finished | Jul 09 07:36:24 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-d50b05cc-a4d9-428c-a126-286bd4524373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524741836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.524741836 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.1819307540 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 55559111113 ps |
| CPU time | 533.56 seconds |
| Started | Jul 09 07:35:32 PM PDT 24 |
| Finished | Jul 09 07:44:28 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-4d168363-7498-428a-8bdc-b21c4eec69d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819307540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.1819307540 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.2924192184 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 44994440795 ps |
| CPU time | 743.96 seconds |
| Started | Jul 09 07:35:34 PM PDT 24 |
| Finished | Jul 09 07:47:59 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-238bc444-0de9-47d3-805b-5434457e97af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924192184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.2924192184 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.927342765 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 174911593 ps |
| CPU time | 18.85 seconds |
| Started | Jul 09 07:35:36 PM PDT 24 |
| Finished | Jul 09 07:35:58 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-68e3dd98-c042-4825-b988-1203b938f734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927342765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_dela ys.927342765 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.1595513604 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 712186123 ps |
| CPU time | 20.49 seconds |
| Started | Jul 09 07:35:33 PM PDT 24 |
| Finished | Jul 09 07:35:55 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-e2f3d096-f3fd-40e1-afb3-3cf7bf101419 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595513604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.1595513604 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.4275077027 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 151656511 ps |
| CPU time | 8.53 seconds |
| Started | Jul 09 07:35:36 PM PDT 24 |
| Finished | Jul 09 07:35:47 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-233192bc-53c9-4b41-96eb-b6096080e0bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275077027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.4275077027 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.1907704432 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 7466805706 ps |
| CPU time | 76.63 seconds |
| Started | Jul 09 07:35:31 PM PDT 24 |
| Finished | Jul 09 07:36:48 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-c65f9a41-8358-47a6-bde4-e73a3e8db92d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907704432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.1907704432 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.3354437784 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 4745045311 ps |
| CPU time | 80.19 seconds |
| Started | Jul 09 07:35:36 PM PDT 24 |
| Finished | Jul 09 07:37:00 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-4212b828-05ed-4b1e-88fa-4f487501cf49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354437784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.3354437784 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.1603085522 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 46297614 ps |
| CPU time | 6.36 seconds |
| Started | Jul 09 07:35:32 PM PDT 24 |
| Finished | Jul 09 07:35:40 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-77178460-f77d-45a0-9d30-76d72470600d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603085522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.1603085522 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.2806323592 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 11685285712 ps |
| CPU time | 399.47 seconds |
| Started | Jul 09 07:35:32 PM PDT 24 |
| Finished | Jul 09 07:42:12 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-144ec5f9-489c-499b-bfc6-99c6ec08faaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806323592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.2806323592 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.4116823482 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 11695188234 ps |
| CPU time | 384.74 seconds |
| Started | Jul 09 07:35:34 PM PDT 24 |
| Finished | Jul 09 07:42:01 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-9b17c244-5d06-4ad0-ab5b-6898412701b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116823482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.4116823482 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.3527760012 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 314122838 ps |
| CPU time | 94.87 seconds |
| Started | Jul 09 07:35:36 PM PDT 24 |
| Finished | Jul 09 07:37:14 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-c4346318-66bb-4978-8537-a94b2f8e1d3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527760012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.3527760012 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.2352197628 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 8701450918 ps |
| CPU time | 376.4 seconds |
| Started | Jul 09 07:35:35 PM PDT 24 |
| Finished | Jul 09 07:41:53 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-45ed24b7-3386-4d21-879f-c8df566fc44e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352197628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.2352197628 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.3367270553 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 114760535 ps |
| CPU time | 15.77 seconds |
| Started | Jul 09 07:35:33 PM PDT 24 |
| Finished | Jul 09 07:35:50 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-745d883d-ce2c-4b68-ae3f-8bf0c622fb82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367270553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.3367270553 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.1973478162 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 677710204 ps |
| CPU time | 31.37 seconds |
| Started | Jul 09 07:35:41 PM PDT 24 |
| Finished | Jul 09 07:36:16 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-84c6626e-06d5-4537-8b44-28bd91d70d8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973478162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .1973478162 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3023012223 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 100016817584 ps |
| CPU time | 1733.4 seconds |
| Started | Jul 09 07:35:47 PM PDT 24 |
| Finished | Jul 09 08:04:46 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-27bd9582-8232-4a50-88e8-6fde113598b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023012223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.3023012223 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.238187819 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 1117965552 ps |
| CPU time | 40.29 seconds |
| Started | Jul 09 07:35:44 PM PDT 24 |
| Finished | Jul 09 07:36:28 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-001c8959-61b2-496d-9780-93b6c550476f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238187819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_addr .238187819 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.4084728669 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 541470252 ps |
| CPU time | 39.41 seconds |
| Started | Jul 09 07:35:44 PM PDT 24 |
| Finished | Jul 09 07:36:27 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-94dede1a-f930-461b-9baf-d0714d1bfefc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084728669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.4084728669 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.979229287 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 1640572043 ps |
| CPU time | 62.03 seconds |
| Started | Jul 09 07:35:41 PM PDT 24 |
| Finished | Jul 09 07:36:46 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-d0d36d0c-5e6d-47c9-8e9f-4dc08f0d54f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979229287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.979229287 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.888886842 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 61467265553 ps |
| CPU time | 639.01 seconds |
| Started | Jul 09 07:35:45 PM PDT 24 |
| Finished | Jul 09 07:46:28 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-d8bdb7db-67ea-45fb-b881-f35b5eec4c4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888886842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.888886842 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.1733616157 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 19164963985 ps |
| CPU time | 321.2 seconds |
| Started | Jul 09 07:35:44 PM PDT 24 |
| Finished | Jul 09 07:41:10 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-e6a742e2-d260-466d-b394-902c39d5e7cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733616157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.1733616157 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.726257822 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 553981869 ps |
| CPU time | 45.28 seconds |
| Started | Jul 09 07:35:40 PM PDT 24 |
| Finished | Jul 09 07:36:28 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-39a60f1b-b1d0-4313-af0a-edd3ff8bbf09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726257822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_dela ys.726257822 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.2397987210 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1965043114 ps |
| CPU time | 64.64 seconds |
| Started | Jul 09 07:35:44 PM PDT 24 |
| Finished | Jul 09 07:36:53 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-b1a89f93-b943-4ff6-9084-3e8822db71a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397987210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.2397987210 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.460385854 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 50183671 ps |
| CPU time | 6.19 seconds |
| Started | Jul 09 07:35:35 PM PDT 24 |
| Finished | Jul 09 07:35:44 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-151dd266-bce9-486e-a30b-261236c275a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460385854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.460385854 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.256763607 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 7789211655 ps |
| CPU time | 82.48 seconds |
| Started | Jul 09 07:35:48 PM PDT 24 |
| Finished | Jul 09 07:37:16 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-8b450659-cda7-4592-a2c3-f905466041c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256763607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.256763607 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.349968534 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 5860815330 ps |
| CPU time | 97.5 seconds |
| Started | Jul 09 07:35:48 PM PDT 24 |
| Finished | Jul 09 07:37:31 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-5d83c3b9-8d59-4d20-920d-9936f075275f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349968534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.349968534 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.2354663962 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 53736982 ps |
| CPU time | 6.59 seconds |
| Started | Jul 09 07:35:44 PM PDT 24 |
| Finished | Jul 09 07:35:55 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-7bafad05-feec-473f-807f-f69bc15d16c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354663962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.2354663962 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.1579760853 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 13922659558 ps |
| CPU time | 517.67 seconds |
| Started | Jul 09 07:35:44 PM PDT 24 |
| Finished | Jul 09 07:44:26 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-99c8a711-7a85-4f48-baf0-f49298754b5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579760853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.1579760853 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.3326506962 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 910453406 ps |
| CPU time | 61.64 seconds |
| Started | Jul 09 07:35:44 PM PDT 24 |
| Finished | Jul 09 07:36:50 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-9927eaf0-ce76-4011-852d-7c725cac9a5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326506962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.3326506962 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.4119043355 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 5336066755 ps |
| CPU time | 629.31 seconds |
| Started | Jul 09 07:35:47 PM PDT 24 |
| Finished | Jul 09 07:46:22 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-d6fe8c04-168d-4ab0-9dfe-2dc3ba353f07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119043355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.4119043355 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.901619462 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 94638585 ps |
| CPU time | 55.82 seconds |
| Started | Jul 09 07:35:39 PM PDT 24 |
| Finished | Jul 09 07:36:38 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-b243a11d-ecf0-4bfc-abb7-2e6de2a73c03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901619462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_reset_error.901619462 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.9630295 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 1293363794 ps |
| CPU time | 54.26 seconds |
| Started | Jul 09 07:35:53 PM PDT 24 |
| Finished | Jul 09 07:36:54 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-64555ea1-3b56-4ac6-9d2e-9c82f0337e35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9630295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.9630295 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.1719791622 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 2230012429 ps |
| CPU time | 118.31 seconds |
| Started | Jul 09 07:35:43 PM PDT 24 |
| Finished | Jul 09 07:37:45 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-5262337d-3f32-4cc5-a823-abf6e06711f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719791622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .1719791622 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.4058843441 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 77327560646 ps |
| CPU time | 1265.21 seconds |
| Started | Jul 09 07:35:47 PM PDT 24 |
| Finished | Jul 09 07:56:56 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-d0820601-58e4-4ca0-97e6-f893fbce2345 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058843441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.4058843441 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3770490400 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 297020480 ps |
| CPU time | 28.27 seconds |
| Started | Jul 09 07:35:53 PM PDT 24 |
| Finished | Jul 09 07:36:29 PM PDT 24 |
| Peak memory | 576448 kb |
| Host | smart-cba46971-83e3-404a-bc17-479f25502328 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770490400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.3770490400 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.3724448988 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 454534063 ps |
| CPU time | 35.28 seconds |
| Started | Jul 09 07:35:48 PM PDT 24 |
| Finished | Jul 09 07:36:29 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-2e4637a7-b99a-47b0-b5c6-472fe62defa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724448988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.3724448988 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.1671680058 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2331116884 ps |
| CPU time | 73.5 seconds |
| Started | Jul 09 07:35:53 PM PDT 24 |
| Finished | Jul 09 07:37:14 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-3b327106-f0e7-479a-b133-413271081aa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671680058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.1671680058 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.3989697430 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 20380684768 ps |
| CPU time | 224.61 seconds |
| Started | Jul 09 07:35:48 PM PDT 24 |
| Finished | Jul 09 07:39:38 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-9e25f68a-5242-4e33-9985-f7f649293598 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989697430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.3989697430 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.355215762 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 26409052282 ps |
| CPU time | 455.27 seconds |
| Started | Jul 09 07:35:48 PM PDT 24 |
| Finished | Jul 09 07:43:29 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-1af89852-90eb-488f-977e-b2e8cabfb47a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355215762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.355215762 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.4073256213 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 223145123 ps |
| CPU time | 23.01 seconds |
| Started | Jul 09 07:35:39 PM PDT 24 |
| Finished | Jul 09 07:36:05 PM PDT 24 |
| Peak memory | 576440 kb |
| Host | smart-71f16daf-617e-4737-bc36-392dc635838f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073256213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.4073256213 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.1511212485 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 1375591966 ps |
| CPU time | 39.68 seconds |
| Started | Jul 09 07:35:44 PM PDT 24 |
| Finished | Jul 09 07:36:28 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-e4b4ee0f-f706-412d-bd02-4e897402b657 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511212485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.1511212485 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.560337891 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 168458582 ps |
| CPU time | 7.98 seconds |
| Started | Jul 09 07:35:50 PM PDT 24 |
| Finished | Jul 09 07:36:04 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-311fc4b3-be81-490e-a990-1a8b2544efd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560337891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.560337891 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.1628732719 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 5238833683 ps |
| CPU time | 50.57 seconds |
| Started | Jul 09 07:35:40 PM PDT 24 |
| Finished | Jul 09 07:36:34 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-c271cafc-22ed-4d5a-8aee-0895c8965e98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628732719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.1628732719 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.3230411375 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 3904281303 ps |
| CPU time | 65.67 seconds |
| Started | Jul 09 07:35:39 PM PDT 24 |
| Finished | Jul 09 07:36:47 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-187958bc-b0b0-4fc6-8a12-e34b53923937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230411375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.3230411375 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.781009959 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 46744252 ps |
| CPU time | 6.68 seconds |
| Started | Jul 09 07:35:45 PM PDT 24 |
| Finished | Jul 09 07:35:56 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-703197e9-3853-47ee-a772-80e8ed7928e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781009959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delays .781009959 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.988800405 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 2728443420 ps |
| CPU time | 233.52 seconds |
| Started | Jul 09 07:35:45 PM PDT 24 |
| Finished | Jul 09 07:39:43 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-a9e76713-8dcf-4500-b95f-3815d6268060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988800405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.988800405 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.3405968261 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 11208366884 ps |
| CPU time | 372.24 seconds |
| Started | Jul 09 07:35:48 PM PDT 24 |
| Finished | Jul 09 07:42:05 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-4c0f5f5e-0697-4d69-9d89-b16747503afd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405968261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.3405968261 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.358995976 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 4062848127 ps |
| CPU time | 470.9 seconds |
| Started | Jul 09 07:35:44 PM PDT 24 |
| Finished | Jul 09 07:43:38 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-320d9ef6-f8d6-40e4-928f-3ff1c357b1e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358995976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_ with_rand_reset.358995976 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.2387390009 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 1393119142 ps |
| CPU time | 157.87 seconds |
| Started | Jul 09 07:35:45 PM PDT 24 |
| Finished | Jul 09 07:38:27 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-2e4c18a3-c37a-4852-97ff-3db93bbddbc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387390009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.2387390009 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.2618195487 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 1218268694 ps |
| CPU time | 49.31 seconds |
| Started | Jul 09 07:35:44 PM PDT 24 |
| Finished | Jul 09 07:36:37 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-00c131ca-96b5-4b3d-8d0f-4539e4314665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618195487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.2618195487 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.3620390837 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 3186398363 ps |
| CPU time | 116.95 seconds |
| Started | Jul 09 07:35:48 PM PDT 24 |
| Finished | Jul 09 07:37:50 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-0e834387-9c04-4bf3-981a-10103c44a8ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620390837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .3620390837 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.1712828384 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 87165841536 ps |
| CPU time | 1628.49 seconds |
| Started | Jul 09 07:35:47 PM PDT 24 |
| Finished | Jul 09 08:03:01 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-5f660d95-9f66-4bb5-8486-a7746e8ba22e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712828384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.1712828384 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.378690268 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 1019399379 ps |
| CPU time | 41.95 seconds |
| Started | Jul 09 07:35:52 PM PDT 24 |
| Finished | Jul 09 07:36:41 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-d7fefbaa-6cd4-4a82-b4af-a92d4160efe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378690268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_addr .378690268 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.2643745514 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 2042739119 ps |
| CPU time | 72.08 seconds |
| Started | Jul 09 07:35:47 PM PDT 24 |
| Finished | Jul 09 07:37:03 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-af3a7957-a4b3-47ef-9340-c00c9ae4e976 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643745514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.2643745514 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.1956590759 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 526870612 ps |
| CPU time | 42.65 seconds |
| Started | Jul 09 07:35:48 PM PDT 24 |
| Finished | Jul 09 07:36:36 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-243934d8-b68c-4274-95ac-d4feeb0b4470 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956590759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.1956590759 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.1003787136 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 64762218290 ps |
| CPU time | 715.77 seconds |
| Started | Jul 09 07:35:46 PM PDT 24 |
| Finished | Jul 09 07:47:47 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-93eeb88d-3c90-4efc-ad69-1925eda124ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003787136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.1003787136 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.2134352588 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 34688794563 ps |
| CPU time | 577.16 seconds |
| Started | Jul 09 07:35:46 PM PDT 24 |
| Finished | Jul 09 07:45:27 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-91a4538a-ccd9-4700-8a91-43facd7fef99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134352588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.2134352588 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.3599422662 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 329990050 ps |
| CPU time | 26.34 seconds |
| Started | Jul 09 07:35:43 PM PDT 24 |
| Finished | Jul 09 07:36:13 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-27f594e3-e12c-4489-99dc-8a31a069e4dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599422662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.3599422662 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.2516371146 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 2318164762 ps |
| CPU time | 73.28 seconds |
| Started | Jul 09 07:35:48 PM PDT 24 |
| Finished | Jul 09 07:37:07 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-19cf1813-13a6-4172-9183-dcfd6799a8de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516371146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.2516371146 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.252371430 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 49812507 ps |
| CPU time | 6.29 seconds |
| Started | Jul 09 07:35:43 PM PDT 24 |
| Finished | Jul 09 07:35:53 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-755381fd-1ff5-46ee-8ee7-b338197c84fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252371430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.252371430 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.2825732896 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 8353011333 ps |
| CPU time | 84.84 seconds |
| Started | Jul 09 07:35:52 PM PDT 24 |
| Finished | Jul 09 07:37:24 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-25507db8-be92-4722-946e-694ee852d937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825732896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.2825732896 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.2175980803 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 5462008118 ps |
| CPU time | 83.94 seconds |
| Started | Jul 09 07:35:47 PM PDT 24 |
| Finished | Jul 09 07:37:17 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-8e9ebbd4-83e2-47f2-9ce5-c08f3b724921 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175980803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.2175980803 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1250110962 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 47668828 ps |
| CPU time | 6.62 seconds |
| Started | Jul 09 07:35:44 PM PDT 24 |
| Finished | Jul 09 07:35:55 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-fe19cf28-7c2a-45fc-833a-733b15e88a50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250110962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.1250110962 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.4200225993 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 5891979202 ps |
| CPU time | 183.1 seconds |
| Started | Jul 09 07:35:47 PM PDT 24 |
| Finished | Jul 09 07:38:55 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-ac4c3789-b5cd-4535-b6fd-6ec93a83b4a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200225993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.4200225993 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.1344516767 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 6753086640 ps |
| CPU time | 199.4 seconds |
| Started | Jul 09 07:35:43 PM PDT 24 |
| Finished | Jul 09 07:39:06 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-07d0885f-85e7-493a-8334-9953c1cac86f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344516767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.1344516767 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1827785649 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 179685803 ps |
| CPU time | 29.35 seconds |
| Started | Jul 09 07:35:45 PM PDT 24 |
| Finished | Jul 09 07:36:19 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-5c23980a-aad1-4ced-a8e7-ca0a421f8a43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827785649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.1827785649 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.1338962805 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 1372642726 ps |
| CPU time | 55.71 seconds |
| Started | Jul 09 07:35:51 PM PDT 24 |
| Finished | Jul 09 07:36:53 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-cac61aa6-3fea-4c4c-816a-5ef3a73f2966 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338962805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.1338962805 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.2192719194 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 6374392742 ps |
| CPU time | 607.87 seconds |
| Started | Jul 09 07:25:38 PM PDT 24 |
| Finished | Jul 09 07:36:00 PM PDT 24 |
| Peak memory | 599012 kb |
| Host | smart-343a2830-bcc5-4ffd-b808-9d576312c1c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192719194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.2192719194 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.1595231430 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 15839182578 ps |
| CPU time | 1728.23 seconds |
| Started | Jul 09 07:25:42 PM PDT 24 |
| Finished | Jul 09 07:54:46 PM PDT 24 |
| Peak memory | 593304 kb |
| Host | smart-67a529d8-f256-4b14-a049-0c2f4688df44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595231430 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.1595231430 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.564307233 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 3365842380 ps |
| CPU time | 152.39 seconds |
| Started | Jul 09 07:25:37 PM PDT 24 |
| Finished | Jul 09 07:28:21 PM PDT 24 |
| Peak memory | 604016 kb |
| Host | smart-526ed96a-a2f8-4333-8c36-b484bda08b04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564307233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.564307233 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.411763681 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 224774494 ps |
| CPU time | 19.55 seconds |
| Started | Jul 09 07:25:42 PM PDT 24 |
| Finished | Jul 09 07:26:17 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-8fda54c4-c105-40a3-a6ac-969c86e4b3d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411763681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.411763681 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.1221535724 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 64464998591 ps |
| CPU time | 1146.83 seconds |
| Started | Jul 09 07:25:40 PM PDT 24 |
| Finished | Jul 09 07:45:00 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-9d036ba4-f10c-49dc-97b5-aec924976007 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221535724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.1221535724 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.1502774369 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 1151632038 ps |
| CPU time | 45.51 seconds |
| Started | Jul 09 07:25:41 PM PDT 24 |
| Finished | Jul 09 07:26:42 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-79b85bd0-b882-47ae-abca-422a7c26d59a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502774369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .1502774369 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.2804583687 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 332247649 ps |
| CPU time | 28.3 seconds |
| Started | Jul 09 07:25:42 PM PDT 24 |
| Finished | Jul 09 07:26:26 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-b5016978-7893-43b2-856d-25d1b61b446e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804583687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2804583687 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.2796085373 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 568592132 ps |
| CPU time | 50.77 seconds |
| Started | Jul 09 07:25:42 PM PDT 24 |
| Finished | Jul 09 07:26:47 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-c02253e1-77db-4e28-afd9-d31b993e59b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796085373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.2796085373 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.3875113345 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 45108107261 ps |
| CPU time | 456.22 seconds |
| Started | Jul 09 07:25:41 PM PDT 24 |
| Finished | Jul 09 07:33:32 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-cefa69b6-1593-4336-8688-05950a7eb7b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875113345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3875113345 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.524467063 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 35790380356 ps |
| CPU time | 613.44 seconds |
| Started | Jul 09 07:25:40 PM PDT 24 |
| Finished | Jul 09 07:36:07 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-f2956424-c689-4367-9f00-9d00a269e4bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524467063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.524467063 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.1185387571 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 600614025 ps |
| CPU time | 51.75 seconds |
| Started | Jul 09 07:25:41 PM PDT 24 |
| Finished | Jul 09 07:26:48 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-0e4d1439-913d-4ced-89f0-6759c132d89e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185387571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.1185387571 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.3636709195 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 32595536 ps |
| CPU time | 5.36 seconds |
| Started | Jul 09 07:25:39 PM PDT 24 |
| Finished | Jul 09 07:25:58 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-99a7486d-99e3-4617-8ece-c7bce2dc6a38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636709195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3636709195 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.2834252754 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 139200888 ps |
| CPU time | 6.92 seconds |
| Started | Jul 09 07:25:51 PM PDT 24 |
| Finished | Jul 09 07:26:17 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-07c5afa4-ba16-4b11-9c57-5ccaa9c7e418 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834252754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2834252754 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.4279424481 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 8996098177 ps |
| CPU time | 92.49 seconds |
| Started | Jul 09 07:25:38 PM PDT 24 |
| Finished | Jul 09 07:27:24 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-3514d6f6-5345-49ab-8980-70d9516ebd62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279424481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.4279424481 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1662188915 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 4463988346 ps |
| CPU time | 77.38 seconds |
| Started | Jul 09 07:25:41 PM PDT 24 |
| Finished | Jul 09 07:27:14 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-7801c58a-59c5-406d-8555-fac1f75822e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662188915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1662188915 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.977453258 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 58608875 ps |
| CPU time | 7.32 seconds |
| Started | Jul 09 07:25:38 PM PDT 24 |
| Finished | Jul 09 07:25:59 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-54c65c50-967e-4d65-8556-03e9340b3a83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977453258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays. 977453258 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.2363521264 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 11628388506 ps |
| CPU time | 455.04 seconds |
| Started | Jul 09 07:25:44 PM PDT 24 |
| Finished | Jul 09 07:33:35 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-2ab8c5a1-69d3-46fe-962f-e61312c03775 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363521264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2363521264 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.3680393770 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 4124800739 ps |
| CPU time | 127.27 seconds |
| Started | Jul 09 07:25:50 PM PDT 24 |
| Finished | Jul 09 07:28:15 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-85a0e7da-7afd-4595-a042-dfb959dab66d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680393770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3680393770 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.2784479974 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 50591008 ps |
| CPU time | 33.88 seconds |
| Started | Jul 09 07:25:41 PM PDT 24 |
| Finished | Jul 09 07:26:30 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-04243f17-da89-4113-a30c-f1c6f08ef902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784479974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.2784479974 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.128022390 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 8493263955 ps |
| CPU time | 472.04 seconds |
| Started | Jul 09 07:25:37 PM PDT 24 |
| Finished | Jul 09 07:33:42 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-bcf272ef-95aa-469e-8f18-25e5773b5b81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128022390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_reset_error.128022390 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.432072960 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 1353572055 ps |
| CPU time | 54.34 seconds |
| Started | Jul 09 07:25:41 PM PDT 24 |
| Finished | Jul 09 07:26:50 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-d237f712-9987-4ea3-9a56-8c1926a20743 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432072960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.432072960 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.2282104101 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 141304040 ps |
| CPU time | 11.68 seconds |
| Started | Jul 09 07:35:51 PM PDT 24 |
| Finished | Jul 09 07:36:09 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-a782beaa-93b3-4ad5-be5f-061ef950033b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282104101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .2282104101 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.296704355 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 2926122440 ps |
| CPU time | 52.08 seconds |
| Started | Jul 09 07:35:52 PM PDT 24 |
| Finished | Jul 09 07:36:51 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-7be76d5d-12d2-4867-aaee-a4458f825d80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296704355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_d evice_slow_rsp.296704355 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.2917606499 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 1475776492 ps |
| CPU time | 54.75 seconds |
| Started | Jul 09 07:35:49 PM PDT 24 |
| Finished | Jul 09 07:36:50 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-07737d39-b181-41bb-9ae0-d318c015f0a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917606499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.2917606499 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.2603313885 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 603318384 ps |
| CPU time | 48.2 seconds |
| Started | Jul 09 07:35:52 PM PDT 24 |
| Finished | Jul 09 07:36:47 PM PDT 24 |
| Peak memory | 576444 kb |
| Host | smart-3da7eb55-96d6-4303-bc95-fb9b9d40bd07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603313885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.2603313885 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.2786856001 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 382683809 ps |
| CPU time | 30.74 seconds |
| Started | Jul 09 07:35:54 PM PDT 24 |
| Finished | Jul 09 07:36:31 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-d0ce0d0b-e82c-48cf-ae38-8ed0804aa24d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786856001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.2786856001 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.2515917338 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 19011106245 ps |
| CPU time | 183.38 seconds |
| Started | Jul 09 07:35:52 PM PDT 24 |
| Finished | Jul 09 07:39:02 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-6758d0d5-350d-45af-80bd-c9f0990c0138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515917338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.2515917338 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.3278759376 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 64537992073 ps |
| CPU time | 1081.07 seconds |
| Started | Jul 09 07:35:51 PM PDT 24 |
| Finished | Jul 09 07:53:59 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-7a267198-7f90-491b-8e27-435e288054ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278759376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.3278759376 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.1963232983 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 74465135 ps |
| CPU time | 9.53 seconds |
| Started | Jul 09 07:35:52 PM PDT 24 |
| Finished | Jul 09 07:36:08 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-f15cffb9-3eee-4015-9544-88b23e13f6fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963232983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.1963232983 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.1583876402 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 399775924 ps |
| CPU time | 29.35 seconds |
| Started | Jul 09 07:35:49 PM PDT 24 |
| Finished | Jul 09 07:36:25 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-f92ff100-03d7-4d79-94ac-e47f54e2b8b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583876402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.1583876402 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.721339956 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 223384860 ps |
| CPU time | 9.97 seconds |
| Started | Jul 09 07:35:46 PM PDT 24 |
| Finished | Jul 09 07:36:00 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-74514a53-e3cb-4988-ad58-f9d7ebaf99fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721339956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.721339956 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.805279405 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 7653102596 ps |
| CPU time | 80.35 seconds |
| Started | Jul 09 07:35:48 PM PDT 24 |
| Finished | Jul 09 07:37:13 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-861c8c55-d6d2-4dac-ab90-33f68d99b415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805279405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.805279405 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1370416551 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 5102276534 ps |
| CPU time | 91.07 seconds |
| Started | Jul 09 07:35:52 PM PDT 24 |
| Finished | Jul 09 07:37:30 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-63d0eb84-a9c9-4c04-a22e-7f83e8bb9140 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370416551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.1370416551 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3834386139 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 56955594 ps |
| CPU time | 7.2 seconds |
| Started | Jul 09 07:35:48 PM PDT 24 |
| Finished | Jul 09 07:36:00 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-c915a835-a06c-4dee-92d7-978448764737 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834386139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.3834386139 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.2971853170 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 11672619300 ps |
| CPU time | 383.45 seconds |
| Started | Jul 09 07:35:53 PM PDT 24 |
| Finished | Jul 09 07:42:24 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-f6ec27cf-fabe-4fee-aea6-14e7bdff4100 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971853170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.2971853170 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.72832023 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 4194710910 ps |
| CPU time | 305.07 seconds |
| Started | Jul 09 07:35:52 PM PDT 24 |
| Finished | Jul 09 07:41:04 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-c3e41464-a9d6-4c07-a2ce-5cff6b9a14ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72832023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.72832023 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.3011387923 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 247962363 ps |
| CPU time | 73.27 seconds |
| Started | Jul 09 07:35:49 PM PDT 24 |
| Finished | Jul 09 07:37:09 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-0a4d84d2-3021-46fb-8f71-a80c3089eacf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011387923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.3011387923 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3570388596 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 3791268524 ps |
| CPU time | 439.8 seconds |
| Started | Jul 09 07:35:50 PM PDT 24 |
| Finished | Jul 09 07:43:16 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-5537d9b1-64f4-442b-b88d-5b4d93f1699f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570388596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.3570388596 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.87783594 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 843365087 ps |
| CPU time | 35.26 seconds |
| Started | Jul 09 07:35:49 PM PDT 24 |
| Finished | Jul 09 07:36:30 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-c6f51780-87a1-4bcd-a441-11a346d6c71a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87783594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.87783594 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.1658194977 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 2360978653 ps |
| CPU time | 103.01 seconds |
| Started | Jul 09 07:35:44 PM PDT 24 |
| Finished | Jul 09 07:37:31 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-f96a2b06-5637-496f-bc5d-d841a88116a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658194977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .1658194977 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.521378581 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 42544678893 ps |
| CPU time | 723.81 seconds |
| Started | Jul 09 07:35:49 PM PDT 24 |
| Finished | Jul 09 07:47:59 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-1b5ae40a-d846-43d8-9044-87fd51e9525c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521378581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_d evice_slow_rsp.521378581 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3306649173 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 249395851 ps |
| CPU time | 25.78 seconds |
| Started | Jul 09 07:35:50 PM PDT 24 |
| Finished | Jul 09 07:36:22 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-fae71919-ddc7-4c49-a0f4-0b35a4cce7e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306649173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.3306649173 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.4014768800 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 916780061 ps |
| CPU time | 30.93 seconds |
| Started | Jul 09 07:35:50 PM PDT 24 |
| Finished | Jul 09 07:36:28 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-569e96a5-a616-44e4-a382-315913ba2942 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014768800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.4014768800 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.4036358366 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 134835086 ps |
| CPU time | 13.51 seconds |
| Started | Jul 09 07:35:49 PM PDT 24 |
| Finished | Jul 09 07:36:08 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-5e746242-7672-44a1-9bab-c51442eb3d10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036358366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.4036358366 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.162060929 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 100961230918 ps |
| CPU time | 1081.63 seconds |
| Started | Jul 09 07:35:49 PM PDT 24 |
| Finished | Jul 09 07:53:57 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-bd92ce28-9aa5-4ac1-adee-0c0f83b3bb65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162060929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.162060929 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.666073385 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 46641681367 ps |
| CPU time | 796.04 seconds |
| Started | Jul 09 07:35:47 PM PDT 24 |
| Finished | Jul 09 07:49:07 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-97d9a574-8760-41ac-a7f9-2a388a9675bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666073385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.666073385 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.714933911 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 509516061 ps |
| CPU time | 39.75 seconds |
| Started | Jul 09 07:35:49 PM PDT 24 |
| Finished | Jul 09 07:36:35 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-a7126e0b-2dab-42fc-b1be-9e3992ccc775 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714933911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_dela ys.714933911 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.2978291354 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 120289206 ps |
| CPU time | 12.09 seconds |
| Started | Jul 09 07:35:50 PM PDT 24 |
| Finished | Jul 09 07:36:08 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-b20c6071-995d-4dd9-8c1f-d5d3fa6bf404 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978291354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.2978291354 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.3445209400 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 163257272 ps |
| CPU time | 8.25 seconds |
| Started | Jul 09 07:35:50 PM PDT 24 |
| Finished | Jul 09 07:36:05 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-686a7070-9467-489f-b818-16584060231c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445209400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.3445209400 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.2484564817 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 9152374707 ps |
| CPU time | 92.79 seconds |
| Started | Jul 09 07:35:42 PM PDT 24 |
| Finished | Jul 09 07:37:18 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-72333b1b-8a44-46ce-9880-22ab897ee616 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484564817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.2484564817 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1778829328 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 6228846113 ps |
| CPU time | 98.82 seconds |
| Started | Jul 09 07:35:49 PM PDT 24 |
| Finished | Jul 09 07:37:34 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-34d2bf11-8817-4a43-9c86-88b0638551f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778829328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.1778829328 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2120039309 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 44678845 ps |
| CPU time | 6.12 seconds |
| Started | Jul 09 07:35:50 PM PDT 24 |
| Finished | Jul 09 07:36:02 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-d1d77ab4-592d-400e-9c37-4574db3c3eff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120039309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.2120039309 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.572658444 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 1687186786 ps |
| CPU time | 123.3 seconds |
| Started | Jul 09 07:35:53 PM PDT 24 |
| Finished | Jul 09 07:38:03 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-47d14a54-452e-41af-927b-98facec2bed2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572658444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.572658444 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.2072092328 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 2633427750 ps |
| CPU time | 81.62 seconds |
| Started | Jul 09 07:35:52 PM PDT 24 |
| Finished | Jul 09 07:37:20 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-fd45ac0f-9740-4d7a-9a69-1d834637a0c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072092328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.2072092328 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.4218269185 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 86633793 ps |
| CPU time | 20.39 seconds |
| Started | Jul 09 07:35:52 PM PDT 24 |
| Finished | Jul 09 07:36:19 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-2daa0119-1679-47a8-9c6a-ec83bb34c839 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218269185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.4218269185 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3736733517 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 6505646682 ps |
| CPU time | 267.36 seconds |
| Started | Jul 09 07:35:53 PM PDT 24 |
| Finished | Jul 09 07:40:27 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-1db2cd9c-518e-4219-8a51-1679dc98bc11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736733517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.3736733517 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.2408992285 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 738117644 ps |
| CPU time | 30.95 seconds |
| Started | Jul 09 07:35:50 PM PDT 24 |
| Finished | Jul 09 07:36:27 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-7cf251ae-3f97-4b18-a09d-0db7ba4b26d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408992285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.2408992285 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.1098521654 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 144962320 ps |
| CPU time | 19.74 seconds |
| Started | Jul 09 07:35:47 PM PDT 24 |
| Finished | Jul 09 07:36:12 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-ba2c867a-e85a-42d0-b323-43893d9a7782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098521654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .1098521654 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.2829985994 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 37931070314 ps |
| CPU time | 608.13 seconds |
| Started | Jul 09 07:35:53 PM PDT 24 |
| Finished | Jul 09 07:46:09 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-b983a66a-a9da-4b59-ad68-67448759a4d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829985994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.2829985994 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.3980224587 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 633066670 ps |
| CPU time | 24.5 seconds |
| Started | Jul 09 07:35:47 PM PDT 24 |
| Finished | Jul 09 07:36:16 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-2c93d01b-3077-4d16-ac73-36b8f7985bdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980224587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.3980224587 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.2738712514 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 603642304 ps |
| CPU time | 22.87 seconds |
| Started | Jul 09 07:35:41 PM PDT 24 |
| Finished | Jul 09 07:36:07 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-a960a15d-828b-496a-aaf9-15e3a9e7c70b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738712514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.2738712514 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.2589872238 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 465745455 ps |
| CPU time | 19.88 seconds |
| Started | Jul 09 07:35:53 PM PDT 24 |
| Finished | Jul 09 07:36:19 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-e51969cf-5cf4-46ac-aff7-93ce36991d15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589872238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.2589872238 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.870409388 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 4783383514 ps |
| CPU time | 51.58 seconds |
| Started | Jul 09 07:35:52 PM PDT 24 |
| Finished | Jul 09 07:36:51 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-ab4ffb5c-00de-400a-9d3c-da2ae92c6a2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870409388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.870409388 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.3934809459 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 58649028774 ps |
| CPU time | 1017.39 seconds |
| Started | Jul 09 07:35:48 PM PDT 24 |
| Finished | Jul 09 07:52:52 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-07f25c1b-573a-46d6-9bf9-9cc8db1d0c66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934809459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.3934809459 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.3996575933 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 227933905 ps |
| CPU time | 20.7 seconds |
| Started | Jul 09 07:35:48 PM PDT 24 |
| Finished | Jul 09 07:36:14 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-90309f4e-cf8d-4560-9d69-b1b1ad54c42d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996575933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.3996575933 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.4168568936 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 787318482 ps |
| CPU time | 23.99 seconds |
| Started | Jul 09 07:35:42 PM PDT 24 |
| Finished | Jul 09 07:36:09 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-831cee8d-5a2b-4eb9-998d-2e01cba59497 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168568936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.4168568936 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.523298769 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 204939019 ps |
| CPU time | 8.66 seconds |
| Started | Jul 09 07:35:53 PM PDT 24 |
| Finished | Jul 09 07:36:09 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-d5553363-af74-42a0-b634-96f44ae7f5ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523298769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.523298769 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.2849576552 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 8313345322 ps |
| CPU time | 87.92 seconds |
| Started | Jul 09 07:35:56 PM PDT 24 |
| Finished | Jul 09 07:37:30 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-2f64d46e-d6bf-42ea-a555-e75ef5158593 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849576552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.2849576552 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.613062235 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 4984210395 ps |
| CPU time | 80.72 seconds |
| Started | Jul 09 07:35:55 PM PDT 24 |
| Finished | Jul 09 07:37:22 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-77e7de8c-b012-4181-9934-909a23a47bac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613062235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.613062235 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.4103955985 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 51862658 ps |
| CPU time | 6.63 seconds |
| Started | Jul 09 07:35:52 PM PDT 24 |
| Finished | Jul 09 07:36:06 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-3c1ae275-7f7e-402c-ab0b-222af2d616e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103955985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.4103955985 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.3022120742 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 2541005756 ps |
| CPU time | 243.13 seconds |
| Started | Jul 09 07:35:53 PM PDT 24 |
| Finished | Jul 09 07:40:03 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-4da3f72a-ba7b-47e1-be16-18f7df7d3b04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022120742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.3022120742 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.544358482 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 2785063088 ps |
| CPU time | 196.51 seconds |
| Started | Jul 09 07:35:48 PM PDT 24 |
| Finished | Jul 09 07:39:10 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-8b4f351f-a5d7-4da1-89e3-07eebaa6c7a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544358482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.544358482 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3221144055 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 18644011 ps |
| CPU time | 12.26 seconds |
| Started | Jul 09 07:35:46 PM PDT 24 |
| Finished | Jul 09 07:36:03 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-f7853343-93eb-41c7-bb5c-4a05fba03bec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221144055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.3221144055 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.3021012229 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 98191210 ps |
| CPU time | 6.63 seconds |
| Started | Jul 09 07:35:47 PM PDT 24 |
| Finished | Jul 09 07:35:59 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-38b7ab37-17c1-4a92-9364-f45ca271ac53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021012229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.3021012229 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.3822436085 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 1151836687 ps |
| CPU time | 44.39 seconds |
| Started | Jul 09 07:35:47 PM PDT 24 |
| Finished | Jul 09 07:36:36 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-7c0d0cdd-cc01-4024-adeb-f8f09f1f18b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822436085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.3822436085 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.2879660820 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 15807579 ps |
| CPU time | 6.61 seconds |
| Started | Jul 09 07:35:55 PM PDT 24 |
| Finished | Jul 09 07:36:08 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-2495094d-673e-47b2-b315-3ed2f94b9697 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879660820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .2879660820 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.1453817636 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 218481264 ps |
| CPU time | 10.78 seconds |
| Started | Jul 09 07:35:46 PM PDT 24 |
| Finished | Jul 09 07:36:02 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-995ba94f-ba3e-4fb6-8ded-93cdf16a2836 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453817636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.1453817636 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.898224408 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 85585732 ps |
| CPU time | 9.42 seconds |
| Started | Jul 09 07:35:51 PM PDT 24 |
| Finished | Jul 09 07:36:06 PM PDT 24 |
| Peak memory | 576416 kb |
| Host | smart-ee5b0195-c7a2-4306-8541-ca122aeed130 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898224408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.898224408 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.1948631092 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 443506987 ps |
| CPU time | 36.22 seconds |
| Started | Jul 09 07:35:53 PM PDT 24 |
| Finished | Jul 09 07:36:36 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-d2011cfc-4784-4e8d-8e32-5de543afd90c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948631092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.1948631092 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.1555829546 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 81573027552 ps |
| CPU time | 855 seconds |
| Started | Jul 09 07:35:51 PM PDT 24 |
| Finished | Jul 09 07:50:12 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-6fb7b029-1072-49b2-a3c7-36d2d75b36a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555829546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.1555829546 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.4069576196 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 33561020794 ps |
| CPU time | 619.05 seconds |
| Started | Jul 09 07:35:50 PM PDT 24 |
| Finished | Jul 09 07:46:16 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-612c6e15-2db4-42dd-b285-0b4550e85be2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069576196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.4069576196 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.1063120988 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 564029800 ps |
| CPU time | 42.34 seconds |
| Started | Jul 09 07:35:51 PM PDT 24 |
| Finished | Jul 09 07:36:40 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-1eb6c5d4-3c1a-44b7-8f2c-a70199eb3588 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063120988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del ays.1063120988 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.3063912549 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 1725040867 ps |
| CPU time | 48.07 seconds |
| Started | Jul 09 07:35:51 PM PDT 24 |
| Finished | Jul 09 07:36:46 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-6e533889-8b09-4051-857e-623ca6ef205b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063912549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.3063912549 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.2775154773 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 200776161 ps |
| CPU time | 9.28 seconds |
| Started | Jul 09 07:35:51 PM PDT 24 |
| Finished | Jul 09 07:36:07 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-b6096fc0-8fac-41ba-a523-523f35f79e31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775154773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.2775154773 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.285379305 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 7209277327 ps |
| CPU time | 76.03 seconds |
| Started | Jul 09 07:35:49 PM PDT 24 |
| Finished | Jul 09 07:37:11 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-63987313-41bb-4dc8-8343-d42e0e1a87f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285379305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.285379305 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.3916401052 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 5340078533 ps |
| CPU time | 81.78 seconds |
| Started | Jul 09 07:35:52 PM PDT 24 |
| Finished | Jul 09 07:37:21 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-e5cb5b58-a4f8-4c1d-8dd6-4c660b657248 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916401052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.3916401052 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.4080286897 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 48496597 ps |
| CPU time | 6.42 seconds |
| Started | Jul 09 07:35:53 PM PDT 24 |
| Finished | Jul 09 07:36:07 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-e2b7f1e5-3944-4a98-950e-0021651918ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080286897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.4080286897 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.2809030886 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 15254346598 ps |
| CPU time | 505.94 seconds |
| Started | Jul 09 07:35:57 PM PDT 24 |
| Finished | Jul 09 07:44:28 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-b2aa872a-19d4-4f18-8dbf-2d233ce005b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809030886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.2809030886 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.1614865364 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 2491417806 ps |
| CPU time | 199.6 seconds |
| Started | Jul 09 07:35:56 PM PDT 24 |
| Finished | Jul 09 07:39:22 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-8b4f5d36-4665-4458-a4d1-3588702405fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614865364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.1614865364 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3343827165 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 10247627982 ps |
| CPU time | 497.14 seconds |
| Started | Jul 09 07:35:56 PM PDT 24 |
| Finished | Jul 09 07:44:19 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-47b65c21-1220-4d3e-bb2b-0224cbe4d22b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343827165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.3343827165 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.1740337578 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 5419775024 ps |
| CPU time | 274.87 seconds |
| Started | Jul 09 07:35:56 PM PDT 24 |
| Finished | Jul 09 07:40:37 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-571822ca-ad86-41ce-9d83-52c14c0662b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740337578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.1740337578 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.2276568916 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 266923739 ps |
| CPU time | 31 seconds |
| Started | Jul 09 07:35:57 PM PDT 24 |
| Finished | Jul 09 07:36:33 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-6a519bf0-b679-48bd-8e67-4dc212dbed51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276568916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.2276568916 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.3415553886 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2990788233 ps |
| CPU time | 135.23 seconds |
| Started | Jul 09 07:35:56 PM PDT 24 |
| Finished | Jul 09 07:38:17 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-6f623b0e-b057-4e18-bff6-4b33f2a21d3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415553886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .3415553886 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3762305211 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 104409008798 ps |
| CPU time | 1953.08 seconds |
| Started | Jul 09 07:35:55 PM PDT 24 |
| Finished | Jul 09 08:08:35 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-1f12e789-4c5e-47db-9f73-70694de37515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762305211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.3762305211 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.1035096116 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 928563000 ps |
| CPU time | 32.06 seconds |
| Started | Jul 09 07:36:01 PM PDT 24 |
| Finished | Jul 09 07:36:36 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-9f4b11ff-9959-45da-8347-8ce08b99f53d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035096116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.1035096116 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.3483695294 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 94926637 ps |
| CPU time | 9.4 seconds |
| Started | Jul 09 07:36:07 PM PDT 24 |
| Finished | Jul 09 07:36:18 PM PDT 24 |
| Peak memory | 576416 kb |
| Host | smart-8679a30b-5401-4187-9dbb-d7e4f58a91aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483695294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.3483695294 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.4183398041 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 460305164 ps |
| CPU time | 39.56 seconds |
| Started | Jul 09 07:35:57 PM PDT 24 |
| Finished | Jul 09 07:36:42 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-3868ad62-9f00-41db-8cd4-342003a99dc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183398041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.4183398041 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.4173704011 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 29630272548 ps |
| CPU time | 300.3 seconds |
| Started | Jul 09 07:35:55 PM PDT 24 |
| Finished | Jul 09 07:41:02 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-08424108-f1f3-4d12-b3b9-4f47f21b7b9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173704011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.4173704011 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.3151631219 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 7627030726 ps |
| CPU time | 128.91 seconds |
| Started | Jul 09 07:35:56 PM PDT 24 |
| Finished | Jul 09 07:38:11 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-ec01997c-20b7-46de-bd29-6d186c4951ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151631219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.3151631219 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.3030830893 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 111548192 ps |
| CPU time | 13.86 seconds |
| Started | Jul 09 07:35:54 PM PDT 24 |
| Finished | Jul 09 07:36:14 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-769e6c57-4bc7-4f93-8bdb-c0a501e79611 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030830893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.3030830893 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.358450298 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 1999291664 ps |
| CPU time | 62.28 seconds |
| Started | Jul 09 07:36:03 PM PDT 24 |
| Finished | Jul 09 07:37:07 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-95c2640e-41b0-4e19-a590-e80b8048c573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358450298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.358450298 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.997038837 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 47523738 ps |
| CPU time | 6.17 seconds |
| Started | Jul 09 07:35:57 PM PDT 24 |
| Finished | Jul 09 07:36:09 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-d61348a8-4534-42cf-b122-d551ee63312d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997038837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.997038837 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.625080925 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 8181863058 ps |
| CPU time | 89.69 seconds |
| Started | Jul 09 07:35:56 PM PDT 24 |
| Finished | Jul 09 07:37:32 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-205c12f1-e5f0-4de8-9c88-7e3e6aa2f930 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625080925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.625080925 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.1586006348 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 5645807952 ps |
| CPU time | 94.07 seconds |
| Started | Jul 09 07:35:55 PM PDT 24 |
| Finished | Jul 09 07:37:35 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-7c899b94-bd96-4be0-a8ae-67247179fa61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586006348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.1586006348 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.618219698 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 50496398 ps |
| CPU time | 6.87 seconds |
| Started | Jul 09 07:35:48 PM PDT 24 |
| Finished | Jul 09 07:36:01 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-0901e146-8994-42f1-9479-fd9a71dd5128 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618219698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delays .618219698 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.61940202 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 4536235494 ps |
| CPU time | 168.07 seconds |
| Started | Jul 09 07:36:09 PM PDT 24 |
| Finished | Jul 09 07:38:58 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-19946c0b-d08f-4ee0-b3f7-7c06c2b4d1c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61940202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.61940202 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.1714872461 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 11734150304 ps |
| CPU time | 387.29 seconds |
| Started | Jul 09 07:36:08 PM PDT 24 |
| Finished | Jul 09 07:42:38 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-8e40bac4-82a7-4f35-884a-3fe7a9ceeda9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714872461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.1714872461 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.2609589197 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 59979372 ps |
| CPU time | 42.37 seconds |
| Started | Jul 09 07:36:03 PM PDT 24 |
| Finished | Jul 09 07:36:47 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-30ce86b3-473d-44f1-bc51-81ab4e8dfb4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609589197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_rand_reset.2609589197 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3746352490 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 2153656240 ps |
| CPU time | 225.46 seconds |
| Started | Jul 09 07:36:02 PM PDT 24 |
| Finished | Jul 09 07:39:50 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-0f66ef9d-30c3-406d-8306-c60b89031747 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746352490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.3746352490 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.3076581164 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 1081380646 ps |
| CPU time | 40.2 seconds |
| Started | Jul 09 07:36:08 PM PDT 24 |
| Finished | Jul 09 07:36:50 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-63c6fe59-4091-4c6c-b899-4769de6ef1ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076581164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.3076581164 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.3711755957 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1078831122 ps |
| CPU time | 92.23 seconds |
| Started | Jul 09 07:36:18 PM PDT 24 |
| Finished | Jul 09 07:37:52 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-dc4e6ca0-b7ff-4eac-b541-990cf5b06a14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711755957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .3711755957 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.2494637722 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 56766786717 ps |
| CPU time | 1063.29 seconds |
| Started | Jul 09 07:36:17 PM PDT 24 |
| Finished | Jul 09 07:54:01 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-69593cf5-74b7-4a9d-aa8b-fc88ffcbf578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494637722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.2494637722 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.464649319 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 91597570 ps |
| CPU time | 6.68 seconds |
| Started | Jul 09 07:36:36 PM PDT 24 |
| Finished | Jul 09 07:36:44 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-17531dfa-583f-4d66-9421-9d09071ae5e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464649319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr .464649319 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.2063489425 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 563778491 ps |
| CPU time | 43.84 seconds |
| Started | Jul 09 07:36:27 PM PDT 24 |
| Finished | Jul 09 07:37:12 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-37f42f00-b263-4b6a-962d-c4da5342ac05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063489425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.2063489425 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.1070856970 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 1947792060 ps |
| CPU time | 76.24 seconds |
| Started | Jul 09 07:36:07 PM PDT 24 |
| Finished | Jul 09 07:37:25 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-79b76784-812d-4039-8bd0-700d760e4cb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070856970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.1070856970 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.3397392741 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 76758192612 ps |
| CPU time | 882.49 seconds |
| Started | Jul 09 07:36:11 PM PDT 24 |
| Finished | Jul 09 07:50:55 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-823d0f02-30b3-4bdf-8eec-9c752c332dcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397392741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.3397392741 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.3001530824 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 7390451759 ps |
| CPU time | 128.07 seconds |
| Started | Jul 09 07:36:18 PM PDT 24 |
| Finished | Jul 09 07:38:27 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-3709b3eb-529a-4a39-a748-a97a49e94dd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001530824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.3001530824 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.15467807 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 507656677 ps |
| CPU time | 45.26 seconds |
| Started | Jul 09 07:36:10 PM PDT 24 |
| Finished | Jul 09 07:36:56 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-eacf32f9-1bb7-441b-9b87-79f457eb2ea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15467807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_delay s.15467807 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.2044790444 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2087704880 ps |
| CPU time | 57.04 seconds |
| Started | Jul 09 07:36:28 PM PDT 24 |
| Finished | Jul 09 07:37:26 PM PDT 24 |
| Peak memory | 576452 kb |
| Host | smart-dad7da4c-b578-40e8-9660-3be6de850afc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044790444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.2044790444 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.524551209 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 171579580 ps |
| CPU time | 8.1 seconds |
| Started | Jul 09 07:36:03 PM PDT 24 |
| Finished | Jul 09 07:36:13 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-591a8b27-2813-4ddf-84d2-ca28fa1615fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524551209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.524551209 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.2400317234 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 9918901614 ps |
| CPU time | 101.13 seconds |
| Started | Jul 09 07:36:11 PM PDT 24 |
| Finished | Jul 09 07:37:53 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-2604f2ee-4d56-4d7d-b2e6-47c645ecc5d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400317234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.2400317234 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.2872612290 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 4850880618 ps |
| CPU time | 83.02 seconds |
| Started | Jul 09 07:36:09 PM PDT 24 |
| Finished | Jul 09 07:37:34 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-6434ad90-bee6-42c9-b083-1b43eac49ae7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872612290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.2872612290 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.237813630 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 50222497 ps |
| CPU time | 6.71 seconds |
| Started | Jul 09 07:36:12 PM PDT 24 |
| Finished | Jul 09 07:36:20 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-92b1b2c9-2e81-485d-b44d-3d9f0c5ab9f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237813630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delays .237813630 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.351727354 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 5429383569 ps |
| CPU time | 224.03 seconds |
| Started | Jul 09 07:36:33 PM PDT 24 |
| Finished | Jul 09 07:40:18 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-2024e6bc-e429-4001-b106-1fb715f03cd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351727354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.351727354 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.4232955723 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 4005049440 ps |
| CPU time | 216.57 seconds |
| Started | Jul 09 07:36:32 PM PDT 24 |
| Finished | Jul 09 07:40:10 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-ca60f4f1-f69d-4680-a56e-a79e8abafc6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232955723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.4232955723 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.4192745934 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 477426758 ps |
| CPU time | 43.2 seconds |
| Started | Jul 09 07:36:38 PM PDT 24 |
| Finished | Jul 09 07:37:22 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-c335656b-f5b8-4147-82f8-6f64419a5cca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192745934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.4192745934 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.899691459 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 409030066 ps |
| CPU time | 17.83 seconds |
| Started | Jul 09 07:36:32 PM PDT 24 |
| Finished | Jul 09 07:36:51 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-30217bb8-1878-41f5-94ff-c6d9bf6e0d3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899691459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.899691459 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.1653142496 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 490092703 ps |
| CPU time | 26.83 seconds |
| Started | Jul 09 07:36:48 PM PDT 24 |
| Finished | Jul 09 07:37:16 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-20acce30-e9df-4d24-b4ab-f5d38357086b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653142496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .1653142496 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.4131575450 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 104774013793 ps |
| CPU time | 1877.22 seconds |
| Started | Jul 09 07:36:43 PM PDT 24 |
| Finished | Jul 09 08:08:02 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-0e5ca1fa-9631-4e15-9704-df407b401482 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131575450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.4131575450 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.214654978 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 37879893 ps |
| CPU time | 7.17 seconds |
| Started | Jul 09 07:36:47 PM PDT 24 |
| Finished | Jul 09 07:36:55 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-2454fb69-a019-414e-9b4d-32e194b9b3fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214654978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_addr .214654978 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.2226534270 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 2604809392 ps |
| CPU time | 79.74 seconds |
| Started | Jul 09 07:36:48 PM PDT 24 |
| Finished | Jul 09 07:38:08 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-a430ac7c-7aa9-47b8-9afb-024869cc606e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226534270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.2226534270 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.2529888312 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 1681817631 ps |
| CPU time | 58.88 seconds |
| Started | Jul 09 07:36:44 PM PDT 24 |
| Finished | Jul 09 07:37:44 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-e7bc9e87-a73f-415b-8bfa-94b8813f8f6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529888312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.2529888312 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.4155456779 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 11554300994 ps |
| CPU time | 117.32 seconds |
| Started | Jul 09 07:36:46 PM PDT 24 |
| Finished | Jul 09 07:38:44 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-f3ca4231-a9e6-4854-a442-3bf15ab09ae1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155456779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.4155456779 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.1390546575 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 44520134949 ps |
| CPU time | 762.58 seconds |
| Started | Jul 09 07:36:45 PM PDT 24 |
| Finished | Jul 09 07:49:29 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-d3c4f2f4-49da-4657-9dc7-512ae844212f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390546575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.1390546575 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.3577972282 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 276502511 ps |
| CPU time | 24.36 seconds |
| Started | Jul 09 07:36:46 PM PDT 24 |
| Finished | Jul 09 07:37:11 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-1169506d-8f77-4514-8a9b-bc9372a2faf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577972282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.3577972282 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.2464005126 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 2028547861 ps |
| CPU time | 64.9 seconds |
| Started | Jul 09 07:36:44 PM PDT 24 |
| Finished | Jul 09 07:37:51 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-107bd65a-35b5-421a-86d8-1424a18ee0f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464005126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.2464005126 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.2578982071 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 34475880 ps |
| CPU time | 5.23 seconds |
| Started | Jul 09 07:36:38 PM PDT 24 |
| Finished | Jul 09 07:36:44 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-1fae4941-8dd8-45d1-80b5-8e98db0621d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578982071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.2578982071 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.2139164215 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 8802993149 ps |
| CPU time | 90.57 seconds |
| Started | Jul 09 07:36:43 PM PDT 24 |
| Finished | Jul 09 07:38:14 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-c5646b6d-e69b-4f3a-9420-885a07092280 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139164215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.2139164215 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.532706612 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 6534230623 ps |
| CPU time | 106.39 seconds |
| Started | Jul 09 07:36:38 PM PDT 24 |
| Finished | Jul 09 07:38:25 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-e3dc2915-1d9c-4a91-9386-f93d7f2e6bb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532706612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.532706612 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.125685095 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 37824654 ps |
| CPU time | 5.89 seconds |
| Started | Jul 09 07:36:41 PM PDT 24 |
| Finished | Jul 09 07:36:48 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-5b5a0643-9b53-46eb-b914-4964b0d6da9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125685095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays .125685095 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.2868850468 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 2843745046 ps |
| CPU time | 243.16 seconds |
| Started | Jul 09 07:36:44 PM PDT 24 |
| Finished | Jul 09 07:40:48 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-300995cb-ed01-4b1f-ab87-a4328574978a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868850468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.2868850468 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.1664916387 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 1178983799 ps |
| CPU time | 78.67 seconds |
| Started | Jul 09 07:36:53 PM PDT 24 |
| Finished | Jul 09 07:38:14 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-0a34264b-456c-4f38-aa70-633def915656 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664916387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.1664916387 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.3884139060 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 313989454 ps |
| CPU time | 94.24 seconds |
| Started | Jul 09 07:36:44 PM PDT 24 |
| Finished | Jul 09 07:38:20 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-d3e57a49-5b45-4091-813f-000325bcc979 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884139060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.3884139060 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.136618479 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 5829623782 ps |
| CPU time | 645.12 seconds |
| Started | Jul 09 07:36:59 PM PDT 24 |
| Finished | Jul 09 07:47:46 PM PDT 24 |
| Peak memory | 577788 kb |
| Host | smart-8603350a-5e58-4ed9-b333-aeacd2404b81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136618479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_reset_error.136618479 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.448530982 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 210947429 ps |
| CPU time | 26.01 seconds |
| Started | Jul 09 07:36:43 PM PDT 24 |
| Finished | Jul 09 07:37:11 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-01842f23-6c27-4ded-967d-2f151528d471 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448530982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.448530982 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.3202661743 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 2135834230 ps |
| CPU time | 97.05 seconds |
| Started | Jul 09 07:37:01 PM PDT 24 |
| Finished | Jul 09 07:38:41 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-1a08993d-85ca-424b-a75d-456f4eb9310c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202661743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .3202661743 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2364586983 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 44785223881 ps |
| CPU time | 839.53 seconds |
| Started | Jul 09 07:37:01 PM PDT 24 |
| Finished | Jul 09 07:51:03 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-ced51bdf-e797-427c-b280-a124b0dfed08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364586983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.2364586983 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.4146045870 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 1266051571 ps |
| CPU time | 53 seconds |
| Started | Jul 09 07:37:02 PM PDT 24 |
| Finished | Jul 09 07:37:58 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-b1e9d835-8f8b-4456-89a4-e3afcb9f798f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146045870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.4146045870 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.1834747529 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 1113069818 ps |
| CPU time | 40.24 seconds |
| Started | Jul 09 07:37:03 PM PDT 24 |
| Finished | Jul 09 07:37:46 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-ff378be3-017f-4cb9-8a7d-276f8cde71e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834747529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.1834747529 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.1752584959 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 604605271 ps |
| CPU time | 21.99 seconds |
| Started | Jul 09 07:36:53 PM PDT 24 |
| Finished | Jul 09 07:37:17 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-5953cb8a-633a-482d-ae5e-fa0f49e57f0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752584959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.1752584959 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.76881509 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 63284829889 ps |
| CPU time | 686.57 seconds |
| Started | Jul 09 07:36:54 PM PDT 24 |
| Finished | Jul 09 07:48:22 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-c5400374-bb12-4b17-a6dd-6234a11b452c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76881509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.76881509 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.187310325 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 31294565433 ps |
| CPU time | 523.34 seconds |
| Started | Jul 09 07:37:00 PM PDT 24 |
| Finished | Jul 09 07:45:45 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-5bd19515-5d58-4c89-985c-fc339b1d34ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187310325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.187310325 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.3444953619 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 543373616 ps |
| CPU time | 44.85 seconds |
| Started | Jul 09 07:36:52 PM PDT 24 |
| Finished | Jul 09 07:37:38 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-418052ee-8cb2-4533-afe8-9961d57192d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444953619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.3444953619 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.538358557 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 2549428387 ps |
| CPU time | 72.73 seconds |
| Started | Jul 09 07:37:02 PM PDT 24 |
| Finished | Jul 09 07:38:17 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-8684bf8d-bdb1-4627-8394-0c5c09390de5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538358557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.538358557 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.1776577574 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 212951262 ps |
| CPU time | 8.41 seconds |
| Started | Jul 09 07:36:54 PM PDT 24 |
| Finished | Jul 09 07:37:04 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-2a495644-f8cb-4805-8274-6c892644cc70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776577574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.1776577574 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.3316573190 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 9267917462 ps |
| CPU time | 98.9 seconds |
| Started | Jul 09 07:36:54 PM PDT 24 |
| Finished | Jul 09 07:38:35 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-fb4e7487-7b0c-43c5-93a6-5f8dff75cc7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316573190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.3316573190 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.1873208778 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 5675264284 ps |
| CPU time | 98.59 seconds |
| Started | Jul 09 07:36:53 PM PDT 24 |
| Finished | Jul 09 07:38:33 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-f396afef-dbfe-4d18-a0c3-892c9d62adce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873208778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.1873208778 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.1433638848 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 50492988 ps |
| CPU time | 5.76 seconds |
| Started | Jul 09 07:36:52 PM PDT 24 |
| Finished | Jul 09 07:37:00 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-c5f5d37d-51e9-4010-81b9-3dc584590dfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433638848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.1433638848 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.1048351144 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 8146118778 ps |
| CPU time | 308.63 seconds |
| Started | Jul 09 07:37:03 PM PDT 24 |
| Finished | Jul 09 07:42:14 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-70f58508-9413-40cc-b2a8-76a0dda0c2e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048351144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.1048351144 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.2952428460 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 2715138971 ps |
| CPU time | 225.12 seconds |
| Started | Jul 09 07:37:01 PM PDT 24 |
| Finished | Jul 09 07:40:48 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-1c4728fc-eeb8-487a-9a1c-5b5a849757e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952428460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.2952428460 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3970350952 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 551938107 ps |
| CPU time | 164.64 seconds |
| Started | Jul 09 07:37:00 PM PDT 24 |
| Finished | Jul 09 07:39:47 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-9c63d611-28eb-4e28-82fc-7b424190a22e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970350952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.3970350952 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.618065636 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 4357816950 ps |
| CPU time | 314.31 seconds |
| Started | Jul 09 07:37:01 PM PDT 24 |
| Finished | Jul 09 07:42:19 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-b261e06d-1886-4d88-a358-bd324d52ebf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618065636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_reset_error.618065636 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.2895228612 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 629787108 ps |
| CPU time | 28.39 seconds |
| Started | Jul 09 07:37:03 PM PDT 24 |
| Finished | Jul 09 07:37:34 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-88bb193b-ee09-476a-a7a9-3cd5ff207ef8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895228612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.2895228612 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.3094682427 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 650314921 ps |
| CPU time | 28.09 seconds |
| Started | Jul 09 07:37:07 PM PDT 24 |
| Finished | Jul 09 07:37:38 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-e0ebab1d-33d6-40b0-ab96-3ecef49fecab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094682427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .3094682427 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.3847870122 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 155328718 ps |
| CPU time | 9.43 seconds |
| Started | Jul 09 07:37:07 PM PDT 24 |
| Finished | Jul 09 07:37:18 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-a451900b-d6bd-4b2c-b313-dbf71e930f86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847870122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.3847870122 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.4258929189 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 2223207320 ps |
| CPU time | 81.5 seconds |
| Started | Jul 09 07:37:07 PM PDT 24 |
| Finished | Jul 09 07:38:31 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-a312e50b-1752-42a3-bfb3-a878c5df0a57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258929189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.4258929189 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.1470051391 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 1714215507 ps |
| CPU time | 64.79 seconds |
| Started | Jul 09 07:36:59 PM PDT 24 |
| Finished | Jul 09 07:38:06 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-fc04ec00-18aa-4acd-b45c-7826c81e5d33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470051391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.1470051391 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.1274021324 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 58228103587 ps |
| CPU time | 642.67 seconds |
| Started | Jul 09 07:37:03 PM PDT 24 |
| Finished | Jul 09 07:47:48 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-5b7e641a-cf59-462f-9c08-306e9e0143ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274021324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.1274021324 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.1371296408 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 47695762791 ps |
| CPU time | 846.79 seconds |
| Started | Jul 09 07:37:11 PM PDT 24 |
| Finished | Jul 09 07:51:19 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-af9b0873-0628-4e41-90af-90ab50b019b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371296408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.1371296408 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.2626279542 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 164020158 ps |
| CPU time | 19.09 seconds |
| Started | Jul 09 07:36:59 PM PDT 24 |
| Finished | Jul 09 07:37:20 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-d34cec01-3016-4672-b2d2-67d13487ca43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626279542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.2626279542 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.3267801205 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 1829369676 ps |
| CPU time | 54.44 seconds |
| Started | Jul 09 07:37:11 PM PDT 24 |
| Finished | Jul 09 07:38:06 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-be8259d2-d867-436f-b249-a05a85df6966 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267801205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.3267801205 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.2979358354 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 227229866 ps |
| CPU time | 9.47 seconds |
| Started | Jul 09 07:37:03 PM PDT 24 |
| Finished | Jul 09 07:37:15 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-6ad8c09e-4970-42bc-80cd-20e5a4b8da5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979358354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.2979358354 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.3205973937 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 9015301978 ps |
| CPU time | 94.49 seconds |
| Started | Jul 09 07:37:03 PM PDT 24 |
| Finished | Jul 09 07:38:40 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-25b78d6d-f171-410b-9c2b-7094fc50689c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205973937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.3205973937 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.2451295255 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 5262012594 ps |
| CPU time | 91.86 seconds |
| Started | Jul 09 07:37:00 PM PDT 24 |
| Finished | Jul 09 07:38:33 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-03e696d0-fc30-45b0-a955-2b95ce7de7fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451295255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.2451295255 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.4202299045 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 44705217 ps |
| CPU time | 6.01 seconds |
| Started | Jul 09 07:37:00 PM PDT 24 |
| Finished | Jul 09 07:37:09 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-08668a47-bdab-4c1a-866f-10c7ed0707d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202299045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.4202299045 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.2695809173 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 1068908168 ps |
| CPU time | 77.73 seconds |
| Started | Jul 09 07:37:07 PM PDT 24 |
| Finished | Jul 09 07:38:27 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-efd74962-6a25-48f3-9565-26f6325a87b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695809173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.2695809173 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2693495656 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 3392192415 ps |
| CPU time | 219.37 seconds |
| Started | Jul 09 07:37:07 PM PDT 24 |
| Finished | Jul 09 07:40:49 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-5737f306-e54c-4a2e-af5a-97432aa407e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693495656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.2693495656 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.4037363013 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 5864004723 ps |
| CPU time | 444.4 seconds |
| Started | Jul 09 07:37:08 PM PDT 24 |
| Finished | Jul 09 07:44:35 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-62e0451c-96fa-4727-a0b8-d4eb52450de4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037363013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.4037363013 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.2833894540 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 598983675 ps |
| CPU time | 163.42 seconds |
| Started | Jul 09 07:37:08 PM PDT 24 |
| Finished | Jul 09 07:39:54 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-e25deada-370a-4431-8e63-274c2d35e104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833894540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.2833894540 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.3537990251 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 342954930 ps |
| CPU time | 39.47 seconds |
| Started | Jul 09 07:37:08 PM PDT 24 |
| Finished | Jul 09 07:37:50 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-50480e67-2088-42e3-8421-ec735be5341b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537990251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.3537990251 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.991451639 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 256604813 ps |
| CPU time | 31.07 seconds |
| Started | Jul 09 07:37:08 PM PDT 24 |
| Finished | Jul 09 07:37:41 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-ca3ae3bb-8a0e-47c1-86e7-651c7955d40d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991451639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device. 991451639 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.1578784293 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 121536658367 ps |
| CPU time | 2200.33 seconds |
| Started | Jul 09 07:37:05 PM PDT 24 |
| Finished | Jul 09 08:13:47 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-cb3a4608-1327-4ec2-99c2-f1ecdc4f28fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578784293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.1578784293 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.902505742 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 87612469 ps |
| CPU time | 12.25 seconds |
| Started | Jul 09 07:37:15 PM PDT 24 |
| Finished | Jul 09 07:37:29 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-0838e57e-a8b8-4703-aedf-5e4bfb5bfa4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902505742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr .902505742 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.220386904 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 204724817 ps |
| CPU time | 10.54 seconds |
| Started | Jul 09 07:37:17 PM PDT 24 |
| Finished | Jul 09 07:37:29 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-d0c4faf4-c486-4fb1-9e5a-60d02317055f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220386904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.220386904 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.2278016389 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 402916431 ps |
| CPU time | 36.87 seconds |
| Started | Jul 09 07:37:08 PM PDT 24 |
| Finished | Jul 09 07:37:47 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-63d3ce4e-3daa-4f0a-8972-9c239a566f87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278016389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2278016389 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.1057391442 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 93190149535 ps |
| CPU time | 1000.27 seconds |
| Started | Jul 09 07:37:07 PM PDT 24 |
| Finished | Jul 09 07:53:50 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-be17b5bd-64cb-42d0-8639-0aeec08999de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057391442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.1057391442 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.2704102585 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 44708079744 ps |
| CPU time | 848.14 seconds |
| Started | Jul 09 07:37:10 PM PDT 24 |
| Finished | Jul 09 07:51:20 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-6fbf9ea1-b011-444a-8a33-97c699c0a817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704102585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.2704102585 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.3815152569 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 338865145 ps |
| CPU time | 27.03 seconds |
| Started | Jul 09 07:37:07 PM PDT 24 |
| Finished | Jul 09 07:37:37 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-96debde7-0345-477c-9f36-558029ac457a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815152569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.3815152569 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.1832123600 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 164810835 ps |
| CPU time | 15.23 seconds |
| Started | Jul 09 07:37:06 PM PDT 24 |
| Finished | Jul 09 07:37:23 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-822dbfdd-9bdc-47f5-8436-231f0ffabc0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832123600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.1832123600 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.3861474241 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 41447491 ps |
| CPU time | 5.84 seconds |
| Started | Jul 09 07:37:06 PM PDT 24 |
| Finished | Jul 09 07:37:14 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-79f46e2c-c270-473d-849f-fae7919743c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861474241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.3861474241 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.416241206 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 6697697120 ps |
| CPU time | 71.02 seconds |
| Started | Jul 09 07:37:09 PM PDT 24 |
| Finished | Jul 09 07:38:22 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-6cb2e561-9a18-4690-8011-a32f4df4eee7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416241206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.416241206 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.3533087302 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 4776198625 ps |
| CPU time | 83.14 seconds |
| Started | Jul 09 07:37:07 PM PDT 24 |
| Finished | Jul 09 07:38:32 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-c5089d3f-098c-4a71-a3fa-fba91d7d4a3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533087302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.3533087302 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.4000355993 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 47671889 ps |
| CPU time | 6.29 seconds |
| Started | Jul 09 07:37:07 PM PDT 24 |
| Finished | Jul 09 07:37:15 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-d5ac1df5-2f74-4765-8d7e-f1921637bb0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000355993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.4000355993 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.1108013963 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 3958793021 ps |
| CPU time | 364.92 seconds |
| Started | Jul 09 07:37:15 PM PDT 24 |
| Finished | Jul 09 07:43:22 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-36605f60-2773-46c5-abdc-36d0f6895e1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108013963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.1108013963 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.3425974154 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 3380910775 ps |
| CPU time | 257.1 seconds |
| Started | Jul 09 07:37:15 PM PDT 24 |
| Finished | Jul 09 07:41:34 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-0aa3d052-0ace-4f97-8710-188920f1377e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425974154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.3425974154 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.1795372715 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 11001557457 ps |
| CPU time | 511.95 seconds |
| Started | Jul 09 07:37:16 PM PDT 24 |
| Finished | Jul 09 07:45:49 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-c841088c-c3f5-4871-af5a-850db9b3befb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795372715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.1795372715 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.3293489721 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 25423184 ps |
| CPU time | 5.84 seconds |
| Started | Jul 09 07:37:17 PM PDT 24 |
| Finished | Jul 09 07:37:25 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-1afaaa1a-b05e-4494-b9a7-617e6e5880ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293489721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.3293489721 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.3131368214 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 4132616155 ps |
| CPU time | 365.23 seconds |
| Started | Jul 09 07:25:45 PM PDT 24 |
| Finished | Jul 09 07:32:07 PM PDT 24 |
| Peak memory | 597180 kb |
| Host | smart-f7c69467-4dff-4874-bdff-a3573036869c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131368214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.3131368214 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.3707486789 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 16676066125 ps |
| CPU time | 2085.58 seconds |
| Started | Jul 09 07:25:42 PM PDT 24 |
| Finished | Jul 09 08:00:43 PM PDT 24 |
| Peak memory | 593356 kb |
| Host | smart-c17898b5-30ef-44c3-98dd-c637ae040c7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707486789 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.3707486789 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.2940216219 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 4355645986 ps |
| CPU time | 274.81 seconds |
| Started | Jul 09 07:25:39 PM PDT 24 |
| Finished | Jul 09 07:30:27 PM PDT 24 |
| Peak memory | 599196 kb |
| Host | smart-290474d7-f39d-4651-80ba-e75789fd6715 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940216219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.2940216219 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.920240221 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 710047623 ps |
| CPU time | 45.12 seconds |
| Started | Jul 09 07:25:39 PM PDT 24 |
| Finished | Jul 09 07:26:38 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-97b2ce13-9f73-4476-8959-216bd073f231 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920240221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.920240221 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2246053084 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 134488742757 ps |
| CPU time | 2426.95 seconds |
| Started | Jul 09 07:25:48 PM PDT 24 |
| Finished | Jul 09 08:06:34 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-0a6d6e11-050e-4f95-9b7d-5d568f4df471 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246053084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.2246053084 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.1775621437 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 725271147 ps |
| CPU time | 28.04 seconds |
| Started | Jul 09 07:25:46 PM PDT 24 |
| Finished | Jul 09 07:26:31 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-640f231c-4d03-4423-9d19-466cdcb907b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775621437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .1775621437 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.3777406290 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 595529950 ps |
| CPU time | 48.96 seconds |
| Started | Jul 09 07:25:47 PM PDT 24 |
| Finished | Jul 09 07:26:54 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-f67cc26e-9f04-492d-9387-c6fda62f7e5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777406290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3777406290 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.793764195 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 74855919 ps |
| CPU time | 9.49 seconds |
| Started | Jul 09 07:25:39 PM PDT 24 |
| Finished | Jul 09 07:26:01 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-7a479529-32b5-417c-9fbc-80ccfcd06898 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793764195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.793764195 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.3595003377 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 2040500295 ps |
| CPU time | 21.8 seconds |
| Started | Jul 09 07:25:39 PM PDT 24 |
| Finished | Jul 09 07:26:15 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-7d5d86e0-0ace-44bb-b3d8-501283beb8fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595003377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3595003377 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.3003066175 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 4410550605 ps |
| CPU time | 78.92 seconds |
| Started | Jul 09 07:25:41 PM PDT 24 |
| Finished | Jul 09 07:27:15 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-d7d4e9c8-8529-4ac9-b8d1-568683c80961 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003066175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3003066175 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.915478889 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 154515682 ps |
| CPU time | 16.91 seconds |
| Started | Jul 09 07:25:38 PM PDT 24 |
| Finished | Jul 09 07:26:09 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-46ef716e-e7a6-497c-b415-00cc88bda48a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915478889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delay s.915478889 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.3612273649 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 2309998704 ps |
| CPU time | 68.2 seconds |
| Started | Jul 09 07:25:46 PM PDT 24 |
| Finished | Jul 09 07:27:11 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-473a6e3d-2f4e-4ef5-a8a1-0680eeb04c76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612273649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3612273649 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.2908476603 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 57021960 ps |
| CPU time | 6.29 seconds |
| Started | Jul 09 07:25:41 PM PDT 24 |
| Finished | Jul 09 07:26:02 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-cf2c14dd-b70f-4309-bdbc-bf553ee31e7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908476603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2908476603 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.2075396148 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 9181703649 ps |
| CPU time | 97.77 seconds |
| Started | Jul 09 07:25:39 PM PDT 24 |
| Finished | Jul 09 07:27:30 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-3ab7903b-3082-426a-8983-1847936e60f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075396148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2075396148 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.539065506 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 5126199227 ps |
| CPU time | 83 seconds |
| Started | Jul 09 07:25:43 PM PDT 24 |
| Finished | Jul 09 07:27:21 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-1bdba87b-0365-43bd-ba14-c1df25a8db78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539065506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.539065506 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.964962387 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 50056434 ps |
| CPU time | 6.4 seconds |
| Started | Jul 09 07:25:40 PM PDT 24 |
| Finished | Jul 09 07:25:59 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-fc9d2b11-318f-458b-b660-2a62a1e8ead9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964962387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays. 964962387 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.1267410373 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 17584635968 ps |
| CPU time | 597.52 seconds |
| Started | Jul 09 07:25:46 PM PDT 24 |
| Finished | Jul 09 07:36:01 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-cf0ed7b9-7e0f-4248-9e82-ffe637eaa144 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267410373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1267410373 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.180551892 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 2135330651 ps |
| CPU time | 170.68 seconds |
| Started | Jul 09 07:25:45 PM PDT 24 |
| Finished | Jul 09 07:28:51 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-1bdea8a0-e087-4310-8031-b634cb46bdcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180551892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.180551892 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.1844013267 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 1615451540 ps |
| CPU time | 142.12 seconds |
| Started | Jul 09 07:25:46 PM PDT 24 |
| Finished | Jul 09 07:28:25 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-48597fd8-7ba7-426e-8db9-79123518b8e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844013267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.1844013267 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3092934527 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 118798786 ps |
| CPU time | 70.9 seconds |
| Started | Jul 09 07:25:45 PM PDT 24 |
| Finished | Jul 09 07:27:13 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-2e142099-49f4-4af4-8c46-f37b4630159c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092934527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.3092934527 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.180144262 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 1527683455 ps |
| CPU time | 53.95 seconds |
| Started | Jul 09 07:25:46 PM PDT 24 |
| Finished | Jul 09 07:26:57 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-f9bc710c-4d73-4c1b-a072-40dfd883480b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180144262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.180144262 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.1318040616 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 953787839 ps |
| CPU time | 67.47 seconds |
| Started | Jul 09 07:37:15 PM PDT 24 |
| Finished | Jul 09 07:38:25 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-093e430d-48ed-4ae3-863f-66413ec0d9f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318040616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .1318040616 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.1818929482 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 76419939472 ps |
| CPU time | 1515.06 seconds |
| Started | Jul 09 07:37:15 PM PDT 24 |
| Finished | Jul 09 08:02:32 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-615df5d0-839a-4f50-863c-84d81112ccf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818929482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.1818929482 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.3771459835 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1399584427 ps |
| CPU time | 53.19 seconds |
| Started | Jul 09 07:37:14 PM PDT 24 |
| Finished | Jul 09 07:38:09 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-0b57d6d5-985f-4885-95e6-db4a82bbf0d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771459835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.3771459835 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.793576465 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 59528264 ps |
| CPU time | 7.75 seconds |
| Started | Jul 09 07:37:13 PM PDT 24 |
| Finished | Jul 09 07:37:22 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-7d130eef-ed72-4422-a726-1e21cc9d0d55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793576465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.793576465 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.3404983248 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 2550821923 ps |
| CPU time | 99.04 seconds |
| Started | Jul 09 07:37:14 PM PDT 24 |
| Finished | Jul 09 07:38:54 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-5fb70540-513e-4b9c-9eb9-1b622a2bbefa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404983248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.3404983248 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.2114137530 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 86772783947 ps |
| CPU time | 925.9 seconds |
| Started | Jul 09 07:37:18 PM PDT 24 |
| Finished | Jul 09 07:52:45 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-49a4258a-3c4e-4e42-a0a9-62daf91ff6f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114137530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.2114137530 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.2029934716 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 24869078066 ps |
| CPU time | 411.68 seconds |
| Started | Jul 09 07:37:16 PM PDT 24 |
| Finished | Jul 09 07:44:09 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-52180555-8ac5-495b-b64a-4cbf6b279826 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029934716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.2029934716 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.249073834 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 181249911 ps |
| CPU time | 17.87 seconds |
| Started | Jul 09 07:37:15 PM PDT 24 |
| Finished | Jul 09 07:37:35 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-1ec8e0b5-3d2d-46f3-9f67-4625cc49c4a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249073834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_dela ys.249073834 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.1020931901 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 2258454351 ps |
| CPU time | 75.64 seconds |
| Started | Jul 09 07:37:16 PM PDT 24 |
| Finished | Jul 09 07:38:33 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-88e82da8-f0b6-42ea-a161-0f3bfc3203b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020931901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.1020931901 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.2160898252 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 163972913 ps |
| CPU time | 7.58 seconds |
| Started | Jul 09 07:37:15 PM PDT 24 |
| Finished | Jul 09 07:37:24 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-c3e67c04-6908-4810-8b95-204bcd189b4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160898252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.2160898252 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.3322882579 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 9009655432 ps |
| CPU time | 91.16 seconds |
| Started | Jul 09 07:37:18 PM PDT 24 |
| Finished | Jul 09 07:38:51 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-4e5caf65-29ff-4720-91a9-4821fdf9f9fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322882579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.3322882579 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.4052055011 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 4603222020 ps |
| CPU time | 77.63 seconds |
| Started | Jul 09 07:37:17 PM PDT 24 |
| Finished | Jul 09 07:38:36 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-ed2e0e35-78b1-4cea-9539-566834282deb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052055011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.4052055011 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.100273003 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 39939238 ps |
| CPU time | 5.95 seconds |
| Started | Jul 09 07:37:18 PM PDT 24 |
| Finished | Jul 09 07:37:26 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-0d085bda-87e5-461e-b2b4-8f888b645d05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100273003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delays .100273003 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.1237026444 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 9051224990 ps |
| CPU time | 329.11 seconds |
| Started | Jul 09 07:37:15 PM PDT 24 |
| Finished | Jul 09 07:42:46 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-6932b581-3a79-4799-b491-c638baff30ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237026444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.1237026444 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.3081074838 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 7950429086 ps |
| CPU time | 271.23 seconds |
| Started | Jul 09 07:37:23 PM PDT 24 |
| Finished | Jul 09 07:41:57 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-b5fed130-c232-4855-ac77-853511953e90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081074838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.3081074838 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.238489285 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 9432046316 ps |
| CPU time | 418.72 seconds |
| Started | Jul 09 07:37:21 PM PDT 24 |
| Finished | Jul 09 07:44:23 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-0f77e0d7-1e47-4bc6-ab8b-deb84c4ab7dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238489285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_ with_rand_reset.238489285 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.1640529407 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 9342501 ps |
| CPU time | 7.64 seconds |
| Started | Jul 09 07:37:21 PM PDT 24 |
| Finished | Jul 09 07:37:33 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-f65e19e4-4c51-42d6-883a-d791ea6579be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640529407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.1640529407 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.3225829549 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1375619004 ps |
| CPU time | 58.18 seconds |
| Started | Jul 09 07:37:16 PM PDT 24 |
| Finished | Jul 09 07:38:16 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-cad840c7-54e2-4b4d-bbd4-44e62e667fd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225829549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.3225829549 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.1344430306 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 1003076169 ps |
| CPU time | 39.92 seconds |
| Started | Jul 09 07:37:22 PM PDT 24 |
| Finished | Jul 09 07:38:05 PM PDT 24 |
| Peak memory | 576464 kb |
| Host | smart-98d7a635-7904-4571-9ec2-48e5c7662685 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344430306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .1344430306 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.650553643 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 63722108328 ps |
| CPU time | 1160.85 seconds |
| Started | Jul 09 07:37:20 PM PDT 24 |
| Finished | Jul 09 07:56:44 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-a66f5063-67c4-40f0-af38-424699abff03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650553643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_d evice_slow_rsp.650553643 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.4101711295 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 453860611 ps |
| CPU time | 20.25 seconds |
| Started | Jul 09 07:37:30 PM PDT 24 |
| Finished | Jul 09 07:37:53 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-18bcf62a-f0c1-4ce4-bf9e-eea01a741ad4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101711295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.4101711295 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.3259372166 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 183296801 ps |
| CPU time | 16.58 seconds |
| Started | Jul 09 07:37:22 PM PDT 24 |
| Finished | Jul 09 07:37:42 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-5af4b50b-489e-4fdd-a7a0-21576027388c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259372166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.3259372166 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.4248630017 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 488952264 ps |
| CPU time | 19.94 seconds |
| Started | Jul 09 07:37:21 PM PDT 24 |
| Finished | Jul 09 07:37:45 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-8d275b54-46ee-488b-a0e8-423283cf7660 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248630017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.4248630017 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.1451054853 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 67308604485 ps |
| CPU time | 712.12 seconds |
| Started | Jul 09 07:37:22 PM PDT 24 |
| Finished | Jul 09 07:49:18 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-86b2b64f-80fa-4aff-9e7e-20d6480d4892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451054853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.1451054853 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.3446052726 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 55266043847 ps |
| CPU time | 972.8 seconds |
| Started | Jul 09 07:37:21 PM PDT 24 |
| Finished | Jul 09 07:53:37 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-cd1b67ea-e487-4d9a-977c-413a24edcdfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446052726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.3446052726 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.2060088016 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 563306042 ps |
| CPU time | 45.77 seconds |
| Started | Jul 09 07:37:21 PM PDT 24 |
| Finished | Jul 09 07:38:10 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-ffc64651-de02-4923-adfe-1c6d845cdf59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060088016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.2060088016 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.3119301126 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 324947757 ps |
| CPU time | 12.1 seconds |
| Started | Jul 09 07:37:21 PM PDT 24 |
| Finished | Jul 09 07:37:36 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-21056223-6ed8-4db2-b5af-771ae80df177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119301126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.3119301126 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.4180254886 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 47683583 ps |
| CPU time | 6.6 seconds |
| Started | Jul 09 07:37:20 PM PDT 24 |
| Finished | Jul 09 07:37:29 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-2db466f2-b1ee-482a-84a9-c0675a92b7b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180254886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.4180254886 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.1034012042 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 10589169348 ps |
| CPU time | 116.96 seconds |
| Started | Jul 09 07:37:21 PM PDT 24 |
| Finished | Jul 09 07:39:22 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-e286c40f-1e76-4721-9ef9-28fbcf2ede5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034012042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.1034012042 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.3594896362 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 4701545526 ps |
| CPU time | 78.66 seconds |
| Started | Jul 09 07:37:23 PM PDT 24 |
| Finished | Jul 09 07:38:45 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-77a9870b-ecdd-425f-bc8b-a9e3b10ec64b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594896362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.3594896362 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.831743233 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 48354946 ps |
| CPU time | 6.7 seconds |
| Started | Jul 09 07:37:21 PM PDT 24 |
| Finished | Jul 09 07:37:30 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-bdca0d14-bdba-4049-9715-5fe7309fae6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831743233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delays .831743233 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.4281969398 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 10963538754 ps |
| CPU time | 371.97 seconds |
| Started | Jul 09 07:37:30 PM PDT 24 |
| Finished | Jul 09 07:43:44 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-6b469145-587d-4ca6-a48d-b9f8c99892db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281969398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.4281969398 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.3263141289 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 422840473 ps |
| CPU time | 214.81 seconds |
| Started | Jul 09 07:37:30 PM PDT 24 |
| Finished | Jul 09 07:41:07 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-ac53f42d-0136-4b11-ba00-dfda990d05f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263141289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.3263141289 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.301846825 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 3178905090 ps |
| CPU time | 162.52 seconds |
| Started | Jul 09 07:37:30 PM PDT 24 |
| Finished | Jul 09 07:40:15 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-8d342287-0cdb-48ce-8c7c-899560ca5db8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301846825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_reset_error.301846825 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.2358602693 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 268743163 ps |
| CPU time | 28.99 seconds |
| Started | Jul 09 07:37:20 PM PDT 24 |
| Finished | Jul 09 07:37:50 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-7990bb88-9a86-4c6c-b123-76ba7447d675 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358602693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.2358602693 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.3369273159 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 195518048 ps |
| CPU time | 19.3 seconds |
| Started | Jul 09 07:37:39 PM PDT 24 |
| Finished | Jul 09 07:38:01 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-9be87b9e-bb75-419a-ba02-2dc45e6f11a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369273159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .3369273159 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1236115283 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 133942710148 ps |
| CPU time | 2481.93 seconds |
| Started | Jul 09 07:37:39 PM PDT 24 |
| Finished | Jul 09 08:19:02 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-0046c44f-62b5-4142-8d8f-41c8048bf7c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236115283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.1236115283 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.4078905621 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 748924765 ps |
| CPU time | 31.08 seconds |
| Started | Jul 09 07:37:39 PM PDT 24 |
| Finished | Jul 09 07:38:11 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-6ef1240d-37e9-4fed-a11f-311dd836f15c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078905621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.4078905621 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.1466564733 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 58616417 ps |
| CPU time | 7.8 seconds |
| Started | Jul 09 07:37:38 PM PDT 24 |
| Finished | Jul 09 07:37:46 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-81812aad-0d2e-47a6-881d-ccbac66d668c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466564733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.1466564733 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.2211611464 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1627452251 ps |
| CPU time | 59.31 seconds |
| Started | Jul 09 07:37:30 PM PDT 24 |
| Finished | Jul 09 07:38:31 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-99d56206-5786-4403-ae31-111c60f55337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211611464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.2211611464 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.1662152310 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 71000589267 ps |
| CPU time | 752.58 seconds |
| Started | Jul 09 07:37:29 PM PDT 24 |
| Finished | Jul 09 07:50:04 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-60d28b40-eed8-4123-ba73-e22be321d31a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662152310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.1662152310 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.278324316 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 31319385825 ps |
| CPU time | 517.84 seconds |
| Started | Jul 09 07:37:43 PM PDT 24 |
| Finished | Jul 09 07:46:22 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-2f9e01e0-ed80-4ce9-92c4-06d681b01863 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278324316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.278324316 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.2080195086 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 373870805 ps |
| CPU time | 35.22 seconds |
| Started | Jul 09 07:37:29 PM PDT 24 |
| Finished | Jul 09 07:38:07 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-2255e7cb-8d7a-4573-8805-e9c4ce655a99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080195086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.2080195086 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.3662672082 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 49103599 ps |
| CPU time | 6.26 seconds |
| Started | Jul 09 07:37:39 PM PDT 24 |
| Finished | Jul 09 07:37:46 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-98f7f934-00e4-498e-bbb3-19899d3f0dd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662672082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.3662672082 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.1112428956 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 183706760 ps |
| CPU time | 8.66 seconds |
| Started | Jul 09 07:37:30 PM PDT 24 |
| Finished | Jul 09 07:37:41 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-850cdfdc-8089-4475-8a2e-d27496c8543b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112428956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.1112428956 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.2746907375 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 9489255261 ps |
| CPU time | 100.26 seconds |
| Started | Jul 09 07:37:30 PM PDT 24 |
| Finished | Jul 09 07:39:12 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-c7d6ef4c-0432-4f55-b1a3-8ac2424b8e96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746907375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.2746907375 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.4250498445 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 4716907753 ps |
| CPU time | 75.26 seconds |
| Started | Jul 09 07:37:31 PM PDT 24 |
| Finished | Jul 09 07:38:49 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-ca07e6cc-db8b-43ee-9cf0-68c855f4ba5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250498445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.4250498445 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1390254014 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 53810322 ps |
| CPU time | 6.47 seconds |
| Started | Jul 09 07:37:31 PM PDT 24 |
| Finished | Jul 09 07:37:39 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-4f168b69-591f-4d20-9d4b-4b7928c4ec40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390254014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.1390254014 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1455802700 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 8770108218 ps |
| CPU time | 499.05 seconds |
| Started | Jul 09 07:37:37 PM PDT 24 |
| Finished | Jul 09 07:45:58 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-fd2c103c-4908-4bb0-b609-98a75ffeba47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455802700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.1455802700 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1035420959 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 281503795 ps |
| CPU time | 90.09 seconds |
| Started | Jul 09 07:37:43 PM PDT 24 |
| Finished | Jul 09 07:39:14 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-89ff7610-4efd-4e9a-a563-4f07b1219f6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035420959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.1035420959 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.2813929868 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 1295370566 ps |
| CPU time | 53.65 seconds |
| Started | Jul 09 07:37:39 PM PDT 24 |
| Finished | Jul 09 07:38:34 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-7793e3bd-07a7-4b9f-bcb1-bc011a7d9934 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813929868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.2813929868 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.1758152171 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 343553445 ps |
| CPU time | 27.02 seconds |
| Started | Jul 09 07:37:46 PM PDT 24 |
| Finished | Jul 09 07:38:15 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-1dc98d8b-f060-47fa-8a1c-21cb50f3ee50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758152171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .1758152171 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.3967972133 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 138341984616 ps |
| CPU time | 2351.85 seconds |
| Started | Jul 09 07:37:46 PM PDT 24 |
| Finished | Jul 09 08:16:59 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-e58b7050-12a9-4392-8595-bc45b9b49032 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967972133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.3967972133 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.3815923365 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 148510537 ps |
| CPU time | 19.36 seconds |
| Started | Jul 09 07:37:46 PM PDT 24 |
| Finished | Jul 09 07:38:07 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-87b33c4e-40be-4505-a834-d91495e847cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815923365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.3815923365 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.3431053270 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 613957608 ps |
| CPU time | 49.23 seconds |
| Started | Jul 09 07:37:44 PM PDT 24 |
| Finished | Jul 09 07:38:35 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-922b2fab-7cd8-4954-a45a-c88f0fc1387a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431053270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.3431053270 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.3598198938 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 2524768660 ps |
| CPU time | 83.03 seconds |
| Started | Jul 09 07:37:43 PM PDT 24 |
| Finished | Jul 09 07:39:07 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-dbf14cd0-288e-4d16-bb6c-916c9d9a6ec3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598198938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.3598198938 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.3004229923 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 80731859850 ps |
| CPU time | 910.31 seconds |
| Started | Jul 09 07:37:39 PM PDT 24 |
| Finished | Jul 09 07:52:50 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-4b3f0fba-887a-4901-924d-94924747ea80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004229923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.3004229923 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.4056908200 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 61909365347 ps |
| CPU time | 1249.53 seconds |
| Started | Jul 09 07:37:45 PM PDT 24 |
| Finished | Jul 09 07:58:36 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-833a18f0-ccd8-441c-93f2-874e59e91fd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056908200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.4056908200 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.1925193818 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 254814864 ps |
| CPU time | 21.94 seconds |
| Started | Jul 09 07:37:39 PM PDT 24 |
| Finished | Jul 09 07:38:03 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-78f7e0b0-918e-4038-b28e-c6df0cb4e219 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925193818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.1925193818 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.1018547294 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 185975115 ps |
| CPU time | 15.43 seconds |
| Started | Jul 09 07:37:49 PM PDT 24 |
| Finished | Jul 09 07:38:06 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-a174fd1a-e1a2-4793-bea9-3f60696adab7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018547294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.1018547294 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.2100663489 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 256662899 ps |
| CPU time | 10.3 seconds |
| Started | Jul 09 07:37:37 PM PDT 24 |
| Finished | Jul 09 07:37:48 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-c8fca86e-8130-4da6-a792-4db7a8615e63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100663489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.2100663489 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.1275341147 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 6359807012 ps |
| CPU time | 67.75 seconds |
| Started | Jul 09 07:37:39 PM PDT 24 |
| Finished | Jul 09 07:38:48 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-0fd63c7d-3960-4f8d-bd95-c0e7ed4c4641 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275341147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.1275341147 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.2967352088 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 5751318386 ps |
| CPU time | 97.07 seconds |
| Started | Jul 09 07:37:37 PM PDT 24 |
| Finished | Jul 09 07:39:15 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-12dec22b-840d-47d7-9dc4-10f75d9aedca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967352088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.2967352088 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.2930178801 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 48294285 ps |
| CPU time | 6.4 seconds |
| Started | Jul 09 07:37:39 PM PDT 24 |
| Finished | Jul 09 07:37:47 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-3c0d7036-4022-4a50-b089-dc207d250c66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930178801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.2930178801 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.2650097137 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 14713244699 ps |
| CPU time | 589.02 seconds |
| Started | Jul 09 07:37:49 PM PDT 24 |
| Finished | Jul 09 07:47:38 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-67be31e9-2ae0-4f1b-ad24-8ab673aab811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650097137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.2650097137 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2451680142 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 676816705 ps |
| CPU time | 70.39 seconds |
| Started | Jul 09 07:37:49 PM PDT 24 |
| Finished | Jul 09 07:39:00 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-4cfd5ded-5808-4de2-94a8-e49e5a897659 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451680142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.2451680142 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.456472293 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 4305168035 ps |
| CPU time | 210.34 seconds |
| Started | Jul 09 07:37:46 PM PDT 24 |
| Finished | Jul 09 07:41:19 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-3dde7c75-922a-41af-b05f-5d8bccd14372 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456472293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_ with_rand_reset.456472293 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.1966089126 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 3495533459 ps |
| CPU time | 211.55 seconds |
| Started | Jul 09 07:37:46 PM PDT 24 |
| Finished | Jul 09 07:41:19 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-9ce9475b-7fb4-435d-be7a-f53ff89ba7f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966089126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.1966089126 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.2729608674 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 890666082 ps |
| CPU time | 41.11 seconds |
| Started | Jul 09 07:37:47 PM PDT 24 |
| Finished | Jul 09 07:38:30 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-9895541b-9dab-4edc-a1d4-8a1e5ced230a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729608674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.2729608674 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.2638366385 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 1081664795 ps |
| CPU time | 77.7 seconds |
| Started | Jul 09 07:37:52 PM PDT 24 |
| Finished | Jul 09 07:39:12 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-7f2d651b-d32d-460a-b915-10687f2ae58c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638366385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .2638366385 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.2602372819 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 121327750048 ps |
| CPU time | 2237.68 seconds |
| Started | Jul 09 07:37:52 PM PDT 24 |
| Finished | Jul 09 08:15:12 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-d123fb4d-dad8-473c-9f3a-d7eca802d767 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602372819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.2602372819 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.2688951281 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 258706454 ps |
| CPU time | 28.5 seconds |
| Started | Jul 09 07:37:52 PM PDT 24 |
| Finished | Jul 09 07:38:22 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-7541cff3-88df-4f42-acd8-093f54052b36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688951281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.2688951281 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.3497869513 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 459169740 ps |
| CPU time | 30.79 seconds |
| Started | Jul 09 07:37:55 PM PDT 24 |
| Finished | Jul 09 07:38:27 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-e9d0ff10-af74-4343-b95f-0d82f7ef869a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497869513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.3497869513 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.3571058825 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 896608203 ps |
| CPU time | 35.37 seconds |
| Started | Jul 09 07:37:51 PM PDT 24 |
| Finished | Jul 09 07:38:28 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-5991333d-33a4-464c-ae3c-c0f34c8c37ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571058825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.3571058825 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.3655000225 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 102705773346 ps |
| CPU time | 1255.26 seconds |
| Started | Jul 09 07:37:53 PM PDT 24 |
| Finished | Jul 09 07:58:50 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-64d7d23a-4598-4877-a0d6-dfbb150fe72f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655000225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.3655000225 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.191838543 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 17237719507 ps |
| CPU time | 304.49 seconds |
| Started | Jul 09 07:37:53 PM PDT 24 |
| Finished | Jul 09 07:43:00 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-9187df17-a518-4e02-9fde-0251a07e14ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191838543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.191838543 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.31254807 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 274078842 ps |
| CPU time | 23.21 seconds |
| Started | Jul 09 07:37:53 PM PDT 24 |
| Finished | Jul 09 07:38:18 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-6427d5ae-5171-43c3-8757-01595fce7460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31254807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_delay s.31254807 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.678133280 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 515423153 ps |
| CPU time | 16.63 seconds |
| Started | Jul 09 07:37:51 PM PDT 24 |
| Finished | Jul 09 07:38:09 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-7f36b1f9-7c9c-47d5-9711-745411a249cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678133280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.678133280 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.3745687822 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 146775707 ps |
| CPU time | 8.14 seconds |
| Started | Jul 09 07:37:46 PM PDT 24 |
| Finished | Jul 09 07:37:56 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-5f3690a2-6f8e-4a3b-b330-fdfb45356051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745687822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.3745687822 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.263008491 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 6236917241 ps |
| CPU time | 64.16 seconds |
| Started | Jul 09 07:37:58 PM PDT 24 |
| Finished | Jul 09 07:39:03 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-3ef5b570-b4f4-4b17-a911-b31d75685d22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263008491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.263008491 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.249939383 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 4539436614 ps |
| CPU time | 72.84 seconds |
| Started | Jul 09 07:37:52 PM PDT 24 |
| Finished | Jul 09 07:39:07 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-756344a7-1ba2-4853-8e32-ae560241a06b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249939383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.249939383 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3928719522 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 54336014 ps |
| CPU time | 6.72 seconds |
| Started | Jul 09 07:37:44 PM PDT 24 |
| Finished | Jul 09 07:37:52 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-64b95dd7-2ca7-493a-be40-191f99f8687b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928719522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.3928719522 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.2422392427 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 2875754499 ps |
| CPU time | 124.64 seconds |
| Started | Jul 09 07:37:52 PM PDT 24 |
| Finished | Jul 09 07:39:59 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-28193023-8bfd-4a01-b99a-0c7563883bc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422392427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.2422392427 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.1515408004 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 1549847487 ps |
| CPU time | 110.57 seconds |
| Started | Jul 09 07:37:52 PM PDT 24 |
| Finished | Jul 09 07:39:44 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-931a05f5-0f7f-4734-b983-ba35cb9a8991 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515408004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.1515408004 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.763580064 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 1544500084 ps |
| CPU time | 196.85 seconds |
| Started | Jul 09 07:37:54 PM PDT 24 |
| Finished | Jul 09 07:41:12 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-3add2999-196c-4343-95aa-e5b86a186023 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763580064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_ with_rand_reset.763580064 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.962056580 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 7160200240 ps |
| CPU time | 360.12 seconds |
| Started | Jul 09 07:37:52 PM PDT 24 |
| Finished | Jul 09 07:43:54 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-f8d80c04-2f6f-451f-82fa-3aa5e633cc09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962056580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_reset_error.962056580 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.1067550345 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 288090911 ps |
| CPU time | 32.79 seconds |
| Started | Jul 09 07:37:52 PM PDT 24 |
| Finished | Jul 09 07:38:26 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-79f517c4-3f7c-4996-ba75-dac99219adca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067550345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.1067550345 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.2282109470 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 758814456 ps |
| CPU time | 52.04 seconds |
| Started | Jul 09 07:38:03 PM PDT 24 |
| Finished | Jul 09 07:38:57 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-d24cf4e3-ffbf-46f7-91e4-fff4f4ffa152 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282109470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device .2282109470 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3941207745 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 108365396 ps |
| CPU time | 14.47 seconds |
| Started | Jul 09 07:38:06 PM PDT 24 |
| Finished | Jul 09 07:38:22 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-72b265c7-ec74-4bcb-a257-544a976b0bba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941207745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.3941207745 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.3294927226 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 200052251 ps |
| CPU time | 18.68 seconds |
| Started | Jul 09 07:38:01 PM PDT 24 |
| Finished | Jul 09 07:38:21 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-326b3987-fcf0-4ff8-9d75-8b5e038682db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294927226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.3294927226 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.184409117 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 343310040 ps |
| CPU time | 32.95 seconds |
| Started | Jul 09 07:37:59 PM PDT 24 |
| Finished | Jul 09 07:38:33 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-0e411390-80f2-40e2-9a0b-3602840db82b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184409117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.184409117 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.3857677119 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 3455638613 ps |
| CPU time | 36.68 seconds |
| Started | Jul 09 07:37:51 PM PDT 24 |
| Finished | Jul 09 07:38:29 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-c6899c68-0c33-43bb-9923-325f115a8554 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857677119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.3857677119 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.2566939232 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 63456740218 ps |
| CPU time | 1194.02 seconds |
| Started | Jul 09 07:38:03 PM PDT 24 |
| Finished | Jul 09 07:57:58 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-b6a69322-7ac4-468d-9cb4-5e26670c4409 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566939232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.2566939232 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.1790821579 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 281842170 ps |
| CPU time | 27.24 seconds |
| Started | Jul 09 07:37:53 PM PDT 24 |
| Finished | Jul 09 07:38:22 PM PDT 24 |
| Peak memory | 576484 kb |
| Host | smart-9fe47ee6-fc7e-4736-a690-e11c7d8c1207 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790821579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.1790821579 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.1797488213 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 501855089 ps |
| CPU time | 17.58 seconds |
| Started | Jul 09 07:38:07 PM PDT 24 |
| Finished | Jul 09 07:38:26 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-3b14bba5-be31-4254-801b-9c6f42832703 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797488213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.1797488213 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.678899981 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 221552246 ps |
| CPU time | 8.53 seconds |
| Started | Jul 09 07:37:56 PM PDT 24 |
| Finished | Jul 09 07:38:05 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-c2630610-bd0d-47c4-8df1-a76a0bd78cef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678899981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.678899981 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.3286447279 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 9283454719 ps |
| CPU time | 99.78 seconds |
| Started | Jul 09 07:37:58 PM PDT 24 |
| Finished | Jul 09 07:39:39 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-7e6b88d4-5fcc-449b-8232-8073bf088a81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286447279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.3286447279 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.3480443059 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 4654098969 ps |
| CPU time | 80 seconds |
| Started | Jul 09 07:37:55 PM PDT 24 |
| Finished | Jul 09 07:39:16 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-e94b9008-d819-434a-8444-2d459e481f18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480443059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.3480443059 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.1016003499 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 41848021 ps |
| CPU time | 6.38 seconds |
| Started | Jul 09 07:37:52 PM PDT 24 |
| Finished | Jul 09 07:38:00 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-e6af8ab3-d318-4d1f-b45b-3ae9a7e573ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016003499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.1016003499 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.3915558173 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 3374507081 ps |
| CPU time | 124.95 seconds |
| Started | Jul 09 07:38:01 PM PDT 24 |
| Finished | Jul 09 07:40:07 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-79a78c77-dbba-4fb4-977e-4bc5e7c1ff69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915558173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.3915558173 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.3978830746 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 2647943134 ps |
| CPU time | 99.7 seconds |
| Started | Jul 09 07:38:04 PM PDT 24 |
| Finished | Jul 09 07:39:45 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-fa45ff7d-d8c2-488c-a2bd-710fdfa884ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978830746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.3978830746 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.550425761 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 276505982 ps |
| CPU time | 87.11 seconds |
| Started | Jul 09 07:38:00 PM PDT 24 |
| Finished | Jul 09 07:39:28 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-0e874ec7-ad28-4e69-9742-f146ad1f5624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550425761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_ with_rand_reset.550425761 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2310609752 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 2302023000 ps |
| CPU time | 162.16 seconds |
| Started | Jul 09 07:38:07 PM PDT 24 |
| Finished | Jul 09 07:40:50 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-eec11558-2608-45c9-a065-d126f117f27e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310609752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.2310609752 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.603339374 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 314617589 ps |
| CPU time | 38.74 seconds |
| Started | Jul 09 07:38:03 PM PDT 24 |
| Finished | Jul 09 07:38:44 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-5108704e-43ad-4972-aa7a-8a7ae8970ab0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603339374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.603339374 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.3425075371 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 831823963 ps |
| CPU time | 63.21 seconds |
| Started | Jul 09 07:38:15 PM PDT 24 |
| Finished | Jul 09 07:39:21 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-841d6d04-0227-4377-80ab-5c02312a78f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425075371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .3425075371 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3865589592 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 8619255885 ps |
| CPU time | 161.15 seconds |
| Started | Jul 09 07:38:18 PM PDT 24 |
| Finished | Jul 09 07:41:01 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-1fd0d0a1-ca45-4c64-a54a-26157b2f9a3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865589592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.3865589592 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.3683256153 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 227789508 ps |
| CPU time | 24.17 seconds |
| Started | Jul 09 07:38:15 PM PDT 24 |
| Finished | Jul 09 07:38:42 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-48848c60-1f29-4a0a-a5b2-88aa2da51c37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683256153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.3683256153 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.3922039038 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 154297589 ps |
| CPU time | 7.27 seconds |
| Started | Jul 09 07:38:15 PM PDT 24 |
| Finished | Jul 09 07:38:25 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-0c8c83bb-f8f9-41a9-beff-dba78968e524 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922039038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.3922039038 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.3861968600 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 1673169662 ps |
| CPU time | 54.88 seconds |
| Started | Jul 09 07:38:07 PM PDT 24 |
| Finished | Jul 09 07:39:03 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-6cd05ab5-9e8d-4f2d-8ce2-cbfc85e6143c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861968600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.3861968600 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.2841626415 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 34803823923 ps |
| CPU time | 373.38 seconds |
| Started | Jul 09 07:38:16 PM PDT 24 |
| Finished | Jul 09 07:44:32 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-f4753c3e-a790-4176-936e-ad6d40957c02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841626415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.2841626415 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.1830938540 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 60147394755 ps |
| CPU time | 1027.07 seconds |
| Started | Jul 09 07:38:18 PM PDT 24 |
| Finished | Jul 09 07:55:27 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-e4cc82b2-a2e3-4604-a6ba-ef26ec91ca31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830938540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.1830938540 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.1178485538 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 161204965 ps |
| CPU time | 16.09 seconds |
| Started | Jul 09 07:38:18 PM PDT 24 |
| Finished | Jul 09 07:38:36 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-e5d45ad2-de31-4dbf-8140-1618514d3198 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178485538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.1178485538 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.3001062996 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 680493394 ps |
| CPU time | 21.05 seconds |
| Started | Jul 09 07:38:17 PM PDT 24 |
| Finished | Jul 09 07:38:41 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-4a76657f-386c-480c-aff6-0e07ab94cfba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001062996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.3001062996 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.428398687 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 51287867 ps |
| CPU time | 7.01 seconds |
| Started | Jul 09 07:38:01 PM PDT 24 |
| Finished | Jul 09 07:38:09 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-66e3cd7c-27fb-4293-ae49-928fa26cb7b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428398687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.428398687 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.671058378 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 5679540573 ps |
| CPU time | 61.37 seconds |
| Started | Jul 09 07:38:08 PM PDT 24 |
| Finished | Jul 09 07:39:10 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-55c5a576-b2ef-4547-a90e-3b526c2ebce8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671058378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.671058378 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.745578290 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 5859635288 ps |
| CPU time | 95.37 seconds |
| Started | Jul 09 07:38:07 PM PDT 24 |
| Finished | Jul 09 07:39:44 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-1db2e3fe-b2fb-44b1-94ff-1047e6525503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745578290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.745578290 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.4003313170 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 52904920 ps |
| CPU time | 6.9 seconds |
| Started | Jul 09 07:38:07 PM PDT 24 |
| Finished | Jul 09 07:38:16 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-341c79bf-7f64-4ddf-a729-1bbb2316d1f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003313170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delay s.4003313170 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.24897398 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 11134513798 ps |
| CPU time | 448.64 seconds |
| Started | Jul 09 07:38:15 PM PDT 24 |
| Finished | Jul 09 07:45:47 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-dce10171-c611-4e5c-8754-fd5255a2a8df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24897398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.24897398 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.2997710059 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 3167933836 ps |
| CPU time | 237.64 seconds |
| Started | Jul 09 07:38:17 PM PDT 24 |
| Finished | Jul 09 07:42:17 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-7c03c33e-e477-4450-8cf5-9dd15ca89c14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997710059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.2997710059 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.894242441 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 5458756359 ps |
| CPU time | 424.59 seconds |
| Started | Jul 09 07:38:16 PM PDT 24 |
| Finished | Jul 09 07:45:24 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-c2f4d37a-bfc9-4931-a317-0afd980607bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894242441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_ with_rand_reset.894242441 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2599650442 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 365470685 ps |
| CPU time | 49.05 seconds |
| Started | Jul 09 07:38:17 PM PDT 24 |
| Finished | Jul 09 07:39:09 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-435d323b-1167-451e-be18-63c4bc461e99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599650442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.2599650442 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.153857946 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 157293590 ps |
| CPU time | 18.79 seconds |
| Started | Jul 09 07:38:15 PM PDT 24 |
| Finished | Jul 09 07:38:37 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-fa742b18-7f8e-4f1e-a95b-a43bbd8a7be4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153857946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.153857946 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.344755068 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 310302727 ps |
| CPU time | 28.86 seconds |
| Started | Jul 09 07:38:26 PM PDT 24 |
| Finished | Jul 09 07:38:59 PM PDT 24 |
| Peak memory | 576444 kb |
| Host | smart-9b5c476f-32c8-47b2-bad1-71e13266141a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344755068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device. 344755068 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.2048552264 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 124015904883 ps |
| CPU time | 2277.36 seconds |
| Started | Jul 09 07:38:27 PM PDT 24 |
| Finished | Jul 09 08:16:28 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-ed8b3275-d1ee-4e9c-a065-2c6e6aabee9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048552264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.2048552264 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3551776150 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 730491333 ps |
| CPU time | 28.99 seconds |
| Started | Jul 09 07:38:22 PM PDT 24 |
| Finished | Jul 09 07:38:55 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-d6e4290a-4804-4c10-87f0-ac5a9a79f939 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551776150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.3551776150 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.3621557166 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 274679959 ps |
| CPU time | 11.21 seconds |
| Started | Jul 09 07:38:23 PM PDT 24 |
| Finished | Jul 09 07:38:38 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-83283e44-e68c-4a9f-bba1-0601ebf1d38b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621557166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.3621557166 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.967710045 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 2069747419 ps |
| CPU time | 66.88 seconds |
| Started | Jul 09 07:38:23 PM PDT 24 |
| Finished | Jul 09 07:39:34 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-0886cae3-239b-4024-a2c4-f386d648302c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967710045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.967710045 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.3632651050 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 16752042111 ps |
| CPU time | 171.58 seconds |
| Started | Jul 09 07:38:24 PM PDT 24 |
| Finished | Jul 09 07:41:19 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-7a361c21-4373-4e87-8832-fe03c7733596 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632651050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.3632651050 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.2560279621 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 15485926873 ps |
| CPU time | 259.32 seconds |
| Started | Jul 09 07:38:22 PM PDT 24 |
| Finished | Jul 09 07:42:44 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-a12868da-5d6b-42f7-b512-91803bc1b6f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560279621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.2560279621 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.1442710843 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 176160665 ps |
| CPU time | 18.66 seconds |
| Started | Jul 09 07:38:23 PM PDT 24 |
| Finished | Jul 09 07:38:45 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-6aec3221-0c4c-4cd8-b48e-ecf32574c98c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442710843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.1442710843 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.1567554534 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2082472347 ps |
| CPU time | 62.02 seconds |
| Started | Jul 09 07:38:23 PM PDT 24 |
| Finished | Jul 09 07:39:29 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-5702c15f-7b46-4e31-beb4-effd3ae4d0cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567554534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.1567554534 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.3545837481 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 189358394 ps |
| CPU time | 8.62 seconds |
| Started | Jul 09 07:38:17 PM PDT 24 |
| Finished | Jul 09 07:38:29 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-7d53101a-b39c-4642-9183-88ab97a5782e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545837481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.3545837481 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.2957610638 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 6457109114 ps |
| CPU time | 66.18 seconds |
| Started | Jul 09 07:38:22 PM PDT 24 |
| Finished | Jul 09 07:39:32 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-87cafa43-7ca0-4d4d-885f-47569ecb60e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957610638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.2957610638 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.3343805426 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 4484640504 ps |
| CPU time | 72.94 seconds |
| Started | Jul 09 07:38:22 PM PDT 24 |
| Finished | Jul 09 07:39:38 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-1fa49f5d-008a-416d-82ea-d3bab321a416 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343805426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.3343805426 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.1738609130 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 62721915 ps |
| CPU time | 6.92 seconds |
| Started | Jul 09 07:38:19 PM PDT 24 |
| Finished | Jul 09 07:38:28 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-d5137d6b-21fc-425a-a7b1-7c05fa2b8af4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738609130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.1738609130 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.883003276 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 12448019003 ps |
| CPU time | 435.82 seconds |
| Started | Jul 09 07:38:22 PM PDT 24 |
| Finished | Jul 09 07:45:42 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-e7f9a348-eeef-4a4e-9994-c91f29691f16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883003276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.883003276 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.3157784636 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 169648695 ps |
| CPU time | 16.59 seconds |
| Started | Jul 09 07:38:26 PM PDT 24 |
| Finished | Jul 09 07:38:47 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-33654427-6a1f-4109-82d8-00a34278a495 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157784636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.3157784636 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.3042810246 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 61792134 ps |
| CPU time | 18.74 seconds |
| Started | Jul 09 07:38:23 PM PDT 24 |
| Finished | Jul 09 07:38:46 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-93c73a48-9a28-4246-bb99-1abf940f3281 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042810246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.3042810246 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.4289495515 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 441780354 ps |
| CPU time | 85.86 seconds |
| Started | Jul 09 07:38:27 PM PDT 24 |
| Finished | Jul 09 07:39:56 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-bb31bb74-8389-463e-94e2-b6f0ad960abd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289495515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.4289495515 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.436963033 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 113940046 ps |
| CPU time | 7.61 seconds |
| Started | Jul 09 07:38:22 PM PDT 24 |
| Finished | Jul 09 07:38:33 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-cbe65f01-20dd-4dc2-911d-0999cec3db11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436963033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.436963033 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.3069867390 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 2832892789 ps |
| CPU time | 112.2 seconds |
| Started | Jul 09 07:38:30 PM PDT 24 |
| Finished | Jul 09 07:40:24 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-0d0de75d-d4bd-4204-b6da-07d11a106fb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069867390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .3069867390 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2468970383 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 30277356663 ps |
| CPU time | 534.91 seconds |
| Started | Jul 09 07:38:30 PM PDT 24 |
| Finished | Jul 09 07:47:27 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-78fb0196-7d07-4b7e-9ae1-989237a81e61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468970383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.2468970383 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3217302210 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 67680761 ps |
| CPU time | 6.28 seconds |
| Started | Jul 09 07:38:32 PM PDT 24 |
| Finished | Jul 09 07:38:40 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-950b8f28-be57-460e-8717-14a9f36561bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217302210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.3217302210 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.2775094234 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 911962777 ps |
| CPU time | 32.08 seconds |
| Started | Jul 09 07:38:33 PM PDT 24 |
| Finished | Jul 09 07:39:07 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-7dc7638e-1825-4bf4-a8fd-b0b3a108da71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775094234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.2775094234 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.2091993388 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 300604146 ps |
| CPU time | 26.09 seconds |
| Started | Jul 09 07:38:22 PM PDT 24 |
| Finished | Jul 09 07:38:52 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-8c4a8399-3411-48af-a3d1-36a6d7dda9b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091993388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.2091993388 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.2862238643 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 103811858417 ps |
| CPU time | 1222.12 seconds |
| Started | Jul 09 07:38:31 PM PDT 24 |
| Finished | Jul 09 07:58:55 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-5c57df59-b7d9-403f-8702-29aa2ceb5c26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862238643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.2862238643 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.3603925341 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 17348744795 ps |
| CPU time | 294.79 seconds |
| Started | Jul 09 07:38:32 PM PDT 24 |
| Finished | Jul 09 07:43:29 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-6a62f231-fb9c-4ae4-9c17-21b81c7c8287 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603925341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.3603925341 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.3723115764 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 513292173 ps |
| CPU time | 45.47 seconds |
| Started | Jul 09 07:38:25 PM PDT 24 |
| Finished | Jul 09 07:39:14 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-a8532aac-159e-4686-a4ef-9cb1549abce0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723115764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.3723115764 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.2938579617 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 2613995120 ps |
| CPU time | 77.64 seconds |
| Started | Jul 09 07:38:31 PM PDT 24 |
| Finished | Jul 09 07:39:50 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-de8dee32-005f-4d12-bf66-75f2611605ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938579617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.2938579617 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.3756609531 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 195921632 ps |
| CPU time | 8.5 seconds |
| Started | Jul 09 07:38:24 PM PDT 24 |
| Finished | Jul 09 07:38:36 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-5c770514-0d57-4b62-b0d0-c7a645f29a67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756609531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.3756609531 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.1013800400 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 7800306737 ps |
| CPU time | 79.88 seconds |
| Started | Jul 09 07:38:24 PM PDT 24 |
| Finished | Jul 09 07:39:47 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-05f760cd-a7b3-48df-91b0-bf81ed33afb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013800400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.1013800400 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.3121753274 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 5072314280 ps |
| CPU time | 87.39 seconds |
| Started | Jul 09 07:38:24 PM PDT 24 |
| Finished | Jul 09 07:39:56 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-681931d9-4b25-4dd1-aee4-b0c86083fe28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121753274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.3121753274 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.3155737604 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 44547777 ps |
| CPU time | 5.99 seconds |
| Started | Jul 09 07:38:24 PM PDT 24 |
| Finished | Jul 09 07:38:33 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-42c80426-cd66-49c0-8b1f-c0ef337cc238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155737604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.3155737604 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.867468740 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 3149710433 ps |
| CPU time | 96.14 seconds |
| Started | Jul 09 07:38:32 PM PDT 24 |
| Finished | Jul 09 07:40:10 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-0822b4db-d74f-40a0-b5dc-e5dcccdb5ccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867468740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.867468740 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.3344924006 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 723544476 ps |
| CPU time | 231.56 seconds |
| Started | Jul 09 07:38:32 PM PDT 24 |
| Finished | Jul 09 07:42:25 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-4ff5da16-02a3-497e-bada-151bb892d62f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344924006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.3344924006 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.3179034380 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 188535868 ps |
| CPU time | 40.14 seconds |
| Started | Jul 09 07:38:32 PM PDT 24 |
| Finished | Jul 09 07:39:14 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-9fc74bbc-ddb0-4387-b49d-4201d921e7f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179034380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.3179034380 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.586736393 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 1125842970 ps |
| CPU time | 47.79 seconds |
| Started | Jul 09 07:38:32 PM PDT 24 |
| Finished | Jul 09 07:39:21 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-90346e02-6656-4c56-bd46-b05e91877d5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586736393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.586736393 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.714737792 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 109835296 ps |
| CPU time | 11.55 seconds |
| Started | Jul 09 07:38:41 PM PDT 24 |
| Finished | Jul 09 07:38:55 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-20de1585-a0da-4eae-b27e-c20bd36353f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714737792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device. 714737792 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.1907384467 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 101861972434 ps |
| CPU time | 1838.68 seconds |
| Started | Jul 09 07:38:39 PM PDT 24 |
| Finished | Jul 09 08:09:20 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-01c8be6c-c913-4ef6-a36b-91c0427aaaa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907384467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.1907384467 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.979082339 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 1075130445 ps |
| CPU time | 38.62 seconds |
| Started | Jul 09 07:38:40 PM PDT 24 |
| Finished | Jul 09 07:39:20 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-03ee7625-d38c-4b70-9e69-a4119d27f874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979082339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_addr .979082339 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.2763774902 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1334383867 ps |
| CPU time | 52.12 seconds |
| Started | Jul 09 07:38:38 PM PDT 24 |
| Finished | Jul 09 07:39:31 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-224cc4b9-b916-44b5-9d5e-cd87512aa557 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763774902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.2763774902 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.948677532 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 2308297397 ps |
| CPU time | 91.97 seconds |
| Started | Jul 09 07:38:39 PM PDT 24 |
| Finished | Jul 09 07:40:12 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-5b589b3d-1946-47c5-8416-173f0f9b420b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948677532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.948677532 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.763035560 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 12020644523 ps |
| CPU time | 132.34 seconds |
| Started | Jul 09 07:38:40 PM PDT 24 |
| Finished | Jul 09 07:40:54 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-45338266-9ae4-44a8-a2ee-cbdacf54384f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763035560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.763035560 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.1462987539 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 7611977948 ps |
| CPU time | 131.6 seconds |
| Started | Jul 09 07:38:38 PM PDT 24 |
| Finished | Jul 09 07:40:51 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-025bf0c5-5534-4e50-a821-744ad0ed8859 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462987539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.1462987539 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.237373924 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 217713896 ps |
| CPU time | 22.95 seconds |
| Started | Jul 09 07:38:38 PM PDT 24 |
| Finished | Jul 09 07:39:01 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-2862e972-e295-48da-9b2a-4f30d420cca1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237373924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_dela ys.237373924 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.3039333096 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 540144966 ps |
| CPU time | 40.35 seconds |
| Started | Jul 09 07:38:41 PM PDT 24 |
| Finished | Jul 09 07:39:24 PM PDT 24 |
| Peak memory | 576456 kb |
| Host | smart-9145d683-4f3b-4461-90d6-697576471ff4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039333096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.3039333096 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.1997458373 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 221362390 ps |
| CPU time | 9.46 seconds |
| Started | Jul 09 07:38:33 PM PDT 24 |
| Finished | Jul 09 07:38:44 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-25861899-9587-44d9-8dbe-eac400342471 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997458373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.1997458373 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.3128632196 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 7605079876 ps |
| CPU time | 82.97 seconds |
| Started | Jul 09 07:38:41 PM PDT 24 |
| Finished | Jul 09 07:40:06 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-2f038c4e-62e0-482d-9de2-dc92fa862566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128632196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.3128632196 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.955449130 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 5700977335 ps |
| CPU time | 98.58 seconds |
| Started | Jul 09 07:38:39 PM PDT 24 |
| Finished | Jul 09 07:40:20 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-0bc4022b-8420-4e91-a778-b50f84a2e40b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955449130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.955449130 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.3478223553 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 54785841 ps |
| CPU time | 6.82 seconds |
| Started | Jul 09 07:38:39 PM PDT 24 |
| Finished | Jul 09 07:38:47 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-21700864-fb9d-4062-a7e2-434be95a336a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478223553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.3478223553 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.3178012557 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 5926486 ps |
| CPU time | 3.84 seconds |
| Started | Jul 09 07:38:42 PM PDT 24 |
| Finished | Jul 09 07:38:48 PM PDT 24 |
| Peak memory | 565232 kb |
| Host | smart-046099da-95a4-4901-9548-dc5b3f646afd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178012557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.3178012557 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.1471911882 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 6670770484 ps |
| CPU time | 205.51 seconds |
| Started | Jul 09 07:38:41 PM PDT 24 |
| Finished | Jul 09 07:42:08 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-a81265b4-40e2-4207-b927-4830e1fc52c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471911882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.1471911882 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1843225715 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 8335190090 ps |
| CPU time | 430.98 seconds |
| Started | Jul 09 07:38:42 PM PDT 24 |
| Finished | Jul 09 07:45:55 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-2749de4b-1d29-4c4c-951f-146b0515a06c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843225715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.1843225715 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.1749709610 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 5193399767 ps |
| CPU time | 252.45 seconds |
| Started | Jul 09 07:38:38 PM PDT 24 |
| Finished | Jul 09 07:42:52 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-9d4b1bd8-3566-4a37-8d2a-ec5c70403be4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749709610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.1749709610 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.2352923608 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 104321630 ps |
| CPU time | 13.6 seconds |
| Started | Jul 09 07:38:41 PM PDT 24 |
| Finished | Jul 09 07:38:57 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-873195f8-834d-4b7b-b93f-756bd8c61ae9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352923608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.2352923608 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.523489542 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 5507489808 ps |
| CPU time | 506.98 seconds |
| Started | Jul 09 07:25:48 PM PDT 24 |
| Finished | Jul 09 07:34:33 PM PDT 24 |
| Peak memory | 599664 kb |
| Host | smart-7d7335f8-52a6-45fd-89b0-3749580ba19b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523489542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.523489542 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.2356605735 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 1619435980 ps |
| CPU time | 72.56 seconds |
| Started | Jul 09 07:25:45 PM PDT 24 |
| Finished | Jul 09 07:27:14 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-201816ee-5b52-480f-927d-c8d82ab094dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356605735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 2356605735 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.913486581 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 29371228781 ps |
| CPU time | 477.14 seconds |
| Started | Jul 09 07:25:53 PM PDT 24 |
| Finished | Jul 09 07:34:10 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-d7787484-9079-468d-93b3-15fa0c34567d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913486581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_de vice_slow_rsp.913486581 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.534938880 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 445579103 ps |
| CPU time | 17.19 seconds |
| Started | Jul 09 07:25:45 PM PDT 24 |
| Finished | Jul 09 07:26:19 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-94cf726e-7c62-4309-91f7-a319049ee075 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534938880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr. 534938880 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.2475374327 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 533333898 ps |
| CPU time | 37.76 seconds |
| Started | Jul 09 07:25:49 PM PDT 24 |
| Finished | Jul 09 07:26:44 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-d699e570-9dfc-409b-af6a-4e398b35fe86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475374327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2475374327 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.1306351535 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 1435734061 ps |
| CPU time | 50.95 seconds |
| Started | Jul 09 07:25:51 PM PDT 24 |
| Finished | Jul 09 07:27:00 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-9819732f-7b98-4235-9d08-e24e1401cf7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306351535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.1306351535 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.596407072 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 98659341077 ps |
| CPU time | 1122.18 seconds |
| Started | Jul 09 07:25:46 PM PDT 24 |
| Finished | Jul 09 07:44:47 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-11db65a7-f96a-40c0-8ab3-16be6700c89f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596407072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.596407072 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.2511063933 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 21763920358 ps |
| CPU time | 389.5 seconds |
| Started | Jul 09 07:25:50 PM PDT 24 |
| Finished | Jul 09 07:32:38 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-5c62f111-eadc-458b-a9dc-c915a93a8ce1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511063933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2511063933 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.2548407181 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 26496211 ps |
| CPU time | 5.37 seconds |
| Started | Jul 09 07:25:45 PM PDT 24 |
| Finished | Jul 09 07:26:07 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-056acc0a-def6-4dcf-89a4-44fbf10f9a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548407181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.2548407181 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.3225664462 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 1882085529 ps |
| CPU time | 54.08 seconds |
| Started | Jul 09 07:25:53 PM PDT 24 |
| Finished | Jul 09 07:27:07 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-1a69a45e-45c2-4ccc-a557-fce9eda20bdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225664462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3225664462 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.1317464072 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 242758566 ps |
| CPU time | 10.66 seconds |
| Started | Jul 09 07:25:44 PM PDT 24 |
| Finished | Jul 09 07:26:11 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-923b0c7d-c99d-4e0b-87f7-278f2a64d580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317464072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1317464072 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.3615309044 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 6662453960 ps |
| CPU time | 65.88 seconds |
| Started | Jul 09 07:25:49 PM PDT 24 |
| Finished | Jul 09 07:27:12 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-e02b79b3-7cd2-424a-83a8-480d71046964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615309044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3615309044 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.1956313520 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 5365450868 ps |
| CPU time | 86.74 seconds |
| Started | Jul 09 07:25:45 PM PDT 24 |
| Finished | Jul 09 07:27:28 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-9b8c0a4d-d407-40b1-9971-5093193faeb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956313520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1956313520 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3259333387 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 41640427 ps |
| CPU time | 6.24 seconds |
| Started | Jul 09 07:25:48 PM PDT 24 |
| Finished | Jul 09 07:26:12 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-6ea88ff0-c664-432d-84f1-6abcc042b32e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259333387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .3259333387 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.787573421 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1259571431 ps |
| CPU time | 120.6 seconds |
| Started | Jul 09 07:25:48 PM PDT 24 |
| Finished | Jul 09 07:28:06 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-32dcc7b1-3263-4f7f-a8e7-e77372a4feed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787573421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.787573421 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.1091204647 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 16431781690 ps |
| CPU time | 626.03 seconds |
| Started | Jul 09 07:25:45 PM PDT 24 |
| Finished | Jul 09 07:36:28 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-b4a45838-2468-44e3-82bd-deee6a05626f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091204647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1091204647 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1785238546 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 302298159 ps |
| CPU time | 127.65 seconds |
| Started | Jul 09 07:25:45 PM PDT 24 |
| Finished | Jul 09 07:28:09 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-98f198b5-28ac-44ab-afcc-8b429b28581f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785238546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.1785238546 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.2365385745 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 754565176 ps |
| CPU time | 214.17 seconds |
| Started | Jul 09 07:25:45 PM PDT 24 |
| Finished | Jul 09 07:29:35 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-86c80cac-91a4-4f3c-a275-a001199131f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365385745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.2365385745 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.862516890 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 210917571 ps |
| CPU time | 11.38 seconds |
| Started | Jul 09 07:25:43 PM PDT 24 |
| Finished | Jul 09 07:26:09 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-c4bfe447-919d-40f0-b54c-c7efaa545587 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862516890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.862516890 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.13466757 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 2248130963 ps |
| CPU time | 103.41 seconds |
| Started | Jul 09 07:38:44 PM PDT 24 |
| Finished | Jul 09 07:40:29 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-c7076515-4394-41e8-919b-1a2a3579e21f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13466757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device.13466757 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.406727561 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 64635614191 ps |
| CPU time | 1085.06 seconds |
| Started | Jul 09 07:38:46 PM PDT 24 |
| Finished | Jul 09 07:56:53 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-7790083d-c9ef-45f6-b2b0-7001aeffa620 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406727561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_d evice_slow_rsp.406727561 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.824487893 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 945081420 ps |
| CPU time | 35.76 seconds |
| Started | Jul 09 07:38:50 PM PDT 24 |
| Finished | Jul 09 07:39:26 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-20f7cc2b-3fde-43fc-9f9f-f9e4306eb260 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824487893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr .824487893 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.3619438993 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 710383601 ps |
| CPU time | 28.27 seconds |
| Started | Jul 09 07:38:46 PM PDT 24 |
| Finished | Jul 09 07:39:16 PM PDT 24 |
| Peak memory | 576504 kb |
| Host | smart-7c88437a-5eec-4b3a-b2e0-d99d0b178b0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619438993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.3619438993 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.2715217999 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 69514186 ps |
| CPU time | 8.81 seconds |
| Started | Jul 09 07:38:45 PM PDT 24 |
| Finished | Jul 09 07:38:56 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-e7fe2773-0da4-49e7-8ee6-cc435ab44107 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715217999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.2715217999 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.2182792354 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 104529636538 ps |
| CPU time | 1093.5 seconds |
| Started | Jul 09 07:38:44 PM PDT 24 |
| Finished | Jul 09 07:57:00 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-7a17c6fc-65f8-4b7b-ba59-4f074d9e3073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182792354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.2182792354 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.1008320714 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 63104598625 ps |
| CPU time | 1245.1 seconds |
| Started | Jul 09 07:38:50 PM PDT 24 |
| Finished | Jul 09 07:59:36 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-c5677eba-7e33-4a72-906b-2c3a238296c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008320714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.1008320714 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.4130255854 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 237919903 ps |
| CPU time | 25 seconds |
| Started | Jul 09 07:38:49 PM PDT 24 |
| Finished | Jul 09 07:39:15 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-85ca1524-40fe-4e22-b437-2c50bc81ea30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130255854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.4130255854 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.3136167370 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 120043603 ps |
| CPU time | 12.65 seconds |
| Started | Jul 09 07:38:46 PM PDT 24 |
| Finished | Jul 09 07:39:00 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-5d3b15aa-5788-41b1-8c3b-278ccf12a24c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136167370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.3136167370 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.1815664391 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 209692371 ps |
| CPU time | 8.77 seconds |
| Started | Jul 09 07:38:47 PM PDT 24 |
| Finished | Jul 09 07:38:57 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-9112e5ca-3931-40da-b0e2-17273208bf23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815664391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.1815664391 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.1299548278 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 8093442768 ps |
| CPU time | 82.68 seconds |
| Started | Jul 09 07:38:45 PM PDT 24 |
| Finished | Jul 09 07:40:09 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-ba26a560-f91e-4058-9d7f-eb7b40f3a39e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299548278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.1299548278 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.1406208191 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 6971394832 ps |
| CPU time | 114.34 seconds |
| Started | Jul 09 07:38:45 PM PDT 24 |
| Finished | Jul 09 07:40:41 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-c5473cf4-6f4f-497f-8513-81c765fda617 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406208191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.1406208191 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.1663619552 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 53003630 ps |
| CPU time | 6.48 seconds |
| Started | Jul 09 07:38:48 PM PDT 24 |
| Finished | Jul 09 07:38:55 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-8b2e7490-7d6d-4540-a29f-3f2bd6a5f637 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663619552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.1663619552 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.1902665991 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 3048433685 ps |
| CPU time | 237.73 seconds |
| Started | Jul 09 07:38:54 PM PDT 24 |
| Finished | Jul 09 07:42:53 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-3267dfe4-6a0d-4423-bd1c-89733b7974b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902665991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.1902665991 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.3927090062 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 3840774756 ps |
| CPU time | 127.7 seconds |
| Started | Jul 09 07:38:52 PM PDT 24 |
| Finished | Jul 09 07:41:01 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-872da2cd-8961-4636-bcf3-e7774876e265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927090062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.3927090062 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2092338968 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 2592203651 ps |
| CPU time | 100.69 seconds |
| Started | Jul 09 07:38:52 PM PDT 24 |
| Finished | Jul 09 07:40:34 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-9a0ff011-e529-4317-920a-5084b5163930 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092338968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.2092338968 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.239393077 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 148171003 ps |
| CPU time | 35.16 seconds |
| Started | Jul 09 07:38:52 PM PDT 24 |
| Finished | Jul 09 07:39:28 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-7449791c-6e99-423c-81de-236720d9fe69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239393077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_reset_error.239393077 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.1257899752 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 268961763 ps |
| CPU time | 13.64 seconds |
| Started | Jul 09 07:38:46 PM PDT 24 |
| Finished | Jul 09 07:39:01 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-dd6fc87d-8405-4e34-860c-0cba96bfb526 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257899752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.1257899752 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.1416401664 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 2044162470 ps |
| CPU time | 101.14 seconds |
| Started | Jul 09 07:38:52 PM PDT 24 |
| Finished | Jul 09 07:40:35 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-3bb87ec6-641c-4ff5-a4ec-bc6d724e53e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416401664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .1416401664 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.2607803222 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 50748022387 ps |
| CPU time | 923.54 seconds |
| Started | Jul 09 07:38:51 PM PDT 24 |
| Finished | Jul 09 07:54:16 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-ad3f6b35-6d67-4e86-871d-cb23ee419988 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607803222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.2607803222 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1092280506 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 839861656 ps |
| CPU time | 34.21 seconds |
| Started | Jul 09 07:39:00 PM PDT 24 |
| Finished | Jul 09 07:39:35 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-5b80e4d8-0369-451f-9f2f-24ddb850fef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092280506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.1092280506 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.848592213 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 305334250 ps |
| CPU time | 14.16 seconds |
| Started | Jul 09 07:38:51 PM PDT 24 |
| Finished | Jul 09 07:39:06 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-d5a1ee72-946f-4f7e-8374-9da2f041e3c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848592213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.848592213 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.3520185973 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 424412475 ps |
| CPU time | 36.83 seconds |
| Started | Jul 09 07:38:55 PM PDT 24 |
| Finished | Jul 09 07:39:32 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-49103346-5b15-458f-9a6d-6a9bf56e9042 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520185973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.3520185973 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.3090228627 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 37638804963 ps |
| CPU time | 398.45 seconds |
| Started | Jul 09 07:38:52 PM PDT 24 |
| Finished | Jul 09 07:45:31 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-3de1a2f9-3998-4e7b-bb3c-6c025814d388 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090228627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.3090228627 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.1460086370 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 46112795179 ps |
| CPU time | 866.66 seconds |
| Started | Jul 09 07:38:52 PM PDT 24 |
| Finished | Jul 09 07:53:21 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-147b95fd-5f30-473a-9a46-9cc26202613f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460086370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.1460086370 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.3213130537 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 471906722 ps |
| CPU time | 39.21 seconds |
| Started | Jul 09 07:38:55 PM PDT 24 |
| Finished | Jul 09 07:39:35 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-c1f26c5c-3c88-4e8a-ab2c-b75aa09017fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213130537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.3213130537 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.2690215695 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 1236457162 ps |
| CPU time | 39.22 seconds |
| Started | Jul 09 07:38:53 PM PDT 24 |
| Finished | Jul 09 07:39:33 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-da4be02b-de91-432c-8d13-76c47602ed9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690215695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.2690215695 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.2392605699 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 44628169 ps |
| CPU time | 5.73 seconds |
| Started | Jul 09 07:38:51 PM PDT 24 |
| Finished | Jul 09 07:38:58 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-aa8edfda-5ada-4b68-bf1d-62eeb2693cce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392605699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.2392605699 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.791921481 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 4414287175 ps |
| CPU time | 45.8 seconds |
| Started | Jul 09 07:38:54 PM PDT 24 |
| Finished | Jul 09 07:39:41 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-b74550c8-cb08-4991-aae7-71091e643069 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791921481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.791921481 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.808985270 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 5556737017 ps |
| CPU time | 93.63 seconds |
| Started | Jul 09 07:38:53 PM PDT 24 |
| Finished | Jul 09 07:40:28 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-a0a78dc4-3833-44e6-a6b8-976ee0e55b10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808985270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.808985270 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.2013182869 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 51032669 ps |
| CPU time | 6.99 seconds |
| Started | Jul 09 07:38:52 PM PDT 24 |
| Finished | Jul 09 07:39:01 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-4b80a9d1-00b9-408a-b167-6934d42a4fc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013182869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.2013182869 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.2783414830 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 1926747123 ps |
| CPU time | 58.36 seconds |
| Started | Jul 09 07:39:03 PM PDT 24 |
| Finished | Jul 09 07:40:02 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-1e438f8f-90eb-46bc-bd92-42194235a68b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783414830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.2783414830 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.3238711900 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 2235456228 ps |
| CPU time | 176.68 seconds |
| Started | Jul 09 07:38:59 PM PDT 24 |
| Finished | Jul 09 07:41:57 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-647d83ea-f0ff-424b-b203-8fdc60980775 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238711900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.3238711900 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.601354700 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 799138651 ps |
| CPU time | 368.7 seconds |
| Started | Jul 09 07:38:58 PM PDT 24 |
| Finished | Jul 09 07:45:07 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-a2934441-16b1-443b-b2ff-8bff745ed20e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601354700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_ with_rand_reset.601354700 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.2287604924 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 3022756971 ps |
| CPU time | 277.53 seconds |
| Started | Jul 09 07:39:00 PM PDT 24 |
| Finished | Jul 09 07:43:39 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-73614cdc-f9fe-47eb-9bb8-34caa3d8a9e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287604924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.2287604924 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.4109883497 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 1248688736 ps |
| CPU time | 52.62 seconds |
| Started | Jul 09 07:38:59 PM PDT 24 |
| Finished | Jul 09 07:39:53 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-9bfa01d8-d333-4b37-8bed-f88fd235f95d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109883497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.4109883497 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.3647355913 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 2218865420 ps |
| CPU time | 103.87 seconds |
| Started | Jul 09 07:39:11 PM PDT 24 |
| Finished | Jul 09 07:40:56 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-00e160cc-8726-41cd-b8c1-42f05a213cb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647355913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .3647355913 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1403272128 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 37224512117 ps |
| CPU time | 686 seconds |
| Started | Jul 09 07:39:07 PM PDT 24 |
| Finished | Jul 09 07:50:35 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-ccefe97e-20ad-4ea1-9ebb-8f7495bc1e06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403272128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.1403272128 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2153244367 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 792630972 ps |
| CPU time | 34.62 seconds |
| Started | Jul 09 07:39:08 PM PDT 24 |
| Finished | Jul 09 07:39:43 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-89222714-731e-42b8-a682-dae5dd5de795 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153244367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.2153244367 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.3619701203 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 1773328894 ps |
| CPU time | 64.82 seconds |
| Started | Jul 09 07:39:09 PM PDT 24 |
| Finished | Jul 09 07:40:15 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-d9b420ec-f286-4e22-9d31-6e4c4431ecac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619701203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.3619701203 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.2145399772 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 880994036 ps |
| CPU time | 29.14 seconds |
| Started | Jul 09 07:39:08 PM PDT 24 |
| Finished | Jul 09 07:39:38 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-c33b2f08-9adc-4786-8cc9-21f752b838f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145399772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.2145399772 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.706757609 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 15299614162 ps |
| CPU time | 161.35 seconds |
| Started | Jul 09 07:39:08 PM PDT 24 |
| Finished | Jul 09 07:41:50 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-d3f0b668-8d0b-4ff9-8b8b-8d66ebf1cef1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706757609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.706757609 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.2040957385 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 12079952356 ps |
| CPU time | 220.02 seconds |
| Started | Jul 09 07:39:07 PM PDT 24 |
| Finished | Jul 09 07:42:48 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-d2fc7e16-103f-4f5f-90c8-84edb6f3461c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040957385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.2040957385 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.3981456752 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 336216110 ps |
| CPU time | 33.28 seconds |
| Started | Jul 09 07:39:08 PM PDT 24 |
| Finished | Jul 09 07:39:43 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-3310cde6-02da-4245-8ed4-52853a034f49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981456752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.3981456752 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.1014189416 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 1425353010 ps |
| CPU time | 40.29 seconds |
| Started | Jul 09 07:39:07 PM PDT 24 |
| Finished | Jul 09 07:39:48 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-74ca4585-1d0c-437a-b195-27ccb264a10e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014189416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.1014189416 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.3751154592 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 125766877 ps |
| CPU time | 7.07 seconds |
| Started | Jul 09 07:39:00 PM PDT 24 |
| Finished | Jul 09 07:39:08 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-054e7eea-16b1-474e-807f-9f27ae862def |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751154592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.3751154592 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.62868713 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 9626816162 ps |
| CPU time | 101.4 seconds |
| Started | Jul 09 07:39:08 PM PDT 24 |
| Finished | Jul 09 07:40:51 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-599c9330-b097-4327-8261-dc22e7756037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62868713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.62868713 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.3803218217 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 5716755759 ps |
| CPU time | 96.48 seconds |
| Started | Jul 09 07:39:08 PM PDT 24 |
| Finished | Jul 09 07:40:45 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-30a4e326-ce33-4bdd-8582-3ad89176fd85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803218217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.3803218217 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.4005248971 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 57871514 ps |
| CPU time | 7.18 seconds |
| Started | Jul 09 07:39:00 PM PDT 24 |
| Finished | Jul 09 07:39:08 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-fd513fac-c49c-429f-8605-6beb1a96921c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005248971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay s.4005248971 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.2890251127 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 14586177998 ps |
| CPU time | 549.83 seconds |
| Started | Jul 09 07:39:11 PM PDT 24 |
| Finished | Jul 09 07:48:22 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-4ced1b91-7c49-411a-ab1c-f2c66caa96cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890251127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.2890251127 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.2263838318 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 6346253968 ps |
| CPU time | 218.62 seconds |
| Started | Jul 09 07:39:16 PM PDT 24 |
| Finished | Jul 09 07:42:55 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-b2ee2fe9-ecc8-4762-9167-c19d179af712 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263838318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.2263838318 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.1759915523 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 14388014600 ps |
| CPU time | 849.13 seconds |
| Started | Jul 09 07:39:14 PM PDT 24 |
| Finished | Jul 09 07:53:24 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-da38f0f4-27a9-40a2-ae91-61b936068d69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759915523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.1759915523 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3038846321 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 2629049488 ps |
| CPU time | 216.56 seconds |
| Started | Jul 09 07:39:17 PM PDT 24 |
| Finished | Jul 09 07:42:54 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-27eeb469-54b2-47d7-a7ff-fc10edb98e00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038846321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.3038846321 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.169877832 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 1108050484 ps |
| CPU time | 49 seconds |
| Started | Jul 09 07:39:05 PM PDT 24 |
| Finished | Jul 09 07:39:55 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-cc04b230-b640-49e4-b621-7b1836239798 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169877832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.169877832 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.418200778 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 1927181528 ps |
| CPU time | 91.73 seconds |
| Started | Jul 09 07:39:18 PM PDT 24 |
| Finished | Jul 09 07:40:50 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-3297f68f-1152-4020-897b-3e182cec224a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418200778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device. 418200778 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.81568877 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 21296834970 ps |
| CPU time | 364.65 seconds |
| Started | Jul 09 07:39:14 PM PDT 24 |
| Finished | Jul 09 07:45:19 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-d674e0fc-0c2b-4b4d-ac6d-983c09179545 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81568877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_de vice_slow_rsp.81568877 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.2988829551 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 250910842 ps |
| CPU time | 29 seconds |
| Started | Jul 09 07:39:22 PM PDT 24 |
| Finished | Jul 09 07:39:52 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-c545cc4d-9e23-40ee-b316-5a6fe032763e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988829551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.2988829551 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.1420768848 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 455486985 ps |
| CPU time | 40.3 seconds |
| Started | Jul 09 07:39:22 PM PDT 24 |
| Finished | Jul 09 07:40:03 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-83b89853-a56f-437e-a7eb-fce29f7b271b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420768848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.1420768848 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.1872398164 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 461735121 ps |
| CPU time | 39.37 seconds |
| Started | Jul 09 07:39:17 PM PDT 24 |
| Finished | Jul 09 07:39:58 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-caaa8964-5a90-4934-abb9-883f97ad7dfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872398164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.1872398164 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.3854247174 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 105057119554 ps |
| CPU time | 1158.19 seconds |
| Started | Jul 09 07:39:16 PM PDT 24 |
| Finished | Jul 09 07:58:35 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-d64f511f-e88d-429d-b5c9-17f6576aab9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854247174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.3854247174 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.75906839 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 38927736674 ps |
| CPU time | 663.65 seconds |
| Started | Jul 09 07:39:17 PM PDT 24 |
| Finished | Jul 09 07:50:22 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-aeb9fc48-02e0-44be-8609-0082d4ebb18a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75906839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.75906839 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.40623565 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 546042785 ps |
| CPU time | 45.35 seconds |
| Started | Jul 09 07:39:14 PM PDT 24 |
| Finished | Jul 09 07:40:00 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-bd8ee743-7229-4db4-adf5-e6a1a5da4f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40623565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_delay s.40623565 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.279620813 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 1823443413 ps |
| CPU time | 54.28 seconds |
| Started | Jul 09 07:39:25 PM PDT 24 |
| Finished | Jul 09 07:40:20 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-6ff5aaeb-f7ac-4b56-bb83-af206a49593b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279620813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.279620813 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.2788970363 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 128718866 ps |
| CPU time | 6.92 seconds |
| Started | Jul 09 07:39:16 PM PDT 24 |
| Finished | Jul 09 07:39:24 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-4e6289d4-2bd2-4c31-8e07-a2e1854d81da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788970363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.2788970363 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.1354432283 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 8137344235 ps |
| CPU time | 89.05 seconds |
| Started | Jul 09 07:39:15 PM PDT 24 |
| Finished | Jul 09 07:40:45 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-9afbd39d-a482-49c8-889a-81481d1a62ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354432283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.1354432283 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.2900191662 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 5258668566 ps |
| CPU time | 87.31 seconds |
| Started | Jul 09 07:39:22 PM PDT 24 |
| Finished | Jul 09 07:40:51 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-6fec9c15-6fdb-4b3b-91d0-ef6987e22aab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900191662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.2900191662 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.1186933849 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 50234424 ps |
| CPU time | 6.25 seconds |
| Started | Jul 09 07:39:16 PM PDT 24 |
| Finished | Jul 09 07:39:23 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-87f0af1f-efb6-42be-878b-2660c1e681b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186933849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.1186933849 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.1555545387 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 18073661902 ps |
| CPU time | 706.61 seconds |
| Started | Jul 09 07:39:22 PM PDT 24 |
| Finished | Jul 09 07:51:10 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-7b30bce0-6649-4111-90d5-e342f6de24c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555545387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.1555545387 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.1845306823 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 2784469382 ps |
| CPU time | 234.36 seconds |
| Started | Jul 09 07:39:22 PM PDT 24 |
| Finished | Jul 09 07:43:18 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-161a434e-fe2f-486b-a9c6-14a4375ccfce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845306823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.1845306823 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3841265773 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 598117641 ps |
| CPU time | 185.45 seconds |
| Started | Jul 09 07:39:25 PM PDT 24 |
| Finished | Jul 09 07:42:32 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-e023dc0b-8bdd-43be-b47e-877993a827a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841265773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.3841265773 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.65381224 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 2798442815 ps |
| CPU time | 293.7 seconds |
| Started | Jul 09 07:39:23 PM PDT 24 |
| Finished | Jul 09 07:44:18 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-266c3883-986a-42a9-9f9b-29faf4438baa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65381224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_ with_reset_error.65381224 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.3525267732 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 153995102 ps |
| CPU time | 18.24 seconds |
| Started | Jul 09 07:39:28 PM PDT 24 |
| Finished | Jul 09 07:39:47 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-6c9b5ef4-bbad-4890-849b-8adbd3850cbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525267732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.3525267732 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.506786605 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 616889742 ps |
| CPU time | 51.49 seconds |
| Started | Jul 09 07:39:30 PM PDT 24 |
| Finished | Jul 09 07:40:22 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-177fa5b1-3579-424d-9831-ec2b97331141 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506786605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device. 506786605 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.587852122 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 88583315267 ps |
| CPU time | 1707.66 seconds |
| Started | Jul 09 07:39:34 PM PDT 24 |
| Finished | Jul 09 08:08:03 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-66ce5658-aefc-428e-abaa-5c0eb420373c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587852122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_d evice_slow_rsp.587852122 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.3165666676 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 305560687 ps |
| CPU time | 31.25 seconds |
| Started | Jul 09 07:39:31 PM PDT 24 |
| Finished | Jul 09 07:40:03 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-32cd11ee-1de6-421d-bcb6-b97ef21858e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165666676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.3165666676 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.565106634 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 292354763 ps |
| CPU time | 12.01 seconds |
| Started | Jul 09 07:39:29 PM PDT 24 |
| Finished | Jul 09 07:39:42 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-2eae1902-5786-4157-bab4-3982ed1df67f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565106634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.565106634 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.1818722248 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 592002808 ps |
| CPU time | 24.27 seconds |
| Started | Jul 09 07:39:23 PM PDT 24 |
| Finished | Jul 09 07:39:48 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-97cfd2eb-44bc-4775-b88a-2d56f22f4ed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818722248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.1818722248 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.1472335858 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 48227551838 ps |
| CPU time | 523.88 seconds |
| Started | Jul 09 07:39:21 PM PDT 24 |
| Finished | Jul 09 07:48:06 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-6ae0e868-f526-465c-b587-e368557e2971 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472335858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.1472335858 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.3592355557 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 37573051169 ps |
| CPU time | 631.08 seconds |
| Started | Jul 09 07:39:26 PM PDT 24 |
| Finished | Jul 09 07:49:58 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-d197826c-4cd7-4c75-bf37-d1691bcc6b8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592355557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.3592355557 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.4051252981 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 632587751 ps |
| CPU time | 54 seconds |
| Started | Jul 09 07:39:23 PM PDT 24 |
| Finished | Jul 09 07:40:18 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-da8432f4-f58f-454f-8d20-70e60bfea325 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051252981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.4051252981 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.987539010 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 95478329 ps |
| CPU time | 10.1 seconds |
| Started | Jul 09 07:39:31 PM PDT 24 |
| Finished | Jul 09 07:39:43 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-ecf2c4dd-52a0-43df-a0e5-777fbf2a4c1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987539010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.987539010 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.3602794588 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 193553455 ps |
| CPU time | 8.51 seconds |
| Started | Jul 09 07:39:21 PM PDT 24 |
| Finished | Jul 09 07:39:30 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-5a33d763-788e-4116-a00d-df4121fa1467 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602794588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.3602794588 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.1548469607 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 8470491261 ps |
| CPU time | 87.41 seconds |
| Started | Jul 09 07:39:26 PM PDT 24 |
| Finished | Jul 09 07:40:54 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-6e4da942-36c8-4300-a5cd-0d0638c6a435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548469607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.1548469607 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.211941572 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 4622432108 ps |
| CPU time | 76.93 seconds |
| Started | Jul 09 07:39:22 PM PDT 24 |
| Finished | Jul 09 07:40:40 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-a54ed3c3-1f8c-49c3-a7ab-73b239a1d310 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211941572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.211941572 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.4249321371 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 37608948 ps |
| CPU time | 5.72 seconds |
| Started | Jul 09 07:39:21 PM PDT 24 |
| Finished | Jul 09 07:39:27 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-1c3380c8-8d99-43a8-befe-759990d9c096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249321371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.4249321371 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.1640624772 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 3642299208 ps |
| CPU time | 137.76 seconds |
| Started | Jul 09 07:39:33 PM PDT 24 |
| Finished | Jul 09 07:41:52 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-465234b9-15f6-4148-ae46-c044abddfd66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640624772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.1640624772 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.2246523939 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 3580006460 ps |
| CPU time | 150.55 seconds |
| Started | Jul 09 07:39:31 PM PDT 24 |
| Finished | Jul 09 07:42:03 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-4b67f9eb-2018-4056-992a-ceb3dbb9b142 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246523939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.2246523939 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.1541931886 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 5881951904 ps |
| CPU time | 364.69 seconds |
| Started | Jul 09 07:39:32 PM PDT 24 |
| Finished | Jul 09 07:45:38 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-4be11e49-518d-43a2-8772-0b67a39a4800 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541931886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.1541931886 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2072837932 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 13464802745 ps |
| CPU time | 696.19 seconds |
| Started | Jul 09 07:39:33 PM PDT 24 |
| Finished | Jul 09 07:51:10 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-ad0a4120-1155-4ed9-a299-ff4f36857674 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072837932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.2072837932 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.1805886654 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 1157629848 ps |
| CPU time | 50.2 seconds |
| Started | Jul 09 07:39:33 PM PDT 24 |
| Finished | Jul 09 07:40:24 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-ede9f3ce-e352-42d5-a4d0-adf1199a61ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805886654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.1805886654 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.2962668062 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 1222382546 ps |
| CPU time | 79.89 seconds |
| Started | Jul 09 07:39:40 PM PDT 24 |
| Finished | Jul 09 07:41:01 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-94614914-20c2-41d9-a1b2-1f1de24c07c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962668062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .2962668062 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.2120153542 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 56013847075 ps |
| CPU time | 939.2 seconds |
| Started | Jul 09 07:39:37 PM PDT 24 |
| Finished | Jul 09 07:55:17 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-6f51037d-d349-4ab1-a9f6-3a2b5fcef102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120153542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.2120153542 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.658253127 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 176929203 ps |
| CPU time | 20.46 seconds |
| Started | Jul 09 07:39:41 PM PDT 24 |
| Finished | Jul 09 07:40:03 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-3770735b-1730-4db5-afa6-6fc062f8f38f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658253127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_addr .658253127 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.507428777 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 2026726307 ps |
| CPU time | 71.29 seconds |
| Started | Jul 09 07:39:42 PM PDT 24 |
| Finished | Jul 09 07:40:55 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-cb0619f3-c42c-4a17-a2f2-81ebba1bce01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507428777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.507428777 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.2643097817 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 441872860 ps |
| CPU time | 36.09 seconds |
| Started | Jul 09 07:39:31 PM PDT 24 |
| Finished | Jul 09 07:40:08 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-bcc22660-619c-412c-a298-71f82ad6f593 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643097817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.2643097817 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.1851387469 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 64723445321 ps |
| CPU time | 747.51 seconds |
| Started | Jul 09 07:39:43 PM PDT 24 |
| Finished | Jul 09 07:52:11 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-d15674a5-d6d9-488a-a3d2-04743bc0a14a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851387469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.1851387469 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.3463525608 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 29849225438 ps |
| CPU time | 485.13 seconds |
| Started | Jul 09 07:39:39 PM PDT 24 |
| Finished | Jul 09 07:47:45 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-e4633407-5581-407e-b633-bff264626add |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463525608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.3463525608 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.3126332673 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 524992563 ps |
| CPU time | 43.5 seconds |
| Started | Jul 09 07:39:40 PM PDT 24 |
| Finished | Jul 09 07:40:24 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-c369e540-1c54-4dde-93aa-a1a55c672559 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126332673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.3126332673 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.456598610 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 1551946567 ps |
| CPU time | 52.79 seconds |
| Started | Jul 09 07:39:40 PM PDT 24 |
| Finished | Jul 09 07:40:34 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-e0adc6ef-fb6e-4fca-858d-f5b9bd7f4d93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456598610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.456598610 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.3606512257 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 190562639 ps |
| CPU time | 9.11 seconds |
| Started | Jul 09 07:39:31 PM PDT 24 |
| Finished | Jul 09 07:39:41 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-bfeaeb64-fae3-4e3e-8dc4-72bc0685e590 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606512257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.3606512257 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.2299961306 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 9344598188 ps |
| CPU time | 97.59 seconds |
| Started | Jul 09 07:39:30 PM PDT 24 |
| Finished | Jul 09 07:41:09 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-8ea88810-6520-4825-9d41-4b8bf60624ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299961306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.2299961306 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.4222943087 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 5791922978 ps |
| CPU time | 94.74 seconds |
| Started | Jul 09 07:39:32 PM PDT 24 |
| Finished | Jul 09 07:41:08 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-418a05cc-1fee-4de9-9f6e-f69456b9c43b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222943087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.4222943087 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.3897840262 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 41324968 ps |
| CPU time | 5.56 seconds |
| Started | Jul 09 07:39:31 PM PDT 24 |
| Finished | Jul 09 07:39:38 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-1cc9f6d5-2290-422f-8998-d831f0191f26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897840262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.3897840262 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.1279132269 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 3325082339 ps |
| CPU time | 137.98 seconds |
| Started | Jul 09 07:39:42 PM PDT 24 |
| Finished | Jul 09 07:42:01 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-e038d555-6aaf-406e-a0b8-1bcfcbd28efa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279132269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.1279132269 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.2902964683 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 6527724156 ps |
| CPU time | 248.11 seconds |
| Started | Jul 09 07:39:47 PM PDT 24 |
| Finished | Jul 09 07:43:56 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-851dc0ac-a1f9-4da4-ab8c-2ff4f4ee64db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902964683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.2902964683 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.1316543534 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 91224406 ps |
| CPU time | 43.2 seconds |
| Started | Jul 09 07:39:36 PM PDT 24 |
| Finished | Jul 09 07:40:20 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-7d89c044-2978-4625-a788-1ea050193239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316543534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.1316543534 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.888448842 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 601046793 ps |
| CPU time | 157.65 seconds |
| Started | Jul 09 07:39:40 PM PDT 24 |
| Finished | Jul 09 07:42:19 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-43d8753d-0cbd-422f-ba7e-8d5b91c48cc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888448842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_reset_error.888448842 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.786345198 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 158508898 ps |
| CPU time | 20.55 seconds |
| Started | Jul 09 07:39:41 PM PDT 24 |
| Finished | Jul 09 07:40:03 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-4e1027b1-5838-4497-b0c5-e2f73174e434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786345198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.786345198 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.2239068669 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 423186296 ps |
| CPU time | 36.65 seconds |
| Started | Jul 09 07:39:48 PM PDT 24 |
| Finished | Jul 09 07:40:25 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-8b6804e6-6ac8-4423-be4d-071958cdb6ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239068669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .2239068669 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.2804911910 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 84780642234 ps |
| CPU time | 1451.64 seconds |
| Started | Jul 09 07:39:36 PM PDT 24 |
| Finished | Jul 09 08:03:48 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-0f9716b6-91de-4155-b7cf-ca98f0082bae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804911910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.2804911910 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.1483789997 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 912434849 ps |
| CPU time | 38.02 seconds |
| Started | Jul 09 07:39:46 PM PDT 24 |
| Finished | Jul 09 07:40:25 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-907f05ae-b678-41ca-b38d-0d38b5c18e60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483789997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.1483789997 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.1374335604 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 278835357 ps |
| CPU time | 23.83 seconds |
| Started | Jul 09 07:39:37 PM PDT 24 |
| Finished | Jul 09 07:40:02 PM PDT 24 |
| Peak memory | 576472 kb |
| Host | smart-1152084c-b220-469c-8ef2-c1d52118cd6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374335604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.1374335604 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.1349545741 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 438741538 ps |
| CPU time | 43.5 seconds |
| Started | Jul 09 07:39:38 PM PDT 24 |
| Finished | Jul 09 07:40:22 PM PDT 24 |
| Peak memory | 576484 kb |
| Host | smart-0e4568e0-dde9-46f4-8316-bcf38ccff05e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349545741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.1349545741 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.3834985841 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 115704971459 ps |
| CPU time | 1222.7 seconds |
| Started | Jul 09 07:39:40 PM PDT 24 |
| Finished | Jul 09 08:00:04 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-af3e48ff-d440-4cc1-94ac-c08c040b474e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834985841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.3834985841 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.486489494 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 29520684258 ps |
| CPU time | 511.01 seconds |
| Started | Jul 09 07:39:41 PM PDT 24 |
| Finished | Jul 09 07:48:14 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-c1927446-9f6a-4cac-b8dc-4d8d4c47cd3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486489494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.486489494 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.2396182141 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 156299021 ps |
| CPU time | 17.46 seconds |
| Started | Jul 09 07:39:47 PM PDT 24 |
| Finished | Jul 09 07:40:05 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-97b0572b-6a71-47b2-9183-7e42316ea3da |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396182141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.2396182141 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.386410165 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 570141408 ps |
| CPU time | 18.91 seconds |
| Started | Jul 09 07:39:37 PM PDT 24 |
| Finished | Jul 09 07:39:57 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-d1a7e1bf-58b0-4d65-bbf1-d130309ce15f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386410165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.386410165 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.1406174643 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 47631127 ps |
| CPU time | 6.03 seconds |
| Started | Jul 09 07:39:37 PM PDT 24 |
| Finished | Jul 09 07:39:44 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-26340b07-2458-47cd-8628-cdb695803998 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406174643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.1406174643 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.3497265899 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 7668771529 ps |
| CPU time | 81.5 seconds |
| Started | Jul 09 07:39:40 PM PDT 24 |
| Finished | Jul 09 07:41:03 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-52782f7a-812c-4e6c-8568-57d24f41256e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497265899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.3497265899 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.613401047 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 5555078577 ps |
| CPU time | 96.02 seconds |
| Started | Jul 09 07:39:39 PM PDT 24 |
| Finished | Jul 09 07:41:16 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-4e2c2359-fb68-43c0-9ab6-cfaeffdbe8a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613401047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.613401047 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.2006728414 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 45689054 ps |
| CPU time | 6.71 seconds |
| Started | Jul 09 07:39:41 PM PDT 24 |
| Finished | Jul 09 07:39:49 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-76546e65-dc9d-4f1d-b0da-c71ac6145478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006728414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.2006728414 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.1323217370 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 614870322 ps |
| CPU time | 46.06 seconds |
| Started | Jul 09 07:39:56 PM PDT 24 |
| Finished | Jul 09 07:40:43 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-0b2024ff-89a1-42de-b7f9-f01bbcad291b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323217370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.1323217370 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.963164810 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 630422459 ps |
| CPU time | 43.8 seconds |
| Started | Jul 09 07:39:57 PM PDT 24 |
| Finished | Jul 09 07:40:42 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-9545ab41-d124-4be1-b05f-53bb28c7aa9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963164810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.963164810 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2408241994 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 13242413114 ps |
| CPU time | 688.44 seconds |
| Started | Jul 09 07:39:45 PM PDT 24 |
| Finished | Jul 09 07:51:14 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-839296bd-b5b6-4fe1-8df3-f088410847ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408241994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_rand_reset.2408241994 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3360524262 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 692323633 ps |
| CPU time | 208.25 seconds |
| Started | Jul 09 07:39:47 PM PDT 24 |
| Finished | Jul 09 07:43:16 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-d1459647-fd13-4c00-b216-2fe8cf3756d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360524262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.3360524262 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.1602783889 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 191082188 ps |
| CPU time | 11.32 seconds |
| Started | Jul 09 07:39:46 PM PDT 24 |
| Finished | Jul 09 07:39:58 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-bfd15f77-d672-49f7-a9dd-54ed69620cf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602783889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.1602783889 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.229073002 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 762283370 ps |
| CPU time | 57.87 seconds |
| Started | Jul 09 07:39:58 PM PDT 24 |
| Finished | Jul 09 07:40:57 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-c922b60f-b453-4b84-b108-12454784da29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229073002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device. 229073002 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2108390116 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 114475766302 ps |
| CPU time | 2026.64 seconds |
| Started | Jul 09 07:39:54 PM PDT 24 |
| Finished | Jul 09 08:13:42 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-513a28e6-9224-46e6-8e50-1f43eff458ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108390116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.2108390116 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.455752960 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 41410619 ps |
| CPU time | 6.6 seconds |
| Started | Jul 09 07:39:55 PM PDT 24 |
| Finished | Jul 09 07:40:02 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-176eea95-c04e-4a0f-8ef6-d09c85bcd5fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455752960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr .455752960 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.771945741 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 352551997 ps |
| CPU time | 33.28 seconds |
| Started | Jul 09 07:39:44 PM PDT 24 |
| Finished | Jul 09 07:40:18 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-a1e01677-4f73-4b36-a33d-8925b90d2093 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771945741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.771945741 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.2148858386 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 45370544441 ps |
| CPU time | 501.06 seconds |
| Started | Jul 09 07:39:56 PM PDT 24 |
| Finished | Jul 09 07:48:18 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-533b0265-7980-4a6e-b00a-16e5dbdc311f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148858386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.2148858386 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.2502932410 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 21342701698 ps |
| CPU time | 366.34 seconds |
| Started | Jul 09 07:39:54 PM PDT 24 |
| Finished | Jul 09 07:46:01 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-69f73a9b-f4b4-4fd2-bd51-c0de45b8e571 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502932410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.2502932410 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.957186072 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 311122525 ps |
| CPU time | 28.77 seconds |
| Started | Jul 09 07:39:56 PM PDT 24 |
| Finished | Jul 09 07:40:25 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-6128c448-49d9-4a08-8c60-d598dfd47b48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957186072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_dela ys.957186072 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.4158221152 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 2061854221 ps |
| CPU time | 56.77 seconds |
| Started | Jul 09 07:39:55 PM PDT 24 |
| Finished | Jul 09 07:40:53 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-c608970e-ca67-4156-afd7-1a20cb210c51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158221152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.4158221152 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.2745098129 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 44952230 ps |
| CPU time | 5.92 seconds |
| Started | Jul 09 07:39:56 PM PDT 24 |
| Finished | Jul 09 07:40:03 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-4638fb34-5782-44ae-95f2-c0a891eb5fe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745098129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.2745098129 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.565287352 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 7061868170 ps |
| CPU time | 72.94 seconds |
| Started | Jul 09 07:39:56 PM PDT 24 |
| Finished | Jul 09 07:41:10 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-5f734efb-b8c6-4ac5-8551-92658820bb7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565287352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.565287352 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.598155592 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 4652098799 ps |
| CPU time | 78.97 seconds |
| Started | Jul 09 07:39:56 PM PDT 24 |
| Finished | Jul 09 07:41:16 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-d4a25c89-2987-4705-9205-8ad79707bd58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598155592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.598155592 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.1767358486 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 39039399 ps |
| CPU time | 5.96 seconds |
| Started | Jul 09 07:39:45 PM PDT 24 |
| Finished | Jul 09 07:39:52 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-8caa0c99-e70b-449b-931f-ff55d1fdcc0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767358486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.1767358486 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.955306622 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1961213260 ps |
| CPU time | 184.3 seconds |
| Started | Jul 09 07:39:56 PM PDT 24 |
| Finished | Jul 09 07:43:01 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-a2afee88-0038-4b6b-869f-b1a5261beb02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955306622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.955306622 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.3845973186 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 2292827891 ps |
| CPU time | 64.64 seconds |
| Started | Jul 09 07:39:54 PM PDT 24 |
| Finished | Jul 09 07:41:00 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-8bd11b9c-e252-4cd1-8506-72d8ebe94385 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845973186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.3845973186 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.1036401159 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 841720650 ps |
| CPU time | 239.38 seconds |
| Started | Jul 09 07:40:01 PM PDT 24 |
| Finished | Jul 09 07:44:01 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-0dfb4464-6f33-47d4-b3e6-2f35743ac6db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036401159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.1036401159 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3849902597 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 5347035522 ps |
| CPU time | 572.84 seconds |
| Started | Jul 09 07:39:55 PM PDT 24 |
| Finished | Jul 09 07:49:29 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-5f04f7aa-f3a6-4d22-8c01-c5b53bcb07c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849902597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.3849902597 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.2219522418 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 96307092 ps |
| CPU time | 14.34 seconds |
| Started | Jul 09 07:40:00 PM PDT 24 |
| Finished | Jul 09 07:40:15 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-fff4bf30-5854-41ba-9625-7721262137d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219522418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.2219522418 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.1652616133 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 725558684 ps |
| CPU time | 48.42 seconds |
| Started | Jul 09 07:40:09 PM PDT 24 |
| Finished | Jul 09 07:40:58 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-518e0427-aecf-46be-8d53-a487162437ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652616133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .1652616133 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.279459006 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 16868836707 ps |
| CPU time | 312.07 seconds |
| Started | Jul 09 07:40:06 PM PDT 24 |
| Finished | Jul 09 07:45:19 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-2b76daa8-ff37-4b21-baf8-f2305b147177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279459006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_d evice_slow_rsp.279459006 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.1647828222 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 191400914 ps |
| CPU time | 11.15 seconds |
| Started | Jul 09 07:40:04 PM PDT 24 |
| Finished | Jul 09 07:40:16 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-bdc43f8a-e8c2-4f6b-a381-5b9d52babdac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647828222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.1647828222 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.3793813556 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 254203400 ps |
| CPU time | 23.46 seconds |
| Started | Jul 09 07:40:05 PM PDT 24 |
| Finished | Jul 09 07:40:30 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-b44ab728-039f-4698-b49e-2cc2802f677c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793813556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.3793813556 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.3355995681 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 1111597356 ps |
| CPU time | 36.11 seconds |
| Started | Jul 09 07:40:08 PM PDT 24 |
| Finished | Jul 09 07:40:44 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-3254652f-d2f8-4b3d-9641-7f7ed58d378b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355995681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.3355995681 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.2252420662 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 20838750047 ps |
| CPU time | 230.67 seconds |
| Started | Jul 09 07:40:08 PM PDT 24 |
| Finished | Jul 09 07:44:00 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-1f500ab7-00cf-4b14-8a01-695365702d64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252420662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.2252420662 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.3209984169 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 54132681800 ps |
| CPU time | 1008.93 seconds |
| Started | Jul 09 07:40:06 PM PDT 24 |
| Finished | Jul 09 07:56:56 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-d6c6acdb-13c3-4a7f-95cc-a71aaee72914 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209984169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.3209984169 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.659531263 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 437284469 ps |
| CPU time | 33.28 seconds |
| Started | Jul 09 07:40:04 PM PDT 24 |
| Finished | Jul 09 07:40:38 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-e9fc491d-65ba-454a-ae84-0f4d5bf278ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659531263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_dela ys.659531263 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.3556787292 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 429161270 ps |
| CPU time | 28.8 seconds |
| Started | Jul 09 07:40:09 PM PDT 24 |
| Finished | Jul 09 07:40:39 PM PDT 24 |
| Peak memory | 576452 kb |
| Host | smart-fa96f3a2-8e02-494b-9657-7633cdb7da3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556787292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.3556787292 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.2621117514 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 225579834 ps |
| CPU time | 9.54 seconds |
| Started | Jul 09 07:39:57 PM PDT 24 |
| Finished | Jul 09 07:40:08 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-7dfa99d1-3305-43ae-9aef-2b3810c3db8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621117514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.2621117514 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.1814932838 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 5649060675 ps |
| CPU time | 56.37 seconds |
| Started | Jul 09 07:39:54 PM PDT 24 |
| Finished | Jul 09 07:40:51 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-9be94e18-e9a7-4978-be0c-8d837398b581 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814932838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.1814932838 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.389957157 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 4280922395 ps |
| CPU time | 74.59 seconds |
| Started | Jul 09 07:39:56 PM PDT 24 |
| Finished | Jul 09 07:41:12 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-2c670f81-1661-4e0c-8a0b-69827be5c65e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389957157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.389957157 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.2210751877 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 39538951 ps |
| CPU time | 5.53 seconds |
| Started | Jul 09 07:39:54 PM PDT 24 |
| Finished | Jul 09 07:40:00 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-37b3ce34-aa19-4c8b-ae8c-427fbae111c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210751877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.2210751877 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.387190818 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 1284568152 ps |
| CPU time | 97.13 seconds |
| Started | Jul 09 07:40:04 PM PDT 24 |
| Finished | Jul 09 07:41:43 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-d41636fa-d1f4-4163-8451-61ef02d87125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387190818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.387190818 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.2556587464 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2239761793 ps |
| CPU time | 159.21 seconds |
| Started | Jul 09 07:40:08 PM PDT 24 |
| Finished | Jul 09 07:42:48 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-af1996b7-2406-49c3-a37c-2a5f2873ddce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556587464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.2556587464 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.4189033993 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 5565679045 ps |
| CPU time | 379.27 seconds |
| Started | Jul 09 07:40:06 PM PDT 24 |
| Finished | Jul 09 07:46:26 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-ae53bbf0-4423-4f5d-822e-628f4a3db1fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189033993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.4189033993 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.1620572309 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 833939703 ps |
| CPU time | 156.85 seconds |
| Started | Jul 09 07:40:08 PM PDT 24 |
| Finished | Jul 09 07:42:46 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-6f53a98d-fc0e-402b-850c-eb528f365a4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620572309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.1620572309 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.2692426109 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 156830453 ps |
| CPU time | 22.13 seconds |
| Started | Jul 09 07:40:07 PM PDT 24 |
| Finished | Jul 09 07:40:30 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-dbcb1517-2f03-42c0-9a2c-4d65153da180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692426109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.2692426109 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.1081207125 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 475298140 ps |
| CPU time | 42.28 seconds |
| Started | Jul 09 07:40:10 PM PDT 24 |
| Finished | Jul 09 07:40:53 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-9f230847-d973-443b-93f0-32a3483b357e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081207125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .1081207125 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.2091704656 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 42489079017 ps |
| CPU time | 814.09 seconds |
| Started | Jul 09 07:40:16 PM PDT 24 |
| Finished | Jul 09 07:53:52 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-5db80b00-75e5-4eb6-b414-b51fda214cb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091704656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.2091704656 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.470609515 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 468467502 ps |
| CPU time | 18.65 seconds |
| Started | Jul 09 07:40:15 PM PDT 24 |
| Finished | Jul 09 07:40:35 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-538666c8-b629-458f-879b-ec2deab8007e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470609515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_addr .470609515 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.2551332245 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 353660101 ps |
| CPU time | 29.5 seconds |
| Started | Jul 09 07:40:17 PM PDT 24 |
| Finished | Jul 09 07:40:47 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-8ea15ef5-acaa-4b40-b6c7-576220c5b67d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551332245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.2551332245 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.6999106 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 429095593 ps |
| CPU time | 37.69 seconds |
| Started | Jul 09 07:40:07 PM PDT 24 |
| Finished | Jul 09 07:40:45 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-5930b408-af11-4886-8554-0cd96966cf9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6999106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.6999106 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.3832803746 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 60889895177 ps |
| CPU time | 677.38 seconds |
| Started | Jul 09 07:40:06 PM PDT 24 |
| Finished | Jul 09 07:51:25 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-766858ed-5260-4248-b9f6-768189cc0076 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832803746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.3832803746 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.25888783 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 32960734663 ps |
| CPU time | 620.34 seconds |
| Started | Jul 09 07:40:05 PM PDT 24 |
| Finished | Jul 09 07:50:27 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-c0e529fd-bd8c-4814-ac0e-0fa3fc6ff811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25888783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.25888783 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.893709940 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 514922391 ps |
| CPU time | 42.92 seconds |
| Started | Jul 09 07:40:03 PM PDT 24 |
| Finished | Jul 09 07:40:47 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-92b7ba5c-21a6-40e5-9ede-79d2f5db9ba8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893709940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_dela ys.893709940 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.668540494 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 546924450 ps |
| CPU time | 16.76 seconds |
| Started | Jul 09 07:40:14 PM PDT 24 |
| Finished | Jul 09 07:40:32 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-c1b82168-9d97-48b8-a3ce-3dbfb5df208b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668540494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.668540494 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.3226696418 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 209162225 ps |
| CPU time | 9.53 seconds |
| Started | Jul 09 07:40:04 PM PDT 24 |
| Finished | Jul 09 07:40:15 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-49c96687-daa6-4beb-9806-5533df5c8474 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226696418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.3226696418 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.3100373694 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 8911177307 ps |
| CPU time | 93.07 seconds |
| Started | Jul 09 07:40:04 PM PDT 24 |
| Finished | Jul 09 07:41:39 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-56ad2e88-c20c-41ce-bead-3c43fc376d48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100373694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.3100373694 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.2528172993 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 3890412593 ps |
| CPU time | 65.68 seconds |
| Started | Jul 09 07:40:04 PM PDT 24 |
| Finished | Jul 09 07:41:11 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-eb68b2ed-0746-474b-a0eb-be12c90e3e5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528172993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.2528172993 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.3976114187 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 40360067 ps |
| CPU time | 5.97 seconds |
| Started | Jul 09 07:40:05 PM PDT 24 |
| Finished | Jul 09 07:40:12 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-c85c25a9-751b-4ddf-912d-64269853e308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976114187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.3976114187 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.1482288511 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 2283650203 ps |
| CPU time | 219.38 seconds |
| Started | Jul 09 07:40:15 PM PDT 24 |
| Finished | Jul 09 07:43:55 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-b789156f-ac66-4cf7-8d8d-7bf415e6c788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482288511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.1482288511 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.2273895244 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 12508243005 ps |
| CPU time | 509.09 seconds |
| Started | Jul 09 07:40:16 PM PDT 24 |
| Finished | Jul 09 07:48:47 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-c4d51b7e-2310-4e8d-aac8-f6907cfa9d37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273895244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.2273895244 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.3590624187 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 500821888 ps |
| CPU time | 148.51 seconds |
| Started | Jul 09 07:40:19 PM PDT 24 |
| Finished | Jul 09 07:42:48 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-6463817c-d8a1-430e-8f3a-b40596ec523c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590624187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.3590624187 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.1994031011 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 40066204 ps |
| CPU time | 32.97 seconds |
| Started | Jul 09 07:40:16 PM PDT 24 |
| Finished | Jul 09 07:40:50 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-8a5a5d57-9a40-473c-b5db-89d96f0df471 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994031011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al l_with_reset_error.1994031011 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1917987870 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 396653781 ps |
| CPU time | 18.45 seconds |
| Started | Jul 09 07:40:14 PM PDT 24 |
| Finished | Jul 09 07:40:34 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-6ca1c57d-4fbd-4b45-b46c-ede9f2444af1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917987870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.1917987870 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.1624266129 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 6064954984 ps |
| CPU time | 655.6 seconds |
| Started | Jul 09 07:25:54 PM PDT 24 |
| Finished | Jul 09 07:37:09 PM PDT 24 |
| Peak memory | 598600 kb |
| Host | smart-4838f24e-bff8-48c3-94f5-72708eaa6c6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624266129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.1624266129 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.4266036587 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 16287867440 ps |
| CPU time | 2245.91 seconds |
| Started | Jul 09 07:25:46 PM PDT 24 |
| Finished | Jul 09 08:03:29 PM PDT 24 |
| Peak memory | 593148 kb |
| Host | smart-8b85d356-be9e-4707-8513-c6fb4f13d665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266036587 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.4266036587 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.2719742690 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 893934467 ps |
| CPU time | 69.81 seconds |
| Started | Jul 09 07:25:48 PM PDT 24 |
| Finished | Jul 09 07:27:16 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-803bd28e-275d-45aa-a499-dae18fac077a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719742690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 2719742690 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.655594043 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 83239410565 ps |
| CPU time | 1463.87 seconds |
| Started | Jul 09 07:25:45 PM PDT 24 |
| Finished | Jul 09 07:50:26 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-8793e03c-a33c-4273-a1a1-3af411893779 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655594043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_de vice_slow_rsp.655594043 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2170080641 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 152589107 ps |
| CPU time | 17.22 seconds |
| Started | Jul 09 07:25:44 PM PDT 24 |
| Finished | Jul 09 07:26:17 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-5c48dee1-3463-4c9c-b663-d11e09a26f68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170080641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .2170080641 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.1122317392 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 534052600 ps |
| CPU time | 20.59 seconds |
| Started | Jul 09 07:25:46 PM PDT 24 |
| Finished | Jul 09 07:26:24 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-9a50bc4f-199b-4611-b655-a209df264dac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122317392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1122317392 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.4199318711 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 66931160 ps |
| CPU time | 8.22 seconds |
| Started | Jul 09 07:25:53 PM PDT 24 |
| Finished | Jul 09 07:26:21 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-97eeba26-786a-4ebb-b206-03a5595765f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199318711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.4199318711 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.2770287229 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 93529864660 ps |
| CPU time | 874.27 seconds |
| Started | Jul 09 07:25:44 PM PDT 24 |
| Finished | Jul 09 07:40:35 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-bf542b69-149f-4059-b711-8560d7af04f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770287229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2770287229 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.2682700117 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 20066516550 ps |
| CPU time | 315.46 seconds |
| Started | Jul 09 07:25:50 PM PDT 24 |
| Finished | Jul 09 07:31:23 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-33824e7a-816f-4c15-bd6a-f1bcb75b1d58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682700117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2682700117 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.381236109 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 121999337 ps |
| CPU time | 12.99 seconds |
| Started | Jul 09 07:25:45 PM PDT 24 |
| Finished | Jul 09 07:26:15 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-6f360d19-1a22-4040-a889-612b8552875b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381236109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delay s.381236109 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.3252665659 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 347968259 ps |
| CPU time | 25.79 seconds |
| Started | Jul 09 07:25:46 PM PDT 24 |
| Finished | Jul 09 07:26:29 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-169540a5-5b37-4955-93cd-430e173135d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252665659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3252665659 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.3471511265 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 45922706 ps |
| CPU time | 6.01 seconds |
| Started | Jul 09 07:25:49 PM PDT 24 |
| Finished | Jul 09 07:26:13 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-0691f3dc-5770-45d6-bbd8-0c699fe909d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471511265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3471511265 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.927857570 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 6802119711 ps |
| CPU time | 63.86 seconds |
| Started | Jul 09 07:25:45 PM PDT 24 |
| Finished | Jul 09 07:27:06 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-fafa151b-1f1c-4f17-b4e0-1369e0c67ce4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927857570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.927857570 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.2738148867 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 4146446716 ps |
| CPU time | 69.93 seconds |
| Started | Jul 09 07:25:47 PM PDT 24 |
| Finished | Jul 09 07:27:15 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-83ee0ecf-0a29-4959-bf78-8bd3f2f20799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738148867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2738148867 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2608352158 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 53044926 ps |
| CPU time | 6.74 seconds |
| Started | Jul 09 07:25:45 PM PDT 24 |
| Finished | Jul 09 07:26:09 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-9bc4c1e7-8aca-4f3f-b0c8-b07d3dbef9c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608352158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .2608352158 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.310247452 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 738393893 ps |
| CPU time | 63.14 seconds |
| Started | Jul 09 07:25:46 PM PDT 24 |
| Finished | Jul 09 07:27:06 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-169c64e8-6c2a-455a-a612-155cd0497ddf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310247452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.310247452 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.112609579 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 12292282344 ps |
| CPU time | 435.23 seconds |
| Started | Jul 09 07:25:45 PM PDT 24 |
| Finished | Jul 09 07:33:17 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-433565d2-de84-4dea-bdd2-7fef8aa87d43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112609579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.112609579 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2036884269 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 4888040549 ps |
| CPU time | 247.32 seconds |
| Started | Jul 09 07:25:46 PM PDT 24 |
| Finished | Jul 09 07:30:10 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-1665cb26-ea91-4326-862c-78c8de5f201c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036884269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.2036884269 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.983568626 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 577761297 ps |
| CPU time | 84.17 seconds |
| Started | Jul 09 07:25:53 PM PDT 24 |
| Finished | Jul 09 07:27:37 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-3db236a4-6355-4628-8edd-9ae9e2b8cbf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983568626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_reset_error.983568626 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.160092746 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 1040962560 ps |
| CPU time | 40.64 seconds |
| Started | Jul 09 07:25:44 PM PDT 24 |
| Finished | Jul 09 07:26:40 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-df6111a2-6db5-4511-a8ee-e8f1e0629fc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160092746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.160092746 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.2008781475 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 973914829 ps |
| CPU time | 82.94 seconds |
| Started | Jul 09 07:40:16 PM PDT 24 |
| Finished | Jul 09 07:41:40 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-3b7570a0-c868-41d7-8348-1a1cdd419988 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008781475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .2008781475 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.1945773028 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 30434595747 ps |
| CPU time | 588.53 seconds |
| Started | Jul 09 07:40:30 PM PDT 24 |
| Finished | Jul 09 07:50:20 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-19efd090-316d-4ab8-aab9-e7adfa590e0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945773028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_ device_slow_rsp.1945773028 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.567089299 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 199301141 ps |
| CPU time | 22.17 seconds |
| Started | Jul 09 07:40:35 PM PDT 24 |
| Finished | Jul 09 07:40:59 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-8a8f6906-ca5d-4570-8529-a6a152d7ff59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567089299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_addr .567089299 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.3727544325 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 373494077 ps |
| CPU time | 31.27 seconds |
| Started | Jul 09 07:40:35 PM PDT 24 |
| Finished | Jul 09 07:41:08 PM PDT 24 |
| Peak memory | 576456 kb |
| Host | smart-79bbd62b-f8d1-42f0-b28f-c489dc28a170 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727544325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.3727544325 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.1957747563 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 1016622251 ps |
| CPU time | 33.9 seconds |
| Started | Jul 09 07:40:15 PM PDT 24 |
| Finished | Jul 09 07:40:50 PM PDT 24 |
| Peak memory | 576472 kb |
| Host | smart-2f88ec01-1cfd-4ae1-ab1d-632ee16d7bf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957747563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.1957747563 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.2451501052 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 48704356948 ps |
| CPU time | 520.01 seconds |
| Started | Jul 09 07:40:17 PM PDT 24 |
| Finished | Jul 09 07:48:58 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-3d93e63a-b0c6-497a-a196-34bf4455e347 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451501052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.2451501052 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.105578793 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 40047608362 ps |
| CPU time | 699.31 seconds |
| Started | Jul 09 07:40:16 PM PDT 24 |
| Finished | Jul 09 07:51:57 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-2186bccd-5c08-44ce-a898-10c86ffdadf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105578793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.105578793 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.3077923203 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 244947823 ps |
| CPU time | 22.14 seconds |
| Started | Jul 09 07:40:18 PM PDT 24 |
| Finished | Jul 09 07:40:41 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-2932a71d-a592-48e6-9008-5ec0223db4f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077923203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.3077923203 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.2946071651 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 340209129 ps |
| CPU time | 11.74 seconds |
| Started | Jul 09 07:40:29 PM PDT 24 |
| Finished | Jul 09 07:40:43 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-59aa246f-839c-4bf6-93ff-cf39919d8ac1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946071651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.2946071651 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.1856174787 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 61443284 ps |
| CPU time | 7.46 seconds |
| Started | Jul 09 07:40:15 PM PDT 24 |
| Finished | Jul 09 07:40:24 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-631ae857-4c2f-40dd-9a4b-832c4237a55c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856174787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.1856174787 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.2395742154 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 4520309379 ps |
| CPU time | 45.47 seconds |
| Started | Jul 09 07:40:15 PM PDT 24 |
| Finished | Jul 09 07:41:02 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-3948c4a1-54ae-4ddb-b7e0-891df0a4ab81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395742154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.2395742154 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.837371138 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 5245839464 ps |
| CPU time | 90.06 seconds |
| Started | Jul 09 07:40:17 PM PDT 24 |
| Finished | Jul 09 07:41:48 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-a805107e-e615-4536-a35d-6deff197575c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837371138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.837371138 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.3698394993 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 48783721 ps |
| CPU time | 6.64 seconds |
| Started | Jul 09 07:40:20 PM PDT 24 |
| Finished | Jul 09 07:40:28 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-f350c8a4-4995-4a63-ac9a-32f6041c102d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698394993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.3698394993 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.4041371686 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 268572186 ps |
| CPU time | 31.35 seconds |
| Started | Jul 09 07:40:35 PM PDT 24 |
| Finished | Jul 09 07:41:08 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-ae819f30-cca9-4597-9a80-810aad448784 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041371686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.4041371686 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.1974023794 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 1272500126 ps |
| CPU time | 52.34 seconds |
| Started | Jul 09 07:40:29 PM PDT 24 |
| Finished | Jul 09 07:41:23 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-5437306c-221a-486a-befa-ad4bc7d88a94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974023794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.1974023794 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.3202014559 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 405731348 ps |
| CPU time | 150.5 seconds |
| Started | Jul 09 07:40:30 PM PDT 24 |
| Finished | Jul 09 07:43:02 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-da5b56e9-4128-4513-aa28-08bf5f1ed736 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202014559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_rand_reset.3202014559 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.2071340294 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 85435351 ps |
| CPU time | 19.91 seconds |
| Started | Jul 09 07:40:28 PM PDT 24 |
| Finished | Jul 09 07:40:49 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-5b05f99c-6073-49e0-a22d-bdcbef6c0d84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071340294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.2071340294 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.3393627531 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 1060038001 ps |
| CPU time | 43.98 seconds |
| Started | Jul 09 07:40:32 PM PDT 24 |
| Finished | Jul 09 07:41:17 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-f3d62f99-742c-49d8-914d-4be5f42f42c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393627531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.3393627531 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.1829198846 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 609500272 ps |
| CPU time | 52.96 seconds |
| Started | Jul 09 07:40:30 PM PDT 24 |
| Finished | Jul 09 07:41:25 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-17b3f2a4-fc98-4c6c-bf3a-a1222a2d442b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829198846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .1829198846 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.2067768975 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 50369468249 ps |
| CPU time | 951.19 seconds |
| Started | Jul 09 07:40:39 PM PDT 24 |
| Finished | Jul 09 07:56:31 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-0104d5e9-d5ce-44fb-a241-73bf100facdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067768975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.2067768975 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2596059082 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 335600741 ps |
| CPU time | 34.45 seconds |
| Started | Jul 09 07:40:42 PM PDT 24 |
| Finished | Jul 09 07:41:18 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-ba3f21c7-16cd-464b-8e3c-7ff19ad2adfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596059082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.2596059082 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.335571136 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 2514693922 ps |
| CPU time | 80.72 seconds |
| Started | Jul 09 07:40:41 PM PDT 24 |
| Finished | Jul 09 07:42:03 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-f6e6ab8f-c340-49bf-a6b5-895ddb0caadc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335571136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.335571136 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.287492878 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 1704401522 ps |
| CPU time | 60.33 seconds |
| Started | Jul 09 07:40:29 PM PDT 24 |
| Finished | Jul 09 07:41:30 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-5c0c10d3-edee-4041-a4d8-fc8c7768af86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287492878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.287492878 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.855735343 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 65397161985 ps |
| CPU time | 643.71 seconds |
| Started | Jul 09 07:40:34 PM PDT 24 |
| Finished | Jul 09 07:51:20 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-c27ce797-4962-403a-b10c-560f48e56450 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855735343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.855735343 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.1270962016 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 56749030396 ps |
| CPU time | 1044.05 seconds |
| Started | Jul 09 07:40:27 PM PDT 24 |
| Finished | Jul 09 07:57:53 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-5e2d16ea-6edd-4f99-8752-ba489a22599b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270962016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.1270962016 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.2190528068 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 359056346 ps |
| CPU time | 31.05 seconds |
| Started | Jul 09 07:40:31 PM PDT 24 |
| Finished | Jul 09 07:41:04 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-9326bb26-d1e8-414c-a347-d338c8f30b40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190528068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.2190528068 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.2027771996 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 2145114540 ps |
| CPU time | 57.17 seconds |
| Started | Jul 09 07:40:41 PM PDT 24 |
| Finished | Jul 09 07:41:39 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-66a4b07e-10e3-44c8-bb23-a8d2f69a4718 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027771996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.2027771996 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.3833622074 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 49246191 ps |
| CPU time | 6.94 seconds |
| Started | Jul 09 07:40:29 PM PDT 24 |
| Finished | Jul 09 07:40:38 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-11dbf264-6c63-41c5-aa77-4c4b0afed6fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833622074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.3833622074 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.4083290684 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 8972052434 ps |
| CPU time | 94.81 seconds |
| Started | Jul 09 07:40:29 PM PDT 24 |
| Finished | Jul 09 07:42:06 PM PDT 24 |
| Peak memory | 574632 kb |
| Host | smart-e376c2ed-bf3c-4c3d-b0cb-f9f937242a96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083290684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.4083290684 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.3088344319 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 6263595730 ps |
| CPU time | 111.8 seconds |
| Started | Jul 09 07:40:30 PM PDT 24 |
| Finished | Jul 09 07:42:24 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-8e416f9b-a8fe-4a9a-bf2b-960f1152c0f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088344319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.3088344319 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.3845736695 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 47059562 ps |
| CPU time | 6.15 seconds |
| Started | Jul 09 07:40:28 PM PDT 24 |
| Finished | Jul 09 07:40:35 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-a0cc7ddf-3fae-4974-820c-00da3d032f75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845736695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.3845736695 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.1495479703 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 2382218675 ps |
| CPU time | 195.79 seconds |
| Started | Jul 09 07:40:41 PM PDT 24 |
| Finished | Jul 09 07:43:58 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-ccaad327-2c87-4806-a869-35a6fd9850e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495479703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.1495479703 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.155509708 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 2287838463 ps |
| CPU time | 167.89 seconds |
| Started | Jul 09 07:40:43 PM PDT 24 |
| Finished | Jul 09 07:43:32 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-dca0aa4c-533a-4289-9df4-fad38cdc6184 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155509708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.155509708 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.3174114356 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 678739953 ps |
| CPU time | 248.96 seconds |
| Started | Jul 09 07:40:40 PM PDT 24 |
| Finished | Jul 09 07:44:50 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-5ebe394c-85e9-4e4c-892e-d2387e0e140d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174114356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.3174114356 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.160273392 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 4493059443 ps |
| CPU time | 177.31 seconds |
| Started | Jul 09 07:40:42 PM PDT 24 |
| Finished | Jul 09 07:43:41 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-99397434-13e8-4362-ba0f-34704cb39b2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160273392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_reset_error.160273392 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.757429253 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 185796964 ps |
| CPU time | 21.79 seconds |
| Started | Jul 09 07:40:41 PM PDT 24 |
| Finished | Jul 09 07:41:05 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-389fac7d-5d80-4da6-8e26-637f112a8c5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757429253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.757429253 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.3603110535 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 353972259 ps |
| CPU time | 16.07 seconds |
| Started | Jul 09 07:40:51 PM PDT 24 |
| Finished | Jul 09 07:41:09 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-df8af2d2-55f7-4edf-a7a2-170f83197c11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603110535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .3603110535 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.1020680315 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 31632514007 ps |
| CPU time | 503.81 seconds |
| Started | Jul 09 07:40:45 PM PDT 24 |
| Finished | Jul 09 07:49:10 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-ec9c5448-af52-4703-9342-9d9f3716c744 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020680315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.1020680315 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1536294231 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 259246586 ps |
| CPU time | 12.79 seconds |
| Started | Jul 09 07:40:48 PM PDT 24 |
| Finished | Jul 09 07:41:03 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-22f38120-82f8-4a4e-9375-7740c14585a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536294231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.1536294231 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.925956439 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 1560596024 ps |
| CPU time | 48.26 seconds |
| Started | Jul 09 07:40:49 PM PDT 24 |
| Finished | Jul 09 07:41:40 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-e8c01b47-7f78-4559-bf8c-6848e4e92c9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925956439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.925956439 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.409572676 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 604042706 ps |
| CPU time | 49.28 seconds |
| Started | Jul 09 07:40:42 PM PDT 24 |
| Finished | Jul 09 07:41:32 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-64d1bf77-2310-42c1-a92d-667ef3e9f56b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409572676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.409572676 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.3995233977 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 9786806216 ps |
| CPU time | 99.39 seconds |
| Started | Jul 09 07:40:42 PM PDT 24 |
| Finished | Jul 09 07:42:23 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-731ec245-d6c5-450c-b6cf-32dbf729ec9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995233977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.3995233977 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.3931064640 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 46043080676 ps |
| CPU time | 810.66 seconds |
| Started | Jul 09 07:40:45 PM PDT 24 |
| Finished | Jul 09 07:54:16 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-7d939525-9e0e-4f39-b241-a644f29f9db3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931064640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.3931064640 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.3706796231 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 39511496 ps |
| CPU time | 5.67 seconds |
| Started | Jul 09 07:40:51 PM PDT 24 |
| Finished | Jul 09 07:40:59 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-96a1061e-0226-41ef-be0a-50e9687a51d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706796231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.3706796231 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.2312978892 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 697825746 ps |
| CPU time | 21.72 seconds |
| Started | Jul 09 07:40:50 PM PDT 24 |
| Finished | Jul 09 07:41:14 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-74c4f382-c56d-4fc7-9867-ba436d3d924c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312978892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.2312978892 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.371323841 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 165041185 ps |
| CPU time | 8.31 seconds |
| Started | Jul 09 07:40:41 PM PDT 24 |
| Finished | Jul 09 07:40:51 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-33eac92b-39aa-4796-bf76-add8b2708d44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371323841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.371323841 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.3822935960 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 6905263817 ps |
| CPU time | 71.34 seconds |
| Started | Jul 09 07:40:41 PM PDT 24 |
| Finished | Jul 09 07:41:54 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-28ec88b1-1f47-4ee8-861a-50f7855450b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822935960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.3822935960 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.1818177792 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 5023089356 ps |
| CPU time | 89.56 seconds |
| Started | Jul 09 07:40:41 PM PDT 24 |
| Finished | Jul 09 07:42:11 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-c1b184c6-38a8-4ac8-9163-af67942d55f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818177792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.1818177792 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2803942922 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 50623305 ps |
| CPU time | 6.95 seconds |
| Started | Jul 09 07:40:41 PM PDT 24 |
| Finished | Jul 09 07:40:49 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-fb676b8c-9295-4b55-b912-6e71dc5962cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803942922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.2803942922 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.3482988462 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 7277486822 ps |
| CPU time | 269 seconds |
| Started | Jul 09 07:40:49 PM PDT 24 |
| Finished | Jul 09 07:45:20 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-6fa0f0d8-d49f-4ab1-836e-152aaa3ea498 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482988462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.3482988462 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.1102614520 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 2179867729 ps |
| CPU time | 65.97 seconds |
| Started | Jul 09 07:40:49 PM PDT 24 |
| Finished | Jul 09 07:41:58 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-42b6b7cc-3b86-4c8c-9be3-17ac56b68963 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102614520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.1102614520 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.3480710060 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 331334430 ps |
| CPU time | 118.37 seconds |
| Started | Jul 09 07:40:51 PM PDT 24 |
| Finished | Jul 09 07:42:52 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-fdabdc25-2ab7-47d3-af96-f93680552b00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480710060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.3480710060 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.669729555 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 419702931 ps |
| CPU time | 136.24 seconds |
| Started | Jul 09 07:40:53 PM PDT 24 |
| Finished | Jul 09 07:43:11 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-f77207bb-25a4-41f8-8d1e-95f92b8b090a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669729555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_reset_error.669729555 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.2733514172 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 922521476 ps |
| CPU time | 40.69 seconds |
| Started | Jul 09 07:40:51 PM PDT 24 |
| Finished | Jul 09 07:41:34 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-4ed64dc2-081d-4282-a17b-f400ee4f8f5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733514172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.2733514172 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.3122699825 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 1222722897 ps |
| CPU time | 59.14 seconds |
| Started | Jul 09 07:40:49 PM PDT 24 |
| Finished | Jul 09 07:41:50 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-0146cd77-cad7-41a9-8b58-47bbf6a82975 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122699825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .3122699825 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.2583328730 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 10993139539 ps |
| CPU time | 183.05 seconds |
| Started | Jul 09 07:40:49 PM PDT 24 |
| Finished | Jul 09 07:43:55 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-833107ee-b8ba-4c0c-ba4c-5d7ee6fd3cd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583328730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.2583328730 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.3943066618 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 1140958162 ps |
| CPU time | 45.98 seconds |
| Started | Jul 09 07:40:48 PM PDT 24 |
| Finished | Jul 09 07:41:35 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-c747dadb-85bd-4364-9996-d504e10debd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943066618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.3943066618 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.2456910376 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 175304422 ps |
| CPU time | 15.88 seconds |
| Started | Jul 09 07:40:49 PM PDT 24 |
| Finished | Jul 09 07:41:06 PM PDT 24 |
| Peak memory | 576440 kb |
| Host | smart-7281276f-4fb7-4590-8ad4-2c6cb45c5e82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456910376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.2456910376 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.3668781772 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 1287744671 ps |
| CPU time | 49.54 seconds |
| Started | Jul 09 07:40:53 PM PDT 24 |
| Finished | Jul 09 07:41:44 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-643a64c3-4480-455d-9db5-3e85c880c70e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668781772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.3668781772 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.1177353833 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 104602379820 ps |
| CPU time | 1156.26 seconds |
| Started | Jul 09 07:40:48 PM PDT 24 |
| Finished | Jul 09 08:00:05 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-d74180a8-1286-4d2f-9672-3abbe860fd24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177353833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.1177353833 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.3635391784 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 55248335644 ps |
| CPU time | 1036.12 seconds |
| Started | Jul 09 07:40:49 PM PDT 24 |
| Finished | Jul 09 07:58:07 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-e48b0657-5142-4c1a-9904-ed500c1326d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635391784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.3635391784 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.2793467039 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 233671718 ps |
| CPU time | 21.33 seconds |
| Started | Jul 09 07:40:52 PM PDT 24 |
| Finished | Jul 09 07:41:16 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-2383d99b-4158-40a9-8e91-8bb80b46b605 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793467039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.2793467039 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.2106551083 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 951284467 ps |
| CPU time | 28 seconds |
| Started | Jul 09 07:40:53 PM PDT 24 |
| Finished | Jul 09 07:41:22 PM PDT 24 |
| Peak memory | 576472 kb |
| Host | smart-05da0076-2617-4414-be41-e5e3754696a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106551083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.2106551083 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.3539798150 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 175982855 ps |
| CPU time | 8.45 seconds |
| Started | Jul 09 07:40:50 PM PDT 24 |
| Finished | Jul 09 07:41:01 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-e996ba9c-15cf-41c9-9e70-a76eceb4edd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539798150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.3539798150 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.3605134266 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 7100466073 ps |
| CPU time | 70.43 seconds |
| Started | Jul 09 07:40:49 PM PDT 24 |
| Finished | Jul 09 07:42:02 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-46817d52-6c90-42a1-ac4f-6e32ad895dc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605134266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.3605134266 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.706334160 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 4594683667 ps |
| CPU time | 78.65 seconds |
| Started | Jul 09 07:40:50 PM PDT 24 |
| Finished | Jul 09 07:42:11 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-c9160fbc-6fe9-4058-a72b-d4470bfda8dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706334160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.706334160 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.1938003113 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 50959451 ps |
| CPU time | 6.84 seconds |
| Started | Jul 09 07:40:49 PM PDT 24 |
| Finished | Jul 09 07:40:58 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-fc6c65c4-3781-4a78-97fd-d99d1f08e02b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938003113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.1938003113 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.2151044598 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 2215736409 ps |
| CPU time | 84.07 seconds |
| Started | Jul 09 07:40:57 PM PDT 24 |
| Finished | Jul 09 07:42:22 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-e2ca8ee9-9c60-4c9e-8b4b-3a5c1aee44fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151044598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.2151044598 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.3499779901 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 8320474966 ps |
| CPU time | 338.66 seconds |
| Started | Jul 09 07:40:59 PM PDT 24 |
| Finished | Jul 09 07:46:39 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-39806965-a23b-46c0-af57-549072325ec3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499779901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.3499779901 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.3631081636 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 158234558 ps |
| CPU time | 24.96 seconds |
| Started | Jul 09 07:40:59 PM PDT 24 |
| Finished | Jul 09 07:41:25 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-f6910290-cd9d-4a38-9f55-cc40be8f6fcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631081636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.3631081636 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.3021394928 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 267792347 ps |
| CPU time | 61.53 seconds |
| Started | Jul 09 07:40:56 PM PDT 24 |
| Finished | Jul 09 07:41:58 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-fde413db-98b2-4b4c-815f-d2e03b68681e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021394928 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.3021394928 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.1912952708 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 571768024 ps |
| CPU time | 22.96 seconds |
| Started | Jul 09 07:40:49 PM PDT 24 |
| Finished | Jul 09 07:41:14 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-70015d4d-734c-488b-8f03-dadc1d21eead |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912952708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.1912952708 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.91829695 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 1429627372 ps |
| CPU time | 58.07 seconds |
| Started | Jul 09 07:40:56 PM PDT 24 |
| Finished | Jul 09 07:41:55 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-96db7766-ebd0-4a48-a627-0882fe139c59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91829695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device.91829695 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.917805256 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 5989077292 ps |
| CPU time | 101.69 seconds |
| Started | Jul 09 07:40:59 PM PDT 24 |
| Finished | Jul 09 07:42:41 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-1b3677f9-ce2f-45a1-b09f-47bc153d9ead |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917805256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_d evice_slow_rsp.917805256 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.2322217987 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 105437351 ps |
| CPU time | 11.25 seconds |
| Started | Jul 09 07:40:59 PM PDT 24 |
| Finished | Jul 09 07:41:11 PM PDT 24 |
| Peak memory | 576472 kb |
| Host | smart-6c30c96c-eefd-4b07-85d5-de2b3e85deda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322217987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.2322217987 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.1849818640 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 483074831 ps |
| CPU time | 17.73 seconds |
| Started | Jul 09 07:40:58 PM PDT 24 |
| Finished | Jul 09 07:41:16 PM PDT 24 |
| Peak memory | 576460 kb |
| Host | smart-bc90ccaa-2509-4826-9487-390ce13ac188 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849818640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.1849818640 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.3702552188 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 416819415 ps |
| CPU time | 37.81 seconds |
| Started | Jul 09 07:41:03 PM PDT 24 |
| Finished | Jul 09 07:41:43 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-cb19997d-87aa-4279-a261-6f6e0e71be93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702552188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.3702552188 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.2074856707 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 33527583251 ps |
| CPU time | 354.57 seconds |
| Started | Jul 09 07:40:57 PM PDT 24 |
| Finished | Jul 09 07:46:53 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-78052860-804f-4998-a35c-f43ec3dce8f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074856707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.2074856707 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.2961222873 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 63141118222 ps |
| CPU time | 1264.32 seconds |
| Started | Jul 09 07:41:00 PM PDT 24 |
| Finished | Jul 09 08:02:06 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-25f491fe-e653-4727-abf1-758f1454b8fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961222873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.2961222873 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.3810944470 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 464076948 ps |
| CPU time | 41.33 seconds |
| Started | Jul 09 07:40:57 PM PDT 24 |
| Finished | Jul 09 07:41:39 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-d812f359-ca9a-467b-a91b-3427921c9f78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810944470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.3810944470 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.1689400675 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 38059118 ps |
| CPU time | 6.14 seconds |
| Started | Jul 09 07:40:56 PM PDT 24 |
| Finished | Jul 09 07:41:03 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-55c293d0-ed2c-459a-a319-ae34a53748db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689400675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.1689400675 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.907535064 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 262619256 ps |
| CPU time | 10.91 seconds |
| Started | Jul 09 07:41:00 PM PDT 24 |
| Finished | Jul 09 07:41:12 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-98d82146-17aa-4715-abab-4672483d9ba8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907535064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.907535064 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.4064611130 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 7664414188 ps |
| CPU time | 76.91 seconds |
| Started | Jul 09 07:40:59 PM PDT 24 |
| Finished | Jul 09 07:42:17 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-c61adbfe-6167-4a5e-bebb-c74f5e4576c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064611130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.4064611130 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.2575289671 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 3978858039 ps |
| CPU time | 67.76 seconds |
| Started | Jul 09 07:40:57 PM PDT 24 |
| Finished | Jul 09 07:42:06 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-ff0d89c5-0c0b-4d65-95ac-1c63973ee489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575289671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.2575289671 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.2263664132 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 49634968 ps |
| CPU time | 6.53 seconds |
| Started | Jul 09 07:40:59 PM PDT 24 |
| Finished | Jul 09 07:41:07 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-519bec19-6b37-4206-abf3-6a900e2d7e76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263664132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.2263664132 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.1760357938 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 11956727905 ps |
| CPU time | 450.1 seconds |
| Started | Jul 09 07:40:57 PM PDT 24 |
| Finished | Jul 09 07:48:28 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-e13b858b-a9aa-432f-ba17-cdd2725e19ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760357938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.1760357938 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.3930236246 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 683487566 ps |
| CPU time | 53.25 seconds |
| Started | Jul 09 07:41:08 PM PDT 24 |
| Finished | Jul 09 07:42:02 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-0d470448-ec35-4781-8a34-98f9ea9d58ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930236246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.3930236246 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.796393022 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 569814213 ps |
| CPU time | 130.23 seconds |
| Started | Jul 09 07:40:57 PM PDT 24 |
| Finished | Jul 09 07:43:08 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-c81f70a3-37a8-4e99-9248-7e6d8a3dc989 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796393022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_ with_rand_reset.796393022 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.3349727807 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 7908800689 ps |
| CPU time | 514.92 seconds |
| Started | Jul 09 07:41:02 PM PDT 24 |
| Finished | Jul 09 07:49:39 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-53f80724-3ced-4a4e-8ad1-28af159db088 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349727807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.3349727807 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.1909569587 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 94090517 ps |
| CPU time | 7.06 seconds |
| Started | Jul 09 07:40:56 PM PDT 24 |
| Finished | Jul 09 07:41:04 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-105d4721-4615-4277-9e71-19b66177d9e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909569587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.1909569587 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.3693779670 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 673955971 ps |
| CPU time | 31.6 seconds |
| Started | Jul 09 07:41:04 PM PDT 24 |
| Finished | Jul 09 07:41:37 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-e730fde4-3e0e-4ec8-aa57-92e2c9994b62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693779670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .3693779670 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.2509741799 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 81288867817 ps |
| CPU time | 1622.51 seconds |
| Started | Jul 09 07:41:07 PM PDT 24 |
| Finished | Jul 09 08:08:11 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-a7d91226-ec17-4e01-9dfc-02604386b459 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509741799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.2509741799 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.3965207474 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 25431325 ps |
| CPU time | 5.53 seconds |
| Started | Jul 09 07:41:07 PM PDT 24 |
| Finished | Jul 09 07:41:14 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-e5660df1-0406-4abd-bad2-3908866bf73c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965207474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.3965207474 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.3366433473 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 847129819 ps |
| CPU time | 33.7 seconds |
| Started | Jul 09 07:41:05 PM PDT 24 |
| Finished | Jul 09 07:41:39 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-dde2ad86-697c-474a-a3f8-7750923dc298 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366433473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.3366433473 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.2039275142 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 971642532 ps |
| CPU time | 32.73 seconds |
| Started | Jul 09 07:41:07 PM PDT 24 |
| Finished | Jul 09 07:41:41 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-328c1746-89c1-4adf-9476-614dca6fc916 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039275142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.2039275142 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.2326408876 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 20855847418 ps |
| CPU time | 220.27 seconds |
| Started | Jul 09 07:41:06 PM PDT 24 |
| Finished | Jul 09 07:44:47 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-7562967d-61bf-4388-b9ba-42c6614a716b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326408876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.2326408876 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.525953723 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 17261976050 ps |
| CPU time | 283.67 seconds |
| Started | Jul 09 07:41:05 PM PDT 24 |
| Finished | Jul 09 07:45:50 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-60756006-f63c-4efd-8057-36d655a811bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525953723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.525953723 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.3770108898 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 38558997 ps |
| CPU time | 6.23 seconds |
| Started | Jul 09 07:41:03 PM PDT 24 |
| Finished | Jul 09 07:41:10 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-f6412463-1e84-4d9f-8102-2b2d51304503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770108898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.3770108898 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.53685340 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 2551795177 ps |
| CPU time | 78.79 seconds |
| Started | Jul 09 07:41:04 PM PDT 24 |
| Finished | Jul 09 07:42:24 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-99418f99-8f78-4c20-a43b-cb6db58d2264 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53685340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.53685340 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.2534961181 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 183772617 ps |
| CPU time | 7.85 seconds |
| Started | Jul 09 07:41:01 PM PDT 24 |
| Finished | Jul 09 07:41:10 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-757d4740-f88c-45dc-9e2c-6719a15278cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534961181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.2534961181 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.3871415556 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 8861696498 ps |
| CPU time | 93.65 seconds |
| Started | Jul 09 07:41:04 PM PDT 24 |
| Finished | Jul 09 07:42:39 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-16225fa5-8bd2-49c2-b785-579e4821973e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871415556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.3871415556 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.1366099685 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 5404329732 ps |
| CPU time | 91.16 seconds |
| Started | Jul 09 07:41:05 PM PDT 24 |
| Finished | Jul 09 07:42:37 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-1c2402c3-33a6-4aed-ac8f-172cc996e707 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366099685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.1366099685 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.3433354745 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 48577901 ps |
| CPU time | 6.9 seconds |
| Started | Jul 09 07:41:06 PM PDT 24 |
| Finished | Jul 09 07:41:14 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-3c0a6c5a-a04a-4064-b1c8-fc907319f604 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433354745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.3433354745 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.1881427590 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 1369040389 ps |
| CPU time | 52 seconds |
| Started | Jul 09 07:41:02 PM PDT 24 |
| Finished | Jul 09 07:41:56 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-968699db-facd-416b-9123-89ac00a806dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881427590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.1881427590 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.942928194 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 5247911814 ps |
| CPU time | 387.84 seconds |
| Started | Jul 09 07:41:03 PM PDT 24 |
| Finished | Jul 09 07:47:32 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-8db1fe99-1df7-471f-a363-154ab4d7b0fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942928194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_ with_rand_reset.942928194 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.3315548940 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 1095297425 ps |
| CPU time | 199.88 seconds |
| Started | Jul 09 07:41:13 PM PDT 24 |
| Finished | Jul 09 07:44:34 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-d97d851b-d7ed-42b8-a891-972ff30a19a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315548940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.3315548940 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.2314176160 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 133648864 ps |
| CPU time | 16.17 seconds |
| Started | Jul 09 07:41:06 PM PDT 24 |
| Finished | Jul 09 07:41:23 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-4df292b9-77a1-439d-afbf-fa35d8a08e20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314176160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.2314176160 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.3798441205 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 2687975900 ps |
| CPU time | 99.67 seconds |
| Started | Jul 09 07:41:13 PM PDT 24 |
| Finished | Jul 09 07:42:54 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-272dddf6-085b-44fc-9e2e-40a2f5ae9395 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798441205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .3798441205 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2804014345 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 65121850568 ps |
| CPU time | 1223.05 seconds |
| Started | Jul 09 07:41:11 PM PDT 24 |
| Finished | Jul 09 08:01:35 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-49f18691-1147-4ded-bc50-354a8f212480 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804014345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.2804014345 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1081691843 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 237038112 ps |
| CPU time | 26.04 seconds |
| Started | Jul 09 07:41:16 PM PDT 24 |
| Finished | Jul 09 07:41:44 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-a4dce645-04ed-4c52-88d8-75c2e7c71f66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081691843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.1081691843 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.488942582 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 932196017 ps |
| CPU time | 35.3 seconds |
| Started | Jul 09 07:41:15 PM PDT 24 |
| Finished | Jul 09 07:41:52 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-35ab8ed9-1354-49a2-92fa-cbdf7e100f85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488942582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.488942582 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.2712030039 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 240411919 ps |
| CPU time | 23.98 seconds |
| Started | Jul 09 07:41:11 PM PDT 24 |
| Finished | Jul 09 07:41:36 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-0a6e1ebf-5c40-4605-8964-b6038cb0d4c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712030039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.2712030039 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.325024762 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 11269562909 ps |
| CPU time | 115.36 seconds |
| Started | Jul 09 07:41:12 PM PDT 24 |
| Finished | Jul 09 07:43:09 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-6cc91259-f4e5-47e4-9956-b8bf4885be40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325024762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.325024762 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.1046408085 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 5029615477 ps |
| CPU time | 87.3 seconds |
| Started | Jul 09 07:41:11 PM PDT 24 |
| Finished | Jul 09 07:42:39 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-9de4b013-70fc-48fe-aaaa-83376ddcd7f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046408085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.1046408085 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.1142601615 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 318599202 ps |
| CPU time | 29.37 seconds |
| Started | Jul 09 07:41:11 PM PDT 24 |
| Finished | Jul 09 07:41:41 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-75a0298f-70a9-44c6-85e6-b021d3804531 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142601615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.1142601615 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.2826856277 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 2405716860 ps |
| CPU time | 64.82 seconds |
| Started | Jul 09 07:41:17 PM PDT 24 |
| Finished | Jul 09 07:42:23 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-f055a83f-40ef-4e01-8a29-8f76807ece94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826856277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.2826856277 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.2661162427 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 51337414 ps |
| CPU time | 6.46 seconds |
| Started | Jul 09 07:41:11 PM PDT 24 |
| Finished | Jul 09 07:41:19 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-9eab462e-f396-4256-911f-4d3ff6836c36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661162427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.2661162427 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.2699225035 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 7922599916 ps |
| CPU time | 83.65 seconds |
| Started | Jul 09 07:41:13 PM PDT 24 |
| Finished | Jul 09 07:42:38 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-e6296fd2-94ae-4ee8-8b72-701a0c5ddbd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699225035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.2699225035 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.2998040946 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 3921447259 ps |
| CPU time | 68.64 seconds |
| Started | Jul 09 07:41:12 PM PDT 24 |
| Finished | Jul 09 07:42:22 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-9997196b-a949-4fc0-8435-747734c77ece |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998040946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.2998040946 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.992673101 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 36765774 ps |
| CPU time | 5.52 seconds |
| Started | Jul 09 07:41:11 PM PDT 24 |
| Finished | Jul 09 07:41:17 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-9d093f89-6185-4ba7-adae-98f690bb26a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992673101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delays .992673101 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.4182395197 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 4144212745 ps |
| CPU time | 412.65 seconds |
| Started | Jul 09 07:41:17 PM PDT 24 |
| Finished | Jul 09 07:48:11 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-b951f508-cbeb-45a9-8364-7f314241f642 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182395197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.4182395197 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.87188713 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 10065039685 ps |
| CPU time | 478.65 seconds |
| Started | Jul 09 07:41:17 PM PDT 24 |
| Finished | Jul 09 07:49:17 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-dafb4dc3-75f0-4cc8-bbf6-7781dd38e1a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87188713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.87188713 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.1484908114 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 4214978337 ps |
| CPU time | 351.27 seconds |
| Started | Jul 09 07:41:16 PM PDT 24 |
| Finished | Jul 09 07:47:09 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-057b5489-bb3a-4401-a49d-474593b133d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484908114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.1484908114 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.569567429 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 166722679 ps |
| CPU time | 39.56 seconds |
| Started | Jul 09 07:41:16 PM PDT 24 |
| Finished | Jul 09 07:41:57 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-7c4ba28c-43fa-4717-a4bc-803f38f153b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569567429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_reset_error.569567429 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.27750549 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 573926002 ps |
| CPU time | 25.16 seconds |
| Started | Jul 09 07:41:16 PM PDT 24 |
| Finished | Jul 09 07:41:43 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-70923ebc-40ff-4cc5-ae39-7e7634cb6201 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27750549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.27750549 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.3027100444 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 418777987 ps |
| CPU time | 16.04 seconds |
| Started | Jul 09 07:41:27 PM PDT 24 |
| Finished | Jul 09 07:41:44 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-d1078ff3-2a1d-4d38-afef-22058ca60b9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027100444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .3027100444 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.3323390704 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 142665940128 ps |
| CPU time | 2500.45 seconds |
| Started | Jul 09 07:41:25 PM PDT 24 |
| Finished | Jul 09 08:23:08 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-ca48360e-6585-481f-bcae-f7811e105401 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323390704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.3323390704 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.2661779405 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 1066521870 ps |
| CPU time | 42.53 seconds |
| Started | Jul 09 07:41:24 PM PDT 24 |
| Finished | Jul 09 07:42:09 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-d7856b64-2d9e-422e-a896-13d891926875 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661779405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.2661779405 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.1877692991 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 1616912415 ps |
| CPU time | 50.08 seconds |
| Started | Jul 09 07:41:25 PM PDT 24 |
| Finished | Jul 09 07:42:17 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-3f0fb309-5507-433a-abe5-da9c603317e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877692991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.1877692991 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.4173347732 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 579305370 ps |
| CPU time | 23.04 seconds |
| Started | Jul 09 07:41:26 PM PDT 24 |
| Finished | Jul 09 07:41:51 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-a2058a61-3918-4f77-abc9-0f862e605acb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173347732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.4173347732 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.3069809719 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 36696983136 ps |
| CPU time | 380.97 seconds |
| Started | Jul 09 07:41:25 PM PDT 24 |
| Finished | Jul 09 07:47:48 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-412279aa-26ab-47db-9362-672899ef5634 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069809719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.3069809719 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.196374479 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 64551422166 ps |
| CPU time | 1176.55 seconds |
| Started | Jul 09 07:41:27 PM PDT 24 |
| Finished | Jul 09 08:01:06 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-d34952f2-5f50-4ea8-8973-64d5db9824bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196374479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.196374479 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.688346682 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 278197549 ps |
| CPU time | 27.4 seconds |
| Started | Jul 09 07:41:29 PM PDT 24 |
| Finished | Jul 09 07:41:58 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-eac84a03-b539-427f-8cb1-f101412fa1dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688346682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_dela ys.688346682 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.1593728676 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 269093590 ps |
| CPU time | 11.2 seconds |
| Started | Jul 09 07:41:28 PM PDT 24 |
| Finished | Jul 09 07:41:40 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-82bb714e-0179-4609-8d69-293ae22438d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593728676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.1593728676 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.342434293 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 45338700 ps |
| CPU time | 5.98 seconds |
| Started | Jul 09 07:41:18 PM PDT 24 |
| Finished | Jul 09 07:41:26 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-8a60d3d1-3a46-4c9e-8a41-3cf395e20977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342434293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.342434293 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.3791700827 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 9896880555 ps |
| CPU time | 92.49 seconds |
| Started | Jul 09 07:41:24 PM PDT 24 |
| Finished | Jul 09 07:42:58 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-065d5fa9-f08c-4219-8338-9886746564d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791700827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.3791700827 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.843455377 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 4942866465 ps |
| CPU time | 84.02 seconds |
| Started | Jul 09 07:41:25 PM PDT 24 |
| Finished | Jul 09 07:42:51 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-eb720f67-1916-4a1e-81f3-3da0754e4400 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843455377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.843455377 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.1698145897 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 48096908 ps |
| CPU time | 6.11 seconds |
| Started | Jul 09 07:41:16 PM PDT 24 |
| Finished | Jul 09 07:41:24 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-8fdb986a-df07-494d-a432-35bef901c7aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698145897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.1698145897 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.1573651904 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 2347826380 ps |
| CPU time | 202.4 seconds |
| Started | Jul 09 07:41:35 PM PDT 24 |
| Finished | Jul 09 07:44:59 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-5d0006b9-e2a6-4af0-b332-7b366102a44c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573651904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.1573651904 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.3458963913 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 1966006475 ps |
| CPU time | 159.73 seconds |
| Started | Jul 09 07:41:36 PM PDT 24 |
| Finished | Jul 09 07:44:17 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-0373429c-38db-40d7-bb32-8db29f3fe458 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458963913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.3458963913 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.874018461 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 1161716556 ps |
| CPU time | 340.03 seconds |
| Started | Jul 09 07:41:31 PM PDT 24 |
| Finished | Jul 09 07:47:13 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-c496bbba-21fc-44bd-ba03-b1b5cbeaf649 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874018461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_ with_rand_reset.874018461 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.33836508 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 3599793984 ps |
| CPU time | 271.58 seconds |
| Started | Jul 09 07:41:31 PM PDT 24 |
| Finished | Jul 09 07:46:04 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-48faf712-e404-4779-89a1-b3b2d600361c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33836508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_ with_reset_error.33836508 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.1281954469 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 643072723 ps |
| CPU time | 27.04 seconds |
| Started | Jul 09 07:41:26 PM PDT 24 |
| Finished | Jul 09 07:41:55 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-330ddd4e-b7b8-457b-8363-c1a0d9102670 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281954469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.1281954469 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.1762624643 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 801443695 ps |
| CPU time | 36.75 seconds |
| Started | Jul 09 07:41:34 PM PDT 24 |
| Finished | Jul 09 07:42:12 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-b7719224-6c62-4d66-a628-dfba9a48f0f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762624643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .1762624643 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.2513956524 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 144330345329 ps |
| CPU time | 2635.37 seconds |
| Started | Jul 09 07:41:33 PM PDT 24 |
| Finished | Jul 09 08:25:30 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-77772ec0-fd41-40ca-8d71-942fb0c55ebe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513956524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.2513956524 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.3839549541 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 728421067 ps |
| CPU time | 28.81 seconds |
| Started | Jul 09 07:41:39 PM PDT 24 |
| Finished | Jul 09 07:42:09 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-f887ec33-25a9-42e0-ac8b-7bafd1526a97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839549541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.3839549541 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.1589893132 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 490476534 ps |
| CPU time | 35.18 seconds |
| Started | Jul 09 07:41:34 PM PDT 24 |
| Finished | Jul 09 07:42:11 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-6bdc1cb0-8046-46e5-851d-401d467ae8fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589893132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.1589893132 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.915729662 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 384101814 ps |
| CPU time | 15.39 seconds |
| Started | Jul 09 07:41:33 PM PDT 24 |
| Finished | Jul 09 07:41:50 PM PDT 24 |
| Peak memory | 576484 kb |
| Host | smart-be780560-83f8-4335-80be-5810f6545464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915729662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.915729662 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.383939677 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 70782342291 ps |
| CPU time | 801.91 seconds |
| Started | Jul 09 07:41:31 PM PDT 24 |
| Finished | Jul 09 07:54:55 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-195eb960-58fa-4d45-bd3f-ad1f575fbd75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383939677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.383939677 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.970437742 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 59713414004 ps |
| CPU time | 1050.25 seconds |
| Started | Jul 09 07:42:28 PM PDT 24 |
| Finished | Jul 09 07:59:59 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-e7094332-af49-424b-b35c-0009ee41a8b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970437742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.970437742 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.1379466788 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 252652849 ps |
| CPU time | 24.93 seconds |
| Started | Jul 09 07:41:34 PM PDT 24 |
| Finished | Jul 09 07:42:00 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-707ffbd3-674e-4ac8-afd4-553a18a12c50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379466788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.1379466788 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.3862963478 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 1293053997 ps |
| CPU time | 37.58 seconds |
| Started | Jul 09 07:41:34 PM PDT 24 |
| Finished | Jul 09 07:42:12 PM PDT 24 |
| Peak memory | 576460 kb |
| Host | smart-33b2b27e-d9de-4641-a201-2debe86ddc2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862963478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.3862963478 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.1027969515 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 172812656 ps |
| CPU time | 8.47 seconds |
| Started | Jul 09 07:41:31 PM PDT 24 |
| Finished | Jul 09 07:41:41 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-c53e0e1a-dde4-4f84-bf3f-975a985612d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027969515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.1027969515 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.1225200267 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 5017342839 ps |
| CPU time | 55.94 seconds |
| Started | Jul 09 07:41:33 PM PDT 24 |
| Finished | Jul 09 07:42:30 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-52bcfc1a-52cd-4ce7-b3a8-589af0f138c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225200267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.1225200267 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.790074322 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 4307123397 ps |
| CPU time | 73.43 seconds |
| Started | Jul 09 07:41:31 PM PDT 24 |
| Finished | Jul 09 07:42:46 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-df174145-f3de-42ec-a58c-6332c23593e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790074322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.790074322 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2777020861 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 55686007 ps |
| CPU time | 6.71 seconds |
| Started | Jul 09 07:41:30 PM PDT 24 |
| Finished | Jul 09 07:41:39 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-e8e920a0-aec2-4ab3-ac43-9074ad92a6ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777020861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.2777020861 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.1925932792 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2285806727 ps |
| CPU time | 174.44 seconds |
| Started | Jul 09 07:41:45 PM PDT 24 |
| Finished | Jul 09 07:44:40 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-b484f4b4-4c31-448f-9476-c15cfcba10b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925932792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.1925932792 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.4249909848 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 2099557701 ps |
| CPU time | 160.22 seconds |
| Started | Jul 09 07:41:42 PM PDT 24 |
| Finished | Jul 09 07:44:24 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-d66af136-7e8e-4b8c-b947-c81466519c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249909848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.4249909848 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.80131689 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 3429848355 ps |
| CPU time | 296.73 seconds |
| Started | Jul 09 07:41:41 PM PDT 24 |
| Finished | Jul 09 07:46:39 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-cbb81bca-f26c-4b11-ae82-b6ee1de89c35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80131689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_w ith_rand_reset.80131689 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.3701835554 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 3607451034 ps |
| CPU time | 128.97 seconds |
| Started | Jul 09 07:41:39 PM PDT 24 |
| Finished | Jul 09 07:43:49 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-9db7d530-95c2-426e-a1f4-90bdca99389f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701835554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.3701835554 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.2938716210 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 646457846 ps |
| CPU time | 29.4 seconds |
| Started | Jul 09 07:41:42 PM PDT 24 |
| Finished | Jul 09 07:42:12 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-5156f5eb-2ed3-4edc-802a-ad41451eb5f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938716210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.2938716210 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.939570292 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 865978461 ps |
| CPU time | 40.04 seconds |
| Started | Jul 09 07:41:42 PM PDT 24 |
| Finished | Jul 09 07:42:23 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-742f4845-06b6-41a7-a7d1-1fafdcf48a3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939570292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device. 939570292 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.2819223161 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 71936672614 ps |
| CPU time | 1363.36 seconds |
| Started | Jul 09 07:41:41 PM PDT 24 |
| Finished | Jul 09 08:04:26 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-795fcfc2-03fd-4c26-8458-a72c8e558c82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819223161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.2819223161 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.3157389254 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 89514414 ps |
| CPU time | 10.36 seconds |
| Started | Jul 09 07:41:47 PM PDT 24 |
| Finished | Jul 09 07:41:58 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-847042eb-b8d9-4b3b-b18d-46dfbf3ed7ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157389254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.3157389254 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.3357705998 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 457752865 ps |
| CPU time | 16.83 seconds |
| Started | Jul 09 07:41:41 PM PDT 24 |
| Finished | Jul 09 07:41:58 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-42199a8e-cfd5-463b-9205-97eddbfc520c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357705998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.3357705998 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.104558943 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 513351879 ps |
| CPU time | 45.84 seconds |
| Started | Jul 09 07:41:41 PM PDT 24 |
| Finished | Jul 09 07:42:28 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-50dc57bc-28a0-44d7-9be2-ced70f666608 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104558943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.104558943 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.3112173309 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 39865011203 ps |
| CPU time | 431.88 seconds |
| Started | Jul 09 07:41:42 PM PDT 24 |
| Finished | Jul 09 07:48:55 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-5aec9a0b-e9e5-491f-9b5b-cca2579e9ccc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112173309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.3112173309 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.2392355372 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 8138390410 ps |
| CPU time | 152.57 seconds |
| Started | Jul 09 07:41:42 PM PDT 24 |
| Finished | Jul 09 07:44:15 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-e6d04f74-af10-4dad-96d3-531bdf55b25b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392355372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.2392355372 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.1921044891 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 533699312 ps |
| CPU time | 43.03 seconds |
| Started | Jul 09 07:41:39 PM PDT 24 |
| Finished | Jul 09 07:42:23 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-5e7dea91-36c9-4e51-8e21-d17466de2961 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921044891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.1921044891 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.3532014839 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 38349745 ps |
| CPU time | 5.44 seconds |
| Started | Jul 09 07:41:38 PM PDT 24 |
| Finished | Jul 09 07:41:44 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-366ea178-1df8-481c-818a-1257945c35ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532014839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.3532014839 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.1431957492 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 236423067 ps |
| CPU time | 8.77 seconds |
| Started | Jul 09 07:41:45 PM PDT 24 |
| Finished | Jul 09 07:41:55 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-293766db-8371-4ccf-9c0b-81acbe663164 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431957492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.1431957492 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.1307951202 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 7160606314 ps |
| CPU time | 70.6 seconds |
| Started | Jul 09 07:41:39 PM PDT 24 |
| Finished | Jul 09 07:42:51 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-f8d923a5-79cc-4a99-a1ec-e685a0e28070 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307951202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.1307951202 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.2237292729 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 5182956389 ps |
| CPU time | 88.17 seconds |
| Started | Jul 09 07:41:45 PM PDT 24 |
| Finished | Jul 09 07:43:14 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-117b93fa-cebc-471b-8b6a-5b4c1092bcd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237292729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.2237292729 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.1221848719 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 47898200 ps |
| CPU time | 6.47 seconds |
| Started | Jul 09 07:41:38 PM PDT 24 |
| Finished | Jul 09 07:41:46 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-a5e0b06f-dc7b-488c-9d5c-3831a5a1ad52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221848719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.1221848719 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.3124384771 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 783173870 ps |
| CPU time | 69.83 seconds |
| Started | Jul 09 07:41:48 PM PDT 24 |
| Finished | Jul 09 07:42:59 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-c9f7f15d-2f84-495a-bbf9-daadac09dcb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124384771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.3124384771 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.3688662521 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 3315881901 ps |
| CPU time | 287.36 seconds |
| Started | Jul 09 07:41:47 PM PDT 24 |
| Finished | Jul 09 07:46:35 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-1657aa91-5f28-49aa-a40c-8f22e5ef55c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688662521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.3688662521 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.200420344 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 8156016922 ps |
| CPU time | 368.8 seconds |
| Started | Jul 09 07:41:47 PM PDT 24 |
| Finished | Jul 09 07:47:56 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-36a7c612-20f5-4b71-803b-d1b2f8ed6dc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200420344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_ with_rand_reset.200420344 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.530475308 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 52513014 ps |
| CPU time | 18.32 seconds |
| Started | Jul 09 07:41:48 PM PDT 24 |
| Finished | Jul 09 07:42:07 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-1bbc4826-f14b-4f9a-8de2-eccb8acecf3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530475308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_reset_error.530475308 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.616093710 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 1379670412 ps |
| CPU time | 58.4 seconds |
| Started | Jul 09 07:41:46 PM PDT 24 |
| Finished | Jul 09 07:42:45 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-9ae2a703-e850-45ca-808b-327127db811d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616093710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.616093710 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.1139350503 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 12610966216 ps |
| CPU time | 1327.24 seconds |
| Started | Jul 09 07:43:32 PM PDT 24 |
| Finished | Jul 09 08:05:40 PM PDT 24 |
| Peak memory | 608276 kb |
| Host | smart-7e94bd95-5eac-4511-ad27-156fbf659559 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139350503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.1139350503 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.3861297297 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 13639128220 ps |
| CPU time | 1552.28 seconds |
| Started | Jul 09 07:43:41 PM PDT 24 |
| Finished | Jul 09 08:09:35 PM PDT 24 |
| Peak memory | 608104 kb |
| Host | smart-b75ec192-f525-4965-9770-2454f0edfb8a |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861297297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.3 861297297 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3077656894 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 5337359416 ps |
| CPU time | 460.75 seconds |
| Started | Jul 09 07:51:15 PM PDT 24 |
| Finished | Jul 09 07:58:56 PM PDT 24 |
| Peak memory | 620156 kb |
| Host | smart-39f07220-54b3-4d85-b4c7-dc1395546978 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 077656894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.3077656894 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.3887944767 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 3378828760 ps |
| CPU time | 297.31 seconds |
| Started | Jul 09 07:51:11 PM PDT 24 |
| Finished | Jul 09 07:56:09 PM PDT 24 |
| Peak memory | 609548 kb |
| Host | smart-07067b1d-dd9f-40c8-a09c-9308d76a056f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3887944767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.3887944767 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2700013320 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 3189527650 ps |
| CPU time | 331.91 seconds |
| Started | Jul 09 07:52:35 PM PDT 24 |
| Finished | Jul 09 07:58:09 PM PDT 24 |
| Peak memory | 609584 kb |
| Host | smart-323f349e-f30f-431a-ad4f-63d49d07a9f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700 013320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.2700013320 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.723097530 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 2799550518 ps |
| CPU time | 233.66 seconds |
| Started | Jul 09 07:54:28 PM PDT 24 |
| Finished | Jul 09 07:58:22 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-2e1dba84-9562-49a3-a542-92bde6d9c6c9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723097530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.723097530 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.1653125638 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 3207488872 ps |
| CPU time | 321.45 seconds |
| Started | Jul 09 07:51:11 PM PDT 24 |
| Finished | Jul 09 07:56:34 PM PDT 24 |
| Peak memory | 608992 kb |
| Host | smart-b3ee2f7b-88a7-400b-b191-b0bc9e5d196a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653125638 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.1653125638 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.1494052001 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 2239687016 ps |
| CPU time | 200.48 seconds |
| Started | Jul 09 07:52:25 PM PDT 24 |
| Finished | Jul 09 07:55:46 PM PDT 24 |
| Peak memory | 609572 kb |
| Host | smart-0b85e941-5563-4347-af25-1d29a85f87a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494052001 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.1494052001 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.980821167 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 3227473253 ps |
| CPU time | 226.12 seconds |
| Started | Jul 09 07:50:18 PM PDT 24 |
| Finished | Jul 09 07:54:05 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-1b368553-de69-4825-9412-fde0841bb6d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980821167 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.980821167 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.522282218 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 2447020424 ps |
| CPU time | 318.79 seconds |
| Started | Jul 09 07:55:42 PM PDT 24 |
| Finished | Jul 09 08:01:04 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-f7aff752-378e-42ad-8516-0c6be3b0492e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522282218 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.522282218 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1070842078 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2895009677 ps |
| CPU time | 291.52 seconds |
| Started | Jul 09 07:53:01 PM PDT 24 |
| Finished | Jul 09 07:57:53 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-d399b13a-9e89-4c73-9da5-e2044b35b749 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1070842078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.1070842078 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.454618771 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 5428068270 ps |
| CPU time | 430.92 seconds |
| Started | Jul 09 07:58:05 PM PDT 24 |
| Finished | Jul 09 08:05:17 PM PDT 24 |
| Peak memory | 619684 kb |
| Host | smart-831ccec8-eaae-46e9-91fe-113f22a85828 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=454618771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.454618771 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2813287550 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 8526345596 ps |
| CPU time | 1952.08 seconds |
| Started | Jul 09 07:56:28 PM PDT 24 |
| Finished | Jul 09 08:29:01 PM PDT 24 |
| Peak memory | 610836 kb |
| Host | smart-89233453-5a3f-45d8-be16-9a01ca4516b6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2813287550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.2813287550 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.408035761 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 7694724208 ps |
| CPU time | 1790.86 seconds |
| Started | Jul 09 07:52:25 PM PDT 24 |
| Finished | Jul 09 08:22:18 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-9df2bfb2-cdef-4ed1-b48a-64ba25c6dbd7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408035761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_toggle.408035761 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1038146120 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 7908114662 ps |
| CPU time | 1378.22 seconds |
| Started | Jul 09 07:52:18 PM PDT 24 |
| Finished | Jul 09 08:15:18 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-c2b46e0c-47d6-4ba2-a638-0008f45264cb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1038146120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.1038146120 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.339769007 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 3987098700 ps |
| CPU time | 596.9 seconds |
| Started | Jul 09 07:52:37 PM PDT 24 |
| Finished | Jul 09 08:02:35 PM PDT 24 |
| Peak memory | 610488 kb |
| Host | smart-c152cd33-e011-4986-b9cf-00ac495b351f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=339769007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.339769007 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1518068997 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 254566364528 ps |
| CPU time | 12724.3 seconds |
| Started | Jul 09 07:50:30 PM PDT 24 |
| Finished | Jul 09 11:22:37 PM PDT 24 |
| Peak memory | 611188 kb |
| Host | smart-dae6f2ac-54d9-464e-aab5-fe2c9827346e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1518068997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1518068997 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.929186910 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 3204275760 ps |
| CPU time | 320.11 seconds |
| Started | Jul 09 07:53:08 PM PDT 24 |
| Finished | Jul 09 07:58:28 PM PDT 24 |
| Peak memory | 608816 kb |
| Host | smart-9c309ca8-7478-4344-b9e0-b4d101d5cc06 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929186910 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_alert_test.929186910 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.3901271425 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 3935487008 ps |
| CPU time | 511.74 seconds |
| Started | Jul 09 07:51:07 PM PDT 24 |
| Finished | Jul 09 07:59:40 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-1e325e04-5f07-406e-b4e0-41b24d14d295 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901271425 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.3901271425 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1872855931 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 7058872668 ps |
| CPU time | 581.54 seconds |
| Started | Jul 09 07:51:54 PM PDT 24 |
| Finished | Jul 09 08:01:37 PM PDT 24 |
| Peak memory | 610924 kb |
| Host | smart-26dd6df3-7f9d-4d19-8cff-90da896ca2a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1872855931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1872855931 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.433646591 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 3551424476 ps |
| CPU time | 322.4 seconds |
| Started | Jul 09 07:52:59 PM PDT 24 |
| Finished | Jul 09 07:58:21 PM PDT 24 |
| Peak memory | 608728 kb |
| Host | smart-7c72ca99-6422-42bc-b217-465890171adc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433646591 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_aon_timer_smoketest.433646591 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1005821509 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 8310807066 ps |
| CPU time | 686.89 seconds |
| Started | Jul 09 07:57:46 PM PDT 24 |
| Finished | Jul 09 08:09:13 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-d7fd1c1c-2dd8-4345-a5f6-3f10286731d7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1005821509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.1005821509 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3819401203 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 5397195198 ps |
| CPU time | 482.84 seconds |
| Started | Jul 09 07:51:07 PM PDT 24 |
| Finished | Jul 09 07:59:11 PM PDT 24 |
| Peak memory | 611068 kb |
| Host | smart-67ce0fee-b452-4fbf-ad47-04e681734bb8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3819401203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3819401203 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.4233232754 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 7764243996 ps |
| CPU time | 1248.24 seconds |
| Started | Jul 09 07:54:22 PM PDT 24 |
| Finished | Jul 09 08:15:11 PM PDT 24 |
| Peak memory | 616296 kb |
| Host | smart-edcda1f5-a9d4-4d4c-83ad-46d31486118a |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233232754 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.4233232754 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2366195470 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 11017597344 ps |
| CPU time | 1017.74 seconds |
| Started | Jul 09 07:50:43 PM PDT 24 |
| Finished | Jul 09 08:07:42 PM PDT 24 |
| Peak memory | 623508 kb |
| Host | smart-72c738db-ecb4-4b4d-8f4f-470b369b29ad |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2366195470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.2366195470 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.271477885 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 3819887880 ps |
| CPU time | 539.79 seconds |
| Started | Jul 09 07:54:49 PM PDT 24 |
| Finished | Jul 09 08:03:49 PM PDT 24 |
| Peak memory | 613100 kb |
| Host | smart-1fa9ac42-9952-4056-a417-89ac011d7b6d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271477885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.271477885 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3091335214 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 3596702120 ps |
| CPU time | 518.99 seconds |
| Started | Jul 09 07:51:24 PM PDT 24 |
| Finished | Jul 09 08:00:04 PM PDT 24 |
| Peak memory | 613256 kb |
| Host | smart-e27d901c-6e61-4cc1-a6ff-d19d43ec688e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091335214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3091335214 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2197540505 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 4281781966 ps |
| CPU time | 802.03 seconds |
| Started | Jul 09 07:51:33 PM PDT 24 |
| Finished | Jul 09 08:04:56 PM PDT 24 |
| Peak memory | 613072 kb |
| Host | smart-66720760-b914-4f31-bcb2-8bcf67dedece |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197540505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2197540505 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2536829752 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 5230921040 ps |
| CPU time | 612.54 seconds |
| Started | Jul 09 07:52:21 PM PDT 24 |
| Finished | Jul 09 08:02:34 PM PDT 24 |
| Peak memory | 611856 kb |
| Host | smart-aab3e3dc-1dea-4f7c-ab4b-df081a0d7d1f |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536829752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2536829752 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.664311066 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 4110323320 ps |
| CPU time | 754.25 seconds |
| Started | Jul 09 07:53:03 PM PDT 24 |
| Finished | Jul 09 08:05:38 PM PDT 24 |
| Peak memory | 613216 kb |
| Host | smart-88640f25-16c8-487a-b973-4daaff842cea |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664311066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.664311066 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3706375210 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 2453403998 ps |
| CPU time | 263.68 seconds |
| Started | Jul 09 07:50:43 PM PDT 24 |
| Finished | Jul 09 07:55:08 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-80ea7915-59b3-4fc9-9048-162877337159 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706375210 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.3706375210 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2703344714 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 3152104504 ps |
| CPU time | 515.41 seconds |
| Started | Jul 09 07:53:08 PM PDT 24 |
| Finished | Jul 09 08:01:44 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-b36ed489-7dcf-4fc3-927a-6724b6f59aec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703344714 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.2703344714 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1585993679 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 2247137245 ps |
| CPU time | 200.93 seconds |
| Started | Jul 09 07:54:58 PM PDT 24 |
| Finished | Jul 09 07:58:20 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-f00b9eed-4075-4dde-b0f7-88ddc3900259 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585993679 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.1585993679 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3622398659 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 4366223632 ps |
| CPU time | 492.03 seconds |
| Started | Jul 09 07:52:45 PM PDT 24 |
| Finished | Jul 09 08:00:58 PM PDT 24 |
| Peak memory | 610600 kb |
| Host | smart-49323398-2052-47b2-87fb-bd9afd60a9a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622398659 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.3622398659 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.344295456 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 4597802552 ps |
| CPU time | 466.27 seconds |
| Started | Jul 09 07:50:50 PM PDT 24 |
| Finished | Jul 09 07:58:37 PM PDT 24 |
| Peak memory | 610412 kb |
| Host | smart-56924cbe-f09a-445e-aecb-47ad66c98e60 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344295456 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.344295456 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.337102349 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 3777855416 ps |
| CPU time | 432.03 seconds |
| Started | Jul 09 07:53:02 PM PDT 24 |
| Finished | Jul 09 08:00:16 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-3138f4b8-a389-484c-8644-9d8baa909046 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337102349 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.337102349 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.312353283 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 5116772504 ps |
| CPU time | 547.32 seconds |
| Started | Jul 09 07:51:19 PM PDT 24 |
| Finished | Jul 09 08:00:27 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-a47e6267-c99c-43d5-ad89-b13fd468158a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312353283 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.312353283 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.4031166085 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 9660943278 ps |
| CPU time | 1418.15 seconds |
| Started | Jul 09 07:53:06 PM PDT 24 |
| Finished | Jul 09 08:16:45 PM PDT 24 |
| Peak memory | 611020 kb |
| Host | smart-1eb35059-1979-40eb-8fa9-a44771c704a6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031166085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.4031166085 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.4119851574 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 3322740270 ps |
| CPU time | 396.02 seconds |
| Started | Jul 09 07:51:25 PM PDT 24 |
| Finished | Jul 09 07:58:02 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-25dad0eb-da4e-4890-a503-0478642e5df6 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119851574 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.4119851574 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1019932038 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 4264637300 ps |
| CPU time | 515.9 seconds |
| Started | Jul 09 07:51:19 PM PDT 24 |
| Finished | Jul 09 07:59:56 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-32cecb77-b4d4-4f9e-bbc0-607500592b8e |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019932038 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.1019932038 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2900152332 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 2545015914 ps |
| CPU time | 263.33 seconds |
| Started | Jul 09 07:56:04 PM PDT 24 |
| Finished | Jul 09 08:00:29 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-36b821a8-7da2-4b36-ac39-1dc9b0327c39 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900152332 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.2900152332 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.1714165742 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 71539019180 ps |
| CPU time | 15156.1 seconds |
| Started | Jul 09 07:52:12 PM PDT 24 |
| Finished | Jul 10 12:04:51 AM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-246c31f2-f1c0-4ceb-a5ca-a7493e83ec8c |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1714165742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.1714165742 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3300918807 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 16851704608 ps |
| CPU time | 4064.36 seconds |
| Started | Jul 09 07:52:24 PM PDT 24 |
| Finished | Jul 09 09:00:10 PM PDT 24 |
| Peak memory | 610816 kb |
| Host | smart-1b57405b-4b77-4d42-bc70-9f3c703e55eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300918807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.3300918807 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1067234517 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 4183897000 ps |
| CPU time | 507.91 seconds |
| Started | Jul 09 07:51:21 PM PDT 24 |
| Finished | Jul 09 07:59:49 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-6c40c55e-aba7-4a4f-9c01-ea2963649150 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10672 34517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.1067234517 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.2555819415 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 2807991416 ps |
| CPU time | 192.87 seconds |
| Started | Jul 09 07:51:08 PM PDT 24 |
| Finished | Jul 09 07:54:21 PM PDT 24 |
| Peak memory | 609628 kb |
| Host | smart-70d1ea2a-243c-4f50-a484-573a79af61ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555819415 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.2555819415 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.522450911 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 5794051771 ps |
| CPU time | 700.09 seconds |
| Started | Jul 09 07:51:01 PM PDT 24 |
| Finished | Jul 09 08:02:42 PM PDT 24 |
| Peak memory | 611612 kb |
| Host | smart-62a544c6-5b0a-4d39-bc11-6cf36505719e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522450911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrn g_lc_hw_debug_en_test.522450911 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.3243224814 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 2932272538 ps |
| CPU time | 269.86 seconds |
| Started | Jul 09 07:57:20 PM PDT 24 |
| Finished | Jul 09 08:01:51 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-5e234c61-5f1a-4132-8fdd-ff1465f0edf1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243224814 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.3243224814 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1750087075 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 5225273472 ps |
| CPU time | 752.81 seconds |
| Started | Jul 09 07:50:16 PM PDT 24 |
| Finished | Jul 09 08:02:50 PM PDT 24 |
| Peak memory | 611272 kb |
| Host | smart-ce4fa7dc-9b18-4929-94c0-22aeff5a7c60 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1750087075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.1750087075 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.155828693 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 4177074990 ps |
| CPU time | 1053.45 seconds |
| Started | Jul 09 07:53:04 PM PDT 24 |
| Finished | Jul 09 08:10:38 PM PDT 24 |
| Peak memory | 609100 kb |
| Host | smart-536bb686-7c1a-4f92-bcc2-13629f93a001 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155828693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_a uto_mode.155828693 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1149861294 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 6789843743 ps |
| CPU time | 1324.4 seconds |
| Started | Jul 09 07:54:07 PM PDT 24 |
| Finished | Jul 09 08:16:12 PM PDT 24 |
| Peak memory | 611032 kb |
| Host | smart-8659f035-c3aa-42c4-9a91-8ee2b61e1cb4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149861294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.1149861294 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.3468167161 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 2913889500 ps |
| CPU time | 740.07 seconds |
| Started | Jul 09 07:52:11 PM PDT 24 |
| Finished | Jul 09 08:04:32 PM PDT 24 |
| Peak memory | 616876 kb |
| Host | smart-039fb343-f1d1-4536-9a3d-5e91aa206379 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468167161 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.3468167161 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.484287214 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 6590827500 ps |
| CPU time | 1433.74 seconds |
| Started | Jul 09 07:52:05 PM PDT 24 |
| Finished | Jul 09 08:16:00 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-7224841a-5dd6-4a67-8f44-d1fd0e664aa9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484287214 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.484287214 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3492308468 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 2813257638 ps |
| CPU time | 202.92 seconds |
| Started | Jul 09 07:52:03 PM PDT 24 |
| Finished | Jul 09 07:55:28 PM PDT 24 |
| Peak memory | 609024 kb |
| Host | smart-c91a53c5-0641-45b5-8cf6-e2150ec5da2c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34 92308468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.3492308468 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.876780518 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 2662596392 ps |
| CPU time | 220.02 seconds |
| Started | Jul 09 07:50:55 PM PDT 24 |
| Finished | Jul 09 07:54:35 PM PDT 24 |
| Peak memory | 609528 kb |
| Host | smart-3eea7775-a24c-49f0-a44d-2f1809780997 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876780518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.876780518 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.195841645 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 4250479436 ps |
| CPU time | 695.06 seconds |
| Started | Jul 09 07:56:10 PM PDT 24 |
| Finished | Jul 09 08:07:46 PM PDT 24 |
| Peak memory | 609472 kb |
| Host | smart-dd1cf1e7-c02e-41e2-9d9a-243cd74d1bba |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=195841645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.195841645 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.4174236984 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 3392822550 ps |
| CPU time | 271.13 seconds |
| Started | Jul 09 07:51:02 PM PDT 24 |
| Finished | Jul 09 07:55:35 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-1b613dea-4881-4641-bbee-8ec3fdbd0a3c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174236984 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.4174236984 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.3209763774 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 2334595640 ps |
| CPU time | 243.28 seconds |
| Started | Jul 09 07:52:40 PM PDT 24 |
| Finished | Jul 09 07:56:44 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-d6a3b54c-9abe-4d85-a9f4-3fe39ec3390b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209763774 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.3209763774 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.420455813 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 3219708600 ps |
| CPU time | 358.72 seconds |
| Started | Jul 09 07:50:23 PM PDT 24 |
| Finished | Jul 09 07:56:22 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-21b93835-e0c0-442d-bd9e-33ec424ce3d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420455813 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_example_manufacturer.420455813 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.1056691316 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 2267369260 ps |
| CPU time | 137.13 seconds |
| Started | Jul 09 07:48:04 PM PDT 24 |
| Finished | Jul 09 07:50:29 PM PDT 24 |
| Peak memory | 609836 kb |
| Host | smart-d3b709d0-23a4-41ac-87b4-ebe12df6ce08 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056691316 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.1056691316 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.394748638 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 59970910818 ps |
| CPU time | 11396.1 seconds |
| Started | Jul 09 07:50:13 PM PDT 24 |
| Finished | Jul 09 11:00:11 PM PDT 24 |
| Peak memory | 625104 kb |
| Host | smart-7ce251d8-94c7-4092-9b1a-e91fa24a183e |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=394748638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.394748638 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.4056946069 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 4567703832 ps |
| CPU time | 611.18 seconds |
| Started | Jul 09 07:51:14 PM PDT 24 |
| Finished | Jul 09 08:01:26 PM PDT 24 |
| Peak memory | 610912 kb |
| Host | smart-711a95bd-e347-4f24-9f6c-3e04d2c775d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=4056946069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.4056946069 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1796179763 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 6571661180 ps |
| CPU time | 1002.24 seconds |
| Started | Jul 09 07:48:46 PM PDT 24 |
| Finished | Jul 09 08:05:28 PM PDT 24 |
| Peak memory | 609044 kb |
| Host | smart-be015ad2-8e18-4e16-ae4e-ae02f6912525 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796179763 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.1796179763 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.710368433 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 6276117688 ps |
| CPU time | 1017.35 seconds |
| Started | Jul 09 07:50:11 PM PDT 24 |
| Finished | Jul 09 08:07:10 PM PDT 24 |
| Peak memory | 610332 kb |
| Host | smart-fff58d1c-3673-47f9-b21a-83abd966aa3c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710368433 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.710368433 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1792352815 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 7899349998 ps |
| CPU time | 1110.75 seconds |
| Started | Jul 09 07:53:33 PM PDT 24 |
| Finished | Jul 09 08:12:05 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-30984ab7-653a-4502-bee8-c90c66eaa5da |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792352815 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1792352815 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3253229876 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 5773548869 ps |
| CPU time | 1060.42 seconds |
| Started | Jul 09 07:50:09 PM PDT 24 |
| Finished | Jul 09 08:07:51 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-dd390ed5-c45e-4ecd-a7aa-95935d84731b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253229876 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.3253229876 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1763359120 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 3968448792 ps |
| CPU time | 450.4 seconds |
| Started | Jul 09 07:51:44 PM PDT 24 |
| Finished | Jul 09 07:59:16 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-274f320f-a2f6-4da9-aa42-806f61b0aeac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763359120 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.1763359120 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2639936870 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 5616460314 ps |
| CPU time | 1352.77 seconds |
| Started | Jul 09 07:53:00 PM PDT 24 |
| Finished | Jul 09 08:15:33 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-52a4b4cb-d468-41ac-9255-adfe024c1d4a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639936870 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.2639936870 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.12923325 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 3211470536 ps |
| CPU time | 278.96 seconds |
| Started | Jul 09 07:52:47 PM PDT 24 |
| Finished | Jul 09 07:57:27 PM PDT 24 |
| Peak memory | 609588 kb |
| Host | smart-09fd6a51-b9e2-461f-a4f7-1142d9004a7b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292332 5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.12923325 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.3592979479 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 20116701854 ps |
| CPU time | 2014.4 seconds |
| Started | Jul 09 07:49:23 PM PDT 24 |
| Finished | Jul 09 08:23:00 PM PDT 24 |
| Peak memory | 612636 kb |
| Host | smart-79b68efe-3817-4854-bc8c-dbff0bd7807c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592979479 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.3592979479 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.239097772 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 26551389833 ps |
| CPU time | 2336.56 seconds |
| Started | Jul 09 07:51:18 PM PDT 24 |
| Finished | Jul 09 08:30:16 PM PDT 24 |
| Peak memory | 614216 kb |
| Host | smart-aeb173e4-54df-4067-829b-b058bfebca9d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=239097772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.239097772 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.676693053 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 3479528768 ps |
| CPU time | 248.32 seconds |
| Started | Jul 09 07:55:50 PM PDT 24 |
| Finished | Jul 09 07:59:59 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-a6b6e337-f1fb-42a2-8915-22e994a613de |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=676693053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.676693053 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.204155795 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3687845902 ps |
| CPU time | 485.33 seconds |
| Started | Jul 09 07:50:54 PM PDT 24 |
| Finished | Jul 09 07:59:01 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-43662d0c-84ce-4b96-a4c4-07ddf455036e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204155795 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_gpio.204155795 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.2768315385 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2915849756 ps |
| CPU time | 278.64 seconds |
| Started | Jul 09 07:51:47 PM PDT 24 |
| Finished | Jul 09 07:56:26 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-43615066-be1a-4bf0-a65b-4f7542002e03 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768315385 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.2768315385 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.3097989786 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 3164444904 ps |
| CPU time | 387.19 seconds |
| Started | Jul 09 07:50:54 PM PDT 24 |
| Finished | Jul 09 07:57:23 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-61529174-a818-4f07-bcff-1e1e202fe8f5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097989786 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.3097989786 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3475141627 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 3058898065 ps |
| CPU time | 323.97 seconds |
| Started | Jul 09 07:52:17 PM PDT 24 |
| Finished | Jul 09 07:57:42 PM PDT 24 |
| Peak memory | 609588 kb |
| Host | smart-a0292d79-adc5-4be5-92d8-db6aabedc0dd |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475141627 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.3475141627 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2005319859 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 3200889598 ps |
| CPU time | 355.52 seconds |
| Started | Jul 09 07:56:19 PM PDT 24 |
| Finished | Jul 09 08:02:15 PM PDT 24 |
| Peak memory | 609496 kb |
| Host | smart-1e76d7d3-0d43-40b2-8b75-a6d2a1076fe7 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005319859 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.2005319859 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.1077189411 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 7278757472 ps |
| CPU time | 1817.86 seconds |
| Started | Jul 09 07:50:43 PM PDT 24 |
| Finished | Jul 09 08:21:01 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-23b4fe8a-a449-48a3-8f36-6b1356b4893f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077189411 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.1077189411 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.1162775226 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 3589581290 ps |
| CPU time | 424.09 seconds |
| Started | Jul 09 07:50:19 PM PDT 24 |
| Finished | Jul 09 07:57:24 PM PDT 24 |
| Peak memory | 610172 kb |
| Host | smart-d7f529c0-d923-44ba-9b31-2867c127c01d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162775226 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.1162775226 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.1732442398 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 3607571390 ps |
| CPU time | 262.19 seconds |
| Started | Jul 09 07:53:49 PM PDT 24 |
| Finished | Jul 09 07:58:12 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-ff2ce17e-bbff-4dc2-9264-b6dec9be6177 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732442398 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.1732442398 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.1789847320 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 62943535641 ps |
| CPU time | 11463.1 seconds |
| Started | Jul 09 07:48:55 PM PDT 24 |
| Finished | Jul 09 11:00:00 PM PDT 24 |
| Peak memory | 625132 kb |
| Host | smart-81da2a0f-6c47-43bb-bf0d-900c160194d4 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1789847320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.1789847320 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.4275086453 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 11338702128 ps |
| CPU time | 2061.43 seconds |
| Started | Jul 09 07:52:56 PM PDT 24 |
| Finished | Jul 09 08:27:19 PM PDT 24 |
| Peak memory | 618040 kb |
| Host | smart-9057cc49-b477-4ae4-8d2a-a270c1a519d2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275 086453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.4275086453 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2002837042 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 9610171390 ps |
| CPU time | 1501.62 seconds |
| Started | Jul 09 07:54:37 PM PDT 24 |
| Finished | Jul 09 08:19:40 PM PDT 24 |
| Peak memory | 618148 kb |
| Host | smart-34925c7d-fe8e-4a78-8533-b499eff0fba9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2002837042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2002837042 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3072433703 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 13103475654 ps |
| CPU time | 3003.62 seconds |
| Started | Jul 09 07:50:00 PM PDT 24 |
| Finished | Jul 09 08:40:05 PM PDT 24 |
| Peak memory | 617884 kb |
| Host | smart-3b6b21db-cc84-4e60-b14d-c59013906f39 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3072433703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.3072433703 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1266288370 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 9160448732 ps |
| CPU time | 2347.13 seconds |
| Started | Jul 09 07:53:45 PM PDT 24 |
| Finished | Jul 09 08:32:53 PM PDT 24 |
| Peak memory | 611252 kb |
| Host | smart-19b21952-b980-48fa-be51-a0690f5716df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126628 8370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.1266288370 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3362247926 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 8810479452 ps |
| CPU time | 1824.63 seconds |
| Started | Jul 09 07:54:47 PM PDT 24 |
| Finished | Jul 09 08:25:13 PM PDT 24 |
| Peak memory | 611232 kb |
| Host | smart-12090032-e336-4f28-aa3e-0b63e8a0e067 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33622 47926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.3362247926 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.2066714197 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 2601192614 ps |
| CPU time | 198.12 seconds |
| Started | Jul 09 07:51:29 PM PDT 24 |
| Finished | Jul 09 07:54:49 PM PDT 24 |
| Peak memory | 608748 kb |
| Host | smart-d5aeb012-ec28-4293-bdb8-16c3074c1ebb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066714197 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.2066714197 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.980008704 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 3351302316 ps |
| CPU time | 330.67 seconds |
| Started | Jul 09 07:55:23 PM PDT 24 |
| Finished | Jul 09 08:00:56 PM PDT 24 |
| Peak memory | 609532 kb |
| Host | smart-0442d1e3-a7fa-4ea8-9864-3836dad35958 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980008704 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_entropy.980008704 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.1772857073 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 2562595034 ps |
| CPU time | 270.04 seconds |
| Started | Jul 09 07:51:19 PM PDT 24 |
| Finished | Jul 09 07:55:50 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-22cf301c-a802-4743-92d0-146574185f92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772857073 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.1772857073 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3045057667 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 2220430180 ps |
| CPU time | 227.6 seconds |
| Started | Jul 09 07:52:38 PM PDT 24 |
| Finished | Jul 09 07:56:26 PM PDT 24 |
| Peak memory | 608912 kb |
| Host | smart-86defab6-d788-4668-9348-1f99034e15c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045057667 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.3045057667 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.726141447 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 2762093544 ps |
| CPU time | 339.84 seconds |
| Started | Jul 09 07:52:32 PM PDT 24 |
| Finished | Jul 09 07:58:13 PM PDT 24 |
| Peak memory | 608672 kb |
| Host | smart-8c8882f6-8268-448e-9b22-73eed38f5c6f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726141447 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_kmac_mode_kmac.726141447 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3206894986 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 2432189502 ps |
| CPU time | 304.89 seconds |
| Started | Jul 09 07:51:33 PM PDT 24 |
| Finished | Jul 09 07:56:39 PM PDT 24 |
| Peak memory | 608896 kb |
| Host | smart-35a51b32-0cd2-4359-9968-963583a8580a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206894986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.3206894986 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3046464607 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 3204829169 ps |
| CPU time | 265.82 seconds |
| Started | Jul 09 07:54:21 PM PDT 24 |
| Finished | Jul 09 07:58:47 PM PDT 24 |
| Peak memory | 609592 kb |
| Host | smart-76e9ac0d-5fc5-4cc5-839a-e9b1485570d9 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30464646 07 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3046464607 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.233771459 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 3113248084 ps |
| CPU time | 334.28 seconds |
| Started | Jul 09 07:54:53 PM PDT 24 |
| Finished | Jul 09 08:00:29 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-96cbac0c-81c6-4943-977e-08a664086f49 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233771459 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_smoketest.233771459 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.479787504 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 2742611730 ps |
| CPU time | 248.09 seconds |
| Started | Jul 09 07:50:01 PM PDT 24 |
| Finished | Jul 09 07:54:10 PM PDT 24 |
| Peak memory | 608732 kb |
| Host | smart-30b60a51-6f25-4355-b630-2d2caea1e20d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479787504 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.479787504 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.36986847 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 2781791070 ps |
| CPU time | 162.14 seconds |
| Started | Jul 09 07:50:41 PM PDT 24 |
| Finished | Jul 09 07:53:25 PM PDT 24 |
| Peak memory | 621040 kb |
| Host | smart-752960fb-cfd8-43c7-a4dd-99efa19e67d7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36986847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.36986847 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1812964370 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 4161285206 ps |
| CPU time | 327.51 seconds |
| Started | Jul 09 07:53:13 PM PDT 24 |
| Finished | Jul 09 07:58:42 PM PDT 24 |
| Peak memory | 621276 kb |
| Host | smart-18e86e65-05ec-430d-9c09-1f670f3fbc97 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812964370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.1812964370 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1510028618 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 2943530020 ps |
| CPU time | 133.38 seconds |
| Started | Jul 09 07:51:52 PM PDT 24 |
| Finished | Jul 09 07:54:06 PM PDT 24 |
| Peak memory | 620104 kb |
| Host | smart-407bd656-be6e-4834-9fdc-941acb35235a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1510028618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.1510028618 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2038688408 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 10673450985 ps |
| CPU time | 1034.52 seconds |
| Started | Jul 09 07:49:11 PM PDT 24 |
| Finished | Jul 09 08:06:27 PM PDT 24 |
| Peak memory | 625016 kb |
| Host | smart-a37796c2-e567-4588-ab82-99ba9e8e8f37 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038688408 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.2038688408 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.641256897 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 2502419190 ps |
| CPU time | 106.8 seconds |
| Started | Jul 09 07:52:09 PM PDT 24 |
| Finished | Jul 09 07:53:57 PM PDT 24 |
| Peak memory | 616872 kb |
| Host | smart-2fc2d107-6fce-4769-9c27-26c96cdd1425 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=641256897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.641256897 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1196637419 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 2115755561 ps |
| CPU time | 114.87 seconds |
| Started | Jul 09 07:52:32 PM PDT 24 |
| Finished | Jul 09 07:54:30 PM PDT 24 |
| Peak memory | 618152 kb |
| Host | smart-e31357d1-dc6f-4c2d-a9ff-0dad923be0b8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196637419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1196637419 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2636790870 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 51326569752 ps |
| CPU time | 5845.19 seconds |
| Started | Jul 09 07:49:55 PM PDT 24 |
| Finished | Jul 09 09:27:22 PM PDT 24 |
| Peak memory | 619392 kb |
| Host | smart-f3b3eabe-22bb-47cf-82b8-7750320a4435 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636790870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.2636790870 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3885581075 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 10520320454 ps |
| CPU time | 1222.09 seconds |
| Started | Jul 09 07:53:21 PM PDT 24 |
| Finished | Jul 09 08:13:46 PM PDT 24 |
| Peak memory | 620424 kb |
| Host | smart-99935002-f7a5-4081-adf3-0f20b63de6ed |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885581075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.3885581075 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3367253190 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 49737747920 ps |
| CPU time | 5447.54 seconds |
| Started | Jul 09 07:56:59 PM PDT 24 |
| Finished | Jul 09 09:27:48 PM PDT 24 |
| Peak memory | 619452 kb |
| Host | smart-dc6394ba-0693-4916-971b-b0a98bcf47a6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367253190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.3367253190 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.382895520 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 29646428360 ps |
| CPU time | 2400.98 seconds |
| Started | Jul 09 07:49:24 PM PDT 24 |
| Finished | Jul 09 08:29:26 PM PDT 24 |
| Peak memory | 620212 kb |
| Host | smart-c0db7df8-f017-4fa4-84a1-aa4395b6f9c9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=382895520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testunl ocks.382895520 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.660583444 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 16795601720 ps |
| CPU time | 3647.97 seconds |
| Started | Jul 09 07:50:45 PM PDT 24 |
| Finished | Jul 09 08:51:35 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-2b42c355-ad4a-43c3-946b-6a2da90cdc3d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=660583444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.660583444 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.782343192 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 18634285366 ps |
| CPU time | 3773.42 seconds |
| Started | Jul 09 07:52:31 PM PDT 24 |
| Finished | Jul 09 08:55:26 PM PDT 24 |
| Peak memory | 610560 kb |
| Host | smart-d38dab08-1d70-4479-bed3-79cba008b259 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=782343192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.782343192 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.764399694 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 25203007608 ps |
| CPU time | 3980.78 seconds |
| Started | Jul 09 07:53:15 PM PDT 24 |
| Finished | Jul 09 08:59:37 PM PDT 24 |
| Peak memory | 610832 kb |
| Host | smart-298e8cb0-7238-4be0-9eac-757d6ffe7d1d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764399694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.764399694 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.4044477153 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 3999695124 ps |
| CPU time | 544.36 seconds |
| Started | Jul 09 07:52:27 PM PDT 24 |
| Finished | Jul 09 08:01:33 PM PDT 24 |
| Peak memory | 609048 kb |
| Host | smart-b031d73f-ce99-4243-a3cc-44372d90728f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044477153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.4044477153 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.2412468780 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 6215668632 ps |
| CPU time | 919.2 seconds |
| Started | Jul 09 07:53:23 PM PDT 24 |
| Finished | Jul 09 08:08:43 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-5dbe2e8f-04e7-426c-800c-ca2e374c60b6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2412468780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.2412468780 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.3949022984 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 11700787040 ps |
| CPU time | 2298.51 seconds |
| Started | Jul 09 07:52:16 PM PDT 24 |
| Finished | Jul 09 08:30:36 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-b00f5782-319c-4937-9624-7d0982bed24e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949022984 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.3949022984 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2841007934 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 27403740000 ps |
| CPU time | 5033.77 seconds |
| Started | Jul 09 07:51:28 PM PDT 24 |
| Finished | Jul 09 09:15:24 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-d6d6ee24-e01a-4836-b9e8-473dd5d748e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284100 7934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.2841007934 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3942652343 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 2752663076 ps |
| CPU time | 220.71 seconds |
| Started | Jul 09 07:49:10 PM PDT 24 |
| Finished | Jul 09 07:52:52 PM PDT 24 |
| Peak memory | 608896 kb |
| Host | smart-730f7255-667e-4bbc-a8dd-a951a58e15bd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942652343 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.3942652343 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1997751871 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 8531425224 ps |
| CPU time | 1200.65 seconds |
| Started | Jul 09 07:53:14 PM PDT 24 |
| Finished | Jul 09 08:13:16 PM PDT 24 |
| Peak memory | 610828 kb |
| Host | smart-ab6b6962-6f50-48d1-9180-e153eb6d9594 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1997751871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.1997751871 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2342514940 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 7231187480 ps |
| CPU time | 1081.72 seconds |
| Started | Jul 09 07:49:27 PM PDT 24 |
| Finished | Jul 09 08:07:29 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-d2f15f2a-479f-4178-b4d2-fa0aa589bd70 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2342514940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.2342514940 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1815748708 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 7522534732 ps |
| CPU time | 1186.63 seconds |
| Started | Jul 09 07:51:28 PM PDT 24 |
| Finished | Jul 09 08:11:16 PM PDT 24 |
| Peak memory | 610808 kb |
| Host | smart-9771713f-8533-4f00-990b-7a2c097ecf15 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1815748708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.1815748708 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2898710859 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 3672675060 ps |
| CPU time | 500.17 seconds |
| Started | Jul 09 07:49:30 PM PDT 24 |
| Finished | Jul 09 07:57:50 PM PDT 24 |
| Peak memory | 608800 kb |
| Host | smart-7b20796c-c581-4c3a-8588-afd359dd50c2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2898710859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2898710859 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1793600126 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 2986143456 ps |
| CPU time | 303.31 seconds |
| Started | Jul 09 07:57:00 PM PDT 24 |
| Finished | Jul 09 08:02:04 PM PDT 24 |
| Peak memory | 608760 kb |
| Host | smart-24a8c041-a415-4637-83a0-f4b21fd1f4a9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793600126 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.1793600126 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.1199767758 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2709470512 ps |
| CPU time | 258.7 seconds |
| Started | Jul 09 07:48:14 PM PDT 24 |
| Finished | Jul 09 07:52:34 PM PDT 24 |
| Peak memory | 613384 kb |
| Host | smart-7f88d393-4ae3-4170-86c3-bc0458666969 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199767758 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.1199767758 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.1780640487 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 4921463464 ps |
| CPU time | 626.34 seconds |
| Started | Jul 09 07:53:36 PM PDT 24 |
| Finished | Jul 09 08:04:03 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-051dd44f-3595-4cd6-93b4-a922c5f0f3e3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780640487 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.1780640487 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.764671382 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 4935438056 ps |
| CPU time | 420.28 seconds |
| Started | Jul 09 07:52:04 PM PDT 24 |
| Finished | Jul 09 07:59:06 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-ef12ff6b-3d3d-41c4-a6b2-a97340258941 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764671382 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.764671382 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_virus.2690622382 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 4710192268 ps |
| CPU time | 1378.77 seconds |
| Started | Jul 09 07:57:32 PM PDT 24 |
| Finished | Jul 09 08:20:31 PM PDT 24 |
| Peak memory | 625316 kb |
| Host | smart-87333311-523c-4725-a8f3-29d4a382d408 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device= sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_ regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2690622382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.2690622382 |
| Directory | /workspace/0.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.4166829564 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 8887886639 ps |
| CPU time | 1056.87 seconds |
| Started | Jul 09 07:51:15 PM PDT 24 |
| Finished | Jul 09 08:08:53 PM PDT 24 |
| Peak memory | 611556 kb |
| Host | smart-2c376cad-3b27-4f2b-a768-2eaf77d0f6ab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166 829564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.4166829564 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.641245629 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 22282215282 ps |
| CPU time | 2552.71 seconds |
| Started | Jul 09 07:54:18 PM PDT 24 |
| Finished | Jul 09 08:36:52 PM PDT 24 |
| Peak memory | 611064 kb |
| Host | smart-d42ffcbd-18c6-45a0-a897-ea03403ce1b8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641 245629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.641245629 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3688864508 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 6992580206 ps |
| CPU time | 629.7 seconds |
| Started | Jul 09 07:50:54 PM PDT 24 |
| Finished | Jul 09 08:01:25 PM PDT 24 |
| Peak memory | 611048 kb |
| Host | smart-3dc48aca-96a0-464b-b013-8887262d3185 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688864508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.3688864508 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3302807444 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 6518856862 ps |
| CPU time | 439.81 seconds |
| Started | Jul 09 07:49:41 PM PDT 24 |
| Finished | Jul 09 07:57:02 PM PDT 24 |
| Peak memory | 616468 kb |
| Host | smart-849a05f4-cd01-4a94-bd1c-127f6d144a47 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3302807444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3302807444 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1343004241 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 4084250769 ps |
| CPU time | 327.64 seconds |
| Started | Jul 09 07:51:34 PM PDT 24 |
| Finished | Jul 09 07:57:03 PM PDT 24 |
| Peak memory | 616052 kb |
| Host | smart-ba42ccbe-3fb6-4cae-b761-8a6373fff090 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1343004241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.1343004241 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2085759979 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 10782209154 ps |
| CPU time | 1513.17 seconds |
| Started | Jul 09 07:52:29 PM PDT 24 |
| Finished | Jul 09 08:17:44 PM PDT 24 |
| Peak memory | 611556 kb |
| Host | smart-1143c493-14d5-4c4d-a6e7-5c7b83024a2e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085759979 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2085759979 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3943646399 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 7058351756 ps |
| CPU time | 753.87 seconds |
| Started | Jul 09 07:50:36 PM PDT 24 |
| Finished | Jul 09 08:03:10 PM PDT 24 |
| Peak memory | 610912 kb |
| Host | smart-e10220ea-4d6f-4b65-a78f-ba22867bde23 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943646399 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.3943646399 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2079530082 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 25580920745 ps |
| CPU time | 1527.07 seconds |
| Started | Jul 09 07:49:39 PM PDT 24 |
| Finished | Jul 09 08:15:08 PM PDT 24 |
| Peak memory | 611300 kb |
| Host | smart-f4b8b220-273c-4e84-af10-9dd0c2738964 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2079530082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2079530082 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.779087560 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 23313539688 ps |
| CPU time | 1676.57 seconds |
| Started | Jul 09 07:52:30 PM PDT 24 |
| Finished | Jul 09 08:20:28 PM PDT 24 |
| Peak memory | 610952 kb |
| Host | smart-5aedc179-a07a-45ff-a020-1c9ff6e72355 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=779087560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.779087560 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1740764456 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 2772803288 ps |
| CPU time | 229.44 seconds |
| Started | Jul 09 07:49:20 PM PDT 24 |
| Finished | Jul 09 07:53:11 PM PDT 24 |
| Peak memory | 610020 kb |
| Host | smart-a76c3428-7b99-4eae-b09d-c888e0733265 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740764456 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.1740764456 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3647644700 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 4456981608 ps |
| CPU time | 436.18 seconds |
| Started | Jul 09 07:50:13 PM PDT 24 |
| Finished | Jul 09 07:57:30 PM PDT 24 |
| Peak memory | 617716 kb |
| Host | smart-70dbe99b-d5af-4b9c-a258-64ac01320e21 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3647644700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.3647644700 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.996545871 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 5427456128 ps |
| CPU time | 442.79 seconds |
| Started | Jul 09 07:51:49 PM PDT 24 |
| Finished | Jul 09 07:59:12 PM PDT 24 |
| Peak memory | 609032 kb |
| Host | smart-06f8e7ee-d396-4b51-9c07-c138fbcd189b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99654587 1 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.996545871 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1535489503 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 6648283400 ps |
| CPU time | 675.72 seconds |
| Started | Jul 09 07:54:29 PM PDT 24 |
| Finished | Jul 09 08:05:45 PM PDT 24 |
| Peak memory | 611124 kb |
| Host | smart-0498f4b8-fb5f-4b38-85bb-50e894e289d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1535489503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.1535489503 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3212138279 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 6428501242 ps |
| CPU time | 534.89 seconds |
| Started | Jul 09 08:01:29 PM PDT 24 |
| Finished | Jul 09 08:10:24 PM PDT 24 |
| Peak memory | 609520 kb |
| Host | smart-450bc5e0-d60d-484a-b7cb-7a9fd56c3013 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212138279 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.3212138279 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3405012368 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 8177309000 ps |
| CPU time | 1044.64 seconds |
| Started | Jul 09 07:51:48 PM PDT 24 |
| Finished | Jul 09 08:09:14 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-0a579942-8ef1-4af5-9e20-609ae5618ca0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405012368 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.3405012368 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3637798918 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 5011588176 ps |
| CPU time | 349.22 seconds |
| Started | Jul 09 07:50:00 PM PDT 24 |
| Finished | Jul 09 07:55:51 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-8961bcdf-86a5-4499-9fe6-6bc7711f089f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637798918 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3637798918 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3561861875 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5921878214 ps |
| CPU time | 553.38 seconds |
| Started | Jul 09 07:53:41 PM PDT 24 |
| Finished | Jul 09 08:02:56 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-c6a154b8-2dba-41e1-a1b5-a6dd07e1daa0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561861875 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.3561861875 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.4063654334 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 4227787460 ps |
| CPU time | 538.52 seconds |
| Started | Jul 09 07:50:07 PM PDT 24 |
| Finished | Jul 09 07:59:06 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-857a3173-3f38-437d-adcf-f5fc329bf6a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406 3654334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.4063654334 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1682694571 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 9759094353 ps |
| CPU time | 618.11 seconds |
| Started | Jul 09 07:58:24 PM PDT 24 |
| Finished | Jul 09 08:08:43 PM PDT 24 |
| Peak memory | 617852 kb |
| Host | smart-5d8b4219-62e9-4413-b39c-5c7b6b107212 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682694571 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.1682694571 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3527976504 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 14245017680 ps |
| CPU time | 2092.76 seconds |
| Started | Jul 09 07:56:45 PM PDT 24 |
| Finished | Jul 09 08:31:39 PM PDT 24 |
| Peak memory | 610988 kb |
| Host | smart-9524323a-031b-4ddf-9f90-cbe1ccbfdfea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3527976504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.3527976504 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1553568898 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 4746201800 ps |
| CPU time | 661.91 seconds |
| Started | Jul 09 07:49:34 PM PDT 24 |
| Finished | Jul 09 08:00:36 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-8531ad4d-2c6b-45c3-82b3-6d66aa83b4a0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553568898 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.1553568898 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2618505138 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 6365091906 ps |
| CPU time | 862.49 seconds |
| Started | Jul 09 07:50:21 PM PDT 24 |
| Finished | Jul 09 08:04:44 PM PDT 24 |
| Peak memory | 641788 kb |
| Host | smart-4db9bafa-c3f5-4858-9c72-08502e198996 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2618505138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.2618505138 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.103896301 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 2993341094 ps |
| CPU time | 203.88 seconds |
| Started | Jul 09 07:53:06 PM PDT 24 |
| Finished | Jul 09 07:56:31 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-a895589a-bdb1-475b-a1d4-cc8161e797a5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103896301 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_rstmgr_smoketest.103896301 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.296500577 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 4491164388 ps |
| CPU time | 372.96 seconds |
| Started | Jul 09 07:51:51 PM PDT 24 |
| Finished | Jul 09 07:58:05 PM PDT 24 |
| Peak memory | 609332 kb |
| Host | smart-ff3a2617-9002-47fd-b4fb-1875f4d085f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296500577 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rstmgr_sw_req.296500577 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.56520245 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 2587855280 ps |
| CPU time | 206.27 seconds |
| Started | Jul 09 07:49:44 PM PDT 24 |
| Finished | Jul 09 07:53:11 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-e99dbbea-6fac-4e55-913b-4bdf02b82318 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56520245 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.56520245 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3451034877 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2380851445 ps |
| CPU time | 217.49 seconds |
| Started | Jul 09 07:52:12 PM PDT 24 |
| Finished | Jul 09 07:55:51 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-de6319cf-5732-4305-8243-85dbf2fe7ba2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451034877 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.3451034877 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.550458815 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 4931453554 ps |
| CPU time | 895.38 seconds |
| Started | Jul 09 07:50:56 PM PDT 24 |
| Finished | Jul 09 08:05:53 PM PDT 24 |
| Peak memory | 609560 kb |
| Host | smart-566037fa-4c09-41ec-bb55-1b2d2aeed74b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55045 8815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.550458815 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1404574913 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 5098151976 ps |
| CPU time | 1053.92 seconds |
| Started | Jul 09 07:52:31 PM PDT 24 |
| Finished | Jul 09 08:10:07 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-ef4ae556-dc92-4b29-b15a-448e3b30f5ad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1404574913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.1404574913 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.3993359479 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 6096167080 ps |
| CPU time | 544.11 seconds |
| Started | Jul 09 07:52:42 PM PDT 24 |
| Finished | Jul 09 08:01:47 PM PDT 24 |
| Peak memory | 621564 kb |
| Host | smart-c532d8dd-28e8-4755-80f4-6644edacb4ad |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993359479 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.3993359479 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.4187017603 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 3195596910 ps |
| CPU time | 265.68 seconds |
| Started | Jul 09 07:57:19 PM PDT 24 |
| Finished | Jul 09 08:01:46 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-ef8a4b74-5a12-4e0b-96d6-5ef7ca821542 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187017603 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.4187017603 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.2071674385 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 3484616932 ps |
| CPU time | 312.68 seconds |
| Started | Jul 09 07:49:22 PM PDT 24 |
| Finished | Jul 09 07:54:35 PM PDT 24 |
| Peak memory | 608764 kb |
| Host | smart-40f96e03-1d81-4513-a356-adac4972b7d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071674385 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.2071674385 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.12850136 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 2798241570 ps |
| CPU time | 247.68 seconds |
| Started | Jul 09 07:53:41 PM PDT 24 |
| Finished | Jul 09 07:57:50 PM PDT 24 |
| Peak memory | 608756 kb |
| Host | smart-afc6f2e8-04e5-4522-8295-3c606c790bcd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12850136 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rv_timer_smoketest.12850136 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3799745296 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 5593434118 ps |
| CPU time | 764.23 seconds |
| Started | Jul 09 07:50:50 PM PDT 24 |
| Finished | Jul 09 08:03:36 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-255fcf10-b6d6-4fe9-b155-67b4b03a203d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37997452 96 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.3799745296 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3901399729 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 2573601722 ps |
| CPU time | 196.54 seconds |
| Started | Jul 09 07:52:24 PM PDT 24 |
| Finished | Jul 09 07:55:42 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-8647d231-7f4c-4838-be9d-b28b92081c7b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901399 729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.3901399729 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.105783179 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 8521837920 ps |
| CPU time | 1391.88 seconds |
| Started | Jul 09 07:49:14 PM PDT 24 |
| Finished | Jul 09 08:12:27 PM PDT 24 |
| Peak memory | 610844 kb |
| Host | smart-5fa8dc36-525c-4e4d-8351-19dd865c3192 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105783179 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.105783179 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1392686997 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 7379349576 ps |
| CPU time | 743.67 seconds |
| Started | Jul 09 07:51:48 PM PDT 24 |
| Finished | Jul 09 08:04:12 PM PDT 24 |
| Peak memory | 610744 kb |
| Host | smart-b27d06cb-6c13-43d1-968e-2e81db136457 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392686997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.1392686997 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2209374037 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 7461447432 ps |
| CPU time | 669.92 seconds |
| Started | Jul 09 07:53:38 PM PDT 24 |
| Finished | Jul 09 08:04:49 PM PDT 24 |
| Peak memory | 611008 kb |
| Host | smart-41a3fc32-3b59-4211-9059-e87b9d07d656 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209374037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.2209374037 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.487289244 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 7765854218 ps |
| CPU time | 979.93 seconds |
| Started | Jul 09 07:52:33 PM PDT 24 |
| Finished | Jul 09 08:08:55 PM PDT 24 |
| Peak memory | 625188 kb |
| Host | smart-f401583d-2ed4-42f0-8285-dd85cd8018f6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487289244 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.487289244 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3678317570 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 4119842762 ps |
| CPU time | 539.15 seconds |
| Started | Jul 09 07:55:11 PM PDT 24 |
| Finished | Jul 09 08:04:11 PM PDT 24 |
| Peak memory | 625164 kb |
| Host | smart-c0397740-6818-4591-a1bc-e6af74450b3f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678317570 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.3678317570 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.3468962872 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2996865543 ps |
| CPU time | 351.35 seconds |
| Started | Jul 09 07:53:07 PM PDT 24 |
| Finished | Jul 09 07:58:59 PM PDT 24 |
| Peak memory | 618760 kb |
| Host | smart-f7387816-edfa-4560-b8f1-5554898bc35b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468962872 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.3468962872 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3574909021 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 4252235800 ps |
| CPU time | 697.61 seconds |
| Started | Jul 09 07:51:17 PM PDT 24 |
| Finished | Jul 09 08:02:56 PM PDT 24 |
| Peak memory | 610532 kb |
| Host | smart-871f41f3-d8a8-4752-9843-7e893130a944 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574909021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.3574909021 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2644807102 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 4853064758 ps |
| CPU time | 539.59 seconds |
| Started | Jul 09 07:51:16 PM PDT 24 |
| Finished | Jul 09 08:00:16 PM PDT 24 |
| Peak memory | 611120 kb |
| Host | smart-b38b384c-fdc0-4c9c-9153-b17b4b4226ae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644807102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2644807102 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2785375832 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 5071182707 ps |
| CPU time | 475.19 seconds |
| Started | Jul 09 07:53:33 PM PDT 24 |
| Finished | Jul 09 08:01:29 PM PDT 24 |
| Peak memory | 611148 kb |
| Host | smart-cb7c34cb-b273-408e-a8fd-5bb81797df13 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785375832 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2785375832 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.455451179 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 3343438584 ps |
| CPU time | 253.17 seconds |
| Started | Jul 09 07:55:18 PM PDT 24 |
| Finished | Jul 09 07:59:32 PM PDT 24 |
| Peak memory | 608776 kb |
| Host | smart-bc159a46-4a3b-4beb-b9b7-541525d14549 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455451179 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_sram_ctrl_smoketest.455451179 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1332269441 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 20593613472 ps |
| CPU time | 3515.44 seconds |
| Started | Jul 09 07:54:53 PM PDT 24 |
| Finished | Jul 09 08:53:30 PM PDT 24 |
| Peak memory | 610920 kb |
| Host | smart-3a8925ff-e9f0-46f1-a7d4-b4ca22eed292 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332269441 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.1332269441 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3323878706 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 4994798347 ps |
| CPU time | 709.07 seconds |
| Started | Jul 09 07:52:22 PM PDT 24 |
| Finished | Jul 09 08:04:15 PM PDT 24 |
| Peak memory | 614148 kb |
| Host | smart-114c9e29-e71e-485b-ac90-bad42a839407 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323878706 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.3323878706 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3626977598 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2855120142 ps |
| CPU time | 267.69 seconds |
| Started | Jul 09 07:53:29 PM PDT 24 |
| Finished | Jul 09 07:57:59 PM PDT 24 |
| Peak memory | 613504 kb |
| Host | smart-706615ec-d195-41da-aefd-fd87e8a570e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626977598 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.3626977598 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.219479643 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 3279690448 ps |
| CPU time | 421.69 seconds |
| Started | Jul 09 07:52:21 PM PDT 24 |
| Finished | Jul 09 07:59:24 PM PDT 24 |
| Peak memory | 609072 kb |
| Host | smart-373c5a64-4b58-49b9-8071-bd5910d0899e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219479643 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.219479643 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3230678800 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 24632768804 ps |
| CPU time | 1394.27 seconds |
| Started | Jul 09 07:52:42 PM PDT 24 |
| Finished | Jul 09 08:15:57 PM PDT 24 |
| Peak memory | 615152 kb |
| Host | smart-85f358c8-4d02-4095-8f74-1a2ed32ecbf4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32306788 00 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.3230678800 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3441153061 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5729365300 ps |
| CPU time | 474.95 seconds |
| Started | Jul 09 07:50:09 PM PDT 24 |
| Finished | Jul 09 07:58:06 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-50e6738e-82b1-4fae-bb73-dc107e56358b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441153061 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3441153061 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2785796108 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 3574365474 ps |
| CPU time | 685.67 seconds |
| Started | Jul 09 07:51:34 PM PDT 24 |
| Finished | Jul 09 08:03:01 PM PDT 24 |
| Peak memory | 619016 kb |
| Host | smart-56191841-2fdb-4237-b39a-9c9bd68101b4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2785796108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.2785796108 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.2495266236 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 3000145636 ps |
| CPU time | 287.8 seconds |
| Started | Jul 09 07:52:56 PM PDT 24 |
| Finished | Jul 09 07:57:45 PM PDT 24 |
| Peak memory | 616456 kb |
| Host | smart-688bcc9b-0a0b-4aa4-a601-bfb02796b002 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495266236 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.2495266236 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.64208097 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 8245429313 ps |
| CPU time | 1714.79 seconds |
| Started | Jul 09 07:48:26 PM PDT 24 |
| Finished | Jul 09 08:17:02 PM PDT 24 |
| Peak memory | 624936 kb |
| Host | smart-5282f8d9-c656-4ac2-a4c5-fbeeef942803 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64208097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_bau drate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_a lt_clk_freq.64208097 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3500366461 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 8772941709 ps |
| CPU time | 1160.94 seconds |
| Started | Jul 09 07:53:06 PM PDT 24 |
| Finished | Jul 09 08:12:29 PM PDT 24 |
| Peak memory | 624952 kb |
| Host | smart-9fd54eb9-d879-48a3-9227-b8c96961a399 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500366461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3500366461 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2169304914 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 3990633280 ps |
| CPU time | 616.56 seconds |
| Started | Jul 09 07:49:05 PM PDT 24 |
| Finished | Jul 09 07:59:23 PM PDT 24 |
| Peak memory | 622696 kb |
| Host | smart-b352ccae-644e-4613-b44d-194c1abb7ba6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169304914 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.2169304914 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.652723376 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 4631704334 ps |
| CPU time | 734.97 seconds |
| Started | Jul 09 07:50:03 PM PDT 24 |
| Finished | Jul 09 08:02:19 PM PDT 24 |
| Peak memory | 622912 kb |
| Host | smart-da34ebf5-f36f-4bb4-b4e4-551c5a43f1ce |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652723376 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.652723376 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3778688314 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 3664914527 ps |
| CPU time | 373.08 seconds |
| Started | Jul 09 07:52:46 PM PDT 24 |
| Finished | Jul 09 07:59:00 PM PDT 24 |
| Peak memory | 609344 kb |
| Host | smart-8d2a3612-e6c1-4d00-92a2-a9625fe6573a |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778688314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.3778688314 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.3248429279 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 12224301628 ps |
| CPU time | 2958.33 seconds |
| Started | Jul 09 07:49:03 PM PDT 24 |
| Finished | Jul 09 08:38:23 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-62117ea4-e27f-40fe-9b1d-53dec125b328 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3248429279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.3248429279 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.966936020 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 32007264496 ps |
| CPU time | 6559.85 seconds |
| Started | Jul 09 07:49:17 PM PDT 24 |
| Finished | Jul 09 09:38:40 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-6e061de4-8f26-41ab-8dee-1481464fa061 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=966936020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.966936020 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.2589854967 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 2520247688 ps |
| CPU time | 328.17 seconds |
| Started | Jul 09 07:49:19 PM PDT 24 |
| Finished | Jul 09 07:54:48 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-917e2f2a-7e01-461e-8c0d-4030155474eb |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589854967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.2589854967 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2871577130 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3550660642 ps |
| CPU time | 599.99 seconds |
| Started | Jul 09 07:49:55 PM PDT 24 |
| Finished | Jul 09 07:59:56 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-c8a8f92b-7076-4637-88b5-0eae0c7a7dca |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287157713 0 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.2871577130 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.3957490863 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 18881323312 ps |
| CPU time | 4319.74 seconds |
| Started | Jul 09 07:49:29 PM PDT 24 |
| Finished | Jul 09 09:01:30 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-b6d54bf7-8027-403b-8e40-6efbb246d4e9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3957490863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.3957490863 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.1225028637 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 3617046744 ps |
| CPU time | 275.15 seconds |
| Started | Jul 09 07:49:15 PM PDT 24 |
| Finished | Jul 09 07:53:50 PM PDT 24 |
| Peak memory | 609636 kb |
| Host | smart-8418ee03-2c07-4a60-8bdd-edee5ecf6dbf |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225028637 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.1225028637 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.1716308713 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 12683509196 ps |
| CPU time | 1789.25 seconds |
| Started | Jul 09 07:56:39 PM PDT 24 |
| Finished | Jul 09 08:26:29 PM PDT 24 |
| Peak memory | 621424 kb |
| Host | smart-605ac2ad-78a8-41b1-a9b5-04bed55bb1fe |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1716308713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.1716308713 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.3384047307 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 2693274651 ps |
| CPU time | 186.35 seconds |
| Started | Jul 09 07:53:35 PM PDT 24 |
| Finished | Jul 09 07:56:43 PM PDT 24 |
| Peak memory | 621836 kb |
| Host | smart-7108125a-f216-4d8d-bc81-645032a59a15 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384047307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.3384047307 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.4127728586 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 8222511225 ps |
| CPU time | 712.39 seconds |
| Started | Jul 09 07:53:03 PM PDT 24 |
| Finished | Jul 09 08:04:56 PM PDT 24 |
| Peak memory | 623012 kb |
| Host | smart-17f67fe5-7931-4ee4-993f-6d24a12c2665 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127728586 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.4127728586 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.1410797235 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 4695054898 ps |
| CPU time | 394.32 seconds |
| Started | Jul 09 07:50:15 PM PDT 24 |
| Finished | Jul 09 07:56:50 PM PDT 24 |
| Peak memory | 621232 kb |
| Host | smart-ed694275-22d3-46a4-8824-0c89ae0b0a69 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1410797235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.1410797235 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.677852413 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 15645385659 ps |
| CPU time | 4986.55 seconds |
| Started | Jul 09 07:56:29 PM PDT 24 |
| Finished | Jul 09 09:19:37 PM PDT 24 |
| Peak memory | 610508 kb |
| Host | smart-057743cb-db3c-46b7-a55f-bff4a2f01320 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677852413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .rom_e2e_asm_init_dev.677852413 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.3219627941 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 15811581461 ps |
| CPU time | 3451.95 seconds |
| Started | Jul 09 07:58:58 PM PDT 24 |
| Finished | Jul 09 08:56:32 PM PDT 24 |
| Peak memory | 610788 kb |
| Host | smart-0b596c63-c2db-4f71-a379-c4c1d45fd243 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219627941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.3219627941 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1912227527 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 15980598350 ps |
| CPU time | 3943.34 seconds |
| Started | Jul 09 07:58:53 PM PDT 24 |
| Finished | Jul 09 09:04:38 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-c3d5207b-8b85-4850-824a-325d8218a4f3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912227527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.1912227527 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.33235344 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 15225016458 ps |
| CPU time | 3522.94 seconds |
| Started | Jul 09 07:57:33 PM PDT 24 |
| Finished | Jul 09 08:56:17 PM PDT 24 |
| Peak memory | 611484 kb |
| Host | smart-fd5b7b1f-448c-4727-b048-8262ad6fe457 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33235344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. rom_e2e_asm_init_rma.33235344 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.226202733 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 10956361058 ps |
| CPU time | 3437.04 seconds |
| Started | Jul 09 07:58:52 PM PDT 24 |
| Finished | Jul 09 08:56:11 PM PDT 24 |
| Peak memory | 610880 kb |
| Host | smart-9590fffe-14b2-4cde-8d34-101754038537 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226202733 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.rom_e2e_asm_init_test_unlocked0.226202733 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1408384440 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 24082941006 ps |
| CPU time | 5844.6 seconds |
| Started | Jul 09 07:59:37 PM PDT 24 |
| Finished | Jul 09 09:37:03 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-df548691-3947-48be-8088-37a4f7e56589 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1408384440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1408384440 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2567289786 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 24071342072 ps |
| CPU time | 6022 seconds |
| Started | Jul 09 07:59:23 PM PDT 24 |
| Finished | Jul 09 09:39:47 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-37386a75-b7b8-44e1-9a2f-bae56caff3c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2567289786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2567289786 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3755869517 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 23394792840 ps |
| CPU time | 5548.93 seconds |
| Started | Jul 09 07:57:41 PM PDT 24 |
| Finished | Jul 09 09:30:11 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-aea04f40-48d5-4c9d-bf71-8cd779fbfd6c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3755869517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3755869517 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3031149832 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 18359280672 ps |
| CPU time | 4457.53 seconds |
| Started | Jul 09 07:59:50 PM PDT 24 |
| Finished | Jul 09 09:14:09 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-761ec556-6c73-4550-9001-e2f57c5c5d75 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031149832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3031149832 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1407287551 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 14622159360 ps |
| CPU time | 4045.36 seconds |
| Started | Jul 09 07:57:25 PM PDT 24 |
| Finished | Jul 09 09:04:52 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-0debd91e-5fd5-4d6a-ac43-47d5b35b5242 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1407287551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1407287551 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2156385793 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 15334734684 ps |
| CPU time | 3786.42 seconds |
| Started | Jul 09 07:57:38 PM PDT 24 |
| Finished | Jul 09 09:00:46 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-b24497a7-a3e8-4105-9880-95e2af8125ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2156385793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2156385793 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.62023167 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 15706307348 ps |
| CPU time | 3682.84 seconds |
| Started | Jul 09 07:57:25 PM PDT 24 |
| Finished | Jul 09 08:58:49 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-8b438286-aac0-43c4-8ac7-ee952f6e8762 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=62023167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.62023167 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.459330409 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 15373920620 ps |
| CPU time | 3780.44 seconds |
| Started | Jul 09 08:00:28 PM PDT 24 |
| Finished | Jul 09 09:03:30 PM PDT 24 |
| Peak memory | 609860 kb |
| Host | smart-67319410-81dd-4f45-b88a-ec03755ba703 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=459330409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.459330409 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.4274768948 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 11815635364 ps |
| CPU time | 3505.84 seconds |
| Started | Jul 09 07:59:53 PM PDT 24 |
| Finished | Jul 09 08:58:20 PM PDT 24 |
| Peak memory | 609896 kb |
| Host | smart-4b8ec3be-b06e-40e3-a9ba-c744472450ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274768948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.4274768948 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3759940673 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 15022933576 ps |
| CPU time | 4213.66 seconds |
| Started | Jul 09 08:02:46 PM PDT 24 |
| Finished | Jul 09 09:13:01 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-68acb2c6-499c-451a-b27d-586a09b23082 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759940673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3759940673 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.676163578 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 15831854700 ps |
| CPU time | 3902.18 seconds |
| Started | Jul 09 07:58:26 PM PDT 24 |
| Finished | Jul 09 09:03:29 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-c063d2f3-809a-4237-a58b-bca5ba152df4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676163578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.676163578 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3419701889 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 15324087656 ps |
| CPU time | 3895.53 seconds |
| Started | Jul 09 07:57:20 PM PDT 24 |
| Finished | Jul 09 09:02:17 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-1c2793fd-edf3-4b83-a42a-3e2ef2c1bb6f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341970 1889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3419701889 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3970751980 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 14511112980 ps |
| CPU time | 4139.88 seconds |
| Started | Jul 09 07:59:33 PM PDT 24 |
| Finished | Jul 09 09:08:34 PM PDT 24 |
| Peak memory | 609788 kb |
| Host | smart-87438717-c8e0-403d-9e54-3a3140584f1c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970751980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3970751980 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.938069960 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 11400577288 ps |
| CPU time | 2692.16 seconds |
| Started | Jul 09 08:01:38 PM PDT 24 |
| Finished | Jul 09 08:46:32 PM PDT 24 |
| Peak memory | 610580 kb |
| Host | smart-b219b329-90d9-4ee2-b1d0-73dc9cae761e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 938069960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.938069960 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.2565852126 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 11900205636 ps |
| CPU time | 2415.96 seconds |
| Started | Jul 09 07:54:26 PM PDT 24 |
| Finished | Jul 09 08:34:45 PM PDT 24 |
| Peak memory | 624148 kb |
| Host | smart-223ad5a2-d8ef-4a9a-a246-5bb1f60f35e0 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25658 52126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.2565852126 |
| Directory | /workspace/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3921735435 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 11177890165 ps |
| CPU time | 1686.47 seconds |
| Started | Jul 09 07:52:54 PM PDT 24 |
| Finished | Jul 09 08:21:02 PM PDT 24 |
| Peak memory | 624540 kb |
| Host | smart-e26422bf-01a2-484d-9fc0-bbdb35e0989d |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39217 35435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.3921735435 |
| Directory | /workspace/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.954660793 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 11188444453 ps |
| CPU time | 1915.64 seconds |
| Started | Jul 09 07:52:42 PM PDT 24 |
| Finished | Jul 09 08:24:40 PM PDT 24 |
| Peak memory | 624596 kb |
| Host | smart-1f3f7b8b-48de-4644-9a6e-157150b702e7 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=954660793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.954660793 |
| Directory | /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2651469862 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 24439631396 ps |
| CPU time | 2277.97 seconds |
| Started | Jul 09 07:54:39 PM PDT 24 |
| Finished | Jul 09 08:32:38 PM PDT 24 |
| Peak memory | 620712 kb |
| Host | smart-207918b5-5527-4682-9516-a334ac1b4c0a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2651469862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.2651469862 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.1269547092 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 24660121108 ps |
| CPU time | 2864.89 seconds |
| Started | Jul 09 07:54:19 PM PDT 24 |
| Finished | Jul 09 08:42:05 PM PDT 24 |
| Peak memory | 621452 kb |
| Host | smart-6295c7c6-ec0c-420f-9ddb-d720e246f419 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1269547092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.1269547092 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1255179438 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 24677535300 ps |
| CPU time | 2533.47 seconds |
| Started | Jul 09 07:52:36 PM PDT 24 |
| Finished | Jul 09 08:34:52 PM PDT 24 |
| Peak memory | 621496 kb |
| Host | smart-72773210-008e-485a-873c-be6a87077f7c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255179438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.1255179438 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.4250749114 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 15321156140 ps |
| CPU time | 4135.75 seconds |
| Started | Jul 09 08:01:13 PM PDT 24 |
| Finished | Jul 09 09:10:10 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-42666c18-13ca-42b9-88ed-74f3e95ca6a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250749114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.4250749114 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3934865265 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 15285743048 ps |
| CPU time | 3491.07 seconds |
| Started | Jul 09 08:00:11 PM PDT 24 |
| Finished | Jul 09 08:58:23 PM PDT 24 |
| Peak memory | 610600 kb |
| Host | smart-45d8a348-be6c-4db4-bcbc-3be60986580e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934865265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.3934865265 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.4082181926 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 14832015270 ps |
| CPU time | 3492.82 seconds |
| Started | Jul 09 07:57:36 PM PDT 24 |
| Finished | Jul 09 08:55:50 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-17f4ccf6-cc71-4274-9173-74a0e28c8cf2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082181926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.4082181926 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3353472294 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 15124777270 ps |
| CPU time | 4029.14 seconds |
| Started | Jul 09 07:56:26 PM PDT 24 |
| Finished | Jul 09 09:03:36 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-9408edb0-30f6-44b7-b0c7-284b71d138e2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353472294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.3353472294 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.981981324 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 23614388280 ps |
| CPU time | 6178.36 seconds |
| Started | Jul 09 08:02:50 PM PDT 24 |
| Finished | Jul 09 09:45:50 PM PDT 24 |
| Peak memory | 611632 kb |
| Host | smart-3d382255-b636-4486-ac77-25767b3f189c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=981981324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.981981324 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2061803555 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 23889873577 ps |
| CPU time | 6669.98 seconds |
| Started | Jul 09 07:57:14 PM PDT 24 |
| Finished | Jul 09 09:48:26 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-4e9a9a36-7fd6-46bb-87cf-8b493f85ff38 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2061803555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.2061803555 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.516058422 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 23885776677 ps |
| CPU time | 6431.65 seconds |
| Started | Jul 09 08:02:55 PM PDT 24 |
| Finished | Jul 09 09:50:08 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-d510b3c3-96d4-413a-b034-6922caadb085 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=516058422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_b ad_b_bad_prod_end.516058422 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2107586430 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 22715276183 ps |
| CPU time | 5968.13 seconds |
| Started | Jul 09 07:58:51 PM PDT 24 |
| Finished | Jul 09 09:38:21 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-92d9cb64-4c8d-49c6-b308-554bc4e281cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2107586430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.2107586430 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2487000885 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 18080419448 ps |
| CPU time | 4531.59 seconds |
| Started | Jul 09 08:00:28 PM PDT 24 |
| Finished | Jul 09 09:16:01 PM PDT 24 |
| Peak memory | 610936 kb |
| Host | smart-d2287d8d-dfe0-4881-bcf9-8f3f830a9ddc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2487000885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.2487000885 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4092195231 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 14908151560 ps |
| CPU time | 3468.76 seconds |
| Started | Jul 09 08:00:13 PM PDT 24 |
| Finished | Jul 09 08:58:03 PM PDT 24 |
| Peak memory | 609332 kb |
| Host | smart-33d665f3-5242-48c4-a51a-c39cb4b61e67 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092195231 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4092195231 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2690793769 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 14410049000 ps |
| CPU time | 3434.75 seconds |
| Started | Jul 09 08:00:10 PM PDT 24 |
| Finished | Jul 09 08:57:26 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-8a9eb3d7-3fcb-4e26-a50b-d2a87ca508f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690793769 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2690793769 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3224298247 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 15131157569 ps |
| CPU time | 3614.36 seconds |
| Started | Jul 09 07:56:48 PM PDT 24 |
| Finished | Jul 09 08:57:03 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-e610a526-e01e-49b7-a0eb-76387e1b84c2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224298247 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3224298247 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.890316995 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 13591762166 ps |
| CPU time | 3985.12 seconds |
| Started | Jul 09 07:59:57 PM PDT 24 |
| Finished | Jul 09 09:06:24 PM PDT 24 |
| Peak memory | 609872 kb |
| Host | smart-f462f5b0-d6af-4c0f-8e5f-bd45bb7ef627 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890316995 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.890316995 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1397945791 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 11162929257 ps |
| CPU time | 3075.88 seconds |
| Started | Jul 09 07:59:33 PM PDT 24 |
| Finished | Jul 09 08:50:51 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-1122e2be-9142-40bc-8c47-5ab374e77d2f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397945791 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1397945791 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.904767074 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 15223841264 ps |
| CPU time | 3613.59 seconds |
| Started | Jul 09 08:02:53 PM PDT 24 |
| Finished | Jul 09 09:03:08 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-b90af5b1-7a8f-4907-a6b6-7dfbcb999e02 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904767074 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.904767074 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2214690978 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 13746625218 ps |
| CPU time | 3717.22 seconds |
| Started | Jul 09 07:57:22 PM PDT 24 |
| Finished | Jul 09 08:59:21 PM PDT 24 |
| Peak memory | 609716 kb |
| Host | smart-976b56be-7059-41bf-8cf5-fc8e84086dcc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214690978 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2214690978 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2115963097 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 14370180632 ps |
| CPU time | 3794.76 seconds |
| Started | Jul 09 08:00:39 PM PDT 24 |
| Finished | Jul 09 09:03:55 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-98601961-7cc2-4c00-903b-649a5b84af52 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115963097 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2115963097 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.780803965 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 14181903337 ps |
| CPU time | 3600.86 seconds |
| Started | Jul 09 07:57:46 PM PDT 24 |
| Finished | Jul 09 08:57:48 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-84c12c85-8ce5-4231-be60-8a7e001dadb1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780803965 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.780803965 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.938092224 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 10548965697 ps |
| CPU time | 2960.9 seconds |
| Started | Jul 09 07:57:14 PM PDT 24 |
| Finished | Jul 09 08:46:36 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-6a9410a8-92ad-43a7-b5eb-105c0dd9a4b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938092224 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.938092224 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.3422233092 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 14374096520 ps |
| CPU time | 3279.08 seconds |
| Started | Jul 09 08:00:29 PM PDT 24 |
| Finished | Jul 09 08:55:09 PM PDT 24 |
| Peak memory | 610632 kb |
| Host | smart-d10e09cf-b672-43f3-8c11-7490ee6782e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=3422233092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.3422233092 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.3191011110 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 17528012436 ps |
| CPU time | 4050.39 seconds |
| Started | Jul 09 07:56:55 PM PDT 24 |
| Finished | Jul 09 09:04:27 PM PDT 24 |
| Peak memory | 610744 kb |
| Host | smart-fa87fa32-5473-4147-97eb-02be1de7097a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191011110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.3191011110 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.1606518973 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 4979017060 ps |
| CPU time | 638.7 seconds |
| Started | Jul 09 07:56:13 PM PDT 24 |
| Finished | Jul 09 08:06:54 PM PDT 24 |
| Peak memory | 609508 kb |
| Host | smart-83785205-7813-4966-9f84-8709958faee5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606518973 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.1606518973 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.3300422956 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 6159715052 ps |
| CPU time | 264.29 seconds |
| Started | Jul 09 07:55:41 PM PDT 24 |
| Finished | Jul 09 08:00:06 PM PDT 24 |
| Peak memory | 624004 kb |
| Host | smart-dfa1cbfc-65a6-4a72-ac41-10aeab4541c2 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3300422956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.3300422956 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.1808656469 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2959750632 ps |
| CPU time | 116.08 seconds |
| Started | Jul 09 07:55:20 PM PDT 24 |
| Finished | Jul 09 07:57:17 PM PDT 24 |
| Peak memory | 616724 kb |
| Host | smart-b9f61063-3184-4dde-ae15-0bdb712d189f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808656469 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.1808656469 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.3118768565 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 13695098250 ps |
| CPU time | 1549.18 seconds |
| Started | Jul 09 07:52:35 PM PDT 24 |
| Finished | Jul 09 08:18:26 PM PDT 24 |
| Peak memory | 608268 kb |
| Host | smart-1a4fd131-fa19-4f8d-878b-696d7765ec08 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118768565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.3 118768565 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2433160469 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4329612286 ps |
| CPU time | 398.18 seconds |
| Started | Jul 09 08:02:11 PM PDT 24 |
| Finished | Jul 09 08:08:50 PM PDT 24 |
| Peak memory | 620188 kb |
| Host | smart-d031362c-4a5f-4ba5-a584-c5fa0bac714c |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 433160469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.2433160469 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.3523837836 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 3101624600 ps |
| CPU time | 330.59 seconds |
| Started | Jul 09 07:56:39 PM PDT 24 |
| Finished | Jul 09 08:02:10 PM PDT 24 |
| Peak memory | 608832 kb |
| Host | smart-e6a8c5e6-668d-4b0c-9ab1-e26140aa9e5b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3523837836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.3523837836 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3933163582 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 18030948516 ps |
| CPU time | 606.14 seconds |
| Started | Jul 09 07:58:18 PM PDT 24 |
| Finished | Jul 09 08:08:27 PM PDT 24 |
| Peak memory | 619460 kb |
| Host | smart-3f5b2dd0-5d38-481b-80b2-d567ca4eff71 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3933163582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3933163582 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.4114424784 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 2664316780 ps |
| CPU time | 200.17 seconds |
| Started | Jul 09 08:05:30 PM PDT 24 |
| Finished | Jul 09 08:08:52 PM PDT 24 |
| Peak memory | 609564 kb |
| Host | smart-89be411a-7bae-4e14-9339-47bb293540ad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114424784 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.4114424784 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2663941792 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 3611448182 ps |
| CPU time | 362.58 seconds |
| Started | Jul 09 08:05:36 PM PDT 24 |
| Finished | Jul 09 08:11:39 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-0ddf9173-60e3-4ea0-b41c-857bc532ecaa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663 941792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.2663941792 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.109563110 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 2504351999 ps |
| CPU time | 215.79 seconds |
| Started | Jul 09 08:01:57 PM PDT 24 |
| Finished | Jul 09 08:05:33 PM PDT 24 |
| Peak memory | 609028 kb |
| Host | smart-8cc2ef77-9e79-4763-b6c2-b9b6bf3fb403 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109563110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.109563110 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.1580795277 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 2844840114 ps |
| CPU time | 276.81 seconds |
| Started | Jul 09 07:57:43 PM PDT 24 |
| Finished | Jul 09 08:02:21 PM PDT 24 |
| Peak memory | 609140 kb |
| Host | smart-26c3bc09-ac3f-409a-8c39-5c5fc6785e8e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580795277 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.1580795277 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.170627011 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 2658904056 ps |
| CPU time | 277.98 seconds |
| Started | Jul 09 08:02:47 PM PDT 24 |
| Finished | Jul 09 08:07:26 PM PDT 24 |
| Peak memory | 608940 kb |
| Host | smart-120bd470-3e96-4fad-9b3d-308cf7104fd5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170627011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.170627011 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.1617283590 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 2604987455 ps |
| CPU time | 320.07 seconds |
| Started | Jul 09 07:59:19 PM PDT 24 |
| Finished | Jul 09 08:04:40 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-d1f97d7d-d792-44e8-bf06-96dc89476b0e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617283590 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.1617283590 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.1852403076 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 2897601940 ps |
| CPU time | 267.62 seconds |
| Started | Jul 09 08:06:34 PM PDT 24 |
| Finished | Jul 09 08:11:02 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-163deaff-3fcf-40c5-9cf2-b027cf0947f4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852403076 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.1852403076 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.791361190 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3033798865 ps |
| CPU time | 274.95 seconds |
| Started | Jul 09 07:58:28 PM PDT 24 |
| Finished | Jul 09 08:03:04 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-c7a8c557-5ddb-4734-968d-fccb300fcda0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=791361190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.791361190 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.4070922705 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 4905687048 ps |
| CPU time | 471.46 seconds |
| Started | Jul 09 08:05:03 PM PDT 24 |
| Finished | Jul 09 08:12:56 PM PDT 24 |
| Peak memory | 619428 kb |
| Host | smart-2159d266-2978-4fdb-988b-2623021f99f0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=4070922705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.4070922705 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3168888488 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 9830058986 ps |
| CPU time | 2155.11 seconds |
| Started | Jul 09 07:59:24 PM PDT 24 |
| Finished | Jul 09 08:35:20 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-a370892f-fcf4-4d6f-aa37-c2e26d29674f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3168888488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.3168888488 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1794582646 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 7697924064 ps |
| CPU time | 1483.62 seconds |
| Started | Jul 09 07:56:53 PM PDT 24 |
| Finished | Jul 09 08:21:37 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-a0183c80-2f46-4e95-9ff4-e2e325361c88 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794582646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.1794582646 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1718343816 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 11825305494 ps |
| CPU time | 1313.35 seconds |
| Started | Jul 09 07:57:47 PM PDT 24 |
| Finished | Jul 09 08:19:41 PM PDT 24 |
| Peak memory | 610892 kb |
| Host | smart-1ff4e627-b05c-4053-9cbb-f94e1886bb56 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718343816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.1718343816 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1907313638 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 8188238520 ps |
| CPU time | 1439.11 seconds |
| Started | Jul 09 08:04:37 PM PDT 24 |
| Finished | Jul 09 08:28:38 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-5bba29f5-a8c9-4182-8053-4ed5b86a2db6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1907313638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.1907313638 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1356025202 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 5162229274 ps |
| CPU time | 495.85 seconds |
| Started | Jul 09 08:05:09 PM PDT 24 |
| Finished | Jul 09 08:13:26 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-758b0a36-ae29-4b3b-a920-90082753146f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1356025202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.1356025202 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3894371822 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 255584411560 ps |
| CPU time | 10943.4 seconds |
| Started | Jul 09 07:56:49 PM PDT 24 |
| Finished | Jul 09 10:59:13 PM PDT 24 |
| Peak memory | 611052 kb |
| Host | smart-b314d808-46be-49c6-bf45-50ee805cb94f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3894371822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3894371822 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.129850964 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3025704348 ps |
| CPU time | 287.04 seconds |
| Started | Jul 09 08:05:43 PM PDT 24 |
| Finished | Jul 09 08:10:30 PM PDT 24 |
| Peak memory | 608792 kb |
| Host | smart-d130b2f8-6e1d-40d2-ada3-dedf46c362a7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129850964 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_alert_test.129850964 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.2502401189 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 4137306992 ps |
| CPU time | 361.68 seconds |
| Started | Jul 09 07:56:29 PM PDT 24 |
| Finished | Jul 09 08:02:32 PM PDT 24 |
| Peak memory | 608956 kb |
| Host | smart-0cc92e04-4fd6-49bf-8a3f-4eb28136f6d3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502401189 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.2502401189 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2529823929 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 7419551790 ps |
| CPU time | 357.15 seconds |
| Started | Jul 09 07:57:59 PM PDT 24 |
| Finished | Jul 09 08:03:56 PM PDT 24 |
| Peak memory | 609548 kb |
| Host | smart-e60f48f2-e57b-4f52-9c75-cc6e54516aad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2529823929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2529823929 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2322855389 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 2809130632 ps |
| CPU time | 220.45 seconds |
| Started | Jul 09 08:03:48 PM PDT 24 |
| Finished | Jul 09 08:07:30 PM PDT 24 |
| Peak memory | 607720 kb |
| Host | smart-6920f870-c42a-4d12-b1c7-b7847820074b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322855389 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.2322855389 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.831173996 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 8091450850 ps |
| CPU time | 810.83 seconds |
| Started | Jul 09 07:58:17 PM PDT 24 |
| Finished | Jul 09 08:11:49 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-69ae5a67-960c-4cd3-afdf-32e8f5f2db1d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 831173996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.831173996 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2365943516 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 4082355656 ps |
| CPU time | 674.75 seconds |
| Started | Jul 09 07:58:06 PM PDT 24 |
| Finished | Jul 09 08:09:22 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-47c05872-8d1d-4773-94b9-2dd39fd007ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2365943516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.2365943516 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.326155422 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 7751961674 ps |
| CPU time | 1289.1 seconds |
| Started | Jul 09 08:03:22 PM PDT 24 |
| Finished | Jul 09 08:24:52 PM PDT 24 |
| Peak memory | 617408 kb |
| Host | smart-8cd00510-75f8-4939-bd19-63a56b12b66b |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326155422 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.326155422 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.528880183 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 9340065851 ps |
| CPU time | 1101.95 seconds |
| Started | Jul 09 08:00:43 PM PDT 24 |
| Finished | Jul 09 08:19:07 PM PDT 24 |
| Peak memory | 623308 kb |
| Host | smart-e0df2763-6bda-44e9-a9dc-1b9fa2a83a06 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=528880183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.528880183 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2536158302 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 3959184712 ps |
| CPU time | 656.77 seconds |
| Started | Jul 09 08:00:19 PM PDT 24 |
| Finished | Jul 09 08:11:17 PM PDT 24 |
| Peak memory | 612144 kb |
| Host | smart-da0b2f70-89b1-4cec-a226-6c21abddfeb6 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536158302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2536158302 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2931462536 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 4002187038 ps |
| CPU time | 652.26 seconds |
| Started | Jul 09 08:00:09 PM PDT 24 |
| Finished | Jul 09 08:11:02 PM PDT 24 |
| Peak memory | 613204 kb |
| Host | smart-d3c5ff5d-27ae-4cc9-96aa-698403f78288 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931462536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2931462536 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.43852662 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 3963889724 ps |
| CPU time | 688.65 seconds |
| Started | Jul 09 07:59:55 PM PDT 24 |
| Finished | Jul 09 08:11:25 PM PDT 24 |
| Peak memory | 613020 kb |
| Host | smart-250607ef-0bed-4b48-9541-8129f55bb2cb |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43852662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.43852662 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2009773338 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 4901558992 ps |
| CPU time | 807.81 seconds |
| Started | Jul 09 07:59:58 PM PDT 24 |
| Finished | Jul 09 08:13:27 PM PDT 24 |
| Peak memory | 613168 kb |
| Host | smart-ee250b35-e9f7-4ed4-990b-045bac937877 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009773338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2009773338 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4253617218 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 4819999320 ps |
| CPU time | 508.7 seconds |
| Started | Jul 09 07:59:57 PM PDT 24 |
| Finished | Jul 09 08:08:27 PM PDT 24 |
| Peak memory | 613156 kb |
| Host | smart-873468a4-cce5-4a0e-97ce-09400b940150 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253617218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.4253617218 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2406010966 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 5373032416 ps |
| CPU time | 729.68 seconds |
| Started | Jul 09 07:59:54 PM PDT 24 |
| Finished | Jul 09 08:12:05 PM PDT 24 |
| Peak memory | 613168 kb |
| Host | smart-52195abc-d355-417f-9ed6-ecdb5dad1675 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406010966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2406010966 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3120880956 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 2707087880 ps |
| CPU time | 171.36 seconds |
| Started | Jul 09 08:01:45 PM PDT 24 |
| Finished | Jul 09 08:04:37 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-9e9545b8-69dc-40aa-9d41-fb0ef16de518 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120880956 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.3120880956 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.635923938 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 3603193768 ps |
| CPU time | 345.18 seconds |
| Started | Jul 09 08:00:53 PM PDT 24 |
| Finished | Jul 09 08:06:39 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-009a375a-4f2c-450c-8108-3d7c8159f8d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635923938 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.635923938 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2186305164 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 3230491060 ps |
| CPU time | 252.75 seconds |
| Started | Jul 09 08:02:09 PM PDT 24 |
| Finished | Jul 09 08:06:23 PM PDT 24 |
| Peak memory | 608844 kb |
| Host | smart-0742a2b0-a657-420a-8624-ca946ace5433 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186305164 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.2186305164 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2580398716 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 4600414134 ps |
| CPU time | 375.56 seconds |
| Started | Jul 09 07:58:52 PM PDT 24 |
| Finished | Jul 09 08:05:09 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-a6cb6028-3215-447c-8b4c-703bebc5b80c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580398716 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.2580398716 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1489685152 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 3977106908 ps |
| CPU time | 453.95 seconds |
| Started | Jul 09 08:01:46 PM PDT 24 |
| Finished | Jul 09 08:09:21 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-8d5fd1a7-3987-4ca7-a52c-9a58f585d0e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489685152 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.1489685152 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.893374085 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 5342479064 ps |
| CPU time | 581.44 seconds |
| Started | Jul 09 07:59:39 PM PDT 24 |
| Finished | Jul 09 08:09:22 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-bd5de4ec-b218-4a9c-b039-3b5c4fec430d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893374085 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.893374085 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2828275678 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 4376793112 ps |
| CPU time | 748.18 seconds |
| Started | Jul 09 07:59:57 PM PDT 24 |
| Finished | Jul 09 08:12:28 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-f623d287-10f2-45ba-a12f-71a945757d66 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828275678 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.2828275678 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.642120243 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 9952362500 ps |
| CPU time | 1484.21 seconds |
| Started | Jul 09 08:00:47 PM PDT 24 |
| Finished | Jul 09 08:25:33 PM PDT 24 |
| Peak memory | 611016 kb |
| Host | smart-4e30303c-0657-4ad6-823e-415f66f9d8f9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642120243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.642120243 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1691645791 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 3633092040 ps |
| CPU time | 341.13 seconds |
| Started | Jul 09 07:58:31 PM PDT 24 |
| Finished | Jul 09 08:04:12 PM PDT 24 |
| Peak memory | 610192 kb |
| Host | smart-f86278af-6b13-4ebb-b707-3c3a65d930f5 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691645791 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.1691645791 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1361277629 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 4547561240 ps |
| CPU time | 581.96 seconds |
| Started | Jul 09 07:59:58 PM PDT 24 |
| Finished | Jul 09 08:09:42 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-4d7be02f-fa23-443f-982a-39c17a8979e1 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361277629 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.1361277629 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1068900196 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 3612203816 ps |
| CPU time | 206.41 seconds |
| Started | Jul 09 08:03:54 PM PDT 24 |
| Finished | Jul 09 08:07:21 PM PDT 24 |
| Peak memory | 608208 kb |
| Host | smart-182bfe2c-d70e-4a3f-9f7d-f46a81e6e84b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068900196 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.1068900196 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2236461625 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 127445584526 ps |
| CPU time | 17184.3 seconds |
| Started | Jul 09 08:02:46 PM PDT 24 |
| Finished | Jul 10 12:49:13 AM PDT 24 |
| Peak memory | 611012 kb |
| Host | smart-9c5917e3-dd93-473a-9986-1840bae50b84 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2236461625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.2236461625 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1926358111 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 4219000214 ps |
| CPU time | 429.86 seconds |
| Started | Jul 09 07:57:28 PM PDT 24 |
| Finished | Jul 09 08:04:39 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-7f116095-cf42-43c4-a73c-b50a7348d6e0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19263 58111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.1926358111 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.3071119676 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3067907578 ps |
| CPU time | 280.03 seconds |
| Started | Jul 09 07:59:32 PM PDT 24 |
| Finished | Jul 09 08:04:13 PM PDT 24 |
| Peak memory | 609496 kb |
| Host | smart-ea254892-a54b-4a1d-97c0-09f6f9d01ba8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071119676 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.3071119676 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.1947981079 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 3258765500 ps |
| CPU time | 285.43 seconds |
| Started | Jul 09 08:03:58 PM PDT 24 |
| Finished | Jul 09 08:08:44 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-e0a3c0f6-9467-4736-9a11-db6ad1613276 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947981079 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.1947981079 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.1287634206 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 5496699914 ps |
| CPU time | 682.51 seconds |
| Started | Jul 09 07:57:02 PM PDT 24 |
| Finished | Jul 09 08:08:26 PM PDT 24 |
| Peak memory | 611188 kb |
| Host | smart-77906c55-a73e-4ddf-9b1a-3fb3694d2de6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1287634206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.1287634206 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.1833599175 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 4380822126 ps |
| CPU time | 1035.64 seconds |
| Started | Jul 09 07:57:47 PM PDT 24 |
| Finished | Jul 09 08:15:03 PM PDT 24 |
| Peak memory | 609388 kb |
| Host | smart-2d68ad81-d545-410e-8537-1c7fa8c48c97 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833599175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.1833599175 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.1541406305 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3465993576 ps |
| CPU time | 551.64 seconds |
| Started | Jul 09 07:57:02 PM PDT 24 |
| Finished | Jul 09 08:06:14 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-ecead21d-51a7-44ed-a665-8f8043afe90a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541406305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.1541406305 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.144876174 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 7886629788 ps |
| CPU time | 1215.98 seconds |
| Started | Jul 09 08:01:24 PM PDT 24 |
| Finished | Jul 09 08:21:41 PM PDT 24 |
| Peak memory | 611200 kb |
| Host | smart-3500e4fd-056c-416e-8f0e-5a2323841b00 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=144876174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.144876174 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1273157272 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 6073529979 ps |
| CPU time | 958.71 seconds |
| Started | Jul 09 07:58:26 PM PDT 24 |
| Finished | Jul 09 08:14:26 PM PDT 24 |
| Peak memory | 611272 kb |
| Host | smart-7d92c254-b306-4f16-a69c-67107846b7e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273157272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.1273157272 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.2706952426 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 3014621620 ps |
| CPU time | 596.17 seconds |
| Started | Jul 09 07:58:40 PM PDT 24 |
| Finished | Jul 09 08:08:37 PM PDT 24 |
| Peak memory | 616892 kb |
| Host | smart-33674ffa-221a-4135-ab5e-e254ab39853c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706952426 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.2706952426 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.1203606328 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 8098163912 ps |
| CPU time | 1639.72 seconds |
| Started | Jul 09 07:57:47 PM PDT 24 |
| Finished | Jul 09 08:25:08 PM PDT 24 |
| Peak memory | 609556 kb |
| Host | smart-4eedf2ed-a927-42b4-9951-258fa5df5bbb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203606328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.1203606328 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1590365954 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2506180388 ps |
| CPU time | 171.66 seconds |
| Started | Jul 09 07:57:47 PM PDT 24 |
| Finished | Jul 09 08:00:39 PM PDT 24 |
| Peak memory | 609580 kb |
| Host | smart-b337d28e-fad5-4163-ba8b-fb47f7736fb4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15 90365954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.1590365954 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3856957681 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 7552635956 ps |
| CPU time | 1823.15 seconds |
| Started | Jul 09 07:59:49 PM PDT 24 |
| Finished | Jul 09 08:30:13 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-1e92f08f-682e-4761-aebe-695473fca5cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3856957681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.3856957681 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2960533354 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 2799578990 ps |
| CPU time | 263.8 seconds |
| Started | Jul 09 07:58:40 PM PDT 24 |
| Finished | Jul 09 08:03:04 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-1b31b83a-2287-4e8f-802f-21c07808b063 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960533354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2960533354 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3267790638 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 3379795738 ps |
| CPU time | 541.73 seconds |
| Started | Jul 09 08:03:22 PM PDT 24 |
| Finished | Jul 09 08:12:24 PM PDT 24 |
| Peak memory | 609532 kb |
| Host | smart-435d5dc1-a37d-47aa-8c99-60c11224e7c4 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3267790638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.3267790638 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.2472807046 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 3004742484 ps |
| CPU time | 288.89 seconds |
| Started | Jul 09 07:54:57 PM PDT 24 |
| Finished | Jul 09 07:59:47 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-ccb25467-3018-45a1-bdf5-e564ecb3926e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472807046 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.2472807046 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.617363383 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 2981420272 ps |
| CPU time | 196 seconds |
| Started | Jul 09 07:56:11 PM PDT 24 |
| Finished | Jul 09 07:59:28 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-6c2133cf-22f0-4f3a-bc0a-ae5e080ca35d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617363383 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.617363383 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.3393848747 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 2895121172 ps |
| CPU time | 206.81 seconds |
| Started | Jul 09 07:55:09 PM PDT 24 |
| Finished | Jul 09 07:58:36 PM PDT 24 |
| Peak memory | 608824 kb |
| Host | smart-b38c2f5b-557f-47eb-baff-2feba884ad37 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393848747 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.3393848747 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.3769486813 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 2503053102 ps |
| CPU time | 108.03 seconds |
| Started | Jul 09 07:53:54 PM PDT 24 |
| Finished | Jul 09 07:55:42 PM PDT 24 |
| Peak memory | 610828 kb |
| Host | smart-5785bf9e-3288-4d12-9e37-a008b76902e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769486813 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.3769486813 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.889829738 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 59264520280 ps |
| CPU time | 11036.5 seconds |
| Started | Jul 09 07:54:52 PM PDT 24 |
| Finished | Jul 09 10:58:50 PM PDT 24 |
| Peak memory | 625120 kb |
| Host | smart-e8a8d8b8-02f9-400d-a5c0-bf2fd177ca3b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=889829738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.889829738 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.912036580 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 6035717218 ps |
| CPU time | 740.83 seconds |
| Started | Jul 09 08:01:56 PM PDT 24 |
| Finished | Jul 09 08:14:17 PM PDT 24 |
| Peak memory | 610956 kb |
| Host | smart-548c15e8-9550-447e-b998-1f21a39bf7ae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=912036580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.912036580 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.118658890 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 5501298486 ps |
| CPU time | 1085.68 seconds |
| Started | Jul 09 07:55:39 PM PDT 24 |
| Finished | Jul 09 08:13:45 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-8e5ddb6d-415a-4bfc-bf5d-efa2e795ae02 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118658890 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_flash_ctrl_access.118658890 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.644876136 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 5890582232 ps |
| CPU time | 957.09 seconds |
| Started | Jul 09 07:55:27 PM PDT 24 |
| Finished | Jul 09 08:11:25 PM PDT 24 |
| Peak memory | 609504 kb |
| Host | smart-40492d04-1f24-41c5-a57c-d3763f123afb |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644876136 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.644876136 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2763153334 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 7861059749 ps |
| CPU time | 1355.58 seconds |
| Started | Jul 09 08:02:10 PM PDT 24 |
| Finished | Jul 09 08:24:47 PM PDT 24 |
| Peak memory | 609572 kb |
| Host | smart-32d975dd-266f-4251-a3c6-7d03d34266f0 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763153334 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2763153334 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1570288172 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 5662468612 ps |
| CPU time | 1405.7 seconds |
| Started | Jul 09 07:54:52 PM PDT 24 |
| Finished | Jul 09 08:18:19 PM PDT 24 |
| Peak memory | 610324 kb |
| Host | smart-d7ab50f8-f2ac-45e7-a58a-aeeadf0e3a7b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570288172 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.1570288172 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1029572709 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 3457342428 ps |
| CPU time | 384.15 seconds |
| Started | Jul 09 07:55:42 PM PDT 24 |
| Finished | Jul 09 08:02:07 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-90e237be-d277-4d32-84d4-bf387cb2fb88 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029572709 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.1029572709 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1872331111 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 4736873442 ps |
| CPU time | 547.25 seconds |
| Started | Jul 09 07:57:17 PM PDT 24 |
| Finished | Jul 09 08:06:25 PM PDT 24 |
| Peak memory | 609612 kb |
| Host | smart-78633edb-9b20-4c84-933f-7219aff1862c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18 72331111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.1872331111 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2603433244 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 5461271000 ps |
| CPU time | 1100.86 seconds |
| Started | Jul 09 08:02:15 PM PDT 24 |
| Finished | Jul 09 08:20:37 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-f74c3636-0b02-4d83-a077-4c0084db2c10 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603433244 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.2603433244 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.396678250 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 3927925560 ps |
| CPU time | 578.16 seconds |
| Started | Jul 09 07:55:54 PM PDT 24 |
| Finished | Jul 09 08:05:33 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-a8968fb9-5571-4ae5-af94-b7fa0e32e59b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396678250 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.396678250 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3083757815 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 4725700871 ps |
| CPU time | 614.39 seconds |
| Started | Jul 09 07:54:12 PM PDT 24 |
| Finished | Jul 09 08:04:27 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-4adb97c1-2e7c-45ad-841e-b36b1ec8061f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3083757815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.3083757815 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3447391380 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 4650122364 ps |
| CPU time | 727.32 seconds |
| Started | Jul 09 08:01:31 PM PDT 24 |
| Finished | Jul 09 08:13:40 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-c15bfec3-7f82-4a3e-aa85-186cf39adf5b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3447391380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3447391380 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.374692473 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 2906964600 ps |
| CPU time | 418.36 seconds |
| Started | Jul 09 08:03:42 PM PDT 24 |
| Finished | Jul 09 08:10:41 PM PDT 24 |
| Peak memory | 608756 kb |
| Host | smart-1f5e0ef0-8c7d-4b63-8e2f-05e6fdcc4aff |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746924 73 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.374692473 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.409260120 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 21266099572 ps |
| CPU time | 1842.32 seconds |
| Started | Jul 09 07:53:58 PM PDT 24 |
| Finished | Jul 09 08:24:42 PM PDT 24 |
| Peak memory | 612572 kb |
| Host | smart-0dd56807-3d01-4330-bf34-e18be5910f27 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409260120 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.409260120 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2426714378 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 26696339990 ps |
| CPU time | 2138.11 seconds |
| Started | Jul 09 08:04:13 PM PDT 24 |
| Finished | Jul 09 08:39:52 PM PDT 24 |
| Peak memory | 614708 kb |
| Host | smart-d01bbe80-7a95-48e7-b081-949298fa3bf2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2426714378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.2426714378 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.191012229 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 2447253630 ps |
| CPU time | 248.9 seconds |
| Started | Jul 09 08:06:29 PM PDT 24 |
| Finished | Jul 09 08:10:39 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-9fae2759-1f6f-4b8f-b4f1-7a47696e8287 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=191012229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.191012229 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.4224856378 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2754534703 ps |
| CPU time | 226.53 seconds |
| Started | Jul 09 08:06:21 PM PDT 24 |
| Finished | Jul 09 08:10:08 PM PDT 24 |
| Peak memory | 609064 kb |
| Host | smart-c87a73a6-1616-404b-baad-9d24441d1c69 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224856378 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.4224856378 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.973566162 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 2680285632 ps |
| CPU time | 264.99 seconds |
| Started | Jul 09 08:01:18 PM PDT 24 |
| Finished | Jul 09 08:05:44 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-cd00635f-63c6-48f8-a6a0-25881de33d93 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973566162 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.973566162 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1873050464 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 3264321012 ps |
| CPU time | 264.64 seconds |
| Started | Jul 09 07:59:12 PM PDT 24 |
| Finished | Jul 09 08:03:38 PM PDT 24 |
| Peak memory | 608768 kb |
| Host | smart-e8251d6a-4e1e-41ca-80f3-941309721d18 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873050464 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.1873050464 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.904031447 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 2403629156 ps |
| CPU time | 255.24 seconds |
| Started | Jul 09 07:57:22 PM PDT 24 |
| Finished | Jul 09 08:01:38 PM PDT 24 |
| Peak memory | 609600 kb |
| Host | smart-47d90e1b-ab9a-447d-a580-233fb992fb51 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904031447 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.904031447 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1028300977 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 3141646895 ps |
| CPU time | 286.74 seconds |
| Started | Jul 09 08:03:35 PM PDT 24 |
| Finished | Jul 09 08:08:23 PM PDT 24 |
| Peak memory | 609588 kb |
| Host | smart-d1f89853-01ba-4e80-9a03-a1dbe7b5738c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028300977 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.1028300977 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.3580769608 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 7334223650 ps |
| CPU time | 1856.07 seconds |
| Started | Jul 09 07:59:30 PM PDT 24 |
| Finished | Jul 09 08:30:27 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-d2bc3140-e34e-43f8-9065-da6b9d218064 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580769608 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_multistream.3580769608 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.2111545516 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 3150664024 ps |
| CPU time | 445.35 seconds |
| Started | Jul 09 08:03:09 PM PDT 24 |
| Finished | Jul 09 08:10:35 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-8efc785b-91d3-447e-8d1a-179ed2af85fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111545516 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.2111545516 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.3148035585 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 3124079328 ps |
| CPU time | 315.9 seconds |
| Started | Jul 09 08:05:20 PM PDT 24 |
| Finished | Jul 09 08:10:37 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-a6d5de5a-54db-4972-9558-204dda682f5d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148035585 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.3148035585 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.533444429 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 64178099516 ps |
| CPU time | 11383.4 seconds |
| Started | Jul 09 07:56:38 PM PDT 24 |
| Finished | Jul 09 11:06:24 PM PDT 24 |
| Peak memory | 625164 kb |
| Host | smart-f94453cd-d635-4f13-8721-89b95449114d |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=533444429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.533444429 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1127596320 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 11909592664 ps |
| CPU time | 2476.1 seconds |
| Started | Jul 09 08:01:16 PM PDT 24 |
| Finished | Jul 09 08:42:33 PM PDT 24 |
| Peak memory | 617008 kb |
| Host | smart-78dfd0e7-bae3-4e88-8979-308dada06a5a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127 596320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.1127596320 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.354782759 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 8436261944 ps |
| CPU time | 1497.03 seconds |
| Started | Jul 09 07:58:09 PM PDT 24 |
| Finished | Jul 09 08:23:08 PM PDT 24 |
| Peak memory | 618016 kb |
| Host | smart-5702ab79-34ac-4c80-995b-27ca273f3517 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=354782759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.354782759 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.299908546 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 9047610496 ps |
| CPU time | 1355.58 seconds |
| Started | Jul 09 08:02:23 PM PDT 24 |
| Finished | Jul 09 08:24:59 PM PDT 24 |
| Peak memory | 617832 kb |
| Host | smart-21ee41d6-d9f8-4906-a325-59367ef3a69e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=299908546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en_ reduced_freq.299908546 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.914204314 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 9166551848 ps |
| CPU time | 1744.7 seconds |
| Started | Jul 09 07:58:44 PM PDT 24 |
| Finished | Jul 09 08:27:50 PM PDT 24 |
| Peak memory | 618108 kb |
| Host | smart-d553fef7-cfbf-40dd-b0b9-2f1d009e4bc1 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=914204314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.914204314 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2672723868 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 6947066792 ps |
| CPU time | 1323.71 seconds |
| Started | Jul 09 08:00:32 PM PDT 24 |
| Finished | Jul 09 08:22:37 PM PDT 24 |
| Peak memory | 611576 kb |
| Host | smart-2f9916bc-baa2-4574-ba3a-79b80f8b0ac3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267272 3868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.2672723868 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1948113815 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 8056471472 ps |
| CPU time | 1529.7 seconds |
| Started | Jul 09 07:59:30 PM PDT 24 |
| Finished | Jul 09 08:25:01 PM PDT 24 |
| Peak memory | 611020 kb |
| Host | smart-85f2b491-31c3-4141-b1ec-cf46e9f16b02 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19481 13815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.1948113815 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.4257773271 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 17912437730 ps |
| CPU time | 3825.87 seconds |
| Started | Jul 09 07:59:29 PM PDT 24 |
| Finished | Jul 09 09:03:16 PM PDT 24 |
| Peak memory | 610992 kb |
| Host | smart-91931198-d51e-4e21-8569-8ecc393cd911 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42577 73271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.4257773271 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.4054048168 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 3187298520 ps |
| CPU time | 216.04 seconds |
| Started | Jul 09 07:58:46 PM PDT 24 |
| Finished | Jul 09 08:02:23 PM PDT 24 |
| Peak memory | 608860 kb |
| Host | smart-0b886f70-90f4-4886-8313-9988db6d7fb2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054048168 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.4054048168 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.2818195111 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 2728735424 ps |
| CPU time | 284.98 seconds |
| Started | Jul 09 07:56:44 PM PDT 24 |
| Finished | Jul 09 08:01:29 PM PDT 24 |
| Peak memory | 608696 kb |
| Host | smart-b86c5d83-eba1-4574-bd90-8f8c6bdc07a5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818195111 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.2818195111 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.2489119898 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 3164207418 ps |
| CPU time | 277.91 seconds |
| Started | Jul 09 08:00:38 PM PDT 24 |
| Finished | Jul 09 08:05:17 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-e95afb5f-6656-4cc0-bb40-94d594042bc3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489119898 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.2489119898 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3024771057 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 3021345652 ps |
| CPU time | 216.73 seconds |
| Started | Jul 09 08:01:12 PM PDT 24 |
| Finished | Jul 09 08:04:49 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-693c4dc9-7222-4e6c-afcd-a74e881f6b6c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024771057 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3024771057 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2106727458 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 2753995496 ps |
| CPU time | 235.59 seconds |
| Started | Jul 09 07:58:55 PM PDT 24 |
| Finished | Jul 09 08:02:52 PM PDT 24 |
| Peak memory | 608732 kb |
| Host | smart-930bc0c8-903e-4ca1-827f-90c18d4f9a25 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106727458 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.2106727458 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.4026265173 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 2614239622 ps |
| CPU time | 240.93 seconds |
| Started | Jul 09 07:58:56 PM PDT 24 |
| Finished | Jul 09 08:02:58 PM PDT 24 |
| Peak memory | 608792 kb |
| Host | smart-d9950eaf-10b3-4db7-8873-1c83abeac771 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026265173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.4026265173 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1857091558 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 3814600613 ps |
| CPU time | 261.1 seconds |
| Started | Jul 09 08:03:23 PM PDT 24 |
| Finished | Jul 09 08:07:45 PM PDT 24 |
| Peak memory | 609624 kb |
| Host | smart-2e4c1bd4-73ce-4d88-96d1-9ea2d412c6e9 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18570915 58 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1857091558 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.410647802 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 2649351720 ps |
| CPU time | 289.83 seconds |
| Started | Jul 09 08:03:06 PM PDT 24 |
| Finished | Jul 09 08:07:57 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-3eaafc8f-90cf-4b3a-bf6e-30b1389f8b45 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410647802 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_smoketest.410647802 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2924982914 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 2515153616 ps |
| CPU time | 299.35 seconds |
| Started | Jul 09 07:54:03 PM PDT 24 |
| Finished | Jul 09 07:59:04 PM PDT 24 |
| Peak memory | 608760 kb |
| Host | smart-145ba6a3-fd09-4557-be73-80d58f31cd60 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924982914 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.2924982914 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.4024596454 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 5455714438 ps |
| CPU time | 443.41 seconds |
| Started | Jul 09 08:00:07 PM PDT 24 |
| Finished | Jul 09 08:07:31 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-af9052e6-022e-4189-8ae5-b701b465daf8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4024596454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.4024596454 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3001884993 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2906068586 ps |
| CPU time | 124.69 seconds |
| Started | Jul 09 08:01:07 PM PDT 24 |
| Finished | Jul 09 08:03:13 PM PDT 24 |
| Peak memory | 621052 kb |
| Host | smart-4fda653d-cc8c-400b-9bf1-dce8a41d9311 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30018849 93 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.3001884993 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1256608895 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 11311690431 ps |
| CPU time | 755.95 seconds |
| Started | Jul 09 07:56:47 PM PDT 24 |
| Finished | Jul 09 08:09:23 PM PDT 24 |
| Peak memory | 623988 kb |
| Host | smart-85ad8382-9129-4366-8c2f-2caf78a5b645 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256608895 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.1256608895 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.588134336 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2641173357 ps |
| CPU time | 111.31 seconds |
| Started | Jul 09 07:56:33 PM PDT 24 |
| Finished | Jul 09 07:58:25 PM PDT 24 |
| Peak memory | 617880 kb |
| Host | smart-0eb7461d-ff42-4bc4-b16a-f9eaae9f1d02 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=588134336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.588134336 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1262418006 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 2405254132 ps |
| CPU time | 104.22 seconds |
| Started | Jul 09 07:55:00 PM PDT 24 |
| Finished | Jul 09 07:56:46 PM PDT 24 |
| Peak memory | 618100 kb |
| Host | smart-72b7c715-d34a-47b9-9359-d286db7ce76d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262418006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1262418006 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3982698142 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 50049043785 ps |
| CPU time | 6301.04 seconds |
| Started | Jul 09 08:00:58 PM PDT 24 |
| Finished | Jul 09 09:46:01 PM PDT 24 |
| Peak memory | 620520 kb |
| Host | smart-c4da879b-bec7-48fd-8f44-cd87a4d864b0 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982698142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_lc_walkthrough_prod.3982698142 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3269375220 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 10492834028 ps |
| CPU time | 899.89 seconds |
| Started | Jul 09 07:59:38 PM PDT 24 |
| Finished | Jul 09 08:14:39 PM PDT 24 |
| Peak memory | 620060 kb |
| Host | smart-db1c1e00-d922-45ed-a81e-0140f0c9c36e |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269375220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.3269375220 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1568724750 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 29130998875 ps |
| CPU time | 2747.19 seconds |
| Started | Jul 09 07:55:31 PM PDT 24 |
| Finished | Jul 09 08:41:19 PM PDT 24 |
| Peak memory | 620436 kb |
| Host | smart-3d5ec1d8-75d2-4322-856f-8fb894f7f68f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1568724750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.1568724750 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2690771573 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 17607002274 ps |
| CPU time | 3343.33 seconds |
| Started | Jul 09 07:57:21 PM PDT 24 |
| Finished | Jul 09 08:53:06 PM PDT 24 |
| Peak memory | 610956 kb |
| Host | smart-b7d9464b-d3a2-4e68-8bf3-13fa537c18f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2690771573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.2690771573 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1762492417 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 18684989168 ps |
| CPU time | 4032.99 seconds |
| Started | Jul 09 07:58:32 PM PDT 24 |
| Finished | Jul 09 09:05:46 PM PDT 24 |
| Peak memory | 610752 kb |
| Host | smart-3de82f3e-c70c-451c-a4bd-7b78a99e56cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1762492417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1762492417 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.819813976 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 24943905944 ps |
| CPU time | 4257.39 seconds |
| Started | Jul 09 08:02:28 PM PDT 24 |
| Finished | Jul 09 09:13:26 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-207bade0-b7a5-4974-ad96-82df7ba3d937 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819813976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.819813976 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.935392200 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 4119970600 ps |
| CPU time | 618.15 seconds |
| Started | Jul 09 07:59:00 PM PDT 24 |
| Finished | Jul 09 08:09:20 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-6c66c2b0-7e39-4697-8683-51f3f5cd2cce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935392200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.935392200 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.2760585935 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 6149965494 ps |
| CPU time | 736.1 seconds |
| Started | Jul 09 07:56:55 PM PDT 24 |
| Finished | Jul 09 08:09:11 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-68aadc2d-a709-4140-afae-5bcfa646ff59 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2760585935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.2760585935 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.2186255386 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 7620586880 ps |
| CPU time | 1934.54 seconds |
| Started | Jul 09 08:04:29 PM PDT 24 |
| Finished | Jul 09 08:36:45 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-ee1a999d-d0a8-402e-b073-61d934bcbfab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186255386 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.2186255386 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1909202925 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 3254992715 ps |
| CPU time | 230.75 seconds |
| Started | Jul 09 07:57:18 PM PDT 24 |
| Finished | Jul 09 08:01:09 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-71ca7e03-5d88-43f5-ac80-f0014cb81cb5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909202925 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.1909202925 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.250632583 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 7709508428 ps |
| CPU time | 1180.92 seconds |
| Started | Jul 09 07:54:40 PM PDT 24 |
| Finished | Jul 09 08:14:22 PM PDT 24 |
| Peak memory | 609484 kb |
| Host | smart-96acf1db-a3ad-4775-9c73-2fb8a37fb974 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=250632583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.250632583 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2161070059 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 9083282384 ps |
| CPU time | 1213.47 seconds |
| Started | Jul 09 07:55:33 PM PDT 24 |
| Finished | Jul 09 08:15:47 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-18418825-ae76-4f25-a311-c90f342e2e08 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2161070059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.2161070059 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1751029667 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 7516203524 ps |
| CPU time | 1091.89 seconds |
| Started | Jul 09 07:55:38 PM PDT 24 |
| Finished | Jul 09 08:13:51 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-41f44929-619e-4a6a-afbe-f77cf263c1fc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1751029667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.1751029667 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1271975673 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 4584283540 ps |
| CPU time | 593.12 seconds |
| Started | Jul 09 07:55:35 PM PDT 24 |
| Finished | Jul 09 08:05:29 PM PDT 24 |
| Peak memory | 608924 kb |
| Host | smart-714c9656-2ae0-43db-83e2-a865db951a98 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1271975673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1271975673 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3960665404 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 3405833024 ps |
| CPU time | 229.69 seconds |
| Started | Jul 09 08:04:18 PM PDT 24 |
| Finished | Jul 09 08:08:08 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-90b96e69-baa4-4cb3-af30-33a2a928461a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960665404 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.3960665404 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.2280100538 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3102465510 ps |
| CPU time | 341.16 seconds |
| Started | Jul 09 07:59:05 PM PDT 24 |
| Finished | Jul 09 08:04:47 PM PDT 24 |
| Peak memory | 608704 kb |
| Host | smart-2bc7c827-874b-4157-82c7-2cc4c518e53f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280100538 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.2280100538 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.4214312384 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 4772683944 ps |
| CPU time | 727.17 seconds |
| Started | Jul 09 08:04:00 PM PDT 24 |
| Finished | Jul 09 08:16:08 PM PDT 24 |
| Peak memory | 609580 kb |
| Host | smart-03d9514d-9186-4888-b8a7-9c99fc9b0f7b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214312384 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.4214312384 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.2763371921 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 4660129510 ps |
| CPU time | 414 seconds |
| Started | Jul 09 08:02:35 PM PDT 24 |
| Finished | Jul 09 08:09:29 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-da7671ac-5ec6-45e9-ad95-a0f82a0147b4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763371921 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.2763371921 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1118298066 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 8672777351 ps |
| CPU time | 1295.11 seconds |
| Started | Jul 09 07:57:12 PM PDT 24 |
| Finished | Jul 09 08:18:48 PM PDT 24 |
| Peak memory | 611508 kb |
| Host | smart-18f187d2-7c04-4370-ae38-8eb10d82cd4a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118 298066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.1118298066 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.597465161 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 29446480954 ps |
| CPU time | 2579.05 seconds |
| Started | Jul 09 07:58:40 PM PDT 24 |
| Finished | Jul 09 08:41:40 PM PDT 24 |
| Peak memory | 611260 kb |
| Host | smart-67594190-1db3-4abe-9bbf-e741bbac2ca5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597 465161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.597465161 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1677473568 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 16230384357 ps |
| CPU time | 1905.4 seconds |
| Started | Jul 09 07:55:01 PM PDT 24 |
| Finished | Jul 09 08:26:47 PM PDT 24 |
| Peak memory | 611696 kb |
| Host | smart-dce41f3e-d6c8-473e-a971-4628781c2401 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1677473568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1677473568 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2662280462 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 25181362392 ps |
| CPU time | 1491.67 seconds |
| Started | Jul 09 08:00:44 PM PDT 24 |
| Finished | Jul 09 08:25:37 PM PDT 24 |
| Peak memory | 610816 kb |
| Host | smart-9c59de85-f9cb-4728-9e60-e84141660d9e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2662280462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2662280462 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3492060766 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 9253698250 ps |
| CPU time | 957.32 seconds |
| Started | Jul 09 07:56:34 PM PDT 24 |
| Finished | Jul 09 08:12:32 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-7e1ed7a8-7155-4200-86ce-a2d6ef50f875 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492060766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.3492060766 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.591410641 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 6871255260 ps |
| CPU time | 507.41 seconds |
| Started | Jul 09 07:57:54 PM PDT 24 |
| Finished | Jul 09 08:06:22 PM PDT 24 |
| Peak memory | 616256 kb |
| Host | smart-982533f9-17e7-4b4c-a763-030d1a7a8c67 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=591410641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.591410641 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3419251755 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 6039721190 ps |
| CPU time | 396.28 seconds |
| Started | Jul 09 07:58:54 PM PDT 24 |
| Finished | Jul 09 08:05:33 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-e892a630-9388-4e10-849b-59082a4a2e4f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419251755 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.3419251755 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.644009112 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 3070645275 ps |
| CPU time | 321.22 seconds |
| Started | Jul 09 08:02:28 PM PDT 24 |
| Finished | Jul 09 08:07:50 PM PDT 24 |
| Peak memory | 616328 kb |
| Host | smart-d3685764-c21a-472a-a6b9-ba02b626cfb4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=644009112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.644009112 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3568480048 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 10834239489 ps |
| CPU time | 1366.48 seconds |
| Started | Jul 09 07:56:29 PM PDT 24 |
| Finished | Jul 09 08:19:17 PM PDT 24 |
| Peak memory | 611416 kb |
| Host | smart-646fb238-6a11-4706-844e-4597ac23d561 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568480048 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3568480048 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.255023867 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 6934636240 ps |
| CPU time | 537.29 seconds |
| Started | Jul 09 08:03:23 PM PDT 24 |
| Finished | Jul 09 08:12:21 PM PDT 24 |
| Peak memory | 610732 kb |
| Host | smart-d72ef460-211f-411d-a7ab-69a2b2798cd0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255023867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.255023867 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2835249381 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 7136751560 ps |
| CPU time | 650.59 seconds |
| Started | Jul 09 07:58:30 PM PDT 24 |
| Finished | Jul 09 08:09:21 PM PDT 24 |
| Peak memory | 610964 kb |
| Host | smart-5f7dbc8e-e204-4cef-99e0-0cb0c05932da |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835249381 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.2835249381 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1676991374 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 20440076175 ps |
| CPU time | 2490.68 seconds |
| Started | Jul 09 07:58:56 PM PDT 24 |
| Finished | Jul 09 08:40:29 PM PDT 24 |
| Peak memory | 611292 kb |
| Host | smart-f5bfa90b-94f9-49b1-bdad-66a316a6ee9b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1676991374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1676991374 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1719901334 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 22366347000 ps |
| CPU time | 1204.58 seconds |
| Started | Jul 09 08:00:35 PM PDT 24 |
| Finished | Jul 09 08:20:41 PM PDT 24 |
| Peak memory | 611104 kb |
| Host | smart-fdcedcf2-3abf-4215-bec2-ce1630351d92 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1719901334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1719901334 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.612306204 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 31027124904 ps |
| CPU time | 3379.25 seconds |
| Started | Jul 09 08:00:00 PM PDT 24 |
| Finished | Jul 09 08:56:21 PM PDT 24 |
| Peak memory | 612556 kb |
| Host | smart-c128a19b-08d0-4c6a-91d1-a3ad4207e2cc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612306204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.612306204 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.740989524 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 6022064880 ps |
| CPU time | 460.12 seconds |
| Started | Jul 09 08:03:24 PM PDT 24 |
| Finished | Jul 09 08:11:06 PM PDT 24 |
| Peak memory | 610860 kb |
| Host | smart-ca428458-a2ce-4f2f-bc5a-78c3980f56a9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=740989524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_sl eep_wake_up.740989524 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4052422405 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 3387479806 ps |
| CPU time | 278.02 seconds |
| Started | Jul 09 07:58:14 PM PDT 24 |
| Finished | Jul 09 08:02:53 PM PDT 24 |
| Peak memory | 608764 kb |
| Host | smart-34f9df92-288f-49a9-be2f-ccdce3c3fa12 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052422405 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.4052422405 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1244273483 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 4961153619 ps |
| CPU time | 535.82 seconds |
| Started | Jul 09 07:54:43 PM PDT 24 |
| Finished | Jul 09 08:03:40 PM PDT 24 |
| Peak memory | 616616 kb |
| Host | smart-fd015410-923e-4d71-a86a-ae3cd7c91140 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1244273483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.1244273483 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2531435838 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 6957973690 ps |
| CPU time | 797.93 seconds |
| Started | Jul 09 08:03:49 PM PDT 24 |
| Finished | Jul 09 08:17:08 PM PDT 24 |
| Peak memory | 611056 kb |
| Host | smart-a1bde171-fe8f-4c57-b8f6-84a88d380138 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2531435838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.2531435838 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2739415358 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 5258115204 ps |
| CPU time | 498.72 seconds |
| Started | Jul 09 08:04:14 PM PDT 24 |
| Finished | Jul 09 08:12:33 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-67b3ca7b-9e99-4b3c-a9ba-b27d3d6c5836 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739415358 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.2739415358 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3115639197 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 8164781380 ps |
| CPU time | 785.86 seconds |
| Started | Jul 09 07:55:02 PM PDT 24 |
| Finished | Jul 09 08:08:09 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-4d145504-0e41-4ce4-aa78-6f17cbd7e878 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115639197 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.3115639197 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.252314263 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 4286872836 ps |
| CPU time | 557.33 seconds |
| Started | Jul 09 07:59:04 PM PDT 24 |
| Finished | Jul 09 08:08:22 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-3c09d434-0164-4c40-8a45-14a50e179485 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252314263 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.252314263 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.994573412 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 5847797476 ps |
| CPU time | 517.72 seconds |
| Started | Jul 09 08:04:47 PM PDT 24 |
| Finished | Jul 09 08:13:26 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-6ff965a5-a49f-4b31-b498-8730428a3e07 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994573412 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.994573412 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2276232731 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 5263157368 ps |
| CPU time | 601.01 seconds |
| Started | Jul 09 07:58:05 PM PDT 24 |
| Finished | Jul 09 08:08:07 PM PDT 24 |
| Peak memory | 610912 kb |
| Host | smart-e2364102-6db5-450a-8442-1b3052c36dea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227 6232731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.2276232731 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3868454531 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9652766330 ps |
| CPU time | 626.49 seconds |
| Started | Jul 09 07:58:55 PM PDT 24 |
| Finished | Jul 09 08:09:22 PM PDT 24 |
| Peak memory | 624992 kb |
| Host | smart-db86b934-406c-47a7-9a77-96c10653fba1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868454531 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.3868454531 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3918694066 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 11875561784 ps |
| CPU time | 2016.75 seconds |
| Started | Jul 09 08:02:23 PM PDT 24 |
| Finished | Jul 09 08:36:00 PM PDT 24 |
| Peak memory | 610972 kb |
| Host | smart-a864c647-99b2-456c-951c-ee4033c9e44d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3918694066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.3918694066 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.384183024 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 5359575344 ps |
| CPU time | 606.79 seconds |
| Started | Jul 09 07:55:24 PM PDT 24 |
| Finished | Jul 09 08:05:32 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-1a1d2521-0c07-4c4f-a508-d3e64d7019df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384183024 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_rstmgr_cpu_info.384183024 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1041318529 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 5302700940 ps |
| CPU time | 660.82 seconds |
| Started | Jul 09 07:56:06 PM PDT 24 |
| Finished | Jul 09 08:07:08 PM PDT 24 |
| Peak memory | 641604 kb |
| Host | smart-9c5e26ad-630b-4ef6-b162-349ef07f4eeb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1041318529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.1041318529 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.765318115 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 2277919610 ps |
| CPU time | 177.82 seconds |
| Started | Jul 09 08:03:17 PM PDT 24 |
| Finished | Jul 09 08:06:16 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-23e326c9-38a0-4997-9a79-d58b0cc4cc7e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765318115 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_rstmgr_smoketest.765318115 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.294376588 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 4610484308 ps |
| CPU time | 314.75 seconds |
| Started | Jul 09 07:59:49 PM PDT 24 |
| Finished | Jul 09 08:05:05 PM PDT 24 |
| Peak memory | 610472 kb |
| Host | smart-59d0266f-d54e-44d5-81cd-264330bc2ad3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294376588 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rstmgr_sw_req.294376588 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3759939254 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 2825706540 ps |
| CPU time | 199.37 seconds |
| Started | Jul 09 07:57:15 PM PDT 24 |
| Finished | Jul 09 08:00:35 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-f553e687-c97e-4807-b87a-43df47d67876 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759939254 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.3759939254 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3392534646 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3480088560 ps |
| CPU time | 217.71 seconds |
| Started | Jul 09 08:01:17 PM PDT 24 |
| Finished | Jul 09 08:04:56 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-b7a05777-3ab3-46c1-88fd-6e28c0e9670e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3392534646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.3392534646 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3320623469 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 2853570557 ps |
| CPU time | 251.86 seconds |
| Started | Jul 09 08:02:08 PM PDT 24 |
| Finished | Jul 09 08:06:21 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-88835f81-68a7-4486-877a-66f76a3123e3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320623469 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.3320623469 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3955082055 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 2483173772 ps |
| CPU time | 134.91 seconds |
| Started | Jul 09 08:02:04 PM PDT 24 |
| Finished | Jul 09 08:04:21 PM PDT 24 |
| Peak memory | 641028 kb |
| Host | smart-fcb579d2-b21e-4ffe-8957-cb631fce6222 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955082055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.3955082055 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3308444528 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 5129339608 ps |
| CPU time | 866.81 seconds |
| Started | Jul 09 08:05:38 PM PDT 24 |
| Finished | Jul 09 08:20:06 PM PDT 24 |
| Peak memory | 609556 kb |
| Host | smart-52252633-e62e-491c-ac85-3bdcbe79e8ab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33084 44528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.3308444528 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1979625421 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 5454665512 ps |
| CPU time | 902.02 seconds |
| Started | Jul 09 07:58:02 PM PDT 24 |
| Finished | Jul 09 08:13:04 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-d4323fd5-a38c-458e-ad2b-b5038e6d6edb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1979625421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.1979625421 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4045137008 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 5291280873 ps |
| CPU time | 773.95 seconds |
| Started | Jul 09 08:03:03 PM PDT 24 |
| Finished | Jul 09 08:15:58 PM PDT 24 |
| Peak memory | 621728 kb |
| Host | smart-3e957062-ad4e-4e33-8456-74f9a119ee94 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045137008 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.4045137008 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3344864699 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 6061451208 ps |
| CPU time | 406.73 seconds |
| Started | Jul 09 08:01:56 PM PDT 24 |
| Finished | Jul 09 08:08:44 PM PDT 24 |
| Peak memory | 620600 kb |
| Host | smart-0245b03d-8c8a-4352-838f-81603538ea19 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344864699 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.3344864699 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4586037 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 4849670450 ps |
| CPU time | 400.13 seconds |
| Started | Jul 09 08:01:30 PM PDT 24 |
| Finished | Jul 09 08:08:12 PM PDT 24 |
| Peak memory | 621456 kb |
| Host | smart-5b1e52d0-6413-40d5-aa33-60ad4d74cb24 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458603 7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4586037 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2533664847 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2523278558 ps |
| CPU time | 217.41 seconds |
| Started | Jul 09 08:03:28 PM PDT 24 |
| Finished | Jul 09 08:07:06 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-63e61274-c28f-4bac-9305-b1509445b9d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533664847 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.2533664847 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.4220176610 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 3116205992 ps |
| CPU time | 278.01 seconds |
| Started | Jul 09 07:59:48 PM PDT 24 |
| Finished | Jul 09 08:04:28 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-98c2e625-c4e0-4a15-8e17-d2b7e7f35183 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220176610 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.4220176610 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2222796765 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 3486320768 ps |
| CPU time | 261.62 seconds |
| Started | Jul 09 08:04:21 PM PDT 24 |
| Finished | Jul 09 08:08:44 PM PDT 24 |
| Peak memory | 610184 kb |
| Host | smart-949e7175-d678-4910-8c56-14c45a6f6c5a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222796765 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.2222796765 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3267750040 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 3371951683 ps |
| CPU time | 262.38 seconds |
| Started | Jul 09 07:58:29 PM PDT 24 |
| Finished | Jul 09 08:02:52 PM PDT 24 |
| Peak memory | 610952 kb |
| Host | smart-e7fda7e5-cd49-46a2-9b47-64779b498bee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267750 040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.3267750040 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3587086405 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4720348568 ps |
| CPU time | 355.89 seconds |
| Started | Jul 09 07:53:55 PM PDT 24 |
| Finished | Jul 09 07:59:51 PM PDT 24 |
| Peak memory | 610716 kb |
| Host | smart-7cc37757-7650-42b1-b536-b696b26432c0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587086405 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.3587086405 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1705070698 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 9883710832 ps |
| CPU time | 1188.08 seconds |
| Started | Jul 09 07:56:21 PM PDT 24 |
| Finished | Jul 09 08:16:10 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-23bf515b-95dc-4ee7-a84c-831a1a5e8bdb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705070698 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.1705070698 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1315144582 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 8140617616 ps |
| CPU time | 673.83 seconds |
| Started | Jul 09 07:59:04 PM PDT 24 |
| Finished | Jul 09 08:10:18 PM PDT 24 |
| Peak memory | 610900 kb |
| Host | smart-c838e866-8597-4525-bf7b-d4cab6367d5b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315144582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.1315144582 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1029604042 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 6824471828 ps |
| CPU time | 602.41 seconds |
| Started | Jul 09 07:59:09 PM PDT 24 |
| Finished | Jul 09 08:09:12 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-e77c95b1-28d5-43eb-82f7-7fb957bcb9e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029604042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.1029604042 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2980132167 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6813459015 ps |
| CPU time | 715.13 seconds |
| Started | Jul 09 07:55:30 PM PDT 24 |
| Finished | Jul 09 08:07:26 PM PDT 24 |
| Peak memory | 625128 kb |
| Host | smart-926c1172-b9b7-468c-80ad-72e9bc34c5bb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980132167 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.2980132167 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.289377689 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 4789488494 ps |
| CPU time | 544.13 seconds |
| Started | Jul 09 07:57:33 PM PDT 24 |
| Finished | Jul 09 08:06:39 PM PDT 24 |
| Peak memory | 625188 kb |
| Host | smart-f17827eb-f53d-4053-93fe-8c0fc252bb2f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289377689 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.289377689 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.389106283 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3447452529 ps |
| CPU time | 383.53 seconds |
| Started | Jul 09 07:56:07 PM PDT 24 |
| Finished | Jul 09 08:02:31 PM PDT 24 |
| Peak memory | 618540 kb |
| Host | smart-60c34ee0-1124-4be2-b14a-a44901df4745 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389106283 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.389106283 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1631545782 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3024858900 ps |
| CPU time | 296.27 seconds |
| Started | Jul 09 07:54:33 PM PDT 24 |
| Finished | Jul 09 07:59:30 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-be0b0b3c-ff38-42ee-aa34-6eb39d3e8449 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631545782 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.1631545782 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1074487150 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 7588135620 ps |
| CPU time | 874.98 seconds |
| Started | Jul 09 07:59:59 PM PDT 24 |
| Finished | Jul 09 08:14:36 PM PDT 24 |
| Peak memory | 610928 kb |
| Host | smart-df16ee69-c599-4dd9-ba25-2718162a97a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074487150 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.1074487150 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.900183620 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 5245406366 ps |
| CPU time | 505.37 seconds |
| Started | Jul 09 07:58:59 PM PDT 24 |
| Finished | Jul 09 08:07:25 PM PDT 24 |
| Peak memory | 610216 kb |
| Host | smart-12d676d2-50d8-4fa6-a0a6-6f09cb0509df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900183620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.900183620 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2210871714 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 4328396057 ps |
| CPU time | 481.31 seconds |
| Started | Jul 09 08:02:22 PM PDT 24 |
| Finished | Jul 09 08:10:24 PM PDT 24 |
| Peak memory | 611088 kb |
| Host | smart-f228b2b4-efb1-4cb2-8745-c9524798bc85 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210871714 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2210871714 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.187095559 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 3124929884 ps |
| CPU time | 204.63 seconds |
| Started | Jul 09 08:03:35 PM PDT 24 |
| Finished | Jul 09 08:07:00 PM PDT 24 |
| Peak memory | 608672 kb |
| Host | smart-39cc2ea5-2a34-4559-8638-1c1faa45baf2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187095559 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_sram_ctrl_smoketest.187095559 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2233484233 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 20849177789 ps |
| CPU time | 4233.43 seconds |
| Started | Jul 09 07:57:20 PM PDT 24 |
| Finished | Jul 09 09:07:55 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-9fb82fc0-126a-4d10-9bcc-419fe91376be |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233484233 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.2233484233 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.330072025 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 5047518018 ps |
| CPU time | 705.02 seconds |
| Started | Jul 09 08:00:15 PM PDT 24 |
| Finished | Jul 09 08:12:02 PM PDT 24 |
| Peak memory | 613772 kb |
| Host | smart-c9580f80-cd66-4cb0-a22d-f24aca50ae35 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330072025 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.330072025 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1652432200 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 3273886676 ps |
| CPU time | 340.71 seconds |
| Started | Jul 09 07:56:38 PM PDT 24 |
| Finished | Jul 09 08:02:20 PM PDT 24 |
| Peak memory | 613800 kb |
| Host | smart-bac03fd4-ed3a-4ced-91a0-ef1e882e341f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652432200 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.1652432200 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.33838821 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3327159204 ps |
| CPU time | 380.86 seconds |
| Started | Jul 09 07:56:13 PM PDT 24 |
| Finished | Jul 09 08:02:35 PM PDT 24 |
| Peak memory | 609588 kb |
| Host | smart-2abadab2-68f7-4334-9cf3-22e1803a29e2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33838821 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.33838821 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.279737165 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 24690405500 ps |
| CPU time | 1783.29 seconds |
| Started | Jul 09 07:56:26 PM PDT 24 |
| Finished | Jul 09 08:26:10 PM PDT 24 |
| Peak memory | 614404 kb |
| Host | smart-ecce251a-1f44-4045-bab2-038045f79777 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27973716 5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.279737165 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1498130581 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 7479205400 ps |
| CPU time | 689.88 seconds |
| Started | Jul 09 08:00:47 PM PDT 24 |
| Finished | Jul 09 08:12:19 PM PDT 24 |
| Peak memory | 609652 kb |
| Host | smart-126a34a2-dcf9-4cdf-ab62-1a67c2507a15 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498130581 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1498130581 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1973243465 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 8497665844 ps |
| CPU time | 1904.45 seconds |
| Started | Jul 09 07:56:30 PM PDT 24 |
| Finished | Jul 09 08:28:15 PM PDT 24 |
| Peak memory | 618996 kb |
| Host | smart-b3c02a46-730b-4e0a-ba34-45ab47e428bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1973243465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.1973243465 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.1212240487 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 3007404350 ps |
| CPU time | 315.39 seconds |
| Started | Jul 09 08:03:28 PM PDT 24 |
| Finished | Jul 09 08:08:45 PM PDT 24 |
| Peak memory | 616428 kb |
| Host | smart-a73fcb21-0840-45e9-9e74-9b5a18cdabc0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212240487 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.1212240487 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.416063589 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 4700572528 ps |
| CPU time | 734.75 seconds |
| Started | Jul 09 08:01:27 PM PDT 24 |
| Finished | Jul 09 08:13:43 PM PDT 24 |
| Peak memory | 624472 kb |
| Host | smart-ca38ed74-f95f-49db-b73e-847fc060bfaa |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416063589 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.416063589 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.4273397091 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 13362534743 ps |
| CPU time | 2826.07 seconds |
| Started | Jul 09 07:58:30 PM PDT 24 |
| Finished | Jul 09 08:45:38 PM PDT 24 |
| Peak memory | 618996 kb |
| Host | smart-7f2bb9b7-3f8a-45e1-9c20-eb08fb372c67 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273397091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.4273397091 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1834686991 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 8356499634 ps |
| CPU time | 839.54 seconds |
| Started | Jul 09 07:56:41 PM PDT 24 |
| Finished | Jul 09 08:10:41 PM PDT 24 |
| Peak memory | 622456 kb |
| Host | smart-652fc78a-3c6b-4310-babf-d462c9020a5b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834686991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1834686991 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2666401554 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 79311823763 ps |
| CPU time | 13866.8 seconds |
| Started | Jul 09 07:54:53 PM PDT 24 |
| Finished | Jul 09 11:46:02 PM PDT 24 |
| Peak memory | 636380 kb |
| Host | smart-3a2482b2-0ef2-4fe4-aa73-eef7a4d14b34 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2666401554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.2666401554 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2732667976 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 4088904456 ps |
| CPU time | 686.89 seconds |
| Started | Jul 09 07:55:20 PM PDT 24 |
| Finished | Jul 09 08:06:48 PM PDT 24 |
| Peak memory | 622688 kb |
| Host | smart-79e6fb64-7a5c-47b9-a5c1-062daefce248 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732667976 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.2732667976 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1736367747 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 3936701240 ps |
| CPU time | 617.96 seconds |
| Started | Jul 09 07:57:53 PM PDT 24 |
| Finished | Jul 09 08:08:12 PM PDT 24 |
| Peak memory | 623992 kb |
| Host | smart-9f70436b-1701-4f9a-a727-687017525eef |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736367747 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.1736367747 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1875150147 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 4607475878 ps |
| CPU time | 696.07 seconds |
| Started | Jul 09 07:59:18 PM PDT 24 |
| Finished | Jul 09 08:10:55 PM PDT 24 |
| Peak memory | 623020 kb |
| Host | smart-a1406824-0d02-43ec-b541-37331476a0cd |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875150147 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.1875150147 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.1201780131 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 3396501457 ps |
| CPU time | 233.47 seconds |
| Started | Jul 09 08:00:17 PM PDT 24 |
| Finished | Jul 09 08:04:11 PM PDT 24 |
| Peak memory | 622248 kb |
| Host | smart-5ab361f8-09d7-4558-8205-b7b312e6fe07 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1201780131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.1201780131 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.2137661049 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 6975599980 ps |
| CPU time | 834.87 seconds |
| Started | Jul 09 08:00:28 PM PDT 24 |
| Finished | Jul 09 08:14:25 PM PDT 24 |
| Peak memory | 621412 kb |
| Host | smart-eb40a2de-e78e-466f-8633-07ca223ceab9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137661049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.2137661049 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.1650389812 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 15687350172 ps |
| CPU time | 3908.12 seconds |
| Started | Jul 09 08:10:16 PM PDT 24 |
| Finished | Jul 09 09:15:25 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-7fe5f56b-0bd8-4025-88e0-b72a80752d91 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650389812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.1650389812 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.3911304522 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 15026880942 ps |
| CPU time | 3435.11 seconds |
| Started | Jul 09 08:06:37 PM PDT 24 |
| Finished | Jul 09 09:03:53 PM PDT 24 |
| Peak memory | 610816 kb |
| Host | smart-b3f6bab2-7d48-43c5-9783-9e9842285028 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911304522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.3911304522 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1810608948 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 15652608854 ps |
| CPU time | 3150.67 seconds |
| Started | Jul 09 08:07:12 PM PDT 24 |
| Finished | Jul 09 08:59:43 PM PDT 24 |
| Peak memory | 611584 kb |
| Host | smart-103c9c32-829a-4484-92b6-cb92ff2d692a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810608948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.1810608948 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.3725851180 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 14745182836 ps |
| CPU time | 3262.95 seconds |
| Started | Jul 09 08:06:54 PM PDT 24 |
| Finished | Jul 09 09:01:18 PM PDT 24 |
| Peak memory | 611592 kb |
| Host | smart-5e8648fc-f646-4194-85ae-750fcbc13f81 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725851180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.3725851180 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.4078307358 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 11562760008 ps |
| CPU time | 2514.01 seconds |
| Started | Jul 09 08:07:32 PM PDT 24 |
| Finished | Jul 09 08:49:27 PM PDT 24 |
| Peak memory | 610904 kb |
| Host | smart-db9c7e7f-21c6-4d64-833a-7c69b935ed1d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078307358 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.4078307358 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2653891660 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 14665432162 ps |
| CPU time | 3878.82 seconds |
| Started | Jul 09 08:06:29 PM PDT 24 |
| Finished | Jul 09 09:11:09 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-37c9f737-0f83-46d8-9cff-cfa8e0560c4a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653891660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.2653891660 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.4054210138 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 14891146696 ps |
| CPU time | 4258.47 seconds |
| Started | Jul 09 08:06:18 PM PDT 24 |
| Finished | Jul 09 09:17:17 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-ce8001c1-ef06-4e2e-894c-4fb51828f5bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054210138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.4054210138 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.310806291 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 15168976504 ps |
| CPU time | 3071.19 seconds |
| Started | Jul 09 08:07:20 PM PDT 24 |
| Finished | Jul 09 08:58:32 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-251ba3b3-6733-4769-9a54-e52177002288 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310806291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_ no_meas.310806291 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.1842217146 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 14751007458 ps |
| CPU time | 3314.03 seconds |
| Started | Jul 09 08:06:38 PM PDT 24 |
| Finished | Jul 09 09:01:53 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-57670207-d87a-48ea-ad26-67c35b5aa72f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842217146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.1842217146 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.491719157 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 24557480562 ps |
| CPU time | 3461.26 seconds |
| Started | Jul 09 08:06:37 PM PDT 24 |
| Finished | Jul 09 09:04:19 PM PDT 24 |
| Peak memory | 611864 kb |
| Host | smart-d8c5bdc3-1b4b-4ee2-943f-d8d369a863d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491719157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.491719157 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.130561140 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 15672967324 ps |
| CPU time | 4636.42 seconds |
| Started | Jul 09 08:06:37 PM PDT 24 |
| Finished | Jul 09 09:23:54 PM PDT 24 |
| Peak memory | 610716 kb |
| Host | smart-23aa7ddb-3056-48c0-8fc4-5bdb63bd1233 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=130561140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.130561140 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.541739226 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 17733482958 ps |
| CPU time | 3675.16 seconds |
| Started | Jul 09 08:07:31 PM PDT 24 |
| Finished | Jul 09 09:08:48 PM PDT 24 |
| Peak memory | 610800 kb |
| Host | smart-ceb0026e-e338-4b0c-83d5-11ea550e680b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541739226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.541739226 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.625890786 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 4716089960 ps |
| CPU time | 304.98 seconds |
| Started | Jul 09 08:03:55 PM PDT 24 |
| Finished | Jul 09 08:09:01 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-4142a01d-6843-4f27-b8bb-d3b9d745b2cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625890786 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.625890786 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.241625839 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 6050742225 ps |
| CPU time | 241.07 seconds |
| Started | Jul 09 08:02:18 PM PDT 24 |
| Finished | Jul 09 08:06:20 PM PDT 24 |
| Peak memory | 624064 kb |
| Host | smart-0a086e92-1021-4ef4-867d-61dd09278650 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=241625839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.241625839 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.394164443 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 1802073516 ps |
| CPU time | 98.51 seconds |
| Started | Jul 09 08:02:08 PM PDT 24 |
| Finished | Jul 09 08:03:47 PM PDT 24 |
| Peak memory | 618024 kb |
| Host | smart-9c9fa7c8-dca0-4628-8b4d-a3f56e9e0338 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394164443 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.394164443 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3112494178 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 5602749464 ps |
| CPU time | 520.72 seconds |
| Started | Jul 09 08:22:25 PM PDT 24 |
| Finished | Jul 09 08:31:07 PM PDT 24 |
| Peak memory | 621596 kb |
| Host | smart-902c9d1a-ff0f-42d9-8336-1f6405a1a5f0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112494178 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.3112494178 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3356428054 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 8739713000 ps |
| CPU time | 1981.42 seconds |
| Started | Jul 09 08:16:47 PM PDT 24 |
| Finished | Jul 09 08:49:50 PM PDT 24 |
| Peak memory | 619044 kb |
| Host | smart-44e0c1af-0e2d-4d93-97bb-0f92b21585c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3356428054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.3356428054 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3855094961 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 3826796680 ps |
| CPU time | 417.44 seconds |
| Started | Jul 09 08:22:37 PM PDT 24 |
| Finished | Jul 09 08:29:36 PM PDT 24 |
| Peak memory | 648664 kb |
| Host | smart-e9b65362-7ca3-42f6-b097-a3eea93848e6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855094961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3855094961 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.1522323533 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 4984977336 ps |
| CPU time | 703.29 seconds |
| Started | Jul 09 08:22:14 PM PDT 24 |
| Finished | Jul 09 08:33:59 PM PDT 24 |
| Peak memory | 650828 kb |
| Host | smart-622eca8c-ee1a-425f-857a-ec9348af0dcc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1522323533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.1522323533 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2697953174 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 10620277347 ps |
| CPU time | 1043.6 seconds |
| Started | Jul 09 08:16:37 PM PDT 24 |
| Finished | Jul 09 08:34:02 PM PDT 24 |
| Peak memory | 623516 kb |
| Host | smart-e32b1df1-92b7-4ca4-95fc-b2abaaf0ee6f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697953174 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.2697953174 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1231416537 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 3917878050 ps |
| CPU time | 686.65 seconds |
| Started | Jul 09 08:17:42 PM PDT 24 |
| Finished | Jul 09 08:29:10 PM PDT 24 |
| Peak memory | 618836 kb |
| Host | smart-d77206b5-0a92-4013-bfaa-302ad4938479 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1231416537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1231416537 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2136118830 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 8706814551 ps |
| CPU time | 746.74 seconds |
| Started | Jul 09 08:16:58 PM PDT 24 |
| Finished | Jul 09 08:29:25 PM PDT 24 |
| Peak memory | 622320 kb |
| Host | smart-ee6e9c3f-1f74-4c55-8211-97fd5d730ff7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136118830 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.2136118830 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3068837646 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 3181138664 ps |
| CPU time | 514.99 seconds |
| Started | Jul 09 08:16:35 PM PDT 24 |
| Finished | Jul 09 08:25:11 PM PDT 24 |
| Peak memory | 618808 kb |
| Host | smart-2446d224-09cf-4bfe-85bd-edd30141e201 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3068837646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.3068837646 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3026431406 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 5173091952 ps |
| CPU time | 365.31 seconds |
| Started | Jul 09 08:20:20 PM PDT 24 |
| Finished | Jul 09 08:26:26 PM PDT 24 |
| Peak memory | 620388 kb |
| Host | smart-f35c1241-c101-4238-859c-1674547c7dc8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026431406 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.3026431406 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.345833978 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 7196201593 ps |
| CPU time | 495.22 seconds |
| Started | Jul 09 08:20:30 PM PDT 24 |
| Finished | Jul 09 08:28:46 PM PDT 24 |
| Peak memory | 622604 kb |
| Host | smart-40d4b3f7-14e8-4bb4-8996-7d899a813339 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345833978 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.345833978 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1948228906 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 3700976408 ps |
| CPU time | 624.61 seconds |
| Started | Jul 09 08:18:24 PM PDT 24 |
| Finished | Jul 09 08:28:49 PM PDT 24 |
| Peak memory | 618772 kb |
| Host | smart-e0f7fae0-6458-4b3e-b08c-64426682ca77 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1948228906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.1948228906 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.4069926979 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 3091652002 ps |
| CPU time | 335.96 seconds |
| Started | Jul 09 08:18:49 PM PDT 24 |
| Finished | Jul 09 08:24:25 PM PDT 24 |
| Peak memory | 648616 kb |
| Host | smart-f8a33352-ba31-4833-b130-fb02e2b9f259 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069926979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4069926979 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.1135011245 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 4765817686 ps |
| CPU time | 570.09 seconds |
| Started | Jul 09 08:20:24 PM PDT 24 |
| Finished | Jul 09 08:29:55 PM PDT 24 |
| Peak memory | 619924 kb |
| Host | smart-549c3c7f-f4ff-4e02-a11d-b3a739598b9f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1135011245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.1135011245 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1220894262 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 8247074352 ps |
| CPU time | 1611.86 seconds |
| Started | Jul 09 08:18:45 PM PDT 24 |
| Finished | Jul 09 08:45:38 PM PDT 24 |
| Peak memory | 619012 kb |
| Host | smart-fb543cc2-9575-489c-a09d-6c23a99375d8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1220894262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.1220894262 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.2087220273 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 4623943992 ps |
| CPU time | 453.31 seconds |
| Started | Jul 09 08:19:01 PM PDT 24 |
| Finished | Jul 09 08:26:35 PM PDT 24 |
| Peak memory | 650100 kb |
| Host | smart-e2888ee3-6e4f-4ac2-8201-0301367a89dc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2087220273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.2087220273 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.997495439 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 7405393568 ps |
| CPU time | 1467.58 seconds |
| Started | Jul 09 08:19:47 PM PDT 24 |
| Finished | Jul 09 08:44:16 PM PDT 24 |
| Peak memory | 618972 kb |
| Host | smart-97e29b4d-3271-4847-9d5d-f36adc27bc1f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=997495439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.997495439 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2949602489 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 5026802648 ps |
| CPU time | 622.43 seconds |
| Started | Jul 09 08:20:32 PM PDT 24 |
| Finished | Jul 09 08:30:55 PM PDT 24 |
| Peak memory | 618840 kb |
| Host | smart-dbb845a1-7671-45c3-b54c-afdf0e8f64bf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2949602489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.2949602489 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.1114560032 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 5089752106 ps |
| CPU time | 635.21 seconds |
| Started | Jul 09 08:19:53 PM PDT 24 |
| Finished | Jul 09 08:30:29 PM PDT 24 |
| Peak memory | 617104 kb |
| Host | smart-a1d7bcaa-f3d8-4a01-8c92-a50b79096b24 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1114560032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.1114560032 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.4166032528 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 9308427344 ps |
| CPU time | 1315.54 seconds |
| Started | Jul 09 08:18:32 PM PDT 24 |
| Finished | Jul 09 08:40:28 PM PDT 24 |
| Peak memory | 619304 kb |
| Host | smart-6f2670de-15a2-44db-a148-3ea212c17816 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4166032528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.4166032528 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2292825957 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 13263983624 ps |
| CPU time | 2543.84 seconds |
| Started | Jul 09 08:19:14 PM PDT 24 |
| Finished | Jul 09 09:01:38 PM PDT 24 |
| Peak memory | 618768 kb |
| Host | smart-022ba9f2-da47-4fe8-a380-9d16aa102e6c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2292825957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.2292825957 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.473374514 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 13644923986 ps |
| CPU time | 1700.85 seconds |
| Started | Jul 09 08:06:16 PM PDT 24 |
| Finished | Jul 09 08:34:38 PM PDT 24 |
| Peak memory | 608316 kb |
| Host | smart-74c4c6a9-76e4-4595-8170-3bef57cc256c |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473374514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.473374514 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4275999852 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4452833720 ps |
| CPU time | 382.49 seconds |
| Started | Jul 09 08:15:54 PM PDT 24 |
| Finished | Jul 09 08:22:18 PM PDT 24 |
| Peak memory | 620056 kb |
| Host | smart-90e91506-e227-4126-86e4-3071cd6b1665 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4 275999852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.4275999852 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.3606560507 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3144096912 ps |
| CPU time | 320.03 seconds |
| Started | Jul 09 08:04:21 PM PDT 24 |
| Finished | Jul 09 08:09:42 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-71aa5329-1a64-4044-90d9-bd599e636a23 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3606560507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.3606560507 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1556491588 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 18087286070 ps |
| CPU time | 430.39 seconds |
| Started | Jul 09 08:16:56 PM PDT 24 |
| Finished | Jul 09 08:24:08 PM PDT 24 |
| Peak memory | 619116 kb |
| Host | smart-1bc84f4d-be28-4432-a235-479c109e4d25 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1556491588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1556491588 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.3981004348 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 3309326328 ps |
| CPU time | 359.17 seconds |
| Started | Jul 09 08:14:52 PM PDT 24 |
| Finished | Jul 09 08:20:51 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-76f18b32-83f9-40ae-94e8-f690f93ef01b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981004348 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.3981004348 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2141491464 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 3303045802 ps |
| CPU time | 299.03 seconds |
| Started | Jul 09 08:14:31 PM PDT 24 |
| Finished | Jul 09 08:19:32 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-c354cf00-964c-424a-baeb-b4c1af27185a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141 491464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.2141491464 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.795459677 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 3201445566 ps |
| CPU time | 358.08 seconds |
| Started | Jul 09 08:17:19 PM PDT 24 |
| Finished | Jul 09 08:23:18 PM PDT 24 |
| Peak memory | 609012 kb |
| Host | smart-7a17fe9a-6a80-4426-99b5-771f10788779 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795459677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.795459677 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.1268417602 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2469274080 ps |
| CPU time | 235.08 seconds |
| Started | Jul 09 08:13:10 PM PDT 24 |
| Finished | Jul 09 08:17:06 PM PDT 24 |
| Peak memory | 609580 kb |
| Host | smart-528c01f9-bd4d-4065-8a58-77a0d258a8d2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268417602 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.1268417602 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.2537512169 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 2712665486 ps |
| CPU time | 244.04 seconds |
| Started | Jul 09 08:13:24 PM PDT 24 |
| Finished | Jul 09 08:17:29 PM PDT 24 |
| Peak memory | 608888 kb |
| Host | smart-a8095c4f-8aab-4443-9ed8-4ee004e424da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537512169 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.2537512169 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.2594085684 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 3531670978 ps |
| CPU time | 358.13 seconds |
| Started | Jul 09 08:14:56 PM PDT 24 |
| Finished | Jul 09 08:20:55 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-51aae44b-9173-4f8a-882f-9401a35c53e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594085684 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.2594085684 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.1645776418 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 3275322116 ps |
| CPU time | 205.26 seconds |
| Started | Jul 09 08:22:37 PM PDT 24 |
| Finished | Jul 09 08:26:05 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-1729ed40-09a5-4f45-b127-7699e8b9b8b0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645776418 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.1645776418 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.1348543554 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 3160462742 ps |
| CPU time | 412.68 seconds |
| Started | Jul 09 08:13:49 PM PDT 24 |
| Finished | Jul 09 08:20:42 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-cba55eee-f4f8-4d2b-8bfd-dd68513e526a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1348543554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.1348543554 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2487875108 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 4715218978 ps |
| CPU time | 671.85 seconds |
| Started | Jul 09 08:14:05 PM PDT 24 |
| Finished | Jul 09 08:25:17 PM PDT 24 |
| Peak memory | 619444 kb |
| Host | smart-aa8b7c81-9745-4c13-9522-3643e1ec241c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2487875108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.2487875108 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1407336511 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 7617249028 ps |
| CPU time | 1510.54 seconds |
| Started | Jul 09 08:15:17 PM PDT 24 |
| Finished | Jul 09 08:40:28 PM PDT 24 |
| Peak memory | 610756 kb |
| Host | smart-313cf2fd-950d-418e-931e-053e5453396d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1407336511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.1407336511 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3020454637 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 8856413584 ps |
| CPU time | 1564.52 seconds |
| Started | Jul 09 08:13:56 PM PDT 24 |
| Finished | Jul 09 08:40:01 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-a83a07c0-fa4a-4891-86c7-0ae36267a91b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020454637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.3020454637 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.148474119 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 13530454600 ps |
| CPU time | 1392.9 seconds |
| Started | Jul 09 08:13:20 PM PDT 24 |
| Finished | Jul 09 08:36:34 PM PDT 24 |
| Peak memory | 611288 kb |
| Host | smart-12d64e46-5687-4f4c-9497-3162953398fc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148474119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.148474119 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.1066240538 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 7970633850 ps |
| CPU time | 1322.15 seconds |
| Started | Jul 09 08:15:32 PM PDT 24 |
| Finished | Jul 09 08:37:35 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-f876bbcf-42c8-4765-865a-337cb7051dec |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1066240538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.1066240538 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1779499841 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 4033565384 ps |
| CPU time | 501.88 seconds |
| Started | Jul 09 08:15:05 PM PDT 24 |
| Finished | Jul 09 08:23:28 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-d3b79819-307e-4656-b877-07228b67974e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1779499841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.1779499841 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4020643465 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 255625952160 ps |
| CPU time | 11930.1 seconds |
| Started | Jul 09 08:13:22 PM PDT 24 |
| Finished | Jul 09 11:32:14 PM PDT 24 |
| Peak memory | 610996 kb |
| Host | smart-be8d0e78-a85f-43ef-9ba6-97e815e8acdd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4020643465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4020643465 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.2848141447 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4166585330 ps |
| CPU time | 481.79 seconds |
| Started | Jul 09 08:15:12 PM PDT 24 |
| Finished | Jul 09 08:23:14 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-1dfeb69c-e978-434d-a13f-295ff31015a8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848141447 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.2848141447 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.462472736 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 6171283944 ps |
| CPU time | 443.65 seconds |
| Started | Jul 09 08:14:52 PM PDT 24 |
| Finished | Jul 09 08:22:17 PM PDT 24 |
| Peak memory | 609584 kb |
| Host | smart-07468ec5-051e-4833-b6cb-41168965a4ad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=462472736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.462472736 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2836770398 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 2530007304 ps |
| CPU time | 346.29 seconds |
| Started | Jul 09 08:17:22 PM PDT 24 |
| Finished | Jul 09 08:23:09 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-401cddde-1064-4fe9-9322-1e8dac5ac59d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836770398 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.2836770398 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2982930406 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 9094914764 ps |
| CPU time | 669.79 seconds |
| Started | Jul 09 08:13:00 PM PDT 24 |
| Finished | Jul 09 08:24:10 PM PDT 24 |
| Peak memory | 611000 kb |
| Host | smart-7dfd1951-df8e-4fe7-bf11-623a1741d2f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2982930406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.2982930406 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1623841571 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 6068939444 ps |
| CPU time | 833.4 seconds |
| Started | Jul 09 08:14:50 PM PDT 24 |
| Finished | Jul 09 08:28:44 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-dc3bf970-0f95-4ff7-8575-a7cad43cd05d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1623841571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.1623841571 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.3374761923 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 7835176414 ps |
| CPU time | 883.2 seconds |
| Started | Jul 09 08:15:25 PM PDT 24 |
| Finished | Jul 09 08:30:10 PM PDT 24 |
| Peak memory | 617304 kb |
| Host | smart-07f22e97-9bf9-41c1-81d9-9164296cae6c |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374761923 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.3374761923 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3561648300 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 14864434355 ps |
| CPU time | 1877.03 seconds |
| Started | Jul 09 08:15:33 PM PDT 24 |
| Finished | Jul 09 08:46:51 PM PDT 24 |
| Peak memory | 610888 kb |
| Host | smart-3813a398-89e6-4b2d-9314-d12671e18b17 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561648300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.3561648300 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1759794574 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 4265031277 ps |
| CPU time | 410.91 seconds |
| Started | Jul 09 08:15:45 PM PDT 24 |
| Finished | Jul 09 08:22:38 PM PDT 24 |
| Peak memory | 622632 kb |
| Host | smart-42d8fb6a-abba-45a0-a8f3-7fb059ba41f1 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1759794574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.1759794574 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3758563821 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 4587136270 ps |
| CPU time | 713.73 seconds |
| Started | Jul 09 08:15:53 PM PDT 24 |
| Finished | Jul 09 08:27:48 PM PDT 24 |
| Peak memory | 613176 kb |
| Host | smart-67a4464f-7cde-40ec-8117-abae3781d424 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758563821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3758563821 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1126800071 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 3809104612 ps |
| CPU time | 631.08 seconds |
| Started | Jul 09 08:15:43 PM PDT 24 |
| Finished | Jul 09 08:26:15 PM PDT 24 |
| Peak memory | 612944 kb |
| Host | smart-7d9a2274-0035-4b89-b873-a9afed3d54ef |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126800071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1126800071 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3647347546 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 4065926216 ps |
| CPU time | 850.58 seconds |
| Started | Jul 09 08:16:29 PM PDT 24 |
| Finished | Jul 09 08:30:40 PM PDT 24 |
| Peak memory | 613148 kb |
| Host | smart-b830d484-2514-4d2e-98b6-c24d4231dd9d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647347546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3647347546 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3763838722 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 5203782722 ps |
| CPU time | 813.65 seconds |
| Started | Jul 09 08:16:32 PM PDT 24 |
| Finished | Jul 09 08:30:07 PM PDT 24 |
| Peak memory | 613236 kb |
| Host | smart-5c284c6f-989e-4280-8720-0bc1f7645336 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763838722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3763838722 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2106952995 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 4401340998 ps |
| CPU time | 595 seconds |
| Started | Jul 09 08:16:41 PM PDT 24 |
| Finished | Jul 09 08:26:37 PM PDT 24 |
| Peak memory | 613244 kb |
| Host | smart-ff09fd60-b52f-4fa7-81f8-e2708d13bdf3 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106952995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2106952995 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1356733083 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 5255460980 ps |
| CPU time | 640.54 seconds |
| Started | Jul 09 08:16:37 PM PDT 24 |
| Finished | Jul 09 08:27:18 PM PDT 24 |
| Peak memory | 613180 kb |
| Host | smart-08b9cd5d-4df4-4be6-ad70-17b3ddc80279 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356733083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1356733083 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1100518091 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 2495139552 ps |
| CPU time | 238.73 seconds |
| Started | Jul 09 08:16:19 PM PDT 24 |
| Finished | Jul 09 08:20:19 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-d09549de-6bc8-41b1-bb09-bc7b08d300b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100518091 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.1100518091 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1831892553 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 3869108770 ps |
| CPU time | 446.81 seconds |
| Started | Jul 09 08:16:00 PM PDT 24 |
| Finished | Jul 09 08:23:28 PM PDT 24 |
| Peak memory | 609556 kb |
| Host | smart-d189ff3b-ce66-423d-8989-b939ffbef2d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831892553 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.1831892553 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3409630827 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 2057504852 ps |
| CPU time | 201.81 seconds |
| Started | Jul 09 08:14:37 PM PDT 24 |
| Finished | Jul 09 08:17:59 PM PDT 24 |
| Peak memory | 608724 kb |
| Host | smart-e568a4fc-8a8d-40a3-a331-b927e406f4fa |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409630827 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.3409630827 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2730476907 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 5740198068 ps |
| CPU time | 461.88 seconds |
| Started | Jul 09 08:13:30 PM PDT 24 |
| Finished | Jul 09 08:21:13 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-4f157665-c12d-4387-872b-0c628005a220 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730476907 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.2730476907 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2398680165 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 5618028478 ps |
| CPU time | 521.6 seconds |
| Started | Jul 09 08:15:42 PM PDT 24 |
| Finished | Jul 09 08:24:25 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-bb36f2e0-c684-4e2f-af1f-7c35ed696566 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398680165 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.2398680165 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.310656807 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 4577102716 ps |
| CPU time | 392.56 seconds |
| Started | Jul 09 08:16:37 PM PDT 24 |
| Finished | Jul 09 08:23:10 PM PDT 24 |
| Peak memory | 609400 kb |
| Host | smart-c5e17f67-6cfa-4305-9c12-cd7f2743b6b9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310656807 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.310656807 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3374710223 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 5417740388 ps |
| CPU time | 589.46 seconds |
| Started | Jul 09 08:16:06 PM PDT 24 |
| Finished | Jul 09 08:25:57 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-699ae320-5893-4f0d-8154-3ea518519385 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374710223 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.3374710223 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1471157381 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 9682118088 ps |
| CPU time | 1327.65 seconds |
| Started | Jul 09 08:16:39 PM PDT 24 |
| Finished | Jul 09 08:38:48 PM PDT 24 |
| Peak memory | 611048 kb |
| Host | smart-0943b203-d3f7-4edb-8b39-45c41431fa87 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471157381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.1471157381 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2494336359 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 3440334372 ps |
| CPU time | 524.95 seconds |
| Started | Jul 09 08:16:41 PM PDT 24 |
| Finished | Jul 09 08:25:27 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-941ad8b8-0896-4cbf-8d35-37c4d1e59a7a |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494336359 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.2494336359 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1281963706 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 4524416294 ps |
| CPU time | 567.97 seconds |
| Started | Jul 09 08:16:47 PM PDT 24 |
| Finished | Jul 09 08:26:16 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-97a97bcc-a624-4ffa-ad51-75a616b307df |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281963706 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.1281963706 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.4236328642 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 3257361848 ps |
| CPU time | 280.39 seconds |
| Started | Jul 09 08:15:46 PM PDT 24 |
| Finished | Jul 09 08:20:27 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-969a39e5-da42-45f4-8075-f5dfc40130e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236328642 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.4236328642 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.80328284 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 26130859500 ps |
| CPU time | 5774.38 seconds |
| Started | Jul 09 08:16:18 PM PDT 24 |
| Finished | Jul 09 09:52:34 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-5288adb1-62fe-4aea-8dc0-1da653c6694e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80328284 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.80328284 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2855865909 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 74578149253 ps |
| CPU time | 12019.9 seconds |
| Started | Jul 09 08:15:42 PM PDT 24 |
| Finished | Jul 09 11:36:04 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-e089f8de-31e8-4a92-a1c9-78da83667200 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2855865909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.2855865909 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3472439593 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 5392285152 ps |
| CPU time | 420.64 seconds |
| Started | Jul 09 08:15:24 PM PDT 24 |
| Finished | Jul 09 08:22:25 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-dc5eadd7-3edd-421f-a6bf-6140521e4e20 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34724 39593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.3472439593 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.4089316471 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 2615443002 ps |
| CPU time | 238.74 seconds |
| Started | Jul 09 08:13:58 PM PDT 24 |
| Finished | Jul 09 08:17:58 PM PDT 24 |
| Peak memory | 609524 kb |
| Host | smart-7c79e33c-d6f8-4b0d-97bf-3ecdcff3a343 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089316471 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.4089316471 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3506473772 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 7452859678 ps |
| CPU time | 896.89 seconds |
| Started | Jul 09 08:15:24 PM PDT 24 |
| Finished | Jul 09 08:30:21 PM PDT 24 |
| Peak memory | 611312 kb |
| Host | smart-af70bd2f-7655-4a0d-b1f8-2026b9b27638 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506473772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.3506473772 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.1111008119 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 2461236126 ps |
| CPU time | 278.36 seconds |
| Started | Jul 09 08:17:02 PM PDT 24 |
| Finished | Jul 09 08:21:41 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-f2f48554-3587-4cb0-b606-fbdd66c3f619 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111008119 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.1111008119 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.2822714077 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 4984318096 ps |
| CPU time | 848.02 seconds |
| Started | Jul 09 08:05:14 PM PDT 24 |
| Finished | Jul 09 08:19:22 PM PDT 24 |
| Peak memory | 611172 kb |
| Host | smart-3ba08a82-1693-4d49-8941-2648a2598c7a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2822714077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.2822714077 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.3022110213 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 4350184984 ps |
| CPU time | 876.4 seconds |
| Started | Jul 09 08:14:24 PM PDT 24 |
| Finished | Jul 09 08:29:01 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-1bb682e4-925c-4218-9a92-255739aec2c1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022110213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.3022110213 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.1910994976 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2917027994 ps |
| CPU time | 513.59 seconds |
| Started | Jul 09 08:15:00 PM PDT 24 |
| Finished | Jul 09 08:23:34 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-0efcde77-de8a-45f4-bf28-428dd100846f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910994976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.1910994976 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.4066488261 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 6149969480 ps |
| CPU time | 1003.95 seconds |
| Started | Jul 09 08:15:57 PM PDT 24 |
| Finished | Jul 09 08:32:42 PM PDT 24 |
| Peak memory | 611268 kb |
| Host | smart-e36210e5-58ab-4d4a-af3b-724542e7dbd3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4066488261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.4066488261 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3511862556 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 7123046637 ps |
| CPU time | 1058.95 seconds |
| Started | Jul 09 08:16:28 PM PDT 24 |
| Finished | Jul 09 08:34:08 PM PDT 24 |
| Peak memory | 611348 kb |
| Host | smart-50137192-2f23-48b7-a259-557e540cc27b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511862556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.3511862556 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.3087498143 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 3160284052 ps |
| CPU time | 513.54 seconds |
| Started | Jul 09 08:15:07 PM PDT 24 |
| Finished | Jul 09 08:23:42 PM PDT 24 |
| Peak memory | 616892 kb |
| Host | smart-d903a5dc-dbba-4417-beee-b51f5c0b3bdd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087498143 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.3087498143 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.1854879955 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 7889149328 ps |
| CPU time | 1516.47 seconds |
| Started | Jul 09 08:14:53 PM PDT 24 |
| Finished | Jul 09 08:40:11 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-021ce0ce-e6e5-418d-a88e-6adbd87ab10d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854879955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.1854879955 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2064069473 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 2731762962 ps |
| CPU time | 198.44 seconds |
| Started | Jul 09 08:14:02 PM PDT 24 |
| Finished | Jul 09 08:17:22 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-e39d9f75-5a3e-4960-9845-9af5e7faade2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20 64069473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.2064069473 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.4165840272 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 8191929790 ps |
| CPU time | 2111.98 seconds |
| Started | Jul 09 08:16:01 PM PDT 24 |
| Finished | Jul 09 08:51:14 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-bf9c9b29-3c0f-4340-9e59-30ee027a4c37 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4165840272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.4165840272 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.4087600143 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 2984476800 ps |
| CPU time | 305.38 seconds |
| Started | Jul 09 08:16:45 PM PDT 24 |
| Finished | Jul 09 08:21:51 PM PDT 24 |
| Peak memory | 609228 kb |
| Host | smart-03c0f8d6-0eb1-47b8-8e3e-d85367ed9b17 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087600143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.4087600143 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3274546823 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 3651942890 ps |
| CPU time | 570.73 seconds |
| Started | Jul 09 08:16:58 PM PDT 24 |
| Finished | Jul 09 08:26:30 PM PDT 24 |
| Peak memory | 609548 kb |
| Host | smart-17580b72-f921-4aed-8191-c6dcb3d605f7 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3274546823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.3274546823 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.3473013925 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 3176538824 ps |
| CPU time | 368.46 seconds |
| Started | Jul 09 08:05:08 PM PDT 24 |
| Finished | Jul 09 08:11:18 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-cd595cbd-f32c-407e-9014-547193521334 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473013925 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.3473013925 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.4098453516 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 2694968300 ps |
| CPU time | 250.36 seconds |
| Started | Jul 09 08:04:56 PM PDT 24 |
| Finished | Jul 09 08:09:07 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-a4b5b770-428d-481a-95fb-9ddbfc3244f1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098453516 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.4098453516 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.2165124234 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 2890303784 ps |
| CPU time | 258.27 seconds |
| Started | Jul 09 08:05:39 PM PDT 24 |
| Finished | Jul 09 08:09:58 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-86e1436f-f5cc-4de7-95db-84b6d417b36e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165124234 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.2165124234 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.2454173222 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2494483248 ps |
| CPU time | 143.43 seconds |
| Started | Jul 09 08:04:28 PM PDT 24 |
| Finished | Jul 09 08:06:52 PM PDT 24 |
| Peak memory | 610744 kb |
| Host | smart-52550133-e85c-4688-b80c-9d5eb16bc0e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454173222 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.2454173222 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1636643253 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 58239571917 ps |
| CPU time | 11074.8 seconds |
| Started | Jul 09 08:04:02 PM PDT 24 |
| Finished | Jul 09 11:08:39 PM PDT 24 |
| Peak memory | 624976 kb |
| Host | smart-6fe7346d-512a-4c75-9b8e-e1d296f1c1bd |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1636643253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.1636643253 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.3697693465 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 6456304394 ps |
| CPU time | 625.5 seconds |
| Started | Jul 09 08:16:06 PM PDT 24 |
| Finished | Jul 09 08:26:32 PM PDT 24 |
| Peak memory | 611164 kb |
| Host | smart-c14b70c7-760d-47f3-bbf5-c9b753da9e06 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3697693465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.3697693465 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.278756494 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 6186125398 ps |
| CPU time | 1017.7 seconds |
| Started | Jul 09 08:09:20 PM PDT 24 |
| Finished | Jul 09 08:26:20 PM PDT 24 |
| Peak memory | 609072 kb |
| Host | smart-7e0d9c9f-fce0-4446-9d97-eeaefddfd959 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278756494 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_flash_ctrl_access.278756494 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2477871433 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 6104116912 ps |
| CPU time | 1142.8 seconds |
| Started | Jul 09 08:07:39 PM PDT 24 |
| Finished | Jul 09 08:26:43 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-9ae1083f-fc20-4803-9ec0-24b5b7536959 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477871433 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.2477871433 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3527212075 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 7234288426 ps |
| CPU time | 1080.39 seconds |
| Started | Jul 09 08:16:33 PM PDT 24 |
| Finished | Jul 09 08:34:34 PM PDT 24 |
| Peak memory | 609572 kb |
| Host | smart-2486a619-9999-4e9f-8262-bdc1346419c4 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527212075 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3527212075 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.99059382 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 5590823824 ps |
| CPU time | 999.24 seconds |
| Started | Jul 09 08:05:56 PM PDT 24 |
| Finished | Jul 09 08:22:36 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-ada5fe06-957b-4503-92aa-1949eab1eed7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99059382 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.99059382 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.240136620 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 3440305102 ps |
| CPU time | 521.96 seconds |
| Started | Jul 09 08:10:01 PM PDT 24 |
| Finished | Jul 09 08:18:44 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-b314a7a0-2ac8-4b4f-8b05-4a9293b8a65d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240136620 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.240136620 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2217975892 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 5167697824 ps |
| CPU time | 482.23 seconds |
| Started | Jul 09 08:06:04 PM PDT 24 |
| Finished | Jul 09 08:14:07 PM PDT 24 |
| Peak memory | 609624 kb |
| Host | smart-9515da67-2cf3-4af4-9a33-99d8dea2d64a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22 17975892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.2217975892 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2855035656 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 5049304200 ps |
| CPU time | 1367.12 seconds |
| Started | Jul 09 08:17:30 PM PDT 24 |
| Finished | Jul 09 08:40:18 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-ba2ed2a9-fd99-481f-8734-5e714801da40 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855035656 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.2855035656 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.440925763 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 4106720044 ps |
| CPU time | 759.82 seconds |
| Started | Jul 09 08:05:35 PM PDT 24 |
| Finished | Jul 09 08:18:16 PM PDT 24 |
| Peak memory | 610356 kb |
| Host | smart-adfeeefc-6bcc-450d-b67f-5bbc1fa3a156 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440925763 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.440925763 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1674708545 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4259775062 ps |
| CPU time | 702.78 seconds |
| Started | Jul 09 08:05:25 PM PDT 24 |
| Finished | Jul 09 08:17:09 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-471b5608-7097-4be0-9ab2-9d6ec85856aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1674708545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.1674708545 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2086249573 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 4487127296 ps |
| CPU time | 664.26 seconds |
| Started | Jul 09 08:17:42 PM PDT 24 |
| Finished | Jul 09 08:28:47 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-16a0963b-2bdf-4959-8a2e-30c2c4918893 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2086249573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2086249573 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2069022451 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 3200006518 ps |
| CPU time | 357.83 seconds |
| Started | Jul 09 08:16:09 PM PDT 24 |
| Finished | Jul 09 08:22:08 PM PDT 24 |
| Peak memory | 609576 kb |
| Host | smart-9190948e-2402-4499-b3ef-691a172a2c16 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069022 451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.2069022451 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.2458958352 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 24181392020 ps |
| CPU time | 1956.04 seconds |
| Started | Jul 09 08:05:42 PM PDT 24 |
| Finished | Jul 09 08:38:19 PM PDT 24 |
| Peak memory | 613500 kb |
| Host | smart-8ecdcf00-3177-4aed-8426-f0857cf27f74 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458958352 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.2458958352 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.83537448 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 19432030741 ps |
| CPU time | 1587.87 seconds |
| Started | Jul 09 08:14:11 PM PDT 24 |
| Finished | Jul 09 08:40:41 PM PDT 24 |
| Peak memory | 614720 kb |
| Host | smart-2584f8f2-be3a-4df3-96e6-2f97f38d24b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=83537448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.83537448 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2162487894 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 3344225032 ps |
| CPU time | 245.66 seconds |
| Started | Jul 09 08:21:27 PM PDT 24 |
| Finished | Jul 09 08:25:33 PM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-f75b7e74-c94d-49f0-8c79-9a1365b76631 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2162487894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.2162487894 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.1900732069 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 2732340076 ps |
| CPU time | 280.34 seconds |
| Started | Jul 09 08:19:46 PM PDT 24 |
| Finished | Jul 09 08:24:27 PM PDT 24 |
| Peak memory | 610532 kb |
| Host | smart-89bd2e8d-bfde-4d8b-9948-56a90d77ac9e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900732069 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.1900732069 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.2956101714 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 3356461168 ps |
| CPU time | 362.44 seconds |
| Started | Jul 09 08:14:40 PM PDT 24 |
| Finished | Jul 09 08:20:44 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-e3ff5683-cee4-4403-84a2-4d1f67cefead |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956101714 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.2956101714 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1414820265 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 2513908030 ps |
| CPU time | 229.08 seconds |
| Started | Jul 09 08:13:54 PM PDT 24 |
| Finished | Jul 09 08:17:44 PM PDT 24 |
| Peak memory | 608796 kb |
| Host | smart-d45fc017-d00b-4dca-97a5-b651c10a97d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414820265 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.1414820265 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.146722641 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 2769934512 ps |
| CPU time | 251.76 seconds |
| Started | Jul 09 08:16:27 PM PDT 24 |
| Finished | Jul 09 08:20:40 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-fc1cfd6e-2cc1-4c6b-bcfa-dacc47433cb0 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146722641 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.146722641 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.478619421 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 3074913193 ps |
| CPU time | 346.99 seconds |
| Started | Jul 09 08:16:54 PM PDT 24 |
| Finished | Jul 09 08:22:42 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-7b8c56f7-987d-4df7-9daf-41bd5a017790 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478619421 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.478619421 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.2831058612 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 7572925234 ps |
| CPU time | 1418.97 seconds |
| Started | Jul 09 08:14:28 PM PDT 24 |
| Finished | Jul 09 08:38:07 PM PDT 24 |
| Peak memory | 609060 kb |
| Host | smart-e653ab60-02c2-42f2-9e00-5c359d24a69a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831058612 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.2831058612 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.1624700225 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 3055040064 ps |
| CPU time | 297.13 seconds |
| Started | Jul 09 08:14:49 PM PDT 24 |
| Finished | Jul 09 08:19:48 PM PDT 24 |
| Peak memory | 608892 kb |
| Host | smart-6dfb0d76-14f3-41cf-bb0b-8d07955440ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624700225 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.1624700225 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.728770926 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 2958041280 ps |
| CPU time | 275.69 seconds |
| Started | Jul 09 08:17:26 PM PDT 24 |
| Finished | Jul 09 08:22:03 PM PDT 24 |
| Peak memory | 608680 kb |
| Host | smart-9b206f0b-2841-45f3-b481-5e92562eef6e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728770926 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_smoketest.728770926 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.4030729134 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 65794478982 ps |
| CPU time | 10720.7 seconds |
| Started | Jul 09 08:06:27 PM PDT 24 |
| Finished | Jul 09 11:05:10 PM PDT 24 |
| Peak memory | 624740 kb |
| Host | smart-e03a4da7-5c71-427a-a206-cb7f0d34ab73 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4030729134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.4030729134 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3689100899 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 10454541268 ps |
| CPU time | 2504.84 seconds |
| Started | Jul 09 08:14:54 PM PDT 24 |
| Finished | Jul 09 08:56:40 PM PDT 24 |
| Peak memory | 617796 kb |
| Host | smart-64a7a3ea-dc3f-4c5d-9cd5-0be6e64affa0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689 100899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.3689100899 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1279568084 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 12128723734 ps |
| CPU time | 1867.63 seconds |
| Started | Jul 09 08:16:28 PM PDT 24 |
| Finished | Jul 09 08:47:37 PM PDT 24 |
| Peak memory | 618152 kb |
| Host | smart-cb433c25-c00c-41e7-a325-3e7ad67ebf74 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1279568084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.1279568084 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2730910645 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 6432225843 ps |
| CPU time | 787.37 seconds |
| Started | Jul 09 08:15:13 PM PDT 24 |
| Finished | Jul 09 08:28:21 PM PDT 24 |
| Peak memory | 617344 kb |
| Host | smart-f9dbeab8-d4a4-4596-ada0-eb3981146c49 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2730910645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2730910645 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2780387737 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 12346126012 ps |
| CPU time | 1917.41 seconds |
| Started | Jul 09 08:13:59 PM PDT 24 |
| Finished | Jul 09 08:45:57 PM PDT 24 |
| Peak memory | 616964 kb |
| Host | smart-4bcf6154-d6da-4298-af60-3f80a6580070 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2780387737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.2780387737 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1189651731 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 10285165744 ps |
| CPU time | 1783.64 seconds |
| Started | Jul 09 08:15:46 PM PDT 24 |
| Finished | Jul 09 08:45:31 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-69a55384-2aae-4be6-9dcc-75699148b806 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11896 51731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.1189651731 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1155613190 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 12658919050 ps |
| CPU time | 3251.54 seconds |
| Started | Jul 09 08:14:57 PM PDT 24 |
| Finished | Jul 09 09:09:10 PM PDT 24 |
| Peak memory | 611300 kb |
| Host | smart-1b363989-6da5-4fff-b9e6-c868da7a69c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11556 13190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.1155613190 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.1991629389 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 2392117076 ps |
| CPU time | 251.13 seconds |
| Started | Jul 09 08:15:10 PM PDT 24 |
| Finished | Jul 09 08:19:22 PM PDT 24 |
| Peak memory | 608848 kb |
| Host | smart-75caace1-2391-4af5-a3b3-6467e0a0c2f4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991629389 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.1991629389 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.620835446 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 2941264216 ps |
| CPU time | 221.01 seconds |
| Started | Jul 09 08:05:59 PM PDT 24 |
| Finished | Jul 09 08:09:41 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-148e69d4-221b-47e5-b354-1f1419061d4b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620835446 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_entropy.620835446 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1835439664 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 2622811480 ps |
| CPU time | 304.99 seconds |
| Started | Jul 09 08:14:05 PM PDT 24 |
| Finished | Jul 09 08:19:11 PM PDT 24 |
| Peak memory | 608604 kb |
| Host | smart-bb4891e8-74cd-4f24-9067-992adbb68e9c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835439664 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.1835439664 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3030276709 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 3033243080 ps |
| CPU time | 300.75 seconds |
| Started | Jul 09 08:14:55 PM PDT 24 |
| Finished | Jul 09 08:19:57 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-f9110e30-07bb-4d30-8bf6-9f8d769fc3b1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030276709 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.3030276709 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1024277483 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2370234188 ps |
| CPU time | 339.93 seconds |
| Started | Jul 09 08:14:06 PM PDT 24 |
| Finished | Jul 09 08:19:47 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-ad39b2aa-0822-45c0-bc8a-92c00937b7bf |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024277483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.1024277483 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3255274820 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 3344623778 ps |
| CPU time | 315.82 seconds |
| Started | Jul 09 08:17:26 PM PDT 24 |
| Finished | Jul 09 08:22:44 PM PDT 24 |
| Peak memory | 609488 kb |
| Host | smart-ebcbda41-43a8-49a9-b100-d5f91e94c820 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32552748 20 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3255274820 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.4263579451 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3011173788 ps |
| CPU time | 385.16 seconds |
| Started | Jul 09 08:17:30 PM PDT 24 |
| Finished | Jul 09 08:23:55 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-22859312-4d51-4053-ad64-1b9ab26b0cfe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263579451 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.4263579451 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.833364677 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 3600289634 ps |
| CPU time | 350.91 seconds |
| Started | Jul 09 08:04:53 PM PDT 24 |
| Finished | Jul 09 08:10:45 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-60b41fa4-ceb7-4471-aac4-5b9f3678fd62 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833364677 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.833364677 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.4163679198 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 4280229972 ps |
| CPU time | 485.17 seconds |
| Started | Jul 09 08:15:29 PM PDT 24 |
| Finished | Jul 09 08:23:36 PM PDT 24 |
| Peak memory | 610828 kb |
| Host | smart-28e3aaf5-d623-4e41-bb3c-21065cf6318f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4163679198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.4163679198 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1619590639 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 2858887845 ps |
| CPU time | 161.6 seconds |
| Started | Jul 09 08:12:53 PM PDT 24 |
| Finished | Jul 09 08:15:36 PM PDT 24 |
| Peak memory | 620896 kb |
| Host | smart-632d86f1-482a-4d9f-95ef-9f03fa28e021 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16195906 39 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.1619590639 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.4086915295 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2533572163 ps |
| CPU time | 138.18 seconds |
| Started | Jul 09 08:12:39 PM PDT 24 |
| Finished | Jul 09 08:14:58 PM PDT 24 |
| Peak memory | 617888 kb |
| Host | smart-c68c121d-d9c7-48af-aa9d-67d7254e1e65 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4086915295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.4086915295 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1082396175 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1969977318 ps |
| CPU time | 98.86 seconds |
| Started | Jul 09 08:12:42 PM PDT 24 |
| Finished | Jul 09 08:14:22 PM PDT 24 |
| Peak memory | 618044 kb |
| Host | smart-8102533f-a2de-4da3-8467-13bad18d8de5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082396175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1082396175 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.4187463781 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 45867451040 ps |
| CPU time | 5759.66 seconds |
| Started | Jul 09 08:12:19 PM PDT 24 |
| Finished | Jul 09 09:48:20 PM PDT 24 |
| Peak memory | 619512 kb |
| Host | smart-4e2e4da1-f112-40bf-b869-0e7547e55893 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187463781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.4187463781 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2960254051 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 47098888717 ps |
| CPU time | 5474.88 seconds |
| Started | Jul 09 08:13:12 PM PDT 24 |
| Finished | Jul 09 09:44:29 PM PDT 24 |
| Peak memory | 620488 kb |
| Host | smart-81654c0a-8571-4369-9c8c-ab4c68eb2e1a |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960254051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.2960254051 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2677936531 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 10041780105 ps |
| CPU time | 972.61 seconds |
| Started | Jul 09 08:12:09 PM PDT 24 |
| Finished | Jul 09 08:28:22 PM PDT 24 |
| Peak memory | 619444 kb |
| Host | smart-a5a1e56b-bd55-4b10-a440-9829bc09b86f |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677936531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.2677936531 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3235617250 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 46326821584 ps |
| CPU time | 5489.2 seconds |
| Started | Jul 09 08:13:16 PM PDT 24 |
| Finished | Jul 09 09:44:46 PM PDT 24 |
| Peak memory | 620448 kb |
| Host | smart-3ee7a80b-fa2f-44ea-9e6b-793196b7dd6a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235617250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.3235617250 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1697773258 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 34833324269 ps |
| CPU time | 1809.29 seconds |
| Started | Jul 09 08:12:43 PM PDT 24 |
| Finished | Jul 09 08:42:53 PM PDT 24 |
| Peak memory | 620680 kb |
| Host | smart-4adcfcd9-2d9a-45c7-bad9-8e1edf1d08ca |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1697773258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.1697773258 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.817775244 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 17150127134 ps |
| CPU time | 3862.11 seconds |
| Started | Jul 09 08:13:55 PM PDT 24 |
| Finished | Jul 09 09:18:18 PM PDT 24 |
| Peak memory | 610756 kb |
| Host | smart-9eba9cc9-335f-4f88-a1b6-eb5ef7b4f809 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=817775244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.817775244 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2931175687 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 18380671247 ps |
| CPU time | 4282.7 seconds |
| Started | Jul 09 08:15:07 PM PDT 24 |
| Finished | Jul 09 09:26:31 PM PDT 24 |
| Peak memory | 610932 kb |
| Host | smart-7421bc67-4eb4-4446-9ed5-3eb088dbc4e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2931175687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2931175687 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1949840158 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 24899918450 ps |
| CPU time | 3390.41 seconds |
| Started | Jul 09 08:17:46 PM PDT 24 |
| Finished | Jul 09 09:14:19 PM PDT 24 |
| Peak memory | 610796 kb |
| Host | smart-8ca21345-a46d-4bbd-8b68-b345dd586986 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949840158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.1949840158 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1204719603 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3541296400 ps |
| CPU time | 426.54 seconds |
| Started | Jul 09 08:12:49 PM PDT 24 |
| Finished | Jul 09 08:19:56 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-25f86c9a-3344-4257-bed8-38c3f109cdd1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204719603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.1204719603 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.2900358459 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 5657404274 ps |
| CPU time | 1001.73 seconds |
| Started | Jul 09 08:13:09 PM PDT 24 |
| Finished | Jul 09 08:29:52 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-d942a97d-00c2-4aa9-b62c-d7ee48761737 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2900358459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.2900358459 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.2349469666 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 6804058788 ps |
| CPU time | 1190.21 seconds |
| Started | Jul 09 08:16:58 PM PDT 24 |
| Finished | Jul 09 08:36:49 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-01a55482-038b-4ed8-b63a-0c5cc6925388 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349469666 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.2349469666 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3706433036 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2601160731 ps |
| CPU time | 194.84 seconds |
| Started | Jul 09 08:12:01 PM PDT 24 |
| Finished | Jul 09 08:15:17 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-0872e63a-b443-4c1a-abb3-f69489e6e3f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706433036 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.3706433036 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.4289039331 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 7208291866 ps |
| CPU time | 1228.83 seconds |
| Started | Jul 09 08:06:39 PM PDT 24 |
| Finished | Jul 09 08:27:09 PM PDT 24 |
| Peak memory | 610816 kb |
| Host | smart-5398c094-7466-4440-a7fb-b7e0a2fdc7a5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4289039331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.4289039331 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1087981399 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 7036452404 ps |
| CPU time | 1360.16 seconds |
| Started | Jul 09 08:05:44 PM PDT 24 |
| Finished | Jul 09 08:28:25 PM PDT 24 |
| Peak memory | 610808 kb |
| Host | smart-ae071db5-370f-4aa3-bd45-c4e775c21ad2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1087981399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.1087981399 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3941963000 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 7047963106 ps |
| CPU time | 1294.12 seconds |
| Started | Jul 09 08:06:52 PM PDT 24 |
| Finished | Jul 09 08:28:27 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-c131147d-6012-46f0-a3c3-5e8e10d0fe1c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3941963000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.3941963000 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3298500224 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 4311856920 ps |
| CPU time | 673.33 seconds |
| Started | Jul 09 08:05:58 PM PDT 24 |
| Finished | Jul 09 08:17:12 PM PDT 24 |
| Peak memory | 610332 kb |
| Host | smart-925a3f90-acac-4f2e-8e5e-e27f1cc5698d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3298500224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3298500224 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1719814316 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 3391359652 ps |
| CPU time | 238.68 seconds |
| Started | Jul 09 08:19:00 PM PDT 24 |
| Finished | Jul 09 08:23:00 PM PDT 24 |
| Peak memory | 608820 kb |
| Host | smart-64685986-d06b-4d33-976b-54241c84a7f6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719814316 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.1719814316 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.2873214599 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 3266070016 ps |
| CPU time | 268.23 seconds |
| Started | Jul 09 08:04:30 PM PDT 24 |
| Finished | Jul 09 08:09:00 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-dd327de1-e2c7-4ec8-bf98-b4cf3ca82c75 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873214599 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.2873214599 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.2740496631 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 3301438760 ps |
| CPU time | 271.28 seconds |
| Started | Jul 09 08:16:31 PM PDT 24 |
| Finished | Jul 09 08:21:03 PM PDT 24 |
| Peak memory | 608880 kb |
| Host | smart-e078156e-53f2-44b2-bb9c-05873f582d5f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740496631 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.2740496631 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.435277462 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 4151137320 ps |
| CPU time | 672.96 seconds |
| Started | Jul 09 08:18:37 PM PDT 24 |
| Finished | Jul 09 08:29:51 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-29fdce56-7562-49e0-a63e-403da2fe8435 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435277462 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.435277462 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.727349878 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 9173113732 ps |
| CPU time | 514.5 seconds |
| Started | Jul 09 08:17:08 PM PDT 24 |
| Finished | Jul 09 08:25:43 PM PDT 24 |
| Peak memory | 611020 kb |
| Host | smart-21811f96-774d-4289-854f-551e372359f1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727349878 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.727349878 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_virus.1660403221 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 4859868486 ps |
| CPU time | 1161.39 seconds |
| Started | Jul 09 08:22:49 PM PDT 24 |
| Finished | Jul 09 08:42:11 PM PDT 24 |
| Peak memory | 625232 kb |
| Host | smart-ba536ce5-9fb0-4d30-93ff-4dbd479b29ae |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device= sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_ regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1660403221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.1660403221 |
| Directory | /workspace/2.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3237898309 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 10396611009 ps |
| CPU time | 1557.51 seconds |
| Started | Jul 09 08:16:34 PM PDT 24 |
| Finished | Jul 09 08:42:33 PM PDT 24 |
| Peak memory | 611544 kb |
| Host | smart-88b8ffcc-56b8-40da-b895-2c2afe1046f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237 898309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.3237898309 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1573135480 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 24740026455 ps |
| CPU time | 2177.48 seconds |
| Started | Jul 09 08:16:40 PM PDT 24 |
| Finished | Jul 09 08:52:58 PM PDT 24 |
| Peak memory | 611096 kb |
| Host | smart-56ccf6b5-e933-46ad-a7ed-368a2928c0c0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157 3135480 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.1573135480 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3377385056 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 13547192097 ps |
| CPU time | 1632.64 seconds |
| Started | Jul 09 08:13:36 PM PDT 24 |
| Finished | Jul 09 08:40:49 PM PDT 24 |
| Peak memory | 611592 kb |
| Host | smart-65caf962-02ff-486a-8504-f7eef30bfecc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3377385056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3377385056 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1143849567 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 25772590714 ps |
| CPU time | 1563.03 seconds |
| Started | Jul 09 08:15:32 PM PDT 24 |
| Finished | Jul 09 08:41:36 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-8351959d-285d-4626-8e61-95de49e606fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1143849567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1143849567 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3574606518 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 9634977760 ps |
| CPU time | 760.6 seconds |
| Started | Jul 09 08:12:53 PM PDT 24 |
| Finished | Jul 09 08:25:35 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-071a9d46-fec6-4bfe-8501-0e5bb4484c87 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574606518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.3574606518 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1790785558 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 5227172410 ps |
| CPU time | 529.19 seconds |
| Started | Jul 09 08:13:05 PM PDT 24 |
| Finished | Jul 09 08:21:55 PM PDT 24 |
| Peak memory | 617096 kb |
| Host | smart-ce1ff391-b5c1-4b85-9029-3041b0435987 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1790785558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1790785558 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1463522285 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 8300186175 ps |
| CPU time | 515.51 seconds |
| Started | Jul 09 08:14:49 PM PDT 24 |
| Finished | Jul 09 08:23:25 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-5223ccf1-b841-4f4d-b37d-83ee93491421 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463522285 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.1463522285 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2256161661 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 3937429290 ps |
| CPU time | 637.05 seconds |
| Started | Jul 09 08:13:15 PM PDT 24 |
| Finished | Jul 09 08:23:52 PM PDT 24 |
| Peak memory | 617068 kb |
| Host | smart-a2af7a90-f938-4217-afdd-87371212001d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2256161661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.2256161661 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4294245409 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 13520875672 ps |
| CPU time | 1420.75 seconds |
| Started | Jul 09 08:13:43 PM PDT 24 |
| Finished | Jul 09 08:37:25 PM PDT 24 |
| Peak memory | 611348 kb |
| Host | smart-1d3ad25b-ddf9-4ade-a6ac-faf6d743bb0d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294245409 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4294245409 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4045129257 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 7516890458 ps |
| CPU time | 413.53 seconds |
| Started | Jul 09 08:15:36 PM PDT 24 |
| Finished | Jul 09 08:22:30 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-541c453d-2000-407b-8ee9-4bac7676d1f6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045129257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4045129257 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2956159624 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 7184195140 ps |
| CPU time | 606.16 seconds |
| Started | Jul 09 08:14:53 PM PDT 24 |
| Finished | Jul 09 08:25:00 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-2391b9cf-0111-4f59-aefb-e17dfd1a7ffe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956159624 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.2956159624 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2214420172 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 23412576602 ps |
| CPU time | 1989.46 seconds |
| Started | Jul 09 08:13:12 PM PDT 24 |
| Finished | Jul 09 08:46:22 PM PDT 24 |
| Peak memory | 611572 kb |
| Host | smart-24cf2cb5-4b8b-4cdd-aa24-187251162c0d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2214420172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2214420172 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1606200474 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 22220715542 ps |
| CPU time | 1837.64 seconds |
| Started | Jul 09 08:15:32 PM PDT 24 |
| Finished | Jul 09 08:46:10 PM PDT 24 |
| Peak memory | 610860 kb |
| Host | smart-1056d46c-a922-446e-b6fc-2cb74bf171ad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1606200474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1606200474 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.691294583 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 28529892122 ps |
| CPU time | 3068.04 seconds |
| Started | Jul 09 08:14:23 PM PDT 24 |
| Finished | Jul 09 09:05:32 PM PDT 24 |
| Peak memory | 611680 kb |
| Host | smart-c56a99bf-10ff-4441-a011-9136bd8704b5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691294583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.691294583 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1946681152 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 5016815364 ps |
| CPU time | 432.92 seconds |
| Started | Jul 09 08:16:09 PM PDT 24 |
| Finished | Jul 09 08:23:23 PM PDT 24 |
| Peak memory | 611272 kb |
| Host | smart-c3ad6df1-d2f3-46cd-81fb-e784f7055feb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1946681152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1946681152 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2001018841 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 3367522348 ps |
| CPU time | 283.32 seconds |
| Started | Jul 09 08:14:19 PM PDT 24 |
| Finished | Jul 09 08:19:03 PM PDT 24 |
| Peak memory | 610004 kb |
| Host | smart-03d29c9a-d5ef-4c41-8918-79cfceac02d5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001018841 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.2001018841 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1951134841 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 4912953094 ps |
| CPU time | 428.31 seconds |
| Started | Jul 09 08:13:10 PM PDT 24 |
| Finished | Jul 09 08:20:19 PM PDT 24 |
| Peak memory | 617224 kb |
| Host | smart-5606cf88-1be2-4149-897e-34fe506ca196 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1951134841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.1951134841 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2847195786 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 5551471064 ps |
| CPU time | 421.98 seconds |
| Started | Jul 09 08:14:01 PM PDT 24 |
| Finished | Jul 09 08:21:04 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-9d77fb08-07ee-4569-ba84-aaf7ae7f349e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28471957 86 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2847195786 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3042745806 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 7309842044 ps |
| CPU time | 606.26 seconds |
| Started | Jul 09 08:16:38 PM PDT 24 |
| Finished | Jul 09 08:26:45 PM PDT 24 |
| Peak memory | 610828 kb |
| Host | smart-24eb1152-8f64-4d05-aebf-1ad7319f7d11 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3042745806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.3042745806 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3677860748 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 5317040200 ps |
| CPU time | 344.69 seconds |
| Started | Jul 09 08:19:22 PM PDT 24 |
| Finished | Jul 09 08:25:08 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-e0afe54c-4213-4c65-b87f-c0f862fc8bba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677860748 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.3677860748 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3724976976 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 6937183974 ps |
| CPU time | 1032.92 seconds |
| Started | Jul 09 08:16:28 PM PDT 24 |
| Finished | Jul 09 08:33:43 PM PDT 24 |
| Peak memory | 611008 kb |
| Host | smart-2837c23b-a07f-45f3-97da-85c4041fe56d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724976976 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.3724976976 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2110279460 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 4822343196 ps |
| CPU time | 623.29 seconds |
| Started | Jul 09 08:13:20 PM PDT 24 |
| Finished | Jul 09 08:23:44 PM PDT 24 |
| Peak memory | 610556 kb |
| Host | smart-873c5ee4-91ca-47f8-b858-90a6eabeddfb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110279460 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2110279460 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3160352316 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 5868049750 ps |
| CPU time | 484.42 seconds |
| Started | Jul 09 08:17:07 PM PDT 24 |
| Finished | Jul 09 08:25:12 PM PDT 24 |
| Peak memory | 610580 kb |
| Host | smart-e721677e-e06e-41c6-86d1-e8bb7b9889d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160352316 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.3160352316 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1468582334 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 5044045784 ps |
| CPU time | 613.57 seconds |
| Started | Jul 09 08:13:07 PM PDT 24 |
| Finished | Jul 09 08:23:21 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-529b0363-5c2d-4f85-bb0e-745ad12fae02 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146 8582334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.1468582334 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.777193301 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 10137502556 ps |
| CPU time | 600.47 seconds |
| Started | Jul 09 08:15:11 PM PDT 24 |
| Finished | Jul 09 08:25:13 PM PDT 24 |
| Peak memory | 619072 kb |
| Host | smart-15d60eed-221f-41ee-962d-8a041a7cad65 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777193301 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.777193301 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1836802114 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 12628277704 ps |
| CPU time | 1507.26 seconds |
| Started | Jul 09 08:13:02 PM PDT 24 |
| Finished | Jul 09 08:38:11 PM PDT 24 |
| Peak memory | 611088 kb |
| Host | smart-e4c1bcb5-90cf-4d9b-8dec-a61d8a7b5fb8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1836802114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.1836802114 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2311855270 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 5443292600 ps |
| CPU time | 544.92 seconds |
| Started | Jul 09 08:12:12 PM PDT 24 |
| Finished | Jul 09 08:21:18 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-bff0761d-b749-4d5e-83f2-7f908b98ded5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311855270 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.2311855270 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2978022187 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 5345375610 ps |
| CPU time | 839.1 seconds |
| Started | Jul 09 08:05:36 PM PDT 24 |
| Finished | Jul 09 08:19:36 PM PDT 24 |
| Peak memory | 641800 kb |
| Host | smart-90af736d-00cc-4314-a487-dd4b07b29101 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2978022187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.2978022187 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2556446972 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 3127685280 ps |
| CPU time | 364.53 seconds |
| Started | Jul 09 08:22:46 PM PDT 24 |
| Finished | Jul 09 08:28:53 PM PDT 24 |
| Peak memory | 608796 kb |
| Host | smart-614a8ddb-6f93-4a53-9232-e16aa2e23c48 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556446972 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.2556446972 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2355934487 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 5204321666 ps |
| CPU time | 392.33 seconds |
| Started | Jul 09 08:11:55 PM PDT 24 |
| Finished | Jul 09 08:18:27 PM PDT 24 |
| Peak memory | 610568 kb |
| Host | smart-26a0c71f-9043-4d96-ba92-07f9c20c82da |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355934487 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.2355934487 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1660119899 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 2541909128 ps |
| CPU time | 229.36 seconds |
| Started | Jul 09 08:11:57 PM PDT 24 |
| Finished | Jul 09 08:15:47 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-d914491f-8f9a-4c30-85ca-1872da391f3c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660119899 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.1660119899 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2738642720 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2858253792 ps |
| CPU time | 339.7 seconds |
| Started | Jul 09 08:15:25 PM PDT 24 |
| Finished | Jul 09 08:21:06 PM PDT 24 |
| Peak memory | 609568 kb |
| Host | smart-5c960340-1648-4bf4-93fb-c394277a54f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2738642720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.2738642720 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.820731759 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 3027838038 ps |
| CPU time | 268.03 seconds |
| Started | Jul 09 08:15:51 PM PDT 24 |
| Finished | Jul 09 08:20:20 PM PDT 24 |
| Peak memory | 610468 kb |
| Host | smart-d61691f4-374c-4751-94cf-8a78341057a6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820731759 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.820731759 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3460486 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 5990082632 ps |
| CPU time | 885.19 seconds |
| Started | Jul 09 08:12:51 PM PDT 24 |
| Finished | Jul 09 08:27:37 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-29a4fd20-7f60-4ecb-b6c8-c0b2c65ab90a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3460486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.3460486 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2682279643 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 6151633546 ps |
| CPU time | 630.73 seconds |
| Started | Jul 09 08:15:13 PM PDT 24 |
| Finished | Jul 09 08:25:44 PM PDT 24 |
| Peak memory | 624500 kb |
| Host | smart-cb03f2f4-d649-4a1a-b440-510467a9e3b5 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682279643 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.2682279643 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1064411358 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 6847980824 ps |
| CPU time | 433.67 seconds |
| Started | Jul 09 08:16:45 PM PDT 24 |
| Finished | Jul 09 08:24:00 PM PDT 24 |
| Peak memory | 621268 kb |
| Host | smart-b967b806-b234-4d1e-9f2a-b9828d9d2d3d |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064411358 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.1064411358 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3610231419 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 4010077340 ps |
| CPU time | 555.96 seconds |
| Started | Jul 09 08:15:58 PM PDT 24 |
| Finished | Jul 09 08:25:14 PM PDT 24 |
| Peak memory | 619412 kb |
| Host | smart-404d9145-d4ab-4383-a10a-1656d2b04e62 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361023 1419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3610231419 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.559812295 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 3426729544 ps |
| CPU time | 231.67 seconds |
| Started | Jul 09 08:17:33 PM PDT 24 |
| Finished | Jul 09 08:21:26 PM PDT 24 |
| Peak memory | 608708 kb |
| Host | smart-57b1f2b0-ccdb-44b2-8cef-5683836328ae |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559812295 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rv_plic_smoketest.559812295 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.983969231 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 2851164296 ps |
| CPU time | 233.41 seconds |
| Started | Jul 09 08:13:01 PM PDT 24 |
| Finished | Jul 09 08:16:56 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-9430c7f4-d33a-499b-a6c8-f9597ac5427c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983969231 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_timer_irq.983969231 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4022228259 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 2620661260 ps |
| CPU time | 191.28 seconds |
| Started | Jul 09 08:21:38 PM PDT 24 |
| Finished | Jul 09 08:24:51 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-6cae0670-9a5f-4d33-89f3-2ae1c647a315 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022228259 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.4022228259 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2274194262 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 5381992308 ps |
| CPU time | 843.62 seconds |
| Started | Jul 09 08:15:13 PM PDT 24 |
| Finished | Jul 09 08:29:17 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-ac2470da-5ba8-4a2b-82d2-333b5c3b90c6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22741942 62 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.2274194262 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.159277309 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 3526464634 ps |
| CPU time | 287.94 seconds |
| Started | Jul 09 08:15:22 PM PDT 24 |
| Finished | Jul 09 08:20:11 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-d1cc51d0-5608-4847-8b55-1ec6ff6b8daa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592773 09 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.159277309 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.161213007 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3784492994 ps |
| CPU time | 293.49 seconds |
| Started | Jul 09 08:05:12 PM PDT 24 |
| Finished | Jul 09 08:10:06 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-bbc3c01e-b2fa-4282-abb4-4184cc222659 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161213007 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.161213007 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.689957909 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 9736132692 ps |
| CPU time | 1655.83 seconds |
| Started | Jul 09 08:04:11 PM PDT 24 |
| Finished | Jul 09 08:31:48 PM PDT 24 |
| Peak memory | 610956 kb |
| Host | smart-c5bbeec7-678f-4a2a-8fd3-74d1a376ec2e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689957909 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.689957909 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3689990267 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 7645490704 ps |
| CPU time | 810.04 seconds |
| Started | Jul 09 08:14:39 PM PDT 24 |
| Finished | Jul 09 08:28:10 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-102ee0f4-a628-4198-9795-ac1a255d3b86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689990267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.3689990267 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2026168139 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 7015687544 ps |
| CPU time | 649.88 seconds |
| Started | Jul 09 08:14:33 PM PDT 24 |
| Finished | Jul 09 08:25:24 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-3e64ae39-1b2f-4d3e-b638-8e5954b4a741 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026168139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.2026168139 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.2300800889 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 6794998252 ps |
| CPU time | 759.58 seconds |
| Started | Jul 09 08:04:06 PM PDT 24 |
| Finished | Jul 09 08:16:47 PM PDT 24 |
| Peak memory | 625160 kb |
| Host | smart-18417d70-319d-4b32-b194-6300b8531230 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300800889 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.2300800889 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.995273579 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4363447959 ps |
| CPU time | 484.61 seconds |
| Started | Jul 09 08:06:06 PM PDT 24 |
| Finished | Jul 09 08:14:11 PM PDT 24 |
| Peak memory | 625196 kb |
| Host | smart-cff4b749-d5d7-44f4-a944-c7df8380983b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995273579 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.995273579 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.3775192004 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3108538059 ps |
| CPU time | 375.43 seconds |
| Started | Jul 09 08:05:01 PM PDT 24 |
| Finished | Jul 09 08:11:17 PM PDT 24 |
| Peak memory | 618916 kb |
| Host | smart-4d63e6e9-3aa6-407e-91cb-c176c34bab47 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775192004 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.3775192004 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2155704465 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2498700816 ps |
| CPU time | 209.7 seconds |
| Started | Jul 09 08:06:28 PM PDT 24 |
| Finished | Jul 09 08:09:59 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-fba9b202-a2e9-429b-81b0-01ddb9a586fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155704465 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.2155704465 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3666853762 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 7219231675 ps |
| CPU time | 620.96 seconds |
| Started | Jul 09 08:14:16 PM PDT 24 |
| Finished | Jul 09 08:24:37 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-1da23977-65e9-4e12-a650-8ba33a469e19 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666853762 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3666853762 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.209726246 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 4652775830 ps |
| CPU time | 622.06 seconds |
| Started | Jul 09 08:13:26 PM PDT 24 |
| Finished | Jul 09 08:23:49 PM PDT 24 |
| Peak memory | 609532 kb |
| Host | smart-847d0339-a5a5-470e-81b4-5b10f4aa6ee5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209726246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ sram_ctrl_scrambled_access.209726246 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3465241656 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3974498880 ps |
| CPU time | 574.62 seconds |
| Started | Jul 09 08:15:16 PM PDT 24 |
| Finished | Jul 09 08:24:51 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-91daa6c6-d840-4194-9381-972a12de890b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465241656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3465241656 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4278412240 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 4274970109 ps |
| CPU time | 633.84 seconds |
| Started | Jul 09 08:17:48 PM PDT 24 |
| Finished | Jul 09 08:28:23 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-3bc42c6d-7cba-41a2-86d8-2d5e3ef1641d |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278412240 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4278412240 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1073197049 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 2998754356 ps |
| CPU time | 235.35 seconds |
| Started | Jul 09 08:17:36 PM PDT 24 |
| Finished | Jul 09 08:21:32 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-04573846-4430-4135-8dbf-6d3810a482d5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073197049 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.1073197049 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3472621646 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 20504253582 ps |
| CPU time | 3489.28 seconds |
| Started | Jul 09 08:13:47 PM PDT 24 |
| Finished | Jul 09 09:11:58 PM PDT 24 |
| Peak memory | 611004 kb |
| Host | smart-96af0459-5ba1-461e-9f2f-03324387a322 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472621646 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.3472621646 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1651284423 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 4388272362 ps |
| CPU time | 561.81 seconds |
| Started | Jul 09 08:12:46 PM PDT 24 |
| Finished | Jul 09 08:22:10 PM PDT 24 |
| Peak memory | 614232 kb |
| Host | smart-0dc1b292-48ef-4227-8f1a-a867c8d88094 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651284423 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.1651284423 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.275551369 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3346796337 ps |
| CPU time | 375.9 seconds |
| Started | Jul 09 08:13:01 PM PDT 24 |
| Finished | Jul 09 08:19:19 PM PDT 24 |
| Peak memory | 613492 kb |
| Host | smart-c17c5c79-ae0e-4683-9d8a-42feb7b2c6d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275551369 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.275551369 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2959066743 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4163865050 ps |
| CPU time | 407.72 seconds |
| Started | Jul 09 08:13:08 PM PDT 24 |
| Finished | Jul 09 08:19:57 PM PDT 24 |
| Peak memory | 609572 kb |
| Host | smart-63cb5013-c56a-4e1c-823a-118e08f47710 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959066743 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.2959066743 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3236830256 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 6247506840 ps |
| CPU time | 454.65 seconds |
| Started | Jul 09 08:12:40 PM PDT 24 |
| Finished | Jul 09 08:20:16 PM PDT 24 |
| Peak memory | 611032 kb |
| Host | smart-3a4e75b2-e59d-4551-83ec-1823de3bd0c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236830256 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3236830256 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.59154268 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 3788723552 ps |
| CPU time | 669.72 seconds |
| Started | Jul 09 08:04:10 PM PDT 24 |
| Finished | Jul 09 08:15:21 PM PDT 24 |
| Peak memory | 618720 kb |
| Host | smart-3344d912-9b2f-46f6-972e-13b3a0893349 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=59154268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.59154268 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.945117125 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 2464808496 ps |
| CPU time | 224.28 seconds |
| Started | Jul 09 08:19:42 PM PDT 24 |
| Finished | Jul 09 08:23:27 PM PDT 24 |
| Peak memory | 616532 kb |
| Host | smart-9f1c79a4-d28e-420b-b6e4-463953e83ff8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945117125 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_uart_smoketest.945117125 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.1530965232 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 4514945596 ps |
| CPU time | 553.72 seconds |
| Started | Jul 09 08:03:40 PM PDT 24 |
| Finished | Jul 09 08:12:55 PM PDT 24 |
| Peak memory | 622976 kb |
| Host | smart-25851436-0543-4b4e-bb51-43f2f9994509 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530965232 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.1530965232 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2105489094 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 4129121159 ps |
| CPU time | 702.38 seconds |
| Started | Jul 09 08:04:35 PM PDT 24 |
| Finished | Jul 09 08:16:19 PM PDT 24 |
| Peak memory | 624900 kb |
| Host | smart-ccf5cdd0-9240-49bf-9efd-d75dd2f9f4cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105489094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.2105489094 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.633135119 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 4204946919 ps |
| CPU time | 438.13 seconds |
| Started | Jul 09 08:06:43 PM PDT 24 |
| Finished | Jul 09 08:14:02 PM PDT 24 |
| Peak memory | 624924 kb |
| Host | smart-23d63486-30a4-4623-8fb2-1bb1a8114eae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633135119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.633135119 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.500949844 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 78711675388 ps |
| CPU time | 13840.2 seconds |
| Started | Jul 09 08:04:52 PM PDT 24 |
| Finished | Jul 09 11:55:35 PM PDT 24 |
| Peak memory | 636416 kb |
| Host | smart-c6c8d879-8acc-4d86-927a-1489f775ff87 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=500949844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.500949844 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3614026206 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 3855465004 ps |
| CPU time | 662.82 seconds |
| Started | Jul 09 08:06:35 PM PDT 24 |
| Finished | Jul 09 08:17:38 PM PDT 24 |
| Peak memory | 624112 kb |
| Host | smart-35a47b49-9dc9-4f96-84f2-b4cf11fda6af |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614026206 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.3614026206 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2027551187 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 4185554750 ps |
| CPU time | 695.06 seconds |
| Started | Jul 09 08:04:46 PM PDT 24 |
| Finished | Jul 09 08:16:21 PM PDT 24 |
| Peak memory | 622724 kb |
| Host | smart-1db56ee5-9c16-4a49-b26f-93f98b0b3fa0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027551187 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.2027551187 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3973589450 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 4669137012 ps |
| CPU time | 655.59 seconds |
| Started | Jul 09 08:07:02 PM PDT 24 |
| Finished | Jul 09 08:17:58 PM PDT 24 |
| Peak memory | 623028 kb |
| Host | smart-af196e1d-ec6c-4806-9bc9-a8ccfbad6b6f |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973589450 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.3973589450 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.1960880895 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2807889159 ps |
| CPU time | 184.5 seconds |
| Started | Jul 09 08:14:01 PM PDT 24 |
| Finished | Jul 09 08:17:07 PM PDT 24 |
| Peak memory | 621796 kb |
| Host | smart-26dce329-e55d-450d-9a5f-1b4687391b85 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1960880895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.1960880895 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.2881834561 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 2248298028 ps |
| CPU time | 143.64 seconds |
| Started | Jul 09 08:14:10 PM PDT 24 |
| Finished | Jul 09 08:16:35 PM PDT 24 |
| Peak memory | 621352 kb |
| Host | smart-020e4c9e-7446-4436-bce2-85de01cbd047 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881834561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.2881834561 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.2739070202 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 4974334725 ps |
| CPU time | 436.18 seconds |
| Started | Jul 09 08:15:17 PM PDT 24 |
| Finished | Jul 09 08:22:35 PM PDT 24 |
| Peak memory | 621300 kb |
| Host | smart-1c5cbc57-b9ec-4aa5-ac4d-3bec70d5776e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2739070202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.2739070202 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.3807125595 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 15319885096 ps |
| CPU time | 3241.65 seconds |
| Started | Jul 09 08:22:45 PM PDT 24 |
| Finished | Jul 09 09:16:48 PM PDT 24 |
| Peak memory | 610756 kb |
| Host | smart-e4f13f61-ac88-4315-b3a9-022b34f71573 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807125595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.3807125595 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.1540251995 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 15714526042 ps |
| CPU time | 4618.44 seconds |
| Started | Jul 09 08:20:49 PM PDT 24 |
| Finished | Jul 09 09:37:48 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-7f4931d5-2dc3-4b51-bda7-8990583241bd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540251995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.1540251995 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1772258201 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 15594202474 ps |
| CPU time | 3581.39 seconds |
| Started | Jul 09 08:19:32 PM PDT 24 |
| Finished | Jul 09 09:19:14 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-f1399cf7-71be-4e9d-a131-938dd49908ac |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772258201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.1772258201 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.4204436284 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 15493806092 ps |
| CPU time | 3368.27 seconds |
| Started | Jul 09 08:22:47 PM PDT 24 |
| Finished | Jul 09 09:18:58 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-ddfce56d-55bd-4899-bddc-397ce744d41d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204436284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.4204436284 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.83432287 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 11577402640 ps |
| CPU time | 2713.61 seconds |
| Started | Jul 09 08:23:03 PM PDT 24 |
| Finished | Jul 09 09:08:17 PM PDT 24 |
| Peak memory | 610824 kb |
| Host | smart-0b615c7c-df5d-4350-8e80-a2ba899fbcda |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83432287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.rom_e2e_asm_init_test_unlocked0.83432287 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3339132306 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 14827003074 ps |
| CPU time | 3787.77 seconds |
| Started | Jul 09 08:23:36 PM PDT 24 |
| Finished | Jul 09 09:26:45 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-76a6b12c-20a8-4abc-a2e9-34b4c41f2ef6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339132306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3339132306 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1032676572 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 15218387416 ps |
| CPU time | 3422.51 seconds |
| Started | Jul 09 08:19:34 PM PDT 24 |
| Finished | Jul 09 09:16:37 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-374b5bb8-797b-45af-a89f-91922da8d496 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032676572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.1032676572 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2899739942 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 15481050350 ps |
| CPU time | 3637.81 seconds |
| Started | Jul 09 08:22:12 PM PDT 24 |
| Finished | Jul 09 09:22:51 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-128e1526-c2cd-4552-ae5b-363c80aad176 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899739942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.2899739942 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.321869099 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 14798303119 ps |
| CPU time | 4048.06 seconds |
| Started | Jul 09 08:23:32 PM PDT 24 |
| Finished | Jul 09 09:31:01 PM PDT 24 |
| Peak memory | 611496 kb |
| Host | smart-1dc7fc45-f414-4e39-8df6-65c5b51b9e02 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321869099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_s hutdown_exception_c.321869099 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.297753160 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 26894053384 ps |
| CPU time | 3009.56 seconds |
| Started | Jul 09 08:21:01 PM PDT 24 |
| Finished | Jul 09 09:11:12 PM PDT 24 |
| Peak memory | 612908 kb |
| Host | smart-5d8c5548-41f1-4658-87d5-cefb038e5d11 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297753160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.297753160 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.4154965321 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 16930606400 ps |
| CPU time | 4344.23 seconds |
| Started | Jul 09 08:22:09 PM PDT 24 |
| Finished | Jul 09 09:34:34 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-5d332ce1-3465-4e4e-9a17-55b0c290d59f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154965321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.4154965321 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.4063574267 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 5010110780 ps |
| CPU time | 594.87 seconds |
| Started | Jul 09 08:15:59 PM PDT 24 |
| Finished | Jul 09 08:25:55 PM PDT 24 |
| Peak memory | 609756 kb |
| Host | smart-287a67e4-d6bf-47f2-bb98-a8159854503a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063574267 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.4063574267 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.526577813 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 4929980654 ps |
| CPU time | 338.13 seconds |
| Started | Jul 09 08:18:28 PM PDT 24 |
| Finished | Jul 09 08:24:07 PM PDT 24 |
| Peak memory | 618584 kb |
| Host | smart-3a5117de-8b84-4de5-a80d-1a3fce185195 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=526577813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.526577813 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.2135778746 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2316784312 ps |
| CPU time | 120.27 seconds |
| Started | Jul 09 08:18:00 PM PDT 24 |
| Finished | Jul 09 08:20:00 PM PDT 24 |
| Peak memory | 617928 kb |
| Host | smart-6cf38abe-a1eb-41df-88d4-f4688d684e39 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135778746 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.2135778746 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.741055991 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 3932903208 ps |
| CPU time | 413.83 seconds |
| Started | Jul 09 08:19:42 PM PDT 24 |
| Finished | Jul 09 08:26:37 PM PDT 24 |
| Peak memory | 648976 kb |
| Host | smart-2513ffef-a5cb-468a-8089-46ee5cffe097 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741055991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_s w_alert_handler_lpg_sleep_mode_alerts.741055991 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.1477682699 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 5829049448 ps |
| CPU time | 717.09 seconds |
| Started | Jul 09 08:18:55 PM PDT 24 |
| Finished | Jul 09 08:30:53 PM PDT 24 |
| Peak memory | 650380 kb |
| Host | smart-a4fc780b-fd91-4f2f-af26-b20602e775e0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1477682699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.1477682699 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2346604786 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 4599347200 ps |
| CPU time | 575.33 seconds |
| Started | Jul 09 08:18:31 PM PDT 24 |
| Finished | Jul 09 08:28:07 PM PDT 24 |
| Peak memory | 649148 kb |
| Host | smart-fe198569-19ce-4e34-a38c-4399df6108d3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346604786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2346604786 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.716016181 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3875728330 ps |
| CPU time | 461.72 seconds |
| Started | Jul 09 08:21:52 PM PDT 24 |
| Finished | Jul 09 08:29:34 PM PDT 24 |
| Peak memory | 648868 kb |
| Host | smart-23ad6ed7-b273-4fe3-9e3f-7f358f361021 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716016181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_s w_alert_handler_lpg_sleep_mode_alerts.716016181 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.2616176609 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 6004809480 ps |
| CPU time | 612.27 seconds |
| Started | Jul 09 08:18:52 PM PDT 24 |
| Finished | Jul 09 08:29:05 PM PDT 24 |
| Peak memory | 617052 kb |
| Host | smart-2ab3f0b8-c437-4f29-ad46-5e464db0034f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2616176609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.2616176609 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2713955636 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3496779520 ps |
| CPU time | 357.68 seconds |
| Started | Jul 09 08:21:33 PM PDT 24 |
| Finished | Jul 09 08:27:32 PM PDT 24 |
| Peak memory | 649124 kb |
| Host | smart-343f8ef6-cb10-4c46-9e22-9614cef41383 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713955636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2713955636 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1071753470 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 3083320500 ps |
| CPU time | 310.58 seconds |
| Started | Jul 09 08:18:01 PM PDT 24 |
| Finished | Jul 09 08:23:12 PM PDT 24 |
| Peak memory | 618724 kb |
| Host | smart-9afbafaf-6fd8-4dd3-9cf6-597114cb3103 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071753470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1071753470 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.578764338 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 3441768514 ps |
| CPU time | 349.54 seconds |
| Started | Jul 09 08:20:58 PM PDT 24 |
| Finished | Jul 09 08:26:48 PM PDT 24 |
| Peak memory | 649184 kb |
| Host | smart-abccac31-9ee7-4c30-b535-2c0b46ed5a66 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578764338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_s w_alert_handler_lpg_sleep_mode_alerts.578764338 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.3679336517 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 4932906222 ps |
| CPU time | 623.86 seconds |
| Started | Jul 09 08:21:43 PM PDT 24 |
| Finished | Jul 09 08:32:08 PM PDT 24 |
| Peak memory | 649852 kb |
| Host | smart-d525af47-b7af-4fdf-9270-b816380d9622 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3679336517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.3679336517 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1767826858 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 4106776876 ps |
| CPU time | 564.94 seconds |
| Started | Jul 09 08:20:26 PM PDT 24 |
| Finished | Jul 09 08:29:52 PM PDT 24 |
| Peak memory | 648884 kb |
| Host | smart-a968c2f5-e011-4602-9dad-8bcbd0f8f732 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767826858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1767826858 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.1440097253 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 5056243300 ps |
| CPU time | 649.28 seconds |
| Started | Jul 09 08:19:04 PM PDT 24 |
| Finished | Jul 09 08:29:54 PM PDT 24 |
| Peak memory | 650200 kb |
| Host | smart-e2311a73-90fc-48f1-9a5e-cc3ed95a30b0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1440097253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.1440097253 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.1602137766 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 6046150410 ps |
| CPU time | 648.7 seconds |
| Started | Jul 09 08:17:21 PM PDT 24 |
| Finished | Jul 09 08:28:11 PM PDT 24 |
| Peak memory | 649972 kb |
| Host | smart-8eff564b-4897-4b6a-b87e-6e6ebced9a4d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1602137766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.1602137766 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.877171511 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 6596743200 ps |
| CPU time | 529.28 seconds |
| Started | Jul 09 08:17:42 PM PDT 24 |
| Finished | Jul 09 08:26:32 PM PDT 24 |
| Peak memory | 610860 kb |
| Host | smart-4041457a-0328-4d81-9f17-97f1a89fbff3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=877171511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.877171511 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.72382499 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 9462632000 ps |
| CPU time | 2133.85 seconds |
| Started | Jul 09 08:19:39 PM PDT 24 |
| Finished | Jul 09 08:55:14 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-e1df87ab-77da-41dd-8d9d-128e34e88b94 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72382499 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.72382499 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1363629947 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 6377039039 ps |
| CPU time | 503.65 seconds |
| Started | Jul 09 08:18:49 PM PDT 24 |
| Finished | Jul 09 08:27:13 PM PDT 24 |
| Peak memory | 621632 kb |
| Host | smart-f4d6cb7e-fe41-45ba-9103-28fb9781ea01 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363629947 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.1363629947 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.1528031116 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 4145033704 ps |
| CPU time | 708.34 seconds |
| Started | Jul 09 08:17:37 PM PDT 24 |
| Finished | Jul 09 08:29:27 PM PDT 24 |
| Peak memory | 624012 kb |
| Host | smart-88e9f031-6426-4e3d-96cb-fe27674c01c8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528031116 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.1528031116 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1433029409 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 9010574506 ps |
| CPU time | 1129.03 seconds |
| Started | Jul 09 08:17:44 PM PDT 24 |
| Finished | Jul 09 08:36:35 PM PDT 24 |
| Peak memory | 624868 kb |
| Host | smart-8001140a-ca54-469e-8f3a-0d68d27c514a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433029409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1433029409 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2964541807 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 4079693840 ps |
| CPU time | 436.16 seconds |
| Started | Jul 09 08:23:21 PM PDT 24 |
| Finished | Jul 09 08:30:38 PM PDT 24 |
| Peak memory | 622768 kb |
| Host | smart-843e9b3b-122a-4c67-964b-b3aca6d7ab29 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964541807 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.2964541807 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1467268641 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 4837100942 ps |
| CPU time | 622.19 seconds |
| Started | Jul 09 08:19:44 PM PDT 24 |
| Finished | Jul 09 08:30:06 PM PDT 24 |
| Peak memory | 624356 kb |
| Host | smart-eff4c933-dbc7-4ecc-8fef-d8735c706d63 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467268641 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.1467268641 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1055444004 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 4463737540 ps |
| CPU time | 684.13 seconds |
| Started | Jul 09 08:16:50 PM PDT 24 |
| Finished | Jul 09 08:28:15 PM PDT 24 |
| Peak memory | 622972 kb |
| Host | smart-5f915dc3-0eae-4d0a-a0e0-0e34ab63dda1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055444004 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.1055444004 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.447344396 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 3850119467 ps |
| CPU time | 366.73 seconds |
| Started | Jul 09 08:17:20 PM PDT 24 |
| Finished | Jul 09 08:23:28 PM PDT 24 |
| Peak memory | 622300 kb |
| Host | smart-2f9d38a5-ea0a-4720-ae54-d7954c373acd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=447344396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.447344396 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.3666161386 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 9515652980 ps |
| CPU time | 847.24 seconds |
| Started | Jul 09 08:18:03 PM PDT 24 |
| Finished | Jul 09 08:32:12 PM PDT 24 |
| Peak memory | 622860 kb |
| Host | smart-733bcc04-8e0b-4511-9672-69aa4cd6635d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666161386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.3666161386 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.2542215192 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 4373643202 ps |
| CPU time | 351.88 seconds |
| Started | Jul 09 08:14:08 PM PDT 24 |
| Finished | Jul 09 08:20:00 PM PDT 24 |
| Peak memory | 631056 kb |
| Host | smart-ce092041-cfc7-442f-8738-8fc58fdaeaa4 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542215192 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.2542215192 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.2389461298 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 5045049428 ps |
| CPU time | 329.79 seconds |
| Started | Jul 09 08:13:40 PM PDT 24 |
| Finished | Jul 09 08:19:11 PM PDT 24 |
| Peak memory | 621268 kb |
| Host | smart-a26acc5b-05f5-4a00-ad97-59d56b4ec688 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2389461298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.2389461298 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.224607360 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 5004239162 ps |
| CPU time | 630.95 seconds |
| Started | Jul 09 08:20:47 PM PDT 24 |
| Finished | Jul 09 08:31:19 PM PDT 24 |
| Peak memory | 617012 kb |
| Host | smart-7216298d-34d6-473a-9395-265823187aca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 224607360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.224607360 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.555368939 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 3086058840 ps |
| CPU time | 486.46 seconds |
| Started | Jul 09 08:21:42 PM PDT 24 |
| Finished | Jul 09 08:29:50 PM PDT 24 |
| Peak memory | 649012 kb |
| Host | smart-fc133cdb-32e4-4f80-afb0-aa58d2a438ef |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555368939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_s w_alert_handler_lpg_sleep_mode_alerts.555368939 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.3054461025 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 5087560584 ps |
| CPU time | 581.59 seconds |
| Started | Jul 09 08:21:41 PM PDT 24 |
| Finished | Jul 09 08:31:24 PM PDT 24 |
| Peak memory | 649796 kb |
| Host | smart-ed7002a8-222b-4188-941f-e823dd64dbea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3054461025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.3054461025 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1481698963 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 3710674212 ps |
| CPU time | 449.04 seconds |
| Started | Jul 09 08:24:12 PM PDT 24 |
| Finished | Jul 09 08:31:41 PM PDT 24 |
| Peak memory | 648884 kb |
| Host | smart-ae3d00bf-6af9-45b1-b26f-a68af354bf84 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481698963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1481698963 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.4016695297 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 3956221996 ps |
| CPU time | 352.76 seconds |
| Started | Jul 09 08:21:22 PM PDT 24 |
| Finished | Jul 09 08:27:16 PM PDT 24 |
| Peak memory | 649436 kb |
| Host | smart-67ab67d8-0216-4757-97c3-e98732f415c7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016695297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4016695297 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.3781414426 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 4941870616 ps |
| CPU time | 549.59 seconds |
| Started | Jul 09 08:22:59 PM PDT 24 |
| Finished | Jul 09 08:32:10 PM PDT 24 |
| Peak memory | 650556 kb |
| Host | smart-1a6354f8-ac8c-4f3b-9f9e-ae270ecb6cde |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3781414426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.3781414426 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2341192080 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 4174643820 ps |
| CPU time | 360 seconds |
| Started | Jul 09 08:27:23 PM PDT 24 |
| Finished | Jul 09 08:33:25 PM PDT 24 |
| Peak memory | 648888 kb |
| Host | smart-0c4141b2-730e-4160-94d4-dfe15cebed2d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341192080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2341192080 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1344169788 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3721879848 ps |
| CPU time | 357.49 seconds |
| Started | Jul 09 08:21:42 PM PDT 24 |
| Finished | Jul 09 08:27:40 PM PDT 24 |
| Peak memory | 648892 kb |
| Host | smart-b2ef3c27-26ec-4a86-a5fc-ba06efbb6d39 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344169788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1344169788 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.702801571 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 4374324570 ps |
| CPU time | 698.6 seconds |
| Started | Jul 09 08:20:56 PM PDT 24 |
| Finished | Jul 09 08:32:36 PM PDT 24 |
| Peak memory | 650080 kb |
| Host | smart-cbf1ea19-69f9-4077-87e0-485bf927f746 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 702801571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.702801571 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.496676261 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 4029456644 ps |
| CPU time | 460.76 seconds |
| Started | Jul 09 08:20:32 PM PDT 24 |
| Finished | Jul 09 08:28:14 PM PDT 24 |
| Peak memory | 648504 kb |
| Host | smart-d458d8c3-7924-47b7-a92e-fb3aff53f9db |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496676261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_s w_alert_handler_lpg_sleep_mode_alerts.496676261 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.562159472 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 3622261376 ps |
| CPU time | 331.27 seconds |
| Started | Jul 09 08:19:10 PM PDT 24 |
| Finished | Jul 09 08:24:42 PM PDT 24 |
| Peak memory | 648988 kb |
| Host | smart-8aca4880-aaf4-4772-beee-1c32c942d2a8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562159472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_s w_alert_handler_lpg_sleep_mode_alerts.562159472 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.2065390975 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 5300745924 ps |
| CPU time | 574.68 seconds |
| Started | Jul 09 08:20:13 PM PDT 24 |
| Finished | Jul 09 08:29:48 PM PDT 24 |
| Peak memory | 650264 kb |
| Host | smart-2d24f4ad-3c0f-45db-a109-fb87a98e862d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2065390975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.2065390975 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2697285360 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 3389996954 ps |
| CPU time | 450.64 seconds |
| Started | Jul 09 08:14:45 PM PDT 24 |
| Finished | Jul 09 08:22:16 PM PDT 24 |
| Peak memory | 649188 kb |
| Host | smart-0da1f73a-0861-4208-9dc3-fe6f9b9ffb85 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697285360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.2697285360 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.1084659853 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 6327752892 ps |
| CPU time | 880.3 seconds |
| Started | Jul 09 08:13:11 PM PDT 24 |
| Finished | Jul 09 08:27:52 PM PDT 24 |
| Peak memory | 650748 kb |
| Host | smart-7e913b9e-7007-461c-83ab-679883cab928 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1084659853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.1084659853 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1763859169 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 6740409176 ps |
| CPU time | 532.49 seconds |
| Started | Jul 09 08:13:36 PM PDT 24 |
| Finished | Jul 09 08:22:29 PM PDT 24 |
| Peak memory | 610912 kb |
| Host | smart-dc0fe1a4-8d2a-4ac9-ab84-66dd56f153eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1763859169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1763859169 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3252968004 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 17195894744 ps |
| CPU time | 3688.48 seconds |
| Started | Jul 09 08:18:22 PM PDT 24 |
| Finished | Jul 09 09:19:51 PM PDT 24 |
| Peak memory | 610912 kb |
| Host | smart-348a79ba-cd76-475d-ad1c-d1f728b20cbf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252968004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.3252968004 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.435239748 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 4727989050 ps |
| CPU time | 631.21 seconds |
| Started | Jul 09 08:13:42 PM PDT 24 |
| Finished | Jul 09 08:24:15 PM PDT 24 |
| Peak memory | 611200 kb |
| Host | smart-8a9a6eff-cb8e-41bb-a2ac-290248f7a9d3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=435239748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.435239748 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3976543701 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 11672802900 ps |
| CPU time | 765.44 seconds |
| Started | Jul 09 08:16:46 PM PDT 24 |
| Finished | Jul 09 08:29:33 PM PDT 24 |
| Peak memory | 625060 kb |
| Host | smart-6b3f7317-5b8c-4802-9dac-621234f733f8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976543701 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.3976543701 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3382631406 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 3796963632 ps |
| CPU time | 377.83 seconds |
| Started | Jul 09 08:23:20 PM PDT 24 |
| Finished | Jul 09 08:29:38 PM PDT 24 |
| Peak memory | 619040 kb |
| Host | smart-f91c6feb-51da-4cd8-8460-0a652870c94d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3382631406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.3382631406 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.2915788273 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 4293688836 ps |
| CPU time | 794.46 seconds |
| Started | Jul 09 08:16:25 PM PDT 24 |
| Finished | Jul 09 08:29:41 PM PDT 24 |
| Peak memory | 624376 kb |
| Host | smart-5cdeb5ac-0768-4835-9110-94269245fab9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915788273 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.2915788273 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1230670613 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 4288050808 ps |
| CPU time | 938.11 seconds |
| Started | Jul 09 08:16:45 PM PDT 24 |
| Finished | Jul 09 08:32:25 PM PDT 24 |
| Peak memory | 624904 kb |
| Host | smart-aae100ef-290a-4fca-9318-8d569e94b499 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230670613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.1230670613 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2889101840 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 13966726608 ps |
| CPU time | 1662.48 seconds |
| Started | Jul 09 08:16:43 PM PDT 24 |
| Finished | Jul 09 08:44:26 PM PDT 24 |
| Peak memory | 619036 kb |
| Host | smart-6696fedf-a283-4b7f-9566-62c0d24d8fe0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889101840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2889101840 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.476992373 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 4297509972 ps |
| CPU time | 830.83 seconds |
| Started | Jul 09 08:13:39 PM PDT 24 |
| Finished | Jul 09 08:27:30 PM PDT 24 |
| Peak memory | 624272 kb |
| Host | smart-c12d7eaf-0de2-46d9-b032-1519bea645b0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476992373 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.476992373 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2218372324 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 4600402272 ps |
| CPU time | 645.43 seconds |
| Started | Jul 09 08:18:53 PM PDT 24 |
| Finished | Jul 09 08:29:39 PM PDT 24 |
| Peak memory | 624332 kb |
| Host | smart-8c9397e7-ce57-4496-b03a-e95449a85362 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218372324 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.2218372324 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1230809977 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 4748701096 ps |
| CPU time | 765.39 seconds |
| Started | Jul 09 08:18:50 PM PDT 24 |
| Finished | Jul 09 08:31:36 PM PDT 24 |
| Peak memory | 623000 kb |
| Host | smart-a12ef0f7-0d36-4fc5-bc53-a27df1f2c8c9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230809977 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.1230809977 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.2588416948 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 3637880102 ps |
| CPU time | 180.86 seconds |
| Started | Jul 09 08:11:56 PM PDT 24 |
| Finished | Jul 09 08:14:57 PM PDT 24 |
| Peak memory | 622120 kb |
| Host | smart-aa6174e1-3f4b-4942-9abf-c5761fd70dea |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2588416948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.2588416948 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.459466839 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 2467100038 ps |
| CPU time | 212.4 seconds |
| Started | Jul 09 08:13:20 PM PDT 24 |
| Finished | Jul 09 08:16:53 PM PDT 24 |
| Peak memory | 621808 kb |
| Host | smart-07239f77-91d1-41e8-8a06-b84ed764f9b5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459466839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.459466839 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.4049927454 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 2481308673 ps |
| CPU time | 137.64 seconds |
| Started | Jul 09 08:16:23 PM PDT 24 |
| Finished | Jul 09 08:18:41 PM PDT 24 |
| Peak memory | 629556 kb |
| Host | smart-66bf1809-5423-44ff-954f-064a80d16f31 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049927454 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.4049927454 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.173910424 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 2998106453 ps |
| CPU time | 152.15 seconds |
| Started | Jul 09 08:16:21 PM PDT 24 |
| Finished | Jul 09 08:18:55 PM PDT 24 |
| Peak memory | 620964 kb |
| Host | smart-8bffc9bc-bc2a-4798-830f-f1fda14235b8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=173910424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.173910424 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.959642455 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 5411289160 ps |
| CPU time | 642.49 seconds |
| Started | Jul 09 08:26:42 PM PDT 24 |
| Finished | Jul 09 08:37:25 PM PDT 24 |
| Peak memory | 649892 kb |
| Host | smart-efe52310-4a2d-436c-b562-9e83db5d9447 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 959642455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.959642455 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3511098697 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 4434910664 ps |
| CPU time | 319.96 seconds |
| Started | Jul 09 08:27:26 PM PDT 24 |
| Finished | Jul 09 08:32:47 PM PDT 24 |
| Peak memory | 649244 kb |
| Host | smart-f2496471-da7c-48f3-96c7-cab06174689d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511098697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3511098697 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.4190559308 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 5358757704 ps |
| CPU time | 782.44 seconds |
| Started | Jul 09 08:19:58 PM PDT 24 |
| Finished | Jul 09 08:33:02 PM PDT 24 |
| Peak memory | 650108 kb |
| Host | smart-82c3e1e5-b431-4aba-8dc5-00e6aaa8fc38 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4190559308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.4190559308 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.3394881124 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 4775162224 ps |
| CPU time | 661.35 seconds |
| Started | Jul 09 08:21:07 PM PDT 24 |
| Finished | Jul 09 08:32:09 PM PDT 24 |
| Peak memory | 649928 kb |
| Host | smart-d5416e18-db85-4633-a3fc-be531f97271e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3394881124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.3394881124 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1870693195 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 4336993692 ps |
| CPU time | 511.15 seconds |
| Started | Jul 09 08:25:08 PM PDT 24 |
| Finished | Jul 09 08:33:41 PM PDT 24 |
| Peak memory | 649220 kb |
| Host | smart-4f3e0931-5f64-4b82-9c40-11cc99607718 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870693195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1870693195 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.2879904683 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 4873117626 ps |
| CPU time | 676.44 seconds |
| Started | Jul 09 08:21:09 PM PDT 24 |
| Finished | Jul 09 08:32:26 PM PDT 24 |
| Peak memory | 650492 kb |
| Host | smart-77399000-f512-4d48-9b2f-9d70ac4c7cc1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2879904683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.2879904683 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3075727571 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 4426466412 ps |
| CPU time | 388.82 seconds |
| Started | Jul 09 08:19:22 PM PDT 24 |
| Finished | Jul 09 08:25:51 PM PDT 24 |
| Peak memory | 649084 kb |
| Host | smart-5b8c42b6-a1b1-4edd-af1a-a946a2dce5db |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075727571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3075727571 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.3991887099 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 4855373784 ps |
| CPU time | 705.79 seconds |
| Started | Jul 09 08:20:50 PM PDT 24 |
| Finished | Jul 09 08:32:36 PM PDT 24 |
| Peak memory | 650792 kb |
| Host | smart-f3c99bac-ac98-4bd1-aa86-f6d254e4d6dd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3991887099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.3991887099 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2157014780 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 13648017770 ps |
| CPU time | 2862.75 seconds |
| Started | Jul 09 08:16:46 PM PDT 24 |
| Finished | Jul 09 09:04:30 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-26aa5081-e800-4f3d-b5b3-8ac08bdd2045 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157014780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.2157014780 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.3091660822 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 6408442488 ps |
| CPU time | 752.32 seconds |
| Started | Jul 09 08:18:24 PM PDT 24 |
| Finished | Jul 09 08:30:57 PM PDT 24 |
| Peak memory | 611216 kb |
| Host | smart-5f78682b-f124-420c-b850-35b49808fce7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3091660822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.3091660822 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.4107701162 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 9605063986 ps |
| CPU time | 918.19 seconds |
| Started | Jul 09 08:16:23 PM PDT 24 |
| Finished | Jul 09 08:31:42 PM PDT 24 |
| Peak memory | 624996 kb |
| Host | smart-93f87a29-ca77-45f0-bdb1-292a4dd39d56 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107701162 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.4107701162 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2336057412 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 13245986600 ps |
| CPU time | 2316.41 seconds |
| Started | Jul 09 08:23:16 PM PDT 24 |
| Finished | Jul 09 09:01:54 PM PDT 24 |
| Peak memory | 619048 kb |
| Host | smart-3f89a184-8918-46a5-8fbe-85d353225c44 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2336057412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.2336057412 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3098280565 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3595801656 ps |
| CPU time | 386.46 seconds |
| Started | Jul 09 08:27:27 PM PDT 24 |
| Finished | Jul 09 08:33:55 PM PDT 24 |
| Peak memory | 648812 kb |
| Host | smart-0ccd375c-1bd5-435f-8cd4-492cd9d34724 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098280565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3098280565 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.2913176480 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 5481955928 ps |
| CPU time | 503.42 seconds |
| Started | Jul 09 08:21:21 PM PDT 24 |
| Finished | Jul 09 08:29:45 PM PDT 24 |
| Peak memory | 617008 kb |
| Host | smart-619e7e93-e328-4802-bcde-b30e679829a5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2913176480 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.2913176480 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3139591314 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 4001558648 ps |
| CPU time | 361.27 seconds |
| Started | Jul 09 08:27:40 PM PDT 24 |
| Finished | Jul 09 08:33:43 PM PDT 24 |
| Peak memory | 648940 kb |
| Host | smart-50a0847b-af92-455c-81da-76652c2fb9a4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139591314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3139591314 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.1900487183 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 4677655306 ps |
| CPU time | 593.44 seconds |
| Started | Jul 09 08:27:12 PM PDT 24 |
| Finished | Jul 09 08:37:07 PM PDT 24 |
| Peak memory | 650148 kb |
| Host | smart-8b3cf4bd-ddc9-4805-8f0b-d170345f78a5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1900487183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.1900487183 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.1260726246 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 6069006720 ps |
| CPU time | 654.41 seconds |
| Started | Jul 09 08:20:23 PM PDT 24 |
| Finished | Jul 09 08:31:18 PM PDT 24 |
| Peak memory | 649972 kb |
| Host | smart-ab10acb5-dce0-40d3-975b-3b2f9a93050a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1260726246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.1260726246 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.938189713 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3225487860 ps |
| CPU time | 351.49 seconds |
| Started | Jul 09 08:29:14 PM PDT 24 |
| Finished | Jul 09 08:35:07 PM PDT 24 |
| Peak memory | 648928 kb |
| Host | smart-07289052-ec9c-4ff0-aa9a-44e4bda173fd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938189713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_s w_alert_handler_lpg_sleep_mode_alerts.938189713 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1058655251 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3696942696 ps |
| CPU time | 501.4 seconds |
| Started | Jul 09 08:20:10 PM PDT 24 |
| Finished | Jul 09 08:28:32 PM PDT 24 |
| Peak memory | 648896 kb |
| Host | smart-863cc0d6-edbf-4d1e-883e-f5e8c7162c64 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058655251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1058655251 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.3773261639 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 4873360010 ps |
| CPU time | 674.62 seconds |
| Started | Jul 09 08:20:35 PM PDT 24 |
| Finished | Jul 09 08:31:50 PM PDT 24 |
| Peak memory | 619768 kb |
| Host | smart-a201c9fb-9bad-4565-ab20-019ab12e26e3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3773261639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.3773261639 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1344684603 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 3897066832 ps |
| CPU time | 473.52 seconds |
| Started | Jul 09 08:22:19 PM PDT 24 |
| Finished | Jul 09 08:30:13 PM PDT 24 |
| Peak memory | 648916 kb |
| Host | smart-75a667f8-d6b9-4dce-850b-1f257cb588e9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344684603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1344684603 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.171466137 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 5074688076 ps |
| CPU time | 674.59 seconds |
| Started | Jul 09 08:20:50 PM PDT 24 |
| Finished | Jul 09 08:32:05 PM PDT 24 |
| Peak memory | 650160 kb |
| Host | smart-d16b0e0d-71be-45cf-af57-0bc9ce84705e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 171466137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.171466137 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2816471875 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 3616967962 ps |
| CPU time | 429.37 seconds |
| Started | Jul 09 08:20:39 PM PDT 24 |
| Finished | Jul 09 08:27:49 PM PDT 24 |
| Peak memory | 648952 kb |
| Host | smart-0bd90083-a275-4ed3-b5a4-84de88cbe480 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816471875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2816471875 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.3776970348 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 4462634164 ps |
| CPU time | 548.45 seconds |
| Started | Jul 09 08:21:18 PM PDT 24 |
| Finished | Jul 09 08:30:27 PM PDT 24 |
| Peak memory | 649844 kb |
| Host | smart-df644342-4096-44a9-b9b3-3bf6f0d2c861 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3776970348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.3776970348 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1249676098 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 3503831100 ps |
| CPU time | 404.85 seconds |
| Started | Jul 09 08:22:40 PM PDT 24 |
| Finished | Jul 09 08:29:26 PM PDT 24 |
| Peak memory | 649112 kb |
| Host | smart-8e6893a5-fe6d-434d-83e1-4369113d4ab1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249676098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1249676098 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.1258210077 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 5915907856 ps |
| CPU time | 848.41 seconds |
| Started | Jul 09 08:21:00 PM PDT 24 |
| Finished | Jul 09 08:35:09 PM PDT 24 |
| Peak memory | 610872 kb |
| Host | smart-b5fc5398-bb52-4be0-bdf1-31e7bed0b4a5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1258210077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.1258210077 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.4057445415 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 5112146472 ps |
| CPU time | 483.54 seconds |
| Started | Jul 09 08:20:30 PM PDT 24 |
| Finished | Jul 09 08:28:34 PM PDT 24 |
| Peak memory | 650444 kb |
| Host | smart-374fcde4-7f9c-46ac-89ce-35cb3ea3978e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4057445415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.4057445415 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3389124867 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 3634975272 ps |
| CPU time | 560.28 seconds |
| Started | Jul 09 08:19:59 PM PDT 24 |
| Finished | Jul 09 08:29:20 PM PDT 24 |
| Peak memory | 649060 kb |
| Host | smart-4c4d26e7-4311-4c9b-ac83-dbd20c32fef5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389124867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.3389124867 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.2981972957 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 4303797304 ps |
| CPU time | 793.39 seconds |
| Started | Jul 09 08:15:41 PM PDT 24 |
| Finished | Jul 09 08:28:55 PM PDT 24 |
| Peak memory | 650396 kb |
| Host | smart-1b00dcc4-93fe-494e-866c-9764e1d9b1e2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2981972957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.2981972957 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3413768850 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 21424513380 ps |
| CPU time | 5130.46 seconds |
| Started | Jul 09 08:17:12 PM PDT 24 |
| Finished | Jul 09 09:42:44 PM PDT 24 |
| Peak memory | 610832 kb |
| Host | smart-cac5fab6-b002-42e4-bb8f-509bb172368c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413768850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.3413768850 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.767947360 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 12101725692 ps |
| CPU time | 1206.46 seconds |
| Started | Jul 09 08:19:09 PM PDT 24 |
| Finished | Jul 09 08:39:17 PM PDT 24 |
| Peak memory | 624044 kb |
| Host | smart-3b39a0f6-8f28-411a-a5d2-9aa41b6ddd23 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767947360 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.767947360 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1567535900 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 4034971992 ps |
| CPU time | 657.47 seconds |
| Started | Jul 09 08:19:39 PM PDT 24 |
| Finished | Jul 09 08:30:38 PM PDT 24 |
| Peak memory | 618728 kb |
| Host | smart-25a7c3e1-eba9-49ff-97b4-dd6c390080a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1567535900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.1567535900 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.2348023716 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 6078214232 ps |
| CPU time | 601.61 seconds |
| Started | Jul 09 08:31:01 PM PDT 24 |
| Finished | Jul 09 08:41:03 PM PDT 24 |
| Peak memory | 650512 kb |
| Host | smart-979cbed4-36aa-49ac-acf6-86ae5d9d8ce2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2348023716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.2348023716 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.978957043 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 4345393720 ps |
| CPU time | 342.79 seconds |
| Started | Jul 09 08:21:09 PM PDT 24 |
| Finished | Jul 09 08:26:52 PM PDT 24 |
| Peak memory | 649220 kb |
| Host | smart-a812bbf8-283e-46f5-bb01-f9caae5a6f62 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978957043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_s w_alert_handler_lpg_sleep_mode_alerts.978957043 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.163168894 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 5232649676 ps |
| CPU time | 566.22 seconds |
| Started | Jul 09 08:22:28 PM PDT 24 |
| Finished | Jul 09 08:31:55 PM PDT 24 |
| Peak memory | 650548 kb |
| Host | smart-c4572159-4ae0-43e1-a81e-2c78ba227320 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 163168894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.163168894 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.104702702 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 4775865008 ps |
| CPU time | 594.23 seconds |
| Started | Jul 09 08:23:43 PM PDT 24 |
| Finished | Jul 09 08:33:38 PM PDT 24 |
| Peak memory | 650064 kb |
| Host | smart-2f129baa-19be-488c-a07c-431e27d01955 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 104702702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.104702702 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.3358404826 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 5730463492 ps |
| CPU time | 782.43 seconds |
| Started | Jul 09 08:21:25 PM PDT 24 |
| Finished | Jul 09 08:34:28 PM PDT 24 |
| Peak memory | 649940 kb |
| Host | smart-ac74b013-769d-468a-aa86-1ca8d870a374 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3358404826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.3358404826 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3735378268 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 3514655570 ps |
| CPU time | 404.84 seconds |
| Started | Jul 09 08:23:11 PM PDT 24 |
| Finished | Jul 09 08:29:56 PM PDT 24 |
| Peak memory | 649256 kb |
| Host | smart-ccfedbb1-815a-4b54-a71e-fcd51f3ad26f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735378268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3735378268 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.2130901050 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 6104217620 ps |
| CPU time | 596.83 seconds |
| Started | Jul 09 08:22:51 PM PDT 24 |
| Finished | Jul 09 08:32:48 PM PDT 24 |
| Peak memory | 650176 kb |
| Host | smart-dda08c91-34fa-4965-aefc-7a052fe956ec |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2130901050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.2130901050 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1383766526 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 4193307840 ps |
| CPU time | 321.62 seconds |
| Started | Jul 09 08:24:12 PM PDT 24 |
| Finished | Jul 09 08:29:34 PM PDT 24 |
| Peak memory | 648908 kb |
| Host | smart-d8543ec8-2c3b-4bd5-bddd-1027d9dead9e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383766526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1383766526 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.263267262 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 5807572062 ps |
| CPU time | 606.99 seconds |
| Started | Jul 09 08:24:57 PM PDT 24 |
| Finished | Jul 09 08:35:05 PM PDT 24 |
| Peak memory | 650164 kb |
| Host | smart-392abe95-1613-4aa9-8666-a56e1fc22408 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 263267262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.263267262 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3839824454 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 3100050992 ps |
| CPU time | 345.88 seconds |
| Started | Jul 09 08:23:17 PM PDT 24 |
| Finished | Jul 09 08:29:03 PM PDT 24 |
| Peak memory | 648712 kb |
| Host | smart-9b0b47ab-4e26-4312-b6f0-dcc9186a6a66 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839824454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3839824454 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4108148239 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 3337878034 ps |
| CPU time | 364.8 seconds |
| Started | Jul 09 08:17:17 PM PDT 24 |
| Finished | Jul 09 08:23:23 PM PDT 24 |
| Peak memory | 649104 kb |
| Host | smart-9710df3d-086f-41d9-bd66-80b22514d7ba |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108148239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.4108148239 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3766161256 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 19520673264 ps |
| CPU time | 4734.24 seconds |
| Started | Jul 09 08:14:48 PM PDT 24 |
| Finished | Jul 09 09:33:43 PM PDT 24 |
| Peak memory | 610888 kb |
| Host | smart-d35ffd20-b60f-468e-8b01-cf1c23460d95 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766161256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.3766161256 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.81411192 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 12439666577 ps |
| CPU time | 1055.33 seconds |
| Started | Jul 09 08:15:38 PM PDT 24 |
| Finished | Jul 09 08:33:14 PM PDT 24 |
| Peak memory | 625028 kb |
| Host | smart-34721bd4-2ff3-4018-b831-468543e2e840 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81411192 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.81411192 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.461244521 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 3743959452 ps |
| CPU time | 492.79 seconds |
| Started | Jul 09 08:17:06 PM PDT 24 |
| Finished | Jul 09 08:25:20 PM PDT 24 |
| Peak memory | 618900 kb |
| Host | smart-0beb6338-95af-4621-b626-5ea2913e7e23 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=461244521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.461244521 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.978612109 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 4332660680 ps |
| CPU time | 437.31 seconds |
| Started | Jul 09 08:21:58 PM PDT 24 |
| Finished | Jul 09 08:29:17 PM PDT 24 |
| Peak memory | 649220 kb |
| Host | smart-ed7ffdf7-6090-4ab6-9263-4200380d0c48 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978612109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_s w_alert_handler_lpg_sleep_mode_alerts.978612109 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3006635794 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3735827424 ps |
| CPU time | 282.47 seconds |
| Started | Jul 09 08:22:06 PM PDT 24 |
| Finished | Jul 09 08:26:50 PM PDT 24 |
| Peak memory | 649016 kb |
| Host | smart-84bf5668-c6c7-4d6c-bd03-33820467f211 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006635794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3006635794 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2052563863 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 3362262728 ps |
| CPU time | 468.68 seconds |
| Started | Jul 09 08:24:07 PM PDT 24 |
| Finished | Jul 09 08:31:57 PM PDT 24 |
| Peak memory | 649216 kb |
| Host | smart-ea8d5af3-656f-4919-a2ad-9608d15bcd35 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052563863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2052563863 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.4002938821 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 5074052236 ps |
| CPU time | 592.27 seconds |
| Started | Jul 09 08:22:21 PM PDT 24 |
| Finished | Jul 09 08:32:14 PM PDT 24 |
| Peak memory | 650160 kb |
| Host | smart-0a4e58e2-ab89-4cfa-ab39-a48853629ce8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4002938821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.4002938821 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3860621825 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 3369732128 ps |
| CPU time | 394.86 seconds |
| Started | Jul 09 08:22:51 PM PDT 24 |
| Finished | Jul 09 08:29:27 PM PDT 24 |
| Peak memory | 648908 kb |
| Host | smart-e6ea61a3-4d91-4c0e-8c20-7ef0f968a167 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860621825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3860621825 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3634166454 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 3849789118 ps |
| CPU time | 423.41 seconds |
| Started | Jul 09 08:25:47 PM PDT 24 |
| Finished | Jul 09 08:32:51 PM PDT 24 |
| Peak memory | 649316 kb |
| Host | smart-00dcf94a-8a98-4c9e-a88c-d463ed3ffd08 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634166454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3634166454 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.796562187 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 4723914824 ps |
| CPU time | 440.35 seconds |
| Started | Jul 09 08:22:33 PM PDT 24 |
| Finished | Jul 09 08:29:54 PM PDT 24 |
| Peak memory | 617024 kb |
| Host | smart-c8ec61ae-915f-4eae-906e-352873919d39 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 796562187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.796562187 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1248554342 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 3680918176 ps |
| CPU time | 360.94 seconds |
| Started | Jul 09 08:23:23 PM PDT 24 |
| Finished | Jul 09 08:29:24 PM PDT 24 |
| Peak memory | 648932 kb |
| Host | smart-cbad2757-607a-4d84-b273-4303b381467e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248554342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1248554342 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1284152304 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 4056962640 ps |
| CPU time | 438.02 seconds |
| Started | Jul 09 08:22:12 PM PDT 24 |
| Finished | Jul 09 08:29:31 PM PDT 24 |
| Peak memory | 649136 kb |
| Host | smart-adff01fb-68b0-44e5-8108-1c8fd2c553cb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284152304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1284152304 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4014407002 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 3852173260 ps |
| CPU time | 357.16 seconds |
| Started | Jul 09 08:23:45 PM PDT 24 |
| Finished | Jul 09 08:29:42 PM PDT 24 |
| Peak memory | 649024 kb |
| Host | smart-79801b22-5034-4f39-ba76-e131fd2dcf76 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014407002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4014407002 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.2939401023 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 5677640724 ps |
| CPU time | 753.42 seconds |
| Started | Jul 09 08:24:06 PM PDT 24 |
| Finished | Jul 09 08:36:40 PM PDT 24 |
| Peak memory | 650116 kb |
| Host | smart-6007deca-db10-444a-adff-8f4cd8a2771b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2939401023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.2939401023 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.202351278 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 4100626852 ps |
| CPU time | 513.57 seconds |
| Started | Jul 09 08:23:07 PM PDT 24 |
| Finished | Jul 09 08:31:41 PM PDT 24 |
| Peak memory | 648848 kb |
| Host | smart-d4516e20-8aab-4643-a2da-84aa809919eb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202351278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_s w_alert_handler_lpg_sleep_mode_alerts.202351278 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1050046218 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 4194285936 ps |
| CPU time | 363.74 seconds |
| Started | Jul 09 08:17:56 PM PDT 24 |
| Finished | Jul 09 08:24:00 PM PDT 24 |
| Peak memory | 649128 kb |
| Host | smart-b9486eef-3676-416f-9eec-6cf9c37e92c6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050046218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.1050046218 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.787966577 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 4695742276 ps |
| CPU time | 574.14 seconds |
| Started | Jul 09 08:19:44 PM PDT 24 |
| Finished | Jul 09 08:29:19 PM PDT 24 |
| Peak memory | 650188 kb |
| Host | smart-91e6020f-0335-4dd5-9d2f-a92aad3ca0f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 787966577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.787966577 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2550081157 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 16680821666 ps |
| CPU time | 3077.72 seconds |
| Started | Jul 09 08:17:46 PM PDT 24 |
| Finished | Jul 09 09:09:05 PM PDT 24 |
| Peak memory | 610884 kb |
| Host | smart-ad383f31-196e-4a1e-9c27-a4d4679acb44 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550081157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.2550081157 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1443656058 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 10216875200 ps |
| CPU time | 874 seconds |
| Started | Jul 09 08:15:52 PM PDT 24 |
| Finished | Jul 09 08:30:27 PM PDT 24 |
| Peak memory | 622644 kb |
| Host | smart-9aa33686-2e70-4a0f-a54d-f03eb6bed30e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443656058 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.1443656058 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2407120447 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 13757611376 ps |
| CPU time | 2710.25 seconds |
| Started | Jul 09 08:15:37 PM PDT 24 |
| Finished | Jul 09 09:00:48 PM PDT 24 |
| Peak memory | 619272 kb |
| Host | smart-c60f60cc-33f3-4d6c-b3f9-ee30d3e03fd2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2407120447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.2407120447 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.776338487 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 4452288864 ps |
| CPU time | 337.33 seconds |
| Started | Jul 09 08:23:08 PM PDT 24 |
| Finished | Jul 09 08:28:46 PM PDT 24 |
| Peak memory | 649360 kb |
| Host | smart-16e7fc99-b183-412f-a8f0-eeddbae5c42c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776338487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_s w_alert_handler_lpg_sleep_mode_alerts.776338487 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.2775116587 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 4535524860 ps |
| CPU time | 676.1 seconds |
| Started | Jul 09 08:23:34 PM PDT 24 |
| Finished | Jul 09 08:34:51 PM PDT 24 |
| Peak memory | 650380 kb |
| Host | smart-0c25e484-1361-475a-a5c6-5c5430647273 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2775116587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.2775116587 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1194227988 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 3411071420 ps |
| CPU time | 447.2 seconds |
| Started | Jul 09 08:25:14 PM PDT 24 |
| Finished | Jul 09 08:32:42 PM PDT 24 |
| Peak memory | 648964 kb |
| Host | smart-5736a9f6-8491-419e-bb61-cdd2671f72a3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194227988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1194227988 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.1119650772 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 5185600928 ps |
| CPU time | 583.63 seconds |
| Started | Jul 09 08:25:17 PM PDT 24 |
| Finished | Jul 09 08:35:02 PM PDT 24 |
| Peak memory | 650276 kb |
| Host | smart-2ab30b7c-90c7-4277-b35e-4b1647919bbc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1119650772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.1119650772 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.571787556 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 3188918990 ps |
| CPU time | 359.83 seconds |
| Started | Jul 09 08:23:25 PM PDT 24 |
| Finished | Jul 09 08:29:26 PM PDT 24 |
| Peak memory | 648856 kb |
| Host | smart-1f666601-6ca2-4461-8eba-c7f3ae7c8553 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571787556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_s w_alert_handler_lpg_sleep_mode_alerts.571787556 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.1167243753 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4269441584 ps |
| CPU time | 509.8 seconds |
| Started | Jul 09 08:23:59 PM PDT 24 |
| Finished | Jul 09 08:32:29 PM PDT 24 |
| Peak memory | 649844 kb |
| Host | smart-2154256d-4a7f-4633-ad1d-7a61ff4240fb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1167243753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.1167243753 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3246563120 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 2989662936 ps |
| CPU time | 361.29 seconds |
| Started | Jul 09 08:25:40 PM PDT 24 |
| Finished | Jul 09 08:31:42 PM PDT 24 |
| Peak memory | 648684 kb |
| Host | smart-da6c4db2-7083-45a2-b21b-352a33808d6f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246563120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3246563120 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.691065503 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 4864118228 ps |
| CPU time | 499.82 seconds |
| Started | Jul 09 08:23:42 PM PDT 24 |
| Finished | Jul 09 08:32:02 PM PDT 24 |
| Peak memory | 649956 kb |
| Host | smart-3bf3cdfc-9d6f-4f19-929b-d72685d4cd2e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 691065503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.691065503 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.246212725 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 3335606442 ps |
| CPU time | 420.2 seconds |
| Started | Jul 09 08:25:26 PM PDT 24 |
| Finished | Jul 09 08:32:27 PM PDT 24 |
| Peak memory | 648960 kb |
| Host | smart-becf855a-420b-443a-b54e-8d2b3db64241 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246212725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_s w_alert_handler_lpg_sleep_mode_alerts.246212725 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.4020964842 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 4799943234 ps |
| CPU time | 516.61 seconds |
| Started | Jul 09 08:23:41 PM PDT 24 |
| Finished | Jul 09 08:32:18 PM PDT 24 |
| Peak memory | 650372 kb |
| Host | smart-3e15a8e0-b90b-4841-b963-b64a2b90fe36 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4020964842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.4020964842 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4216735307 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 4008738060 ps |
| CPU time | 419.68 seconds |
| Started | Jul 09 08:23:06 PM PDT 24 |
| Finished | Jul 09 08:30:06 PM PDT 24 |
| Peak memory | 648932 kb |
| Host | smart-e9db48fa-209f-4593-856f-47c38a686071 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216735307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4216735307 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.2218497189 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 5428095000 ps |
| CPU time | 483.76 seconds |
| Started | Jul 09 08:23:24 PM PDT 24 |
| Finished | Jul 09 08:31:29 PM PDT 24 |
| Peak memory | 649752 kb |
| Host | smart-d0eb24c6-2c96-4c42-af89-96430be08c2f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2218497189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.2218497189 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.223408131 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 4501807678 ps |
| CPU time | 351.85 seconds |
| Started | Jul 09 08:24:13 PM PDT 24 |
| Finished | Jul 09 08:30:06 PM PDT 24 |
| Peak memory | 649024 kb |
| Host | smart-be76fc68-2a99-480a-961a-fcd796608f66 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223408131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_s w_alert_handler_lpg_sleep_mode_alerts.223408131 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.222181266 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 5488304982 ps |
| CPU time | 735.69 seconds |
| Started | Jul 09 08:23:22 PM PDT 24 |
| Finished | Jul 09 08:35:38 PM PDT 24 |
| Peak memory | 650092 kb |
| Host | smart-c1d2cdc5-1169-482a-9295-82d6230a2f4b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 222181266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.222181266 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.522981711 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3541747624 ps |
| CPU time | 329.64 seconds |
| Started | Jul 09 08:26:39 PM PDT 24 |
| Finished | Jul 09 08:32:10 PM PDT 24 |
| Peak memory | 648880 kb |
| Host | smart-84edc783-9d9d-4a04-9e66-0c5d03b653d9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522981711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_s w_alert_handler_lpg_sleep_mode_alerts.522981711 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.1979079952 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 5264098110 ps |
| CPU time | 676.23 seconds |
| Started | Jul 09 08:24:33 PM PDT 24 |
| Finished | Jul 09 08:35:50 PM PDT 24 |
| Peak memory | 650300 kb |
| Host | smart-fa466762-6bff-4825-96d3-9c90c7d98d87 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1979079952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.1979079952 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.692447333 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3694483478 ps |
| CPU time | 350.13 seconds |
| Started | Jul 09 08:32:28 PM PDT 24 |
| Finished | Jul 09 08:38:19 PM PDT 24 |
| Peak memory | 648756 kb |
| Host | smart-6ba8d085-05ae-49b5-858c-5e60c2e9dd9a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692447333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_s w_alert_handler_lpg_sleep_mode_alerts.692447333 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.1505697534 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 5914191802 ps |
| CPU time | 682.5 seconds |
| Started | Jul 09 08:27:42 PM PDT 24 |
| Finished | Jul 09 08:39:06 PM PDT 24 |
| Peak memory | 650160 kb |
| Host | smart-ef06bd83-1a1c-4e0d-891f-28856ccf399f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1505697534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.1505697534 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1938872859 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 4617248124 ps |
| CPU time | 399.68 seconds |
| Started | Jul 09 08:24:13 PM PDT 24 |
| Finished | Jul 09 08:30:53 PM PDT 24 |
| Peak memory | 649164 kb |
| Host | smart-182a577a-dbbb-44c6-a043-b0c41f1ef556 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938872859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1938872859 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.1197805132 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 5848046008 ps |
| CPU time | 542.18 seconds |
| Started | Jul 09 08:24:13 PM PDT 24 |
| Finished | Jul 09 08:33:15 PM PDT 24 |
| Peak memory | 649856 kb |
| Host | smart-2a1c8d2e-1e61-4fe8-984b-b07de7945f88 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1197805132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.1197805132 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1481497597 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 3687562440 ps |
| CPU time | 382.54 seconds |
| Started | Jul 09 08:15:27 PM PDT 24 |
| Finished | Jul 09 08:21:50 PM PDT 24 |
| Peak memory | 648580 kb |
| Host | smart-112d9a73-d136-49f9-b3be-58d18280fb59 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481497597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.1481497597 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.754552186 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 5985228408 ps |
| CPU time | 679.65 seconds |
| Started | Jul 09 08:21:20 PM PDT 24 |
| Finished | Jul 09 08:32:41 PM PDT 24 |
| Peak memory | 650236 kb |
| Host | smart-a8c28c8e-7e3e-4a0a-bfd7-c11ca28186e2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 754552186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.754552186 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1140692184 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 17499471046 ps |
| CPU time | 3414.79 seconds |
| Started | Jul 09 08:21:37 PM PDT 24 |
| Finished | Jul 09 09:18:34 PM PDT 24 |
| Peak memory | 610944 kb |
| Host | smart-6d89c3df-86fc-4191-8d48-c58985ac351b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140692184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.1140692184 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.76597775 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 10194964620 ps |
| CPU time | 950.49 seconds |
| Started | Jul 09 08:21:07 PM PDT 24 |
| Finished | Jul 09 08:36:58 PM PDT 24 |
| Peak memory | 623492 kb |
| Host | smart-ce572e47-dc66-4ae4-8e5a-b0977526bb13 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76597775 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.76597775 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2946697642 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 8377316020 ps |
| CPU time | 1258.34 seconds |
| Started | Jul 09 08:15:43 PM PDT 24 |
| Finished | Jul 09 08:36:43 PM PDT 24 |
| Peak memory | 619004 kb |
| Host | smart-97dcd433-da5c-4d11-af1e-cecf19357e11 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2946697642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.2946697642 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.2041579898 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 5536407524 ps |
| CPU time | 483.53 seconds |
| Started | Jul 09 08:25:20 PM PDT 24 |
| Finished | Jul 09 08:33:24 PM PDT 24 |
| Peak memory | 649796 kb |
| Host | smart-7546a6c2-aa86-4394-8e92-60c043ef50a5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2041579898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.2041579898 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.904454997 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 6405790844 ps |
| CPU time | 750.57 seconds |
| Started | Jul 09 08:23:59 PM PDT 24 |
| Finished | Jul 09 08:36:31 PM PDT 24 |
| Peak memory | 650424 kb |
| Host | smart-b1919ac3-89ca-44b3-8494-ca800421fb26 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 904454997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.904454997 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.3846169519 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 4682059468 ps |
| CPU time | 558.25 seconds |
| Started | Jul 09 08:23:58 PM PDT 24 |
| Finished | Jul 09 08:33:17 PM PDT 24 |
| Peak memory | 650248 kb |
| Host | smart-ff3b61c8-a687-4a72-839c-e846c068b8b1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3846169519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.3846169519 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.502973619 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 6555255152 ps |
| CPU time | 551.07 seconds |
| Started | Jul 09 08:24:46 PM PDT 24 |
| Finished | Jul 09 08:33:58 PM PDT 24 |
| Peak memory | 650052 kb |
| Host | smart-93d4194c-20c3-44dc-b56f-aad21f863d92 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 502973619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.502973619 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.3500625905 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 6051084746 ps |
| CPU time | 676.76 seconds |
| Started | Jul 09 08:24:48 PM PDT 24 |
| Finished | Jul 09 08:36:06 PM PDT 24 |
| Peak memory | 650164 kb |
| Host | smart-361c241f-12e5-4cfc-91c9-f9406be46d1a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3500625905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.3500625905 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.924552334 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 5260488220 ps |
| CPU time | 365.03 seconds |
| Started | Jul 09 08:23:23 PM PDT 24 |
| Finished | Jul 09 08:29:28 PM PDT 24 |
| Peak memory | 650196 kb |
| Host | smart-f588f514-b13f-4503-9850-e66068dafc84 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 924552334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.924552334 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.2961396729 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 5680174790 ps |
| CPU time | 552.36 seconds |
| Started | Jul 09 08:27:53 PM PDT 24 |
| Finished | Jul 09 08:37:07 PM PDT 24 |
| Peak memory | 650200 kb |
| Host | smart-4af5f038-ff30-4a87-8ffc-33cfd22d81db |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2961396729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.2961396729 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1500651540 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 5189463026 ps |
| CPU time | 282.65 seconds |
| Started | Jul 09 07:41:49 PM PDT 24 |
| Finished | Jul 09 07:46:33 PM PDT 24 |
| Peak memory | 657688 kb |
| Host | smart-1f0773a6-6cd6-48b6-ae13-11ed392c1a9e |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500651540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.1500651540 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.911279007 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5046852050 ps |
| CPU time | 283.93 seconds |
| Started | Jul 09 07:41:49 PM PDT 24 |
| Finished | Jul 09 07:46:34 PM PDT 24 |
| Peak memory | 649504 kb |
| Host | smart-509a6835-225f-4d37-9ffb-0eed67045e71 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911279007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 1.chip_padctrl_attributes.911279007 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.230005850 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 5439682464 ps |
| CPU time | 180.46 seconds |
| Started | Jul 09 07:41:49 PM PDT 24 |
| Finished | Jul 09 07:44:50 PM PDT 24 |
| Peak memory | 641352 kb |
| Host | smart-673da195-483d-47ef-9240-4bab7f8ce507 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230005850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 2.chip_padctrl_attributes.230005850 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.66124641 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 5150251560 ps |
| CPU time | 219.47 seconds |
| Started | Jul 09 07:41:48 PM PDT 24 |
| Finished | Jul 09 07:45:28 PM PDT 24 |
| Peak memory | 641304 kb |
| Host | smart-7e50fe7c-05e8-4998-b401-169d54b49647 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66124641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/nu ll -cm_name 4.chip_padctrl_attributes.66124641 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3784800572 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4450449259 ps |
| CPU time | 258.81 seconds |
| Started | Jul 09 07:41:46 PM PDT 24 |
| Finished | Jul 09 07:46:06 PM PDT 24 |
| Peak memory | 641380 kb |
| Host | smart-92127a89-e850-4ec5-85ff-e6ad606815b6 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784800572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.3784800572 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2214836179 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4962523816 ps |
| CPU time | 198.63 seconds |
| Started | Jul 09 07:41:47 PM PDT 24 |
| Finished | Jul 09 07:45:07 PM PDT 24 |
| Peak memory | 641356 kb |
| Host | smart-6778e20a-9668-4b18-b483-3abb1324ed52 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214836179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.2214836179 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2868297251 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4999369648 ps |
| CPU time | 240.48 seconds |
| Started | Jul 09 07:41:52 PM PDT 24 |
| Finished | Jul 09 07:45:54 PM PDT 24 |
| Peak memory | 641280 kb |
| Host | smart-d3174f3d-5053-4cc8-a2c0-9be2c6803221 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868297251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.2868297251 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4070666629 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4017154203 ps |
| CPU time | 206.99 seconds |
| Started | Jul 09 07:41:53 PM PDT 24 |
| Finished | Jul 09 07:45:21 PM PDT 24 |
| Peak memory | 641308 kb |
| Host | smart-f6a33a48-d404-4a0e-9347-042abcaa5e74 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070666629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.4070666629 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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